WO2020259082A1 - 缓存的分配方法及装置、存储介质、电子装置 - Google Patents
缓存的分配方法及装置、存储介质、电子装置 Download PDFInfo
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- WO2020259082A1 WO2020259082A1 PCT/CN2020/088364 CN2020088364W WO2020259082A1 WO 2020259082 A1 WO2020259082 A1 WO 2020259082A1 CN 2020088364 W CN2020088364 W CN 2020088364W WO 2020259082 A1 WO2020259082 A1 WO 2020259082A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
- G06F15/7846—On-chip cache and off-chip main memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
- G06F2015/765—Cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
Definitions
- This application relates to the field of multi-core network processors, for example, to a cache allocation method and device, storage medium, and electronic device.
- the embodiments of the present application provide a cache allocation method and device, storage medium, and electronic device to at least solve the increase in memory access delay and maximum access delay caused by the increase in the number of cores and the parallelism of network slicing in the related art Low problem.
- the length of the fetching PC is determined according to the maximum space of instructions and data in each network slice, and network slice information is added when accessing the MEM.
- Fig. 6 is a structural block diagram of a device for allocating a cache according to an embodiment of the present application.
- the device includes: an access module 62, located in the core, configured to detect the access by sending a fetch instruction When both the responses of the first level cache and the second level cache are missing responses, access the third level cache; wherein the instruction fetching instruction is used for requesting access to the cache to return instructions and data;
- the first level cache is the core's Private cache;
- the second-level cache is a public cache corresponding to the core set where the core is located;
- the third-level cache is a common cache shared between multiple core sets;
- the loss response of the second-level cache carries the network Slice information;
- allocation module 64 located in the planning unit set in the three-level cache, set to allocate the multiple core sets to multiple network slices and configure the multiple network slices according to the network slice information
- the response module 66 located in the planning unit, is configured to send a hit response to the core, where the hit response is
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- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (10)
- 一种缓存的分配方法,包括:核在检测到通过发送取指指令所访问的一级缓存与二级缓存的响应均为丢失响应的情况下,访问三级缓存;其中,所述取指指令用于请求访问的缓存返回指令和数据;所述一级缓存为所述核的私有缓存;所述二级缓存为所述核所在的核集合对应的公共缓存;所述三级缓存为多个核集合之间共有的公共缓存;所述二级缓存的丢失响应中携带有网络切片信息;设置于所述三级缓存中的规划单元根据所述网络切片信息将所述多个核集合分配至多个网络切片以及为所述多个网络切片配置相应的缓存;所述规划单元向所述核发送命中响应,其中,所述命中响应用于返回所述核所在的核集合对应的网络切片的缓存中的数据。
- 根据权利要求1所述的方法,其中,规划单元为所述多个网络切片配置相应的缓存,包括:所述规划单元按照预设的划分规则将所述多个网络切片划分为多个网络切片组,其中,所述网络切片组中包括至少一个所述网络切片;所述规划单元在每个所述网络切片组中设置标记信息;所述规划单元按照所述标记信息为具有多个所述网络切片的所述网络切片组中的每个网络切片划分缓存资源块。
- 根据权利要求2所述的方法,其中,所述标记信息包括第一标记信息和第二标记信息;所述规划单元按照所述标记信息为具有多个所述网络切片的所述网络切片组中的每个网络切片划分缓存资源块,包括:所述规划单元根据第一标记信息以及第二标记信息为所述每个网络切片划分缓存资源块,其中,所述第一标记信息用于指示所述网络切片组中所述网络切片的数量,所述第二标记信息用于标记所述网络切片对应的地址信息。
- 根据权利要求3所述的方法,还包括:所述规划单元根据所述网络切片组中的所述网络切片的优先级对每个所述网络切片的地址信息和数据信息进行调整。
- 根据权利要求4所述的方法,还包括:所述核在检测到通过发送所述取指指令所访问的所述三级缓存响应为丢失 响应情况下,向外存发送取指指令,并接收所述外存反馈的取指结果;所述规划单元根据所述取指结果对所述地址信息和所述数据信息进行更新。
- 根据权利要求1-5任一项所述的方法,其中,在访问缓存的情况下,所述核发送的取指指令的数量为N,其中,N为不小于1的正整数。
- 一种缓存的分配装置,包括:访问模块,位于核中,设置为在检测到通过发送取指指令所访问的一级缓存与二级缓存的响应均为丢失响应的情况下,访问三级缓存;其中,所述取指指令用于请求访问的缓存返回指令和数据;所述一级缓存为所述核的私有缓存;所述二级缓存为所述核所在的核集合对应的公共缓存;所述三级缓存为多个核集合之间共有的公共缓存;所述二级缓存的丢失响应中携带有网络切片信息;分配模块,位于设置于所述三级缓存中的规划单元中,设置为根据所述网络切片信息将所述多个核集合分配至多个网络切片以及为所述多个网络切片配置相应的缓存;响应模块,位于所述规划单元中,设置为向所述核发送命中响应,其中,所述命中响应用于返回所述核所在的核集合对应的网络切片的缓存中的数据。
- 根据权利要求7所述的装置,其中,所述分配模块包括:第一划分单元,设置为按照预设的划分规则将所述多个网络切片划分为多个网络切片组,其中,所述网络切片组中包括至少一个所述网络切片;设置单元,设置为在每个所述网络切片组中设置标记信息;第二划分单元,设置为按照所述标记信息为具有多个所述网络切片的所述网络切片组中的每个网络切片划分缓存资源块。
- 一种存储介质,存储有计算机程序,所述计算机程序被设置为运行时执行所述权利要求1至6中任一项所述的方法。
- 一种电子装置,包括存储器和处理器,所述存储器中存储有计算机程序,所述处理器被设置为运行所述计算机程序以执行所述权利要求1至6中任一项所述的方法。
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US17/606,449 US11940915B2 (en) | 2019-06-28 | 2020-04-30 | Cache allocation method and device, storage medium, and electronic device |
EP20832000.2A EP3944091B1 (en) | 2019-06-28 | 2020-04-30 | Cache allocation method and device, storage medium, and electronic device |
KR1020217034546A KR20210141690A (ko) | 2019-06-28 | 2020-04-30 | 캐시 할당 방법 및 장치, 저장 매체, 전자 장치 |
JP2021562299A JP7205033B2 (ja) | 2019-06-28 | 2020-04-30 | キャッシュの割当方法と装置、記憶媒体、電子装置 |
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CN115576872B (zh) * | 2022-11-18 | 2023-03-24 | 北京红山微电子技术有限公司 | 多级缓存的访问检测方法及装置 |
CN117093371B (zh) * | 2023-02-23 | 2024-05-17 | 摩尔线程智能科技(北京)有限责任公司 | 缓存资源分配方法、装置、电子设备和存储介质 |
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CN112148665B (zh) | 2024-01-09 |
US11940915B2 (en) | 2024-03-26 |
KR20210141690A (ko) | 2021-11-23 |
EP3944091A4 (en) | 2022-06-08 |
EP3944091B1 (en) | 2024-01-10 |
JP2022539285A (ja) | 2022-09-08 |
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