WO2020257974A1 - 异质结双极型晶体管及其制备方法 - Google Patents

异质结双极型晶体管及其制备方法 Download PDF

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WO2020257974A1
WO2020257974A1 PCT/CN2019/092549 CN2019092549W WO2020257974A1 WO 2020257974 A1 WO2020257974 A1 WO 2020257974A1 CN 2019092549 W CN2019092549 W CN 2019092549W WO 2020257974 A1 WO2020257974 A1 WO 2020257974A1
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layer
base
emitter
hbt
collector
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English (en)
French (fr)
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龚顺强
徐向明
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a heterojunction bipolar transistor and a preparation method thereof.
  • Heterojunction bipolar transistor is a type of bipolar junction transistor (BJT). It uses different semiconductor materials for its emitter region and base region, and its emitter junction (ie The PN junction between the emitter region and the base region is a heterojunction. Compared with general BJTs, heterojunction bipolar transistors have better high-frequency signal characteristics and base emission efficiency, and are increasingly used in mobile phones, tablets, wireless routers, base stations and other equipment, such as mobile phones Use HBT to amplify the power of radio frequency (RF) signals sent to the base station.
  • RF radio frequency
  • an embodiment of the present application provides a heterojunction bipolar transistor, including: a substrate, a collector region layer, a base region layer, and an emitter region layer stacked on the substrate in sequence, wherein the emitter The zone layer is provided with a plurality of through holes penetrating the emission zone layer, the plurality of through holes are arranged at intervals, and the through holes expose part of the first surface, and the first surface is on the base zone layer facing away from the The surface of the collector region layer; a base electrode is provided on the first surface exposed by the through hole, and the base electrode is spaced from the emitter region layer.
  • a plurality of through holes are arranged at intervals in the emitter layer, and the through holes occupy less area of the emitter layer. That is to say, in the embodiment of the present application, a plurality of through holes are arranged at intervals.
  • the zone layer is much smaller than the emission zone layer lost by the trenches in the prior art. In turn, more emission zone layers remain on the first surface 2031 of the base zone layer, which increases the distance between the emission zone layer and the base zone layer.
  • the area ratio (S E /S B ) increases the power gain of the HBT.
  • the plurality of through holes are distributed in an array, so that the plurality of base electrodes arranged in the plurality of through holes are also distributed in an array, and further, the resistance of the base layer is in the entire HBT device row. Evenly distribute, improve the performance of HBT.
  • the size of the through hole may be 1 to 3 times the minimum design rule of the through hole, wherein the minimum design rule of the through hole is related to the size of the HBT device, the preparation process of the HBT device, etc. , It is the HBT device that can achieve the smallest through hole size allowed in the embodiments of this application.
  • the through hole 2041 can be square, and the size can be 1-5 um in length and 1-5 um in width; it can also be round or other shapes, which is not limited in the embodiment of the present application.
  • an insulating layer is further included between the emitter region layer and the base electrode.
  • the heterojunction bipolar transistor further includes: a collector and an emitter, wherein the collector and the base region layer are spaced apart from the collector region layer.
  • the emitter is arranged on the surface of the emitter layer facing away from the base layer.
  • an embodiment of the present application also provides an amplifying circuit.
  • the amplifying circuit includes the heterojunction bipolar transistor as described in the first aspect.
  • embodiments of the present application also provide a baseband chip, which includes the amplifying circuit described in the second aspect, and the amplifying circuit is used to amplify the power of the transmitted signal.
  • an embodiment of the present application also provides a method for manufacturing a heterojunction bipolar transistor, including:
  • a plurality of through holes penetrating through the emission area layer are opened in the emission area layer, and the plurality of through holes are arranged at intervals to partially expose the first surface of the base area layer;
  • a base electrode is formed on the first surface exposed by the through hole, and the base electrode is spaced from the emitter layer.
  • the multiple through holes are distributed in an array.
  • the forming a base electrode on the first surface exposed by the through hole, the base electrode being spaced from the emitter layer specifically includes:
  • the first photoresist layer is patterned to form a first via hole on the first photoresist layer in the through hole, the first via hole reveals that the base layer is away from the collector region On the surface of the layer, the size of the first via is smaller than the size of the via where the first via is located;
  • first conductive layer Forming a first conductive layer on the first photoresist layer, the first conductive layer filling the first via hole and connecting to the base layer;
  • the method before the forming the first insulating layer on the emitter layer, the method further includes:
  • the second conductive layer is patterned to form an emitter.
  • the method further includes:
  • a collector electrode is formed on the surface of the exposed collector region layer facing away from the substrate.
  • a plurality of through holes are arranged at intervals in the emitter layer, and the through holes occupy less area of the emitter layer. That is, in the embodiment of the present application, a plurality of through holes are arranged at intervals
  • the emission zone layer lost by the hole is much smaller than the emission zone layer lost by the trench in the prior art, and furthermore, more emission zone layers remain on the first surface 2031 of the base zone layer, increasing the emission zone layer and The area ratio of the base layer (S E /S B ), in turn, increases the power gain of the HBT.
  • Fig. 1A is a schematic top view of an HBT provided in the prior art
  • FIG. 1B is a schematic cross-sectional view of an HBT provided in the prior art
  • FIG. 2A is a schematic top view of an HBT provided by an embodiment of this application.
  • FIG. 2B is a schematic cross-sectional view of an HBT provided by an embodiment of this application.
  • FIG. 3A is a schematic top view of an HBT provided by an embodiment of this application.
  • 3B is a schematic cross-sectional view of an HBT provided by an embodiment of the application.
  • FIG. 4A is a schematic top view of an HBT provided by an embodiment of this application.
  • FIG. 4B is a schematic top view of an HBT provided by an embodiment of the application.
  • FIG. 4C is a schematic top view of an HBT provided by an embodiment of the application.
  • FIG. 5 is a schematic top view of an HBT provided by an embodiment of the application.
  • FIG. 6 is a schematic flow chart of a method for preparing HBT according to an embodiment of the application.
  • FIG. 7 is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application.
  • FIG. 8A is a schematic top view of a structure formed in a manufacturing process of an HBT provided by an embodiment of the application.
  • FIG. 8B is a schematic cross-sectional view of a structure formed in a manufacturing process of an HBT provided by an embodiment of the application;
  • 9A is a schematic top view of a structure formed in a manufacturing process of HBT according to an embodiment of the application.
  • 9B is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application.
  • FIG. 10 is a schematic cross-sectional view of a structure formed in a manufacturing process of an HBT provided by an embodiment of the application;
  • FIG. 11 is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application;
  • FIG. 12 is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application;
  • FIG. 13A is a schematic top view of a structure formed in a manufacturing process of an HBT according to an embodiment of the application.
  • FIG. 13B is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application;
  • FIG. 14A is a schematic top view of a structure formed in a manufacturing process of HBT provided by an embodiment of the application;
  • FIG. 14B is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application;
  • 15A is a schematic top view of a structure formed in a manufacturing process of HBT according to an embodiment of the application.
  • 15B is a schematic cross-sectional view of a structure formed in a manufacturing process of HBT according to an embodiment of the application;
  • FIG. 16 is a schematic structural diagram of an integrated circuit device according to an embodiment of the application.
  • Heterojunction bipolar transistor hereinafter referred to as "transistor” or “HBT”
  • transistor is a kind of bipolar junction transistor (BJT)
  • BJT bipolar junction transistor
  • its emitter junction ie the PN junction between the emitter region and the base region
  • heterojunction bipolar transistors have better high-frequency signal characteristics and base transmission efficiency, and are increasingly used in terminals.
  • HBT is used to amplify the radio frequency (RF) sent to the base station. ) The power of the signal.
  • RF radio frequency
  • the power gain of HBT (that is, the ratio of output power to input power) is used as a key indicator for evaluating HBT and used to measure the quality of the process. After the HBT process is cured, the power gain of HBT is usually related to the area ratio (SE/SB) of the emitting area and the base area. The larger the SE/SB, the greater the power gain.
  • SE/SB area ratio
  • FIG. 1A and FIG. 1B a schematic top view and a schematic cross-sectional view of an HBT provided in the prior art are shown.
  • 1B is a schematic cross-sectional view of the HBT shown in FIG. 1A along the dotted line.
  • the HBT includes: a substrate 101, a collector region layer 102, a base region layer 103, and an emission region layer 104 are sequentially formed, and a collector electrode 105 disposed on the surface of the collector region layer 102 facing away from the substrate 101 is disposed in the base region layer.
  • the emitter layer 104 is provided with a trench, the trench penetrates the emitter layer 104 and exposes the surface of the base layer 103, and the base electrode 106 is disposed in the trench and is spaced apart from the emitter layer 104. It can be seen that in order to connect the base 106 to the base layer 103, a larger area trench is opened in the above-mentioned HBT structure. The arrangement of the trench greatly reduces the area of the emitter layer 104, making the power gain of the HBT smaller. .
  • the purpose of the embodiments of the present application is to provide a HBT with higher gain, which has a larger area ratio of the emitter region to the base region.
  • the following describes the HBT provided in the embodiments of the present application.
  • FIG. 2A and 2B show the schematic structural diagrams of the HBT, and the schematic structural diagrams of another HBT shown in Figs. 3A and 3B, wherein Fig. 2A is a schematic top view of the HBT and Fig. 2B is along the dotted line in Fig. 2A 3A is a schematic cross-sectional view of the HBT and FIG. 3B is a schematic cross-sectional view of the HBT along the dotted line in FIG. 3A.
  • the HBT includes: a substrate 201, a collector layer 202, a base layer 203, and an emitter layer 204 stacked on the substrate 201 in sequence, a collector 205, a base 206, an emitter 207, and the like.
  • the substrate 201 may be a silicon wafer, or may be formed of materials such as silicon carbide, gallium arsenide (GaAs), or gallium nitride (GaN).
  • a collector region layer 202 is laminated on a surface 2011 of the substrate 201.
  • the collector region layer 202 is formed on a surface 2011 of the substrate 201.
  • the collector region layer 202 may be formed of a plurality of sub-collection region layers, wherein the plurality of sub-collection region layers are stacked in a direction perpendicular to the surface 2011.
  • the base region layer 203 and the collector electrode 205 are formed on the surface of the collector region layer 202 facing away from the substrate 201, and the base region layer 203 and the collector electrode 205 are spaced apart to ensure insulation between the collector electrode 205 and the base region layer 203.
  • the base region layer 203 may be formed of multiple sub-base region layers, which are stacked on the surface of the collector region layer 202 facing away from the substrate 201.
  • the emitter layer 204 is formed on the surface of the base layer 203 away from the collector layer 202.
  • the emitter layer 204 has a plurality of through holes 2041 penetrating through the emitter layer 204.
  • the plurality of through holes 2041 are arranged at intervals, and the through holes 2041 expose part of the
  • the first surface 2031 is the surface of the base layer 203 facing away from the collector layer 202; the first surface 2031 exposed by the through hole 2041 is provided with a base electrode 206, a base electrode 206 and an emitter layer 204 Phase interval.
  • the first surface 2031 of the base layer 203 is the surface of the base layer 203 away from the collector layer 202.
  • the size of the through hole 2041 is larger than the size of the base electrode 206 provided in the through hole 2041 so that the base electrode 206 can be isolated from the emitter layer 204.
  • the emission area layer 204 may be formed of multiple sub-emission area layers, and the multiple sub-emission area layers are stacked on the surface of the base area layer 203 opposite to the collector area layer 202.
  • a plurality of through holes 2041 are arranged at intervals to occupy a smaller area of the emission zone layer 204, that is, in the embodiment of the present application, a plurality of through holes 2041 lose the emission zone.
  • the layer 204 is much smaller than the emitter layer lost by the trench in the prior art, and furthermore, more emitter layer 204 remains on the first surface 2031 of the base layer 203, increasing the emitter layer 204 and the base layer.
  • area ratio (S E / S B) of the area of the layer 203 in turn, increase the power gain of the HBT.
  • a plurality of through holes 2041 are distributed at the four corners and the middle position of the emitter layer 204.
  • a plurality of through holes 2041 are arranged at intervals in the middle of the emission zone layer 203.
  • a plurality of through holes 2041 may be evenly distributed on the surface of the emitter layer 204 away from the base layer 203 to ensure that the base resistance is evenly distributed on the entire device. It should be understood that the distribution of the multiple through holes 2041 in FIG. 2A and FIG. 3A is not limited, and the multiple through holes 2041 may also be distributed on the surface of the emitter layer 204 away from the base layer 203 in other ways.
  • a plurality of through holes 2041 may be arranged in the collector layer 202 in an array.
  • the multiple through holes 2041 are in the form of an array (2*4 order array in the HBT shown in FIG. 4A, 3*4 order array in the HBT shown in FIG. 4B, and 1*4 order array in the HBT shown in FIG. 4C)
  • Distributed in the emitter layer 204 a base electrode 206 is provided on the surface of the base layer 203 exposed by each through hole 2041, and the base electrode 206 is spaced from the emitter layer 204.
  • the cross-sectional schematic diagram of the HBT along the dotted line shown in FIG. 4A may be as shown in FIG.
  • FIG. 4C The cross-sectional schematic diagram of the HBT along the dotted line shown in FIG. 4C may be as shown in FIG. 3B, which is not repeated in this application.
  • the layer structure of the HBT shown in FIG. 4B is similar to the layer structure of 4A, and will not be repeated in this application.
  • the dimensions of the plurality of through holes 2041 in the above-mentioned FIGS. 2A, 3A, 4A, 4B, and 4C are the same, and the sizes of the base electrodes 206 in the plurality of through holes 2041 are the same, in another embodiment of the present application
  • the size of the multiple through holes 2041 in each HBT may be different or partly different.
  • the size of the base electrode 206 may be different or partly different from each other, which is not limited in the embodiment of the present application.
  • the numbers of the through holes 2041 in the above figures are merely illustrative. In another implementation of the present application, the HBT may also include more or fewer through holes 2041, which is not limited in the embodiment of the present application.
  • the through holes 2041 are distributed on the edge of the emitter layer 204, which further reduces the area of the emitter layer 204 occupied by the through holes 2041, and further improves the power of the HBT. Gain.
  • part of the through holes 2041 are distributed on the edge of the emitter layer 204, which further reduces the area of the emitter layer 204 occupied by the through holes 2041, and further improves the HBT. Power gain.
  • the size of the through hole 2041 may be 1 to 3 times the minimum design rule of the through hole, wherein the minimum design rule of the through hole is related to the size of the HBT device, the preparation process of the HBT device, etc. , It is the HBT device that can achieve the smallest through hole size allowed in the embodiments of this application.
  • the through hole 2041 can be square, and the size can be 1-5 um in length and 1-5 um in width; it can also be round or other shapes, which is not limited in the embodiment of the present application.
  • the above-mentioned HBT may also include an insulating layer.
  • the schematic cross-sectional view of the HBT shown in FIG. 5 is an insulating layer 208 and a redistribution layer added on the basis of the HBT shown in FIG. 2B. 209.
  • the insulating layer 208 can fill the gap between the emitter layer 204 and the base electrode 206 to isolate the emitter layer 204 and the base electrode 206.
  • the insulating layer 208 can also fill the gap between the collector 206 and the base layer 203 to isolate the collector 206 from the base layer 203.
  • the insulating layer 208 may cover the collector layer 202, the base layer 203, and the emitter layer 204, the collector 205, the base 206 or the emitter 207 may penetrate the insulating layer 208, and the collector 205 is away from the collector.
  • the end surface of the zone layer 202, the end surface of the base electrode 206 away from the base zone layer 203, the end surface of the emitter electrode 207 away from the emitter area layer 204, and the surface of the insulating layer 208 away from the emitter area 204 are flush.
  • the insulating layer 208 may include a redistribution layer 209.
  • the circuit connection collector 205 in the redistribution layer 209 is away from the end surface of the collector layer 202, the base electrode 206 is away from the end surface of the base layer 203, and the emitter 207 is away from the emitter area.
  • the HBT may be an NPN type or PNP type transistor.
  • the HBT is an NPN transistor.
  • the material of the base layer 203 or the sub-base layer is a P-type semiconductor.
  • the material of the zone layer 204 or the sub-emitter zone layer is an N-type semiconductor.
  • the HBT is a PNP transistor.
  • the material of the base layer 203 is an N-type semiconductor, and the emitter layer 204 The material is P-type semiconductor.
  • doping Si, S, Se, Te, Sn and other dopants in semiconductor materials such as GaAs, Si, InP, SiC, GaN, AlGaAs, InGaP, etc. can form N-type semiconductors; on the contrary, doping C, Dopants such as Mg, Be, and Zn can form a p-type semiconductor.
  • the semiconductor materials of the collector layer 202, the base layer 203, and the emitter layer 204 of the HBT in the embodiment of the present application may be the same.
  • the collector layer 202 is formed of N-type GaAs
  • the base layer 203 is formed of P-type GaAs
  • the emitter layer 204 is formed of N-type GaAs; in another implementation, the semiconductor materials of the collector layer 202, the base layer 203, and the emitter layer 204 may be different from each other Or partly different.
  • the collector layer 202 is formed of N-type GaAs
  • the base layer 203 is formed of P-type AlGaAs
  • the emitter layer 204 is formed of N-type InGaP.
  • the collector electrode 205, the base electrode 206 or the emitter electrode 207 may be formed of gold (Au), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), titanium (Ti) and other metals or metal alloys, It can also be formed of other conductive materials, such as indium tin oxide (ITO), graphene, etc., which is not limited in the embodiments of the present application.
  • the insulating layer 208 can be formed of inorganic insulating materials such as SiN, SiC, or high molecular polymers or resins, such as epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc.
  • the organic insulating material is formed.
  • the HBT described in the embodiments of the present application can be applied in a power amplifier circuit.
  • the power amplifier circuit can be further mounted on devices with communication functions such as portable mobile phones, tablet wireless routers, and base stations.
  • the power amplifier circuit on the mobile phone is used to amplify the power of the wireless signal sent to the base station.
  • the power amplifying circuit can respond to 2G (2th-Generation mobile communication technology) signals, 3G (3th-Generation mobile communication technology) signals, 4G (4th-Generation mobile communication technology) signals, 5G (5th-Generation mobile communication technology) signals,
  • the power of signals of communication standards such as 5G (5th-Generation Mobile Communication Technology) signals are amplified, and other signals may also be amplified, which is not limited in the embodiment of the present application.
  • an HBT with a suitable structure can be selected according to the requirements of different application scenarios of the HBT, which is not limited in the embodiment of the present application.
  • this application also provides a method for preparing HBT, by which the HBT with stable performance and low cost can be prepared more conveniently. Please refer to the flow chart of the preparation method of HBT shown in FIG. 6, and also refer to the schematic diagrams of the manufacturing process shown in FIGS. 7-15B.
  • the preparation method of the HBT may include, but is not limited to, some or all of the following steps:
  • the substrate 201 may be a silicon wafer, or may be formed of materials such as silicon carbide, gallium arsenide (GaAs), or gallium nitride (GaN).
  • GaAs gallium arsenide
  • GaN gallium nitride
  • a collector region layer 202, a base region layer 203 and an emission region layer 204 are sequentially formed on the substrate 201.
  • the methods for forming the collector region layer 202, the base region layer 203, and the emission region layer 204 are in the prior art, and will not be repeated in the embodiment of the application.
  • the materials of the collector region layer 202, the base region layer 203 and the emission region layer 204 can refer to the relevant description in the above-mentioned embodiment of the structure of the HBT, which will not be repeated in this embodiment of the application.
  • FIGS. 8A and 8B As shown in FIGS. 8A and 8B, an emitter is formed on the surface of the emitter layer 204 away from the base layer 203.
  • 8A is a schematic top view of the HBT formed in step S06
  • FIG. 8B is a schematic cross-sectional view of the HBT along the dotted line in FIG. 8A.
  • a second conductive layer can be formed on the surface of the emitter layer 204 away from the base layer 203 by a coating process, and further, by patterning the second conductive layer, the emitter 204 is formed to expose part of the emitter layer 204 .
  • S06 can also be formed by other processes, such as silk screen printing, 3D printing, and other technologies to form a patterned emitter, which is not limited by the embodiment itself.
  • FIGS. 9A and 9B As shown in FIGS. 9A and 9B, a plurality of through holes 2041 penetrating through the emitter layer 204 are opened in the emitter layer 204, and the plurality of through holes 2041 are arranged at intervals to partially expose the first surface 2031 of the base layer 203.
  • 9A is a schematic top view of the HBT formed in step S08
  • FIG. 9B is a schematic cross-sectional view of the HBT along the dotted line in FIG. 9A.
  • S08 can open a plurality of through holes 2041 penetrating the emitter layer 204 in the emitter layer 204 through a patterning process, which specifically can include forming a layer of photoresist on the structure as shown in FIG. 8A, and exposing the photoresist through a photomask , The developing solution develops the photoresist to remove part of the photoresist to obtain a patterned photoresist, and then use the patterned photoresist layer as a mask to etch the emitter layer 204, and then copy the pattern of the photoresist To the emitter layer 204, a plurality of through holes 2041 penetrating the emitter layer 204 are obtained.
  • the through holes 2041 may be distributed in an array, or distributed in other ways, which is not limited in the embodiment of the present application.
  • a base electrode 206 is formed on the first surface exposed by the through hole 2041, wherein the base electrode 206 is spaced from the emitter layer 204.
  • S10 may include, but is not limited to, the following two implementation manners.
  • a first photoresist layer 1001 is formed on the surface of the emitter layer 204 away from the base layer 203. Wherein, the first photoresist layer 801 fills a plurality of through holes 2041.
  • the first photoresist layer 1001 is patterned to form a first via hole 1011 on the first photoresist layer 1001 in the via hole 2041, and the first via hole 1011 exposes the base
  • the area layer 203 faces away from the surface of the collector area layer 202, and the size of the first via hole 1011 is smaller than the size of the via hole 2041 where the first via hole 1011 is located.
  • the first photoresist layer 1001 is partially exposed through a photomask, and further, the first photoresist layer 1001 is developed by a developer to obtain the structure shown in FIG. 11.
  • a first conductive layer 1002 is formed on the first photoresist layer 801, and the first conductive layer 1002 fills the first via hole 1011 and is connected to the base layer 203.
  • FIG. 13A is a through A schematic top view of the HBT formed in step S108
  • FIG. 13B is a schematic cross-sectional view of the HBT along the dotted line in FIG. 13A.
  • FIGS. 14A and 14B As shown in FIGS. 14A and 14B, part of the base region layer 203 and part of the emitter region layer 204 on the substrate 201 are removed to expose a part of the collector region layer 202.
  • 14A is a schematic top view of the HBT formed through step S12
  • FIG. 14B is a schematic cross-sectional view of the HBT along the dotted line in FIG. 14A.
  • a third photoresist layer can be formed on the structure shown in FIG. 13A, the third photoresist layer is exposed through a photomask, and the third photoresist layer is developed by the developer to remove part of the third photoresist layer. , To obtain a patterned third photoresist layer, and then use the patterned third photoresist layer as a mask to etch the base region layer 203 and the collector region layer 202 to expose a part of the collector region layer 202.
  • a collector electrode 205 is formed on the surface of the exposed collector region layer 202 away from the substrate 201.
  • a third conductive layer can be formed on the third photoresist layer, and further, the third photoresist layer and the third conductive layer disposed on the third photoresist layer are removed by a developer to obtain a collector 205.
  • the method can also form an insulating layer, which can fill the gap between the emitter layer 204 and the base electrode 206 to isolate the emitter layer 204 and the base electrode 206.
  • the insulating layer 208 can also fill the gap between the collector 206 and the base layer 203 to isolate the collector 206 from the base layer 203.
  • the method may further include forming a redistribution layer on the insulating layer, so that the circuit connection collector 205 in the redistribution layer 209 is away from the end surface of the collector layer 202, the base electrode 206 is away from the end surface of the base layer 203, The emitter 207 faces away from the end surface of the emitter layer 204.
  • the HBT obtained by the preparation method of the HBT described in the embodiment of the present application is provided with a plurality of through holes at intervals in the emission region layer, and the through holes occupy less area of the emission region layer.
  • the emitter layer lost by a through hole is much smaller than the emitter layer lost by the trench in the prior art, and furthermore, more emitter layers remain on the first surface 2031 of the base layer, which increases the emitter area.
  • the area ratio of the layer to the base layer (S E /S B ), thereby increasing the power gain of the HBT.
  • the patterning refers to a patterning process, which may include a photolithography process, or a photolithography process and an etching step, or may also include printing, inkjet, and other processes for forming The crafting of the predetermined pattern.
  • the photolithography process refers to the process including film formation, exposure, development, stripping and other processes and the use of photoresist, mask, exposure machine, etc. to form a pattern.
  • the corresponding patterning process can be selected according to the structure formed in the present invention.
  • the etching process includes a dry etching process and a wet etching process.
  • the dry etching process is a process in which the etched material is corroded and removed by the chemical reaction and physical reaction between the etched material and the particles in the plasma. Dry etching methods include plasma etching, reactive ion etching or inductively coupled plasma etching.
  • the wet etching process is an etching method in which the etched substance is stripped off by the chemical reaction between the chemical etching solution and the etched substance. The corresponding etching process can be selected according to the structure formed in the present invention.
  • the preparation of each layer of material can adopt thin film preparation methods, including but not limited to magnetron sputtering coating, chemical vapor deposition, laser sputtering deposition, spin coating, thermal evaporation, etc., preparation methods
  • thin film preparation methods including but not limited to magnetron sputtering coating, chemical vapor deposition, laser sputtering deposition, spin coating, thermal evaporation, etc.
  • preparation methods including but not limited to magnetron sputtering coating, chemical vapor deposition, laser sputtering deposition, spin coating, thermal evaporation, etc.
  • An embodiment of the present application also provides an amplifying circuit, which includes the HBT shown in FIGS. 2A to 5 or the HBT obtained by the above-mentioned HBT preparation method.
  • the embodiments of the present application also provide a chip, which may be a baseband chip or a processing chip, and includes a radio frequency module, wherein the radio frequency module includes the aforementioned amplifying circuit to amplify the power of the transmitted signal.
  • the aforementioned baseband chip or radio frequency module can further be applied to integrated circuit devices.
  • FIG. 16 is a schematic structural diagram of an integrated circuit device 1600 provided by an embodiment of the present application.
  • the integrated circuit device 1600 includes a processor 161 and a radio frequency module 166.
  • the processing module 161 and the radio frequency module 166 can be integrated in One chip can also be integrated in the processing application chip (AP) and the baseband chip respectively.
  • the radio frequency module 166 includes an amplifier circuit, and the amplifier circuit includes the HBT provided in the embodiment of the application or the HBT preparation method provided in the embodiment of the application.
  • the prepared HBT please refer to the relevant descriptions in the above-mentioned structural embodiment and preparation method embodiment of the HBT, and the details are not repeated in the embodiments of this application.
  • the processing module 161 may be integrated with a CPU, a memory, and the like.
  • the integrated circuit device may further include a power management module 162 for supplying power to the integrated circuit 161.
  • the integrated circuit device may further include a communication module 163, an input module 164, and/or an output module 165.
  • the communication module 163 is used to realize the communication connection between the integrated circuit device and other devices or the Internet;
  • the input module 164 is used to realize the user inputting information into the integrated circuit device, and may include a touch panel, a keyboard, a camera, etc.; an output module 165 Used to realize the output of information from the integrated circuit device to the user, which may include a display panel, etc.
  • the power management module 162, the communication module 163, the input module 164 and/or the output module 165 are not necessary components of the integrated circuit device; the power management module 162, the communication module 163, the input module 164 and/or the output module 165 may also It is integrated in the integrated circuit 161, or is separately provided and coupled to the integrated circuit 161, which is not limited in the embodiment of the present application.
  • the integrated circuit device in the embodiment of the application may be a smart phone, a tablet computer, a personal digital assistant, an e-book, a computer, a base station, a smart bracelet, a virtual reality (Virtual Reality, VR) device, and an augmented reality (Augmented Reality, AR) device , Digital TVs, set-top boxes, wireless routers and other devices that include power amplifier circuits.
  • VR Virtual Reality
  • AR Augmented Reality
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • chip packaging method can be executed by robots or numerical control processing, and the device software or process used to execute the chip packaging method can be executed by executing the computer program code stored in the memory. Chip packaging method.

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Abstract

本申请提供了一种异质结双极型晶体管及其制备方法，该异质结双极型晶体管包括基板，依次层叠在所述基板上的集电区层、基区层和发射区层，其中，发射区层开设贯穿发射区层的多个通孔，该多个通孔间隔设置，通孔显露部分所述基区层的第一表面；在通孔显露的第一表面上设有基极，基极与发射区层相间隔。上述异质结双极型晶体管中间隔设置多个通孔占据发射区层更少的面积，使得更多的发射区层保留在基区层的第一表面2031上，增大了发射区层与基区层的面积比例（S E/S B），进而，提高HBT的功率增益。

Description

异质结双极型晶体管及其制备方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种异质结双极型晶体管及其制备方法。
背景技术
异质结双极型晶体管(heterojunction bipolar transistor，HBT)是双极性晶体管(bipolar junction transistor,BJT)的一种，它的发射区和基区使用了不同的半导体材料，它的发射结(即发射区和基区之间的PN结)为异质结。与一般的BJT相比，异质结双极性晶体管具有更好的高频信号特性和基区发射效率，被越来越多地应用于手机、平板电脑、无线路由器、基站等设备，例如手机使用HBT来放大发送到基站的射频(RF)信号的功率。
随着终端产业的快速发展，对高增益的HBT的需求越来越大。如何提高HBT的增益是目前亟待解决的技术问题。
发明内容
第一方面，本申请实施例提供了一种异质结双极型晶体管，包括：基板，依次层叠在所述基板上的集电区层、基区层和发射区层，其中，所述发射区层开设贯穿所述发射区层的多个通孔，所述多个通孔间隔设置，所述通孔显露部分第一表面，所述第一表面为所述基区层上背对所述集电区层的表面；在所述通孔显露的所述第一表面上设有基极，所述基极与发射区层相间隔。
上述异质结双极型晶体管通过在发射区层间隔设置多个通孔，该通孔占据发射区层更少的面积，也就是说，本申请实施例中间隔设置多个通孔损失的发射区层远远小于现有技术中沟槽所损失的发射区层，进而，使得更多的发射区层保留在基区层的第一表面2031上，增大了发射区层与基区层的面积比例(S E/S B)，进而，提高HBT的功率增益。
在本申请一种可能的实现中，所述多个通孔呈阵列分布，使得设置于多个通孔内的多个基极也呈阵列分布，进而，使基区层电阻在整个HBT器件行均匀分布，提高HBT的性能。
在本申请一种可能的实现中，所述通孔的尺寸可以是通孔的最小设计规则的1至3倍，其中，通孔的最小设计规则与HBT器件尺寸、HBT器件的制备工艺等有关，是HBT器件可实现本申请实施例中所允许的最小的通孔尺寸。通常，该通孔2041可以是方形，尺寸可以是长1-5um，宽1-5um；也可以是圆形或其他形状，本申请实施例不作限定。进一步地，发射区层204与基区层203的面积比例(S E/S B)不小于0.5，比如该比例为0.65、0.75、0.8、0.9等。
在本申请一种可能的实现中，所述发射区层和所述基极之间还包括绝缘层。
在本申请一种可能的实现中，所述异质结双极型晶体管还包括：集电极和发射极，其中，所述集电极与所述基区层间隔设置于所述集电区层背对所述基板的表面；所述发射极设置于所述发射区层背对所述基区层的表面。
第二方面，本申请实施例还提供了一种放大电路所述放大电路包括如第一方面所述的异质结双极型晶体管。
第三方面，本申请实施例还提供了一种基带芯片，该基带芯片包括如第二方面所述的放大电路，该放大电路用于对发送的信号的功率进行放大。
第四方面，本申请实施例还提供了一种异质结双极型晶体管的制备方法，包括：
提供一基板；
在所述基板上依次形成集电区层、基区层和发射区层；
在所述发射区层开设贯穿所述发射区层的多个通孔，所述多个通孔间隔设置，以部分显露所述基区层的第一表面；
在所述通孔显露的第一表面上形成基极，所述基极与发射区层相间隔。
在本申请一种可能的实现中，所述多个通孔呈阵列分布。
在本申请一种可能的实现中，所述在所述通孔显露的第一表面上形成基极，所述基极与发射区层相间隔，具体包括：
在所述发射区层上形成第一光刻胶层；
图案化所述第一光刻胶层，以在所述通孔内的第一光刻胶层上形成第一过孔，所述第一过孔显露所述基区层背离所述集电区层的表面，所述第一过孔的尺寸小于所述第一过孔所在通孔的尺寸；
在所述第一光刻胶层上形成第一导电层，所述第一导电层填充所述第一过孔并连接所述基区层；
去除所述第一光刻胶层以及去除所述第一光刻胶层上的所述第一导电层，形成基极。
在本申请一种可能的实现中，所述在所述发射区层上形成第一绝缘层之前，所述方法还包括：
在所述发射区层背离所述基区层的表面形成第二导电层；
图案化所述第二导电层，形成发射极。
在本申请一种可能的实现中，所述去除所述第一绝缘层上的所述第一导电层，形成基极之后，所述方法还包括：
去除所述基板上的部分的所述基区层、部分的发射区层，以裸露部分所述集电区层。
在裸露的所述集电区层背离所述基板的表面上形成集电极。
上述制备方法得到的异质结双极型晶体管通过在发射区层间隔设置多个通孔，该通孔占据发射区层更少的面积，也就是说，本申请实施例中间隔设置多个通孔损失的发射区层远远小于现有技术中沟槽所损失的发射区层，进而，使得更多的发射区层保留在基区层的第一表面2031上，增大了发射区层与基区层的面积比例(S E/S B)，进而，提高HBT的功率增益。
附图说明
图1A为现有技术提供的一种HBT的俯视示意图；
图1B为现有技术提供的一种HBT的剖面示意图；
图2A为本申请实施例提供的一种HBT的俯视示意图；
图2B为本申请实施例提供的一种HBT的剖面示意图；
图3A为本申请实施例提供的一种HBT的俯视示意图；
图3B为本申请实施例提供的一种HBT的剖面示意图
图4A为本申请实施例提供的一种HBT的俯视示意图；
图4B为本申请实施例提供的一种HBT的俯视示意图；
图4C为本申请实施例提供的一种HBT的俯视示意图；
图5为本申请实施例提供的一种HBT的俯视示意图；
图6为本申请实施例提供的一种HBT的制备方法的流程示意图；
图7为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图8A为本申请实施例提供的一种HBT的制备工艺中形成结构的俯视示意图；
图8B为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图9A为本申请实施例提供的一种HBT的制备工艺中形成结构的俯视示意图；
图9B为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图10为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图11为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图12为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图13A为本申请实施例提供的一种HBT的制备工艺中形成结构的俯视示意图；
图13B为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图14A为本申请实施例提供的一种HBT的制备工艺中形成结构的俯视示意图；
图14B为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图15A为本申请实施例提供的一种HBT的制备工艺中形成结构的俯视示意图；
图15B为本申请实施例提供的一种HBT的制备工艺中形成结构的剖面示意图；
图16为本申请实施例提供的一种集成电路设备的结构示意图。
具体实施方式
异质结双极型晶体管(heterojunction bipolar transistor，HBT)，以下简称“晶体管”或“HBT”，是双极性晶体管(bipolar junction transistor,BJT)的一种，它的发射区和基区使用了不同的半导体材料，它的发射结(即发射区和基区之间的PN结)为异质结。与一般的BJT相比，异质结双极性晶体管具有更好的高频信号特性和基区发射效率，被越来越多地应用于终端，例如使用HBT来放大发送到基站的射频(RF)信号的功率。
HBT的功率增益(即输出功率和输入功率的比例)作为评价HBT的关键指标，用来衡量工艺的优劣程度。HBT工艺固化后，通常HBT的功率增益与发射区与基区的面积比例(SE/SB)有关，SE/SB越大，则功率增益越大。
传统的HBT中，集电极、发射极和基极通常呈条状分布，如图1A和图1B所示的现有技术提供的一种HBT俯视示意图和剖面示意图。其中，图1B为图1A所示的HBT沿虚线所示位置的剖面示意图。该HBT包括：基板101，依次形成集电区层102、基区层103和发射区层104，设置于在集电区层102背离基板101的表面上的集电极105，设置于在基 区层103背离集电区层102的表面上的基极106以及设置于在发射区层104背离基区层103的表面上的发射极107。其中，发射区层104开设沟槽，该沟槽贯穿发射区层104，显露基区层103的表面，基极106设置于沟槽内并与发射区层104相间隔。可见，为使得基极106连接到基区层103，上述HBT结构中，开设了较大面积的沟槽，在沟槽的设置大大减少了发射区层104的面积，使得HBT的功率增益较小。
本申请实施例的目的在于提供一种增益更高的HBT，该HBT具有更大的发射区与基区的面积比例。下面介绍本申请实施例提供的HBT。
如图2A和图2B所示的HBT的结构示意图，图3A和图3B所示的另一种HBT的结构示意图，其中，图2A为HBT的俯视示意图和图2B该HBT沿图2A中虚线的剖面示意图，图3A为HBT的俯视示意图和图3B该HBT沿图3A中虚线的剖面示意图。该HBT包括：基板201，依次层叠在基板201上的集电区层202、基区层203和发射区层204，集电极205，基极206和发射极207等。
基板201可以是硅片，也可以是由碳化硅、砷化镓(GaAs)或氮化镓(GaN)等材料形成。该基板201的一表面2011上层叠有集电区层202。
集电区层202形成于基板201的一表面2011上。集电区层202可以由多层子集电区层形成，其中，多层子集电区层沿垂直于表面2011的方向层叠设置。
基区层203和集电极205形成在集电区层202背对基板201的表面，基区层203和集电极205间隔设置，以保证集电极205与基区层203之间绝缘。可选地，基区层203可以由多层子基区层形成，多层子基区层层叠设置于集电区层202背对基板201的表面。
发射区层204形成在基区层203背离集电区层202的表面，发射区层204开设贯穿发射区层204的多个通孔2041，多个通孔2041间隔设置，通孔2041显露部分的第一表面2031，第一表面2031为基区层203上背对集电区层202的表面；在通孔2041显露的第一表面2031上设有基极206，基极206与发射区层204相间隔。其中，基区层203的第一表面2031即为基区层203背离集电区层202的表面。
应理解，通孔2041的尺寸大于该通孔2041内设置的基极206的尺寸，以使得基极206可以与发射区层204相互隔离。
可选地，发射区层204可以由多层子发射区层形成，多层子发射区层层叠设置与基区层203背对集电区层202的表面。
相对于现有技术的HBT，本申请实施例中间隔设置多个通孔2041占据发射区层204更少的面积，也就是说，本申请实施例中间隔设置多个通孔2041损失的发射区层204远远小于现有技术中沟槽所损失的发射区层，进而，使得更多的发射区层204保留在基区层203的第一表面2031上，增大了发射区层204与基区层203的面积比例(S E/S B)，进而，提高HBT的功率增益。
上述图2A和图2B所示的HBT中，多个通孔2041分布于发射区层204的四个角和中间位置。上述图3A、图3B所示的HBT中，多个通孔2041间隔排列于发射区层203中间位置。可选地，多个通孔2041可以均匀地分布于发射区层204背离基区层203的表面，以保证基区电阻在整个器件上的分布均匀。应理解，不限于上述图2A和图3A中多个通孔2041的分布方式，多个通孔2041还可以以其他方式分布于发射区层204背离基区层203的表面。
可选地，多个通孔2041可以以阵列形式排列于集电区层202。如图3A-图3B所示的HBT的俯视示意图。多个通孔2041以阵列(如图4A所示的HBT中2*4阶阵列，图4B所示的HBT中3*4阶阵列，图4C所示的HBT中1*4阶阵列)的形式分布于发射区层204，在每一个通孔2041所裸露的基区层203的表面设置一个基极206，该基极206与发射区层204相间隔。应理解，上述图4A所示的HBT沿虚线的剖面示意图可以如上述图2B所示，本申请不再赘述。上述图4C所示的HBT沿虚线的剖面示意图可以如上述图3B所示，本申请不再赘述。上述图4B所示的HBT的层结构同上述4A的层结构相似，本申请不再赘述。虽然上述图2A、图3A、图4A、图4B、和图4C中多个通孔2041的尺寸相同、该多个通孔2041内的基极206的尺寸相同，在本申请另一实施例中，各个HBT中多个通孔2041的尺寸可以互不相同或部分不同，同理，基极206的尺寸可以互不相同或部分不同，对此本申请实施例不作限定。上述各个图中通孔2041的个数仅仅为实例性说明，在本申请另一种实现中，HBT还可以包括更多或更少的通孔2041，对此，本申请实施例不作限定。
与图4A相比，在图4B所示的HBT中，通孔2041分布于发射区层204的边缘，进一步地减少通孔2041所占据发射区层204的面积，进而，进一步地提高HBT的功率增益。
与图3A相比，在图4C所示的HBT中，部分的通孔2041分布于发射区层204的边缘，进一步地减少通孔2041所占据发射区层204的面积，进而，进一步地提高HBT的功率增益。
在本申请实施例的一种实现中，通孔2041的尺寸可以是通孔的最小设计规则的1至3倍，其中，通孔的最小设计规则与HBT器件尺寸、HBT器件的制备工艺等有关，是HBT器件可实现本申请实施例中所允许的最小的通孔尺寸。通常，该通孔2041可以是方形，尺寸可以是长1-5um，宽1-5um；也可以是圆形或其他形状，本申请实施例不作限定。进一步地，发射区层204与基区层203的面积比例(S E/S B)不小于0.5，比如该比例为0.65、0.75、0.8、0.9等。
在本申请实施例的另一种实现中，上述HBT还可以包括绝缘层，如图5所示的HBT的剖面示意图是在图2B所示的HBT的基础上增加的绝缘层208和重布线层209，该绝缘层208可以填充发射区层204和基极206之间的间隙，以隔离发射区层204和基极206。可选地，该绝缘层208还可以填充集电极206与基区层203之间的间隙，以隔离集电极206与基区层203。
进一步地，该绝缘层208可以是覆盖集电区层202、基区层203和发射区层204，集电极205、基极206或发射极207可以贯穿该绝缘层208，集电极205背离集电区层202的端面、基极206背离基区层203的端面、发射极207背离发射区层204的端面和绝缘层208背离发射区204层的表面齐平。该绝缘层208上可以包括重布线层209，该重布线层209中的电路连接集电极205背离集电区层202的端面、基极206背离基区层203的端面、发射极207背离发射区层204的端面。
本申请实施例中，HBT可以是NPN型或PNP型晶体管。在集电区层202或子集电区层的材质可以是n型半导体的情况下，该HBT为NPN型晶体管，此时，基区层203或子基区层的材质为P型半导体，发射区层204或子发射区层的材质为N型半导体。反之，当在集电区层202和子集电区层的材质可以是P型半导体的情况下，该HBT为PNP型晶体 管，此时，基区层203的材质为N型半导体，发射区层204的材质为P型半导体。
应理解，在半导体材料如GaAs、Si、InP、SiC、GaN、AlGaAs、InGaP等内掺杂Si、S、Se、Te、Sn等掺杂剂，可以形成N型半导体；反之，掺杂C、Mg、Be、Zn等掺杂剂可以形成P性半导体。本申请实施例中HBT的集电区层202、基区层203和发射区层204的半导体材料可以相同，例如，对于HBT为NPN型晶体管来说，集电区层202由N型GaAs形成、基区层203由P型GaAs形成，发射区层204由N型GaAs形成；在另一种实现方式中，集电区层202、基区层203和发射区层204的半导体材料可以互不相同或部分不同，例如，对于HBT为NPN型晶体管来说，集电区层202由N型GaAs形成、基区层203由P型AlGaAs形成，发射区层204由N型InGaP形成。
集电极205、基极206或发射极207可以由金(Au)、铜(Cu)、钯(Pd)、铂(Pt)、银(Ag)、钛(Ti)等金属或金属的合金形成，也可以由其他的导电材料，例如，氧化铟锡(ITO)、石墨烯等形成，对此，本申请实施例不作限定。
可选地，绝缘层208的可以由SiN、SiC等无机绝缘材料形成，或由高分子聚合物或树脂，比如环氧树脂、聚乙烯、聚丙烯、聚烯烃、聚酰胺、聚亚氨酯等有机绝缘材料形成。
本申请实施例所述的HBT可以应用在功率放大电路中。该功率放大电路进一步可以搭载在便携式手机、平板电脑无线路由器、基站等具有通信功能的设备上，例如，手机上的功率放大电路用于对发送到基站的无线信号的功率进行放大。例如，功率放大电路对2G(2th-Generation mobile communication technology)信号、3G(3th-Generation mobile communication technology)信号、4G(4th-Generation mobile communication technology)信号、5G(5th-Generation mobile communication technology)信号、5G(5th-Generation mobile communication technology)信号等通信标准的信号的功率进行放大，也可以对其他的信号进行放大，对此，本申请实施例不作限定。
还应理解，可以根据HBT不同的应用场景的需求选择合适结构的HBT，对此，本申请实施例不作限定。
为制备上述HBT，本申请还提供一种HBT的制备方法，通过该方法能够较便捷的制得性能稳定，成本低的HBT。请参阅图6所示的HBT的制备方法流程图，请一并参阅图7-图15B所示的制造工序的示意图，该HBT的制备方法可以包括但不限于如下部分或全部步骤：
S02：提供一基板。
其中，基板201可以是硅片，也可以是由碳化硅、砷化镓(GaAs)或氮化镓(GaN)等材料形成。
S04：如图7所示，在基板201上依次形成集电区层202、基区层203和发射区层204。
其中，集电区层202、基区层203和发射区层204的形成方法为现有技术，本申请实施例不再赘述。集电区层202、基区层203和发射区层204的材质可以参见上述HBT的结构的实施例中相关描述，本申请实施例不再赘述。
S06：如图8A和8B所示，在发射区层204背离基区层203的表面形成发射极。其中，图8A为通过步骤S06形成的HBT的俯视示意图，图8B为图8A中HBT沿虚线所述位置 的剖面示意图。
具体地，可以通过镀膜工艺在发射区层204背离基区层203的表面形成第二导电层，进一步地，通过图案化该第二导电层，形成发射极204，以显露部分的发射区层204。
应理解，S06还可以通过其他工艺，如，丝印、3D打印等技术形成图案化的发射极，本身实施例不作限定。
S08：如图9A和9B所示，在发射区层204开设贯穿发射区层204的多个通孔2041，多个通孔2041间隔设置，以部分显露基区层203的第一表面2031。其中，图9A为通过步骤S08形成的HBT的俯视示意图，图9B为图9A中HBT沿虚线所述位置的剖面示意图。
S08可以通过图案化工艺在发射区层204开设贯穿发射区层204的多个通孔2041，具体可以包括在如图8A所述的结构上形成一层光刻胶，通过光罩曝光光刻胶，显影液显影光刻胶以去部分光刻胶，得到图案化的光刻胶，进而以图案化的光刻胶层为掩膜，刻蚀发射区层204，进而将光刻胶的图案复制到发射区层204，得到贯穿发射区层204的多个通孔2041。
可选地，通孔2041可以呈阵列分布，或者以其他方式分布，本申请实施例不作限定。
S10：在通孔2041显露的第一表面上形成基极206，其中，基极206与发射区层204相间隔。
应理解，该S10可以包括但不限于如下2种实现方式。
第一实现方式：
S102：如图10所示剖面示意图，在发射区层204背离基区层203的表面形成第一光刻胶层1001。其中，第一光刻胶层801填充多个通孔2041。
S104：如图11所示的剖面示意图，图案化第一光刻胶层1001，以在通孔2041内的第一光刻胶层1001上形成第一过孔1011，第一过孔1011显露基区层203背离集电区层202的表面，第一过孔1011的尺寸小于第一过孔1011所在通孔2041的尺寸。
具体的，通过光罩，部分曝光第一光刻胶层1001，进一步地，通过显影液显影第一光刻胶层1001即可得到如图11所示的结构。
S106：如图12所示的剖面示意图，在第一光刻胶层801上形成第一导电层1002，第一导电层1002填充第一过孔1011并连接基区层203。
S108：去除第一光刻胶层1001以及去除第一光刻胶层1001上的第一导电层1002，形成基极206，得到如图13A和图13B所示的结构，其中，图13A为通过步骤S108形成的HBT的俯视示意图，图13B为图13A中HBT沿虚线所述位置的剖面示意图。
S12：如图14A和图14B所示，去除基板201上的部分的基区层203、部分的发射区层204，以裸露部分集电区层202。其中，图14A为通过步骤S12形成的HBT的俯视示意图，图14B为图14A中HBT沿虚线所述位置的剖面示意图。
具体的，可以在如图13A所示的结构上形成第三光刻胶层，通过光罩曝光第三光刻胶层，显影液显影第三光刻胶层以去部分第三光刻胶层，得到图案化的第三光刻胶层，进而以图案化的第三光刻胶层为掩膜，刻蚀基区层203和集电区层202，以裸露部分集电区层202。
S14：如图15A和图15B所示，在裸露的集电区层202背离基板201的表面上形成集电极205。
具体的，可以在第三光刻胶层上形成第三导电层，进一步地，通过显影液去除第三光刻胶层以及设置于第三光刻胶层上的第三导电层，得到集电极205。
在本申请实施例的一种实现中，该方法还可以形成绝缘层，该绝缘层可以填充发射区层204和基极206之间的间隙，以隔离发射区层204和基极206。可选地，该绝缘层208还可以填充集电极206与基区层203之间的间隙，以隔离集电极206与基区层203。
进一步地，该方法还可以包括在绝缘层上形成重布线层，以使得重布线层209中的电路连接集电极205背离集电区层202的端面、基极206背离基区层203的端面、发射极207背离发射区层204的端面。
本申请实施例所述的HBT的制备方法得到的HBT通过在发射区层间隔设置多个通孔，该通孔占据发射区层更少的面积，也就是说，本申请实施例中间隔设置多个通孔损失的发射区层远远小于现有技术中沟槽所损失的发射区层，进而，使得更多的发射区层保留在基区层的第一表面2031上，增大了发射区层与基区层的面积比例(S E/S B)，进而，提高HBT的功率增益。
应该理解，在本发明各个实施例中，所述图案化即是指构图工艺，可包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影、剥离等工艺过程并利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
还应该理解，在本发明各个实施例中，蚀刻工艺包括干刻工艺和湿刻工艺。其中，干刻工艺是通过被刻蚀材料与等离子体中的粒子之间的化学反应、物理反应，使被刻蚀材料腐蚀去除的过程。干刻的方式包括等离子体刻蚀、反应离子刻蚀或电感耦合等离子体刻蚀等。湿刻工艺是通过化学刻蚀液和被刻蚀物质之间的化学反应将被刻蚀物质剥离下来的刻蚀方法。可根据本发明中所形成的结构选择相应的蚀刻工艺。
还应理解，本申请实施例中，各层材料的制备可以采用薄膜制备方法，包括但不限于磁控溅射镀膜、化学气相沉积、激光溅射沉积、旋涂法，热蒸发等，制备方法的具体选择与所制备的材料等有关，本领域技术人员可以根据需要选择合适的工艺形成本身实施例中各个薄膜结构，此处不再赘述。
本申请实施例还提供了一种放大电路，该放大电路包括如上述图2A-图5示的HBT或者通过上述HBT的制备方法得到的HBT。
本申请实施例还提供了一种芯片，该芯片可以是基带芯片或处理芯片，包括射频模块，其中，射频模块包括上述放大电路，以放大发送的信号的功率。
上述基带芯片或者射频模块，进一步地可以应用于集成电路设备中。请参阅图16，图16是本申请实施例提供的一种集成电路设备1600的结构示意图，该集成电路设备1600包括处理器161和射频模块166，其中，处理模块161和射频模块166可以集成在一个芯片中，也可以分别集成在处应用理芯片(AP)和基带芯片中，射频模块166中包括放大电路，放大电路包括本申请实施例提供的HBT或者包括本申请实施例提供的HBT制备方法制备得到的HBT，具体可参见上述HBT的结构实施例和制备方法的实施例中相关描述，本申 请实施例不再赘述。
在一种具体实现中，处理模块161可以集成有CPU、存储器等。可选地，该集成电路设备还可以包括电源管理模块162，用于对集成电路161进行供电。可选地，该集成电路设备还可以包括通信模块163、输入模块164和/或输出模块165等。其中，通信模块163用于实现集成电路设备与其他设备或互联网的通信连接；输入模块164用于实现用户将信息输入到集成电路设备，可以包括，触控面板、键盘、摄像头等；输出模块165用于实现集成电路设备向用户输出信息，可以包括显示面板等。应理解，电源管理模块162、通信模块163、输入模块164和/或输出模块165不是集成电路设备必须的组成部件；电源管理模块162、通信模块163、输入模块164和/或输出模块165也可以集成在集成电路161中，或单独设置，耦合至集成电路161，本申请实施例不做限定。
本申请实施例中集成电路设备可以是智能手机、平板电脑、个人数字助理、电子书、计算机、基站、智能手环、虚拟现实(VirtualReality，VR)设备、增强现实(Augmented Reality，简称AR)设备、数字电视、机顶盒、无线路由器等包括功率放大电路的设备。应理解，这里所列举的电子设备仅为示例性说明，本申请对此不作限定。
以上不同实施例之间可以交叉引用。例如当一个实施例对某一方面的技术细节做了简略描述，可进一步参考其他实施例的介绍。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，上述列举的芯片封装方法的各实施例，可以通过机器人或者数控加工方式来执行，用于执行芯片封装方法的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述芯片封装方法。
还应理解，本申请实施例中使用“第一”、“第二”等术语来描述各种元素，但这些元素不应受到这样写术语的限制，“第一”、“第二”进用于区分一个元素和另一个元素。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种异质结双极型晶体管，其特征在于，包括：基板，依次层叠在所述基板上的集电区层、基区层和发射区层，其中，所述发射区层开设贯穿所述发射区层的多个通孔，所述多个通孔间隔设置，所述通孔显露部分第一表面，所述第一表面为所述基区层上背对所述集电区层的表面；在所述通孔显露的所述第一表面上设有基极，所述基极与发射区层相间隔。
  2. 如权利要求1所述的异质结双极型晶体管，其特征在于，所述多个通孔呈阵列分布。
  3. 如权利要求1或2所述的异质结双极型晶体管，其特征在于，所述发射区层与所述基区层的面积比例不小于0.5。
  4. 如权利要求1-3任一项所述的异质结双极型晶体管，其特征在于，所述发射区层和所述基极之间还包括绝缘层。
  5. 如权利要求1-4任一项所述的异质结双极型晶体管，其特征在于，所述异质结双极型晶体管还包括：集电极和发射极，其中，所述集电极与所述基区层间隔设置于所述集电区层背对所述基板的表面；所述发射极设置于所述发射区层背对所述基区层的表面。
  6. 一种放大电路，其特征在于，所述放大电路包括如权利要求1-5任一项所述的异质结双极型晶体管。
  7. 一种异质结双极型晶体管的制备方法，其特征在于，包括：
    提供一基板；
    在所述基板上依次形成集电区层、基区层和发射区层；
    在所述发射区层开设贯穿所述发射区层的多个通孔，所述多个通孔间隔设置，以部分显露所述基区层的第一表面；
    在所述通孔显露的第一表面上形成基极，所述基极与发射区层相间隔。
  8. 如权利要求7所述的制备方法，其特征在于，所述多个通孔呈阵列分布。
  9. 如权利要求7或8所述的制备方法，其特征在于，所述在所述通孔显露的第一表面上形成基极，所述基极与发射区层相间隔，具体包括：
    在所述发射区层上形成第一光刻胶层；
    图案化所述第一光刻胶层，以在所述通孔内的第一光刻胶层上形成第一过孔，所述第一过孔显露所述基区层背离所述集电区层的表面，所述第一过孔的尺寸小于所述第一过孔所在通孔的尺寸；
    在所述第一光刻胶层上形成第一导电层，所述第一导电层填充所述第一过孔并连接所述基区层；
    去除所述第一光刻胶层以及去除所述第一光刻胶层上的所述第一导电层，形成基极。
  10. 如权利要求7-9任一项所述的制备方法，其特征在于，所述在所述发射区层上形成第一绝缘层之前，所述方法还包括：
    在所述发射区层背离所述基区层的表面形成第二导电层；
    图案化所述第二导电层，形成发射极。
  11. 如权利要求7-10任一项所述的制备方法，其特征在于，所述去除所述第一绝缘层上的所述第一导电层，形成基极之后，所述方法还包括：
    去除所述基板上的部分的所述基区层、部分的发射区层，以裸露部分所述集电区层；
    在裸露的所述集电区层背离所述基板的表面上形成集电极。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044560A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 超高频硅锗异质结双极晶体管
CN102738178A (zh) * 2012-07-16 2012-10-17 西安电子科技大学 一种基于自对准工艺的双多晶SOI SiGe HBT集成器件及制备方法
WO2019112741A1 (en) * 2017-12-07 2019-06-13 Qualcomm Incorporated Emitter-base mesh structure in heterojunction bipolar transistors for rf applications

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044560A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 超高频硅锗异质结双极晶体管
CN102738178A (zh) * 2012-07-16 2012-10-17 西安电子科技大学 一种基于自对准工艺的双多晶SOI SiGe HBT集成器件及制备方法
WO2019112741A1 (en) * 2017-12-07 2019-06-13 Qualcomm Incorporated Emitter-base mesh structure in heterojunction bipolar transistors for rf applications

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