WO2020253398A1

WO2020253398A1 - Pixel circuit and drive method therefor, display panel, and display apparatus

Info

Publication number: WO2020253398A1
Application number: PCT/CN2020/087812
Authority: WO
Inventors: 王峥
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2019-06-20
Filing date: 2020-04-29
Publication date: 2020-12-24
Also published as: CN110246459A; CN110246459B

Abstract

A pixel circuit and a drive method therefor, a display panel, and a display apparatus. The pixel circuit comprises a first drive circuit and a second drive circuit. The first drive circuit is configured to, according to a data signal, generate a first drive current that drives a first light-emitting element to emit light, and the second drive circuit is configured to, according to a control signal, generate a second drive current that drives a second light-emitting element to emit light. The control signal is obtained according to the data signal and is different from the data signal.

Description

Pixel circuit and driving method thereof, display panel and display device

This application claims the priority of Chinese Patent Application No. 201910535904.7 filed on June 20, 2019, and the contents of the above-mentioned Chinese patent application are quoted here in full as a part of this application.

Technical field

The embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display panel and a display device.

Background technique

Organic Light-Emitting Diode (OLED) display panel has thin thickness, light weight, wide viewing angle, active light emission, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, and operating temperature The advantages of wide range, simple production process, high luminous efficiency and flexible display are becoming more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.

Summary of the invention

At least one embodiment of the present disclosure provides a pixel circuit including a first driving circuit and a second driving circuit, wherein the first driving circuit is configured to generate a first driving current for driving a first light-emitting element to emit light according to a data signal, so The second driving circuit is configured to generate a second driving current for driving the second light-emitting element to emit light according to a control signal, and the control signal is obtained according to the data signal and is different from the data signal.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes a voltage adjustment circuit, wherein the voltage adjustment circuit is configured to generate the control signal according to the data signal.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the voltage regulating circuit includes a first switching transistor, and the gate and the first pole of the first switching transistor are both connected to the control terminal of the first driving circuit The second pole of the first switch transistor is connected to the control terminal of the second driving circuit to form a diode structure.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the voltage regulating circuit includes a diode, the first pole of the diode is connected to the control terminal of the first driving circuit, and the second pole of the diode is connected to the control terminal of the first driving circuit. The control terminal of the second driving circuit is connected.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes the first light-emitting element, wherein a first pole of the first light-emitting element is connected to a first power terminal to receive a first power voltage, and The driving circuit includes a first driving transistor, the gate of the first driving transistor serves as the control terminal of the first driving circuit, and the first electrode of the first driving transistor is connected to the second electrode of the first light-emitting element The second pole of the first driving transistor is connected to the second power terminal to receive the second power voltage.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes the second light-emitting element, wherein the first pole of the second light-emitting element is connected to the first power terminal to receive the first power voltage, The second driving circuit includes a second driving transistor, the gate of the second driving transistor is used as a control terminal of the second driving circuit, and the first electrode of the second driving transistor is connected to the second light emitting element. The second electrode is connected, and the second electrode of the second driving transistor is connected to the second power terminal to receive the second power voltage.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes an input circuit, wherein the input circuit is configured to apply the data signal to the control terminal of the first driving circuit in response to the first scan signal.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the input circuit includes a second switch transistor, and the gate of the second switch transistor is connected to the first scan signal terminal to receive the first scan signal, so The first pole of the second switch transistor is connected to the data signal terminal to receive the data signal, and the second pole of the first switch transistor is connected to the control terminal of the first driving circuit.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes a first storage circuit and a first reset circuit, wherein the first storage circuit is configured to store the data signal, and the first reset circuit is configured to respond to The second scan signal resets the control terminal of the first driving circuit.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the first storage circuit includes a first storage capacitor, the first reset circuit includes a third switch transistor, and the first terminal of the first storage capacitor is connected to the first storage capacitor. The control end of the first drive circuit is coupled, the second end of the first storage capacitor is coupled to the control end of the second drive circuit, and the gate of the third switch transistor is connected to the second scan signal end To receive the second scan signal, the first pole of the third switch transistor is connected to the control terminal of the first drive circuit, and the second pole of the third switch transistor is controlled by the second drive circuit. Terminal connection; or, the first terminal of the first storage capacitor is coupled to the control terminal of the first drive circuit, the second terminal of the first storage capacitor is connected to the second power terminal, and the third switch The gate of the transistor is connected to the second scan signal terminal to receive the second scan signal, the first pole of the third switch transistor is connected to the control terminal of the first drive circuit, and the second terminal of the third switch transistor The two poles are connected with the second power terminal.

For example, the pixel circuit provided by some embodiments of the present disclosure further includes a second storage circuit and a second reset circuit, wherein the second storage circuit is configured to store the control signal, and the second reset circuit is configured to respond to The second scan signal resets the control terminal of the second driving circuit.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the second storage circuit includes a second storage capacitor, the second reset circuit includes a fourth switch transistor, and the first terminal of the second storage capacitor is connected to the second storage capacitor. The control terminal of the second driving circuit is coupled, the second terminal of the second storage capacitor is connected to the second power terminal, and the gate of the fourth switch transistor is connected to the second scanning signal terminal to receive the second For scanning signals, the first pole of the fourth switch transistor is connected to the control terminal of the second drive circuit, and the second pole of the fourth switch transistor is connected to the second power terminal.

For example, in the pixel circuit provided by some embodiments of the present disclosure, the level range of the data signal includes a first range and a second range, and when the level of the data signal is in the first range, The first drive current is greater than zero, the second drive current is equal to zero, and when the level of the data signal is in the second range, the first drive current and the second drive current are both greater than zero .

For example, in the pixel circuit provided by some embodiments of the present disclosure, the light-emitting colors of the first light-emitting element and the second light-emitting element are the same, and the area of the light-emitting region of the first light-emitting element is smaller than that of the second light-emitting element The area of the light-emitting area.

At least one embodiment of the present disclosure further provides a display panel including a plurality of sub-pixels arranged in an array, wherein each of the sub-pixels includes the pixel circuit provided in any embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a display device including the display panel provided in any embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a driving method corresponding to the pixel circuit provided in any embodiment of the present disclosure, including: providing the pixel circuit with the data signal so that the first light-emitting element and the The second light-emitting element collectively displays the gray scale to be displayed corresponding to the data signal.

For example, in the driving method provided by some embodiments of the present disclosure, the gray scale range of the gray scale to be displayed includes a first gray scale range and a second gray scale range, and the level range of the data signal includes the first range And a second range; when the gray scale to be displayed is within the first gray scale range, the pixel circuit is provided with the data signal in the first range, so that the first The light-emitting element emits light and the second light-emitting element does not emit light; when the gray scale to be displayed is within the second gray scale range, the pixel circuit is provided with the pixel circuit within the second range. The data signal causes both the first light-emitting element and the second light-emitting element to emit light.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the drawings of the embodiments. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

FIG. 1A is a schematic diagram of a 2T1C pixel circuit;

FIG. 1B is a schematic diagram of another 2T1C pixel circuit;

2 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

3 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

4 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 2;

FIG. 5 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 3;

6 is a schematic diagram of a circuit structure of another specific implementation example of the pixel circuit shown in FIG. 2;

FIG. 7 is a schematic diagram of a circuit structure of another specific implementation example of the pixel circuit shown in FIG. 3;

FIG. 8 is a signal timing diagram of a pixel circuit driving method provided by at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure; and

FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "a", "one" or "the" do not mean quantity limitation, but mean that there is at least one. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known parts (components) may be omitted. When any part (element) of the embodiment of the present disclosure appears in more than one drawing, the part (element) is represented by the same or similar reference number in each drawing.

The pixel circuit in the OLED display panel generally adopts a matrix driving method, and is divided into active matrix (AM) driving and passive matrix (PM) driving according to whether switching components are introduced in each sub-pixel. For example, AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each sub-pixel. Through the drive control of the thin film transistors and storage capacitors, the current flowing through the OLED can be controlled, so that the OLED can be displayed according to the Grayscale glow. Therefore, AMOLED requires small driving current, low power consumption, and longer life, which can meet the needs of large-scale display with high resolution and multiple grayscale. At the same time, AMOLED has obvious advantages in terms of viewing angle, color restoration, power consumption, and response time, and is suitable for display devices with high information content and high resolution.

The basic pixel circuit used in the AMOLED display panel is usually a 2T1C pixel circuit, that is, two Thin-Film Transistors (TFT) and a storage capacitor Cs are used to realize the basic function of driving the OLED to emit light. Figures 1A and 1B respectively show schematic diagrams of two 2T1C pixel circuits.

As shown in FIG. 1A, a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs. For example, the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data signal line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected To the first voltage terminal to receive the first voltage Vdd (high voltage), the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to The source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).

The driving method of the 2T1C pixel circuit is to control the brightness (gray scale) of the sub-pixels via two TFTs and a storage capacitor Cs. When the scan signal Scan1 is applied through the scan line to turn on the switching transistor T0, the data signal Vdata input by the data driving circuit through the data signal line will charge the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs And the stored data signal Vdata controls the conduction degree of the driving transistor N0, thereby controlling the current flowing through the driving transistor N0 to drive the OLED to emit light, that is, the current determines the gray scale of the sub-pixel to emit light. In the 2T1C pixel circuit shown in FIG. 1A, the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.

As shown in FIG. 1B, another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode is slightly changed, and the driving transistor N0 is an N-type transistor. The changes of the pixel circuit of FIG. 1B relative to FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0. The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage). One end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the second voltage terminal. The working mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and will not be repeated here.

In addition, for the pixel circuit shown in FIGS. 1A and 1B, the switching transistor T0 is not limited to an N-type transistor, but may also be a P-type transistor, so that the polarity of the scan signal Scan1 that is controlled to be turned on or off is changed accordingly. can.

In practical applications, based on the aforementioned 2T1C pixel circuit, the pixel circuit may also include a compensation transistor, a reset transistor, a sensing transistor, etc. to correspondingly have a compensation function, a reset function, a sensing function, etc.

An AMOLED display panel usually includes a plurality of sub-pixels arranged in an array, and each sub-pixel may include, for example, the aforementioned pixel circuit and OLED. The pixel circuit is used to generate and control the driving current flowing through the OLED to drive the OLED to emit light, so as to make the AMOLED display panel display. For example, each sub-pixel usually includes only one OLED, and correspondingly, the pixel circuit usually includes only one driving transistor (refer to FIG. 1A and FIG. 1B). When the AMOLED display panel displays, the gray scale displayed by each sub-pixel is determined by the intensity of the driving current I (that is, the current flowing through the driving transistor to drive the OLED to emit light). The driving current I generated by the pixel circuit in the sub-pixel is proportional to (Vgs-Vth) ² , where Vgs is the voltage difference between the gate and source of the driving transistor, and Vth is the threshold voltage of the driving transistor.

In the research, the inventor of the present application noticed that when there is electrical noise in the pixel circuit (for example, the fluctuation of the data signal Vdata, etc.), the voltage difference actually loaded between the gate and the source of the driving transistor deviates from the expected Vgs If the deviation (that is, the fluctuation of Vgs) is d(Vgs), correspondingly, the actual driving current will deviate from the expected driving current I. If the deviation (that is, the fluctuation of the driving current I) is dI, it can be passed Simple mathematical derivation results in the following formula (1):

The formula (1) shows that under the condition that the fluctuation of Vgs caused by electrical noise (ie d(Vgs)) remains unchanged, the driving current I is larger when displaying high gray scale, that is, |Vgs-Vth| is larger, thus |dI/I| is small, that is, the driving current is less affected; while in low grayscale display, the driving current I is small, that is, |Vgs-Vth| is small, so |dI/I| is large, that is to drive The current is greatly affected. Therefore, during low grayscale display, the fluctuation of Vgs caused by electrical noise may cause the actual displayed grayscale to deviate from the expected displayed grayscale, that is, the display is not accurate, thereby affecting the display effect.

At least one embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a first driving circuit and a second driving circuit. The first driving circuit is configured to generate a first driving current for driving the first light-emitting element to emit light according to the data signal, and the second driving circuit is configured to generate a second driving current for driving the second light-emitting element to emit light according to the control signal. The control signal is derived from the data signal and is different from the data signal.

Some embodiments of the present disclosure also provide a driving method, a display panel, and a display device corresponding to the aforementioned pixel circuit.

The pixel circuit provided by the embodiment of the present disclosure can selectively make the second light-emitting element emit light or not according to the difference of the data signal, so that the second light-emitting element cooperates with the first light-emitting element to jointly display the gray scale corresponding to the data signal. Therefore, when the display panel and the display device including the pixel circuit perform low-gray-scale display, the influence of electrical noise on the display screen can be reduced, thereby improving the display effect.

Hereinafter, some embodiments and examples of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure. For example, the pixel circuit 100 may be used in sub-pixels of an AMOLED display panel, an inorganic light emitting diode display panel, and a Quantum Dot Light Emitting Diode (QLED) display panel. For example, as shown in FIG. 2, the pixel circuit 100 includes a first driving circuit 110, a second driving circuit 120, a first light-emitting element 210 and a second light-emitting element 220. That is, the first driving circuit 110, the second driving circuit 120, the first light emitting element 210, and the second light emitting element 220 are located in the same sub-pixel.

For example, as shown in FIG. 2, the first driving circuit 110 includes a control terminal 111, a first terminal 112, and a second terminal 113, and is configured to generate a first driving current for driving the first light-emitting element 210 to emit light according to a data signal. For example, in some examples, in the light-emitting phase, the first driving circuit 110 may provide the first light-emitting element 210 according to the gray scale to be displayed by the sub-pixels including the pixel circuit 100 (different gray scales correspond to different data signals) The first driving current drives the first light-emitting element 210 to emit light.

For example, the gray scale range of the gray scale to be displayed includes a first gray scale range and a second gray scale range. For example, in some examples, when the gray scale to be displayed is within the first gray scale range, the first light emitting element displays the gray scale to be displayed, that is, the luminance of the first light emitting element 210 meets the requirements of the gray scale to be displayed ; When the gray scale to be displayed is in the second gray scale range, the luminous brightness of the first light emitting element 210 is lower than the requirement of the gray scale to be displayed, and the second light emitting element 220 also emits light, so that the first light emitting element 210 Together with the second light emitting element 220, the gray scale to be displayed is displayed, that is, the superposition of the luminous brightness of the first light emitting element 210 and the second light emitting element 220 meets the requirements of the gray scale to be displayed.

For example, as shown in FIG. 2, the second driving circuit 120 includes a control terminal 121, a first terminal 122, and a second terminal 123, and is configured to generate a second driving current for driving the second light-emitting element 220 to emit light according to a control signal. For example, the control signal can be derived from the data signal and is different from the data signal. For example, in some examples, in the light-emitting stage, when the gray scale to be displayed is within the first gray scale range, the control signal obtained according to the data signal is not sufficient to enable the second driving circuit 120 to provide the second light-emitting element 220 with the second The driving current (that is, the second driving current generated is zero), so that the second light-emitting element 220 does not emit light; when the gray scale to be displayed is within the second gray scale range, the control signal obtained according to the data signal can enable the second driving The circuit 120 provides a second driving current to the second light-emitting element 220 to drive the second light-emitting element 220 to emit light. At this time, the light-emitting brightness of the second light-emitting element 220 and the light-emitting brightness of the first light-emitting element 210 are superimposed (that is, two The sum of the luminous brightness of the individual) meets the requirements of the gray scale to be displayed.

The grayscale range depends on the grayscale signal, and thus, the grayscale range can have various forms. For example, the grayscale signal can be 8 bits, and the corresponding grayscale range is [0,255]; or, the grayscale signal can be 12 bits, and the corresponding grayscale range is [0,4095], etc. Hereinafter, the division of the gray scale range is exemplified by taking the gray scale range of [0,255] as an example, but it should not be regarded as a limitation of the present disclosure. For example, in some examples, the first gray scale range is [0, n], and the second gray scale range is (n, 255], where 0<n<255 and n is an integer, so that the first gray scale range can be Defined as a low gray scale range, the second gray scale range can be defined as a high gray scale range. It should be noted that n is the dividing point between the first gray scale range and the second gray scale range, which can be implemented according to actual application needs The setting is subject to a good display effect, which is not limited in the embodiment of the present disclosure. For example, the value of n can be any suitable value, such as 10, 20, 32, 45, 63 and so on.

For example, the first light-emitting element 210 and the second light-emitting element 220 may use the same type of light-emitting diodes, for example, organic light-emitting diodes (OLED), quantum dot light-emitting diodes (QLED), inorganic light-emitting diodes, etc. may be used. The embodiments of the present disclosure include But it is not limited to this. For example, the first light-emitting element 210 and the second light-emitting element 220 may be composed of the same or different materials, and may be simultaneously formed on the array substrate of the display panel through the same semiconductor process steps. The embodiments of the present disclosure include but are not limited to this. For example, the area of the light emitting area of the first light emitting element 210 is smaller than the area of the light emitting area of the second light emitting element 220.

For example, in an embodiment of the present disclosure, when a low gray scale is displayed, only the first light emitting element 210 is made to emit light, and the second light emitting element 220 does not emit light. Since the area of the light-emitting area of the first light-emitting element 210 is small, compared with the usual pixel circuit that only contains one light-emitting element, in order to achieve the required gray scale, (in the case where the first driving circuit 110 is implemented as an N-type transistor ) The voltage value of the data signal provided to the first light-emitting element 210 is relatively large, so that the difference between the voltage of the data signal at this time and the voltage of the data signal corresponding to the zero gray scale is relatively large, so that the pixel circuit 100 is affected by the driving current The control power is stronger, the anti-interference ability is stronger, and the gray scale display is more accurate. In the case where the first driving circuit 110 is implemented as a P-type transistor, when a low gray scale is displayed, the difference between the voltage of the data signal provided to the first light-emitting element 210 and the voltage of the data signal corresponding to zero gray scale is also large. Therefore, the pixel circuit 100 can also have stronger control over the driving current, stronger anti-interference ability, and more accurate gray scale display.

For example, as shown in FIG. 2, the pixel circuit 100 may further include a voltage adjustment circuit 130. The voltage regulating circuit 130 is configured to generate a control signal according to the data signal. For example, in some examples, as shown in FIG. 2, the voltage regulating circuit 130 is connected to the control terminal 111 of the first driving circuit 110 and the control terminal 121 of the second driving circuit 120 respectively. For example, in some examples, in the data writing phase, the voltage adjustment circuit 130 may generate a control signal according to the data signal received by the control terminal 111 of the first driving circuit 110, and apply the generated control signal to the second driving circuit 120. The control terminal 121 causes the second driving circuit 120 to generate a second driving current for driving the second light-emitting element 220 to emit light according to the control signal during the subsequent light-emitting stage. For example, in some examples, the absolute value of the voltage value of the control signal generated by the voltage regulation circuit 130 is less than the absolute value of the voltage value of the data signal, for example, the voltage value of the control signal and the voltage value of the data signal are both positive and the value of the control signal The voltage value is less than the voltage value of the data signal.

For example, as shown in FIG. 2, the pixel circuit 100 may further include an input circuit 140. The input circuit 140 is configured to apply a data signal to the control terminal 111 of the first driving circuit 110 in response to the first scan signal SN1. For example, in some examples, in the data writing phase, the input circuit 140 is turned on in response to the first scan signal SN1, so as to apply the data signal provided by the data signal terminal DATA to the control terminal 111 of the first driving circuit 110 to In the subsequent light-emitting phase, the first driving circuit 110 generates a first driving current for driving the first light-emitting element 210 to emit light according to the data signal.

For example, as shown in FIG. 2, the pixel circuit 100 may further include a first storage circuit 150 and a first reset circuit 160. The first storage circuit 150 is configured to store a data signal, and the first reset circuit 160 is configured to reset the control terminal 111 of the first driving circuit 110 in response to the second scan signal SN2. For example, in some examples, as shown in FIG. 2, the first storage circuit 150 is connected to the control terminal 111 of the first driving circuit 110, so that the data received by the control terminal 111 of the first driving circuit 110 can be stored during the data writing phase. Data signal. For example, in some examples, as shown in FIG. 2, the first reset circuit 160 is connected to the control terminal 111 of the first driving circuit 110, so that the first driving circuit 110 can be controlled by the second scan signal SN2 in the reset phase. The control terminal 111 and the first storage circuit 150 are reset.

For example, as shown in FIG. 2, the pixel circuit 100 may further include a second storage circuit 170 and a second reset circuit 180. The second storage circuit 170 is configured to store the control signal, and the second reset circuit 180 is configured to reset the control terminal 121 of the second driving circuit 120 in response to the second scan signal SN2. For example, in some examples, as shown in FIG. 2, the second storage circuit 170 is connected to the control terminal 121 of the second drive circuit 120, so that the data received by the control terminal 121 of the second drive circuit 120 can be stored in the data writing stage. control signal. For example, in some examples, as shown in FIG. 2, the second reset circuit 180 is connected to the control terminal 121 of the second drive circuit 120, so that the second scan signal SN2 can respond to the second scan signal SN2 in the reset phase. The control terminal 121 and the second storage circuit 170 are reset.

It should be noted that the first scan signal SN1 and the second scan signal SN2 described in the embodiments of the present disclosure are used to distinguish two scan control signals with different timings. For example, as described below, in an exemplary display device, when the pixel circuits 100 are arranged in an array, the first scan signal SN1 may be a scan control signal for controlling the input circuit 140 in the row of pixel circuits 100; The second scan signal SN2 may be a scan control signal for controlling the input circuit 140 in the pixel circuit 100 of the previous row. At the same time, the second scan signal SN2 also controls the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 of the current row.

FIG. 3 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure. The pixel circuit shown in FIG. 3 is different from the pixel circuit shown in FIG. 2 in that the connection manner of the first storage circuit 150 and the first reset circuit 160 is different. It should be noted that other circuit structures of the pixel circuit shown in FIG. 3 are basically the same as those of the pixel circuit shown in FIG. 2, and the repetitions are not repeated here. Hereinafter, only the differences between the pixel circuit shown in FIG. 3 and the pixel circuit shown in FIG. 2 will be described in comparison.

For example, in the pixel circuit 100 shown in FIG. 2, one end of the first storage circuit 150 is connected to the control terminal 111 of the first drive circuit 110, and the other end of the first storage circuit 150 is connected to the second power terminal ELVSS (used to provide The second power supply voltage VSS) is connected so that the voltage of the other end of the first storage circuit 150 is maintained at the second power supply voltage VSS. For example, in the pixel circuit 100 shown in FIG. 3, one end of the first storage circuit 150 is connected to the control terminal 111 of the first drive circuit 110, and the other end of the first storage circuit 150 is connected to the control terminal 121 of the second drive circuit 120. Connected so that the voltage at the other end of the first storage circuit 150 is consistent with the voltage at the control end 121 of the second drive circuit 120. It should be noted that although the connection modes of the first storage circuit 150 in the pixel circuit 100 shown in FIGS. 2 and 3 are different, it does not affect the first storage circuit 150 to realize its function of storing data signals, and thus does not affect The pixel circuit 100 works normally.

For example, in the pixel circuit 100 shown in FIG. 2, the first reset circuit 160 is connected to the second scan signal terminal (used to provide the second scan signal SN2), the control terminal 111 of the first drive circuit 110, and the second power terminal respectively. ELVSS (the second power supply voltage VSS can be used to reset the control terminal 111 of the first drive circuit 110) connection, so that the control terminal 111 and the first drive circuit 110 can be directly connected to the control terminal 111 and the first drive circuit 110 in the reset phase in response to the second scan signal SN2 A storage circuit 150 is reset. For example, in the pixel circuit 100 shown in FIG. 3, the first reset circuit 160 is connected to the second scan signal terminal, the control terminal 111 of the first drive circuit 110, and the control terminal 121 of the second drive circuit 120, respectively. Phase, the second reset circuit 180 is turned on (the second reset circuit 180 resets the control terminal 121 of the second drive circuit 120 and the second storage circuit 170), so that the first reset circuit 160 can respond to the second The scan signal SN2 indirectly resets the control terminal 111 of the first driving circuit 110 and the first storage circuit 150, that is, the reset operation of the first reset circuit 160 can be realized only when the second reset circuit 180 is turned on. It should be noted that although the connection of the first reset circuit 160 in the pixel circuit 100 shown in FIG. 2 and FIG. 3 is different, it does not affect the first reset circuit 160 to realize its connection to the first driving circuit 110 and the first storage. The circuit 150 performs the function of a reset operation, so that the normal operation of the pixel circuit 100 is not affected.

It should be understood that the connection manner of the first storage circuit 150 and the first reset circuit 160 may also adopt more other forms. For example, in the pixel circuits provided by some embodiments of the present disclosure, the first storage circuit 150 may adopt 2, and the first reset circuit 160 may adopt the connection shown in FIG. 3; alternatively, the first storage circuit 150 may adopt the connection shown in FIG. 3, and the first reset circuit 160 may adopt the connection shown in FIG. The connection method shown etc. It should also be understood that the second storage circuit 170 and the second reset circuit 180 may also have other connection methods, as long as they can achieve their own necessary functions and do not affect the normal operation of the pixel circuit 100.

It should be noted that in practical applications, on the basis of the above-mentioned pixel circuit 100, the pixel circuit provided by the embodiment of the present disclosure may also include a compensation circuit, a sensing circuit, etc., to correspondingly have a compensation function, a sensing function, etc. The embodiment of the present disclosure does not limit this.

4 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 2. As shown in FIG. 4, the pixel circuit 200 includes: a first driving transistor M1, a second driving transistor M2, first to fourth switching transistors T1, T2, T3, T4, a first storage capacitor Cs1, a second storage capacitor Cs2 , And the first light emitting element L1 and the second light emitting element L2. For example, the first light emitting element L1 is the aforementioned first light emitting element 210, and the second light emitting element L2 is the aforementioned second light emitting element 220.

For example, the first light-emitting element 210 and the second light-emitting element 220 may be located in the same sub-pixel. For example, the first light-emitting element 210 and the second light-emitting element 220 may use the same type of light-emitting diodes, for example, organic light-emitting diodes (OLED), quantum dot light-emitting diodes (QLED), inorganic light-emitting diodes, etc. may be used. The embodiments of the present disclosure include But it is not limited to this. For example, the first light-emitting element 210 and the second light-emitting element 220 may be made of the same material, and may also be simultaneously formed on the array substrate of the display panel through the same semiconductor process step. The embodiments of the present disclosure include but are not limited thereto. For example, the light-emitting colors of the first light-emitting element 210 and the second light-emitting element 220 are the same. For example, the area of the light emitting area of the first light emitting element 210 is smaller than the area of the light emitting area of the second light emitting element 220.

In the following embodiments, the first light-emitting element 210 and the second light-emitting element 220 adopt OLEDs as an example for description, and will not be repeated. For example, the OLED can be of various types, such as top-emission, bottom-emission, etc., and can emit red light, green light, blue light, or white light, which is not limited by the embodiments of the present disclosure. In addition, it should be noted that the following embodiments also take each transistor as an N-type transistor as an example for description, but this does not constitute a limitation to the embodiments of the present disclosure.

For example, as shown in FIG. 4, the first driving circuit 110 may be implemented as a first driving transistor M1. For example, as shown in FIG. 4, the first pole (eg, anode) of the first light-emitting element L1 (ie, the first light-emitting element 210) is connected to the first power supply terminal ELVDD to receive the first power supply voltage VDD; the first driving transistor M1 The gate of the first driving circuit 110 is connected to the first node P1 as the control terminal 111, and the first electrode of the first driving transistor M1 is used as the first terminal 112 of the first driving circuit 110 and the second electrode of the first light-emitting element L1 (For example, the cathode) is connected, and the second electrode of the first driving transistor M1 is connected as the second terminal 113 of the first driving circuit 110 and the second power terminal ELVSS to receive the second power voltage VSS. For example, the first power supply voltage VDD may be a driving voltage, such as a high voltage. For example, the second power supply voltage VSS may be a low voltage, for example, the second power supply terminal ELVSS may be grounded (for example, connected to a common ground), so that the second power supply voltage VSS may be a zero voltage.

For example, as shown in FIG. 4, the second driving circuit 120 may be implemented as a second driving transistor M2. For example, as shown in FIG. 4, the first pole (eg, anode) of the second light-emitting element L2 (ie, the second light-emitting element 220) is connected to the first power terminal ELVDD to receive the first power voltage VDD; the second driving transistor M2 The gate of the second driving circuit 120 is connected to the second node P2 as the control terminal 121, and the first electrode of the second driving transistor M2 is used as the first terminal 122 of the second driving circuit 120 and the second electrode of the second light emitting element L2. (For example, the cathode) is connected, and the second electrode of the second driving transistor M2 is connected as the second terminal 123 of the second driving circuit 120 and the second power terminal ELVSS to receive the second power voltage VSS.

For example, the first driving transistor M1 and the second driving transistor M2 may be made of the same material, and may also be formed on the array substrate of the display panel synchronously through the same semiconductor process steps. The embodiments of the present disclosure include but are not limited to this. For example, the threshold voltage Vth1 of the first driving transistor M1 and the threshold voltage Vth2 of the second driving transistor M2 may be the same or different. For example, in some examples, the threshold voltage Vth1 of the first driving transistor M1 may be less than or equal to the threshold voltage Vth2 of the second driving transistor M2.

For example, as shown in FIG. 4, the voltage regulating circuit 130 may be implemented as a first switching transistor T1. For example, as shown in FIG. 4, the gate and the first pole of the first switching transistor T1 are both connected to the first node P1, so as to be connected to the gate of the first driving transistor M1 (that is, the control terminal 111 of the first driving circuit 110) Connected; the second pole of the first switching transistor T1 is connected to the second node P2, thereby connecting with the gate of the second driving transistor M2 (ie, the control terminal 121 of the second driving circuit 120). Thus, the first switching transistor T1 forms a diode structure, and its turn-on voltage drop is the threshold voltage Vtht1 of the first switching transistor T1. For example, in some examples, in the data writing phase, the first switching transistor T1 may compare the magnitude of the data signal Vdata and Vtht1 received at the first node P1 (ie, the gate of the first driving transistor M1), and The control signal Vctrl is generated at the second node P2 and provided to the gate of the second driving transistor M2. For example, in some examples, Vdata>Vctrl>0.

For example, in some examples, when Vdata≤Vtht1, the first switching transistor T1 is turned off, and the control signal Vctrl cannot be generated according to the data signal Vdata (it can also be considered that the generated control signal is Vctrl=0). At this time, the second driving transistor The voltage of the gate of M2 is maintained at, for example, a low voltage during the reset phase (for example, the ground voltage, that is, zero voltage); the first driving transistor M1 can generate a first driving current according to the data signal Vdata to make the first light-emitting element L1 emit light. The second driving transistor M2 does not generate the second driving current (ie, the second driving current is zero), so the second light-emitting element L2 does not emit light; in this case, the first light-emitting element L1 displays the gray scale to be displayed. When Vtht1<Vdata≤Vtht1+Vth2, the first switching transistor T1 is turned on, and the generated control signal is Vctrl=Vdata-Vtht1, where Vctrl≤Vth2, at this time, the voltage of the gate of the second driving transistor M2 is Vctrl, The second driving transistor M2 is turned off; the first driving transistor M1 can generate a first driving current according to the data signal Vdata to make the first light-emitting element L1 emit light, and the second driving transistor M2 does not generate a second driving current (that is, the second driving current is zero ), so that the second light-emitting element L2 does not emit light; in this case, the first light-emitting element L1 displays the gray scale to be displayed. When Vdata>Vtht1+Vth2, the first switching transistor T1 is turned on, and the generated control signal is Vctrl=Vdata-Vtht1, where Vctrl>Vth2, at this time, the voltage of the gate of the second driving transistor M2 is Vctrl, and the second The driving transistor M2 is turned on; the first driving transistor M1 can generate a first driving current according to the data signal Vdata to make the first light-emitting element L1 emit light, and the second driving transistor M2 can generate a second driving current according to the control signal Vctrl to make the second light emission The element L2 emits light; in this case, the second light-emitting element L2 and the first light-emitting element L1 jointly display the gray scale to be displayed.

For example, as shown in FIG. 4, the input circuit 140 may be implemented as a second switching transistor T2. For example, as shown in FIG. 4, the gate of the second switch transistor T2 is connected to the first scan signal terminal to receive the first scan signal SN1, and the first pole of the second switch transistor T2 is connected to the data signal terminal DATA to receive the data signal. Vdata, the second pole of the second switching transistor T2 is connected to the first node P1 (ie, the gate of the first driving transistor M1, that is, the control terminal 111 of the first driving circuit 110). For example, the level range of the data signal Vdata provided by the data signal terminal DATA includes a first range and a second range. For example, the first range corresponds to the first grayscale range of the grayscale to be displayed (for example, the aforementioned [0,n]). For example, for the pixel circuit shown in FIG. 4, in the first range, the data signal satisfies Vdata ≤Vtht1+Vth2; for example, the second range corresponds to the second grayscale range of the grayscale to be displayed. For example, for the pixel circuit shown in FIG. 4, in the second range, the data signal satisfies Vdata>Vtht1+Vth2. For example, in some examples, when the gray scale to be displayed is n (n is the dividing point between the first gray scale range and the second gray scale range), the data signal corresponding to the gray scale n is Vdata(n), and Vdata (n)≤Vtht1+Vth2, at this time, the first driving current is greater than zero, the first light-emitting element L1 emits light, the second driving current is equal to zero, the second light-emitting element L2 does not emit light, and the light-emitting brightness of the first light-emitting element L1 is The requirement of the displayed gray scale n; when the gray scale to be displayed is n+1, the data signal corresponding to the gray scale n+1 is Vdata(n+1), and Vdata(n+1)>Vtht1+Vth2, this When the first driving current and the second driving current are both greater than zero, the first light-emitting element L1 and the second light-emitting element L2 both emit light, and the light-emitting brightness of the second light-emitting element L2 is superimposed with that of the first light-emitting element L1 The grayscale to be displayed is n+1.

For example, as shown in FIG. 4, the first storage circuit 150 may be implemented as a first storage capacitor Cs1. For example, as shown in FIG. 4, the first terminal of the first storage capacitor Cs1 is coupled to the gate of the first driving transistor M1 (that is, the control terminal 111 of the first driving circuit 110), and the second terminal of the first storage capacitor Cs1 Connect with the second power terminal ELVSS. For example, the potential of the first terminal of the first storage capacitor Cs1 may be maintained at the potential of the first node P1, and the potential of the second terminal of the first storage capacitor Cs1 may be maintained at the second power supply voltage VSS. For example, in some examples, in the data writing phase, the data signal Vdata may be applied to the first node P1 (ie, the first end of the first storage capacitor Cs1) through the second switching transistor T2, so that the first storage capacitor Cs1 The data signal Vdata can be stored.

For example, as shown in FIG. 4, the first reset circuit 160 may be implemented as a third switching transistor T3. For example, as shown in FIG. 4, the gate of the third switching transistor T3 is connected to the second scanning signal terminal to receive the second scanning signal SN2, and the first electrode of the third switching transistor T3 is connected to the gate of the first driving transistor M1 ( That is, the control terminal 111) of the first driving circuit 110 is connected, and the second pole of the third switching transistor T3 is connected to the second power terminal ELVSS. For example, in some examples, in the reset phase, the third switching transistor T3 may be turned on in response to the effective level (for example, high level) of the second scan signal SN2, thereby applying the second power supply voltage VSS to the first A gate of the driving transistor M1 to reset the first driving transistor M1 and the first storage capacitor Cs1.

For example, as shown in FIG. 4, the second storage capacitor 170 may be implemented as a second storage capacitor Cs2. For example, as shown in FIG. 4, the first terminal of the second storage capacitor Cs2 is coupled to the gate of the second driving transistor M2 (that is, the control terminal 121 of the second driving circuit 120), and the second terminal of the second storage capacitor Cs2 Connect with the second power terminal ELVSS. For example, the potential of the first terminal of the second storage capacitor Cs2 may be maintained at the potential of the second node P2, and the potential of the second terminal of the second storage capacitor Cs2 may be maintained at the second power supply voltage VSS. For example, in some examples, in the data writing phase, the control signal Vctrl generated by the first switching transistor T1 according to the data signal Vdata is applied to the second node P2 (ie, the first end of the second storage capacitor Cs2), so that the second The storage capacitor Cs2 can store the control signal Vctrl.

For example, as shown in FIG. 4, the second reset circuit 180 may be implemented as a fourth switching transistor T4. For example, as shown in FIG. 4, the gate of the fourth switch transistor T4 is connected to the second scan signal terminal to receive the second scan signal SN2, and the first pole of the fourth switch transistor T4 and the gate of the second drive transistor M2 ( That is, the control terminal 121) of the second driving circuit 120 is connected, and the second pole of the fourth switch transistor T4 is connected to the second power terminal ELVSS. For example, in some examples, in the reset phase, the fourth switching transistor T4 may be turned on in response to the effective level (for example, high level) of the second scan signal SN2, thereby applying the second power supply voltage VSS to the first The gates of the two driving transistors M2 are used to reset the second driving transistor M2 and the second storage capacitor Cs2.

FIG. 5 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 3. The pixel circuit shown in FIG. 5 is different from the pixel circuit shown in FIG. 4 in that the connection mode of the first storage capacitor Cs1 and the third switching transistor T3 is different. It should be noted that other circuit structures of the pixel circuit shown in FIG. 5 are basically the same as those of the pixel circuit shown in FIG. 4, and the repetitions are not repeated here. Hereinafter, only the differences between the pixel circuit shown in FIG. 5 and the pixel circuit shown in FIG. 4 will be described.

For example, in the pixel circuit shown in FIG. 5, the first terminal of the first storage capacitor Cs1 is coupled to the gate of the first driving transistor M1 (that is, the control terminal 111 of the first driving circuit 110), and the first storage capacitor Cs1 The second terminal of is coupled to the gate of the second driving transistor M2 (ie, the control terminal 121 of the second driving circuit 120). For example, the potential of the first terminal of the first storage capacitor Cs1 may still be maintained at the potential of the first node P1, and the potential of the second terminal of the first storage capacitor Cs1 may be maintained at the potential of the second node P2. For example, in the pixel circuit shown in FIG. 5, in the data writing stage, the data signal Vdata can be applied to the first node P1 (that is, the first end of the first storage capacitor Cs1) through the second switching transistor T2, so that, The first storage capacitor Cs1 can still store the data signal Vdata, that is, although the connection mode of the first storage capacitor Cs1 is changed, it does not affect the first storage capacitor Cs1 to realize its data signal storage function, and thus does not affect the normality of the pixel circuit 200 jobs.

For example, in the pixel circuit shown in FIG. 5, the gate of the third switching transistor T3 is connected to the second scanning signal terminal to receive the second scanning signal SN2, and the first electrode of the third switching transistor T3 is connected to the first driving transistor M1. The gate (ie, the control terminal 111 of the first drive circuit 110) is connected, and the second pole of the third switch transistor T3 is connected with the gate of the second drive transistor M2 (ie, the control terminal 121 of the second drive circuit 120). For example, in the pixel circuit shown in FIG. 5, in the reset phase, the third switching transistor T3 and the fourth switching transistor T4 may be turned on simultaneously in response to the effective level (for example, high level) of the second scan signal SN2 Therefore, the third switching transistor T3 can apply the second power supply voltage VSS to the gate of the first driving transistor M1 through the fourth switching transistor T4 to perform a reset operation on the first driving transistor M1 and the first storage capacitor Cs1. The connection mode of the third switch transistor T3 is changed, but it does not affect the third switch transistor T3 to realize its function of resetting the first driving transistor M1 and the first storage capacitor Cs1, thereby not affecting the normal operation of the pixel circuit 200.

It should be noted that, in the embodiment of the present disclosure, the first storage capacitor Cs1 (that is, the first storage circuit 150), the third switching transistor T3 (that is, the first reset circuit 160), and the second storage capacitor Cs2 (that is, the second The connection between the storage circuit 170) and the fourth switch transistor T4 (ie, the second reset circuit 180) includes but is not limited to the connection shown in FIGS. 4 and 5, as long as it can realize its own necessary functions and does not affect the pixel circuit It works normally.

It is understandable that since the first switching transistor T1 forms a diode structure in the pixel circuit shown in FIGS. 4 and 5, the first switching transistor T1 can be replaced with a diode D0 to obtain the corresponding results shown in FIGS. 6 and 7的pixel circuit. For example, the interconnected gate and first pole of the first switching transistor T1 in the pixel circuit shown in FIGS. 4 and 5 may serve as the first pole (for example, the anode) of the diode D0, and the second pole of the first switching transistor T1 The two poles can be used as the second pole (for example, the negative electrode) of the diode D0, so as long as the first switching transistor T1 in the pixel circuit shown in FIGS. 4 and 5 is replaced by the diode D0, and the first pole of the diode D0 Connected to the first node P1 (ie the gate of the first drive transistor M1, that is, the control terminal 111 of the first drive circuit 110), the second pole of the diode D0 and the second node P2 (ie, the gate of the second drive transistor M2) The pixel circuit shown in FIG. 6 and FIG. 7 can be obtained by connecting the control terminal 121 of the second driving circuit 120).

It should be noted that the other structures of the pixel circuit shown in FIG. 6 are basically the same as those of the pixel circuit shown in FIG. 4, and the other structures of the pixel circuit shown in FIG. 7 are the same as those of the pixel circuit shown in FIG. 5. They are basically the same, so I won’t repeat them here.

In the pixel circuit provided by the embodiment of the present disclosure, the first light-emitting element L1 and the second light-emitting element L2 are located in the same sub-pixel and have the same light-emitting color. Compared with a normal sub-pixel including only one light-emitting element L0, assuming that the area and aperture ratio of the sub-pixel are the same, the sum of the light-emitting areas of the first light-emitting element L1 and the second light-emitting element L2 should be equal to the light-emitting element L0 The area of the light-emitting area. For example, in low grayscale display, only the first light-emitting element L1 emits light. In order to make the light-emitting brightness of the first light-emitting element L1 consistent with that of the light-emitting element L0, the area of the light-emitting area of the first light-emitting element L1 is smaller than that of the light-emitting element. For the area of the light-emitting area of the element L0, the first driving transistor M1 needs to operate at a higher Vgs (ie the voltage difference between the gate and the source); thus, even if there is a fluctuation in Vgs caused by electrical noise (ie d(Vgs) ), its impact on the display screen will be relatively reduced, which can improve the display effect. For example, in some examples, the area of the light-emitting area of the first light-emitting element L1 may be smaller than the area of the light-emitting area of the second light-emitting element L2, so that the Vgs of the first driving transistor M1 during low-gray-scale display can be further increased, and thus Further reduce the influence of electrical noise on the display screen to further improve the display effect.

It should be noted that, in the embodiments of the present disclosure, the storage capacitors Cs1 and Cs2 can be capacitive devices manufactured through a process, for example, a capacitor device can be realized by manufacturing a special capacitor electrode, and each electrode of the capacitor can be made by a metal layer, a semiconductor Layers (for example, doped polysilicon), etc., and the storage capacitors Cs1 and Cs2 can also be parasitic capacitances between various devices, which can be realized by the transistor itself and other devices and circuits. The connection manner of the storage capacitors Cs1 and Cs2 is not limited to the manner described above, and may also be other applicable connection manners, as long as the level of the corresponding node can be stored.

It should be noted that in the description of the embodiments of the present disclosure, the first node P1 and the second node P2 do not represent actual components, but represent the junction of related electrical connections in the circuit diagram.

It should be noted that the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are used as examples for description. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is the second pole.

In addition, the transistors in the embodiments of the present disclosure are all described with an N-type transistor as an example. At this time, the first electrode of the transistor is the drain and the second electrode is the source. In addition, the first electrode of the diode is the anode, and the second electrode of the diode is the anode. The second pole is the negative pole. It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the pixel circuit provided by the embodiments of the present disclosure may also be P-type transistors. In this case, the first electrode of the transistor is the source, the second electrode is the drain, and the first electrode of the diode The second pole of the diode is the anode, and only the poles of the selected type of transistor are connected with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal provides the corresponding high voltage or Low voltage is fine. When N-type transistors are used, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) can be used as the active layer of the thin film transistor. Compared with the use of low temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated non-crystalline silicon), As the active layer of the thin film transistor, crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.

It should be noted that in the embodiments of the present disclosure, the anodes of the light-emitting elements L1 and L2 are connected to the first power supply voltage VDD (high voltage) as an example for description, and the embodiments of the present disclosure include but are not limited to this . For example, the cathodes of the light-emitting elements L1 and L2 can also be connected to the second power supply voltage VSS (low voltage), and the anodes are directly or indirectly connected to the driving circuit. For example, refer to the 2T1C pixel circuit shown in FIG. 1A.

It should be noted that in the pixel circuit provided by the embodiment of the present disclosure, the "effective level" refers to a level that enables the operated transistor included in it to be turned on, and correspondingly, the "ineffective level" refers to It is a level at which the operated transistor included in it cannot be turned on (that is, the transistor is turned off). According to factors such as the type (N-type or P-type) of the transistor in the circuit structure of the pixel circuit, the effective level may be higher or lower than the inactive level. For example, in the embodiment of the present disclosure, when each transistor is an N-type transistor, the effective level is a high level and the ineffective level is a low level.

At least one embodiment of the present disclosure also provides a driving method of the pixel circuit. FIG. 8 is a signal timing diagram of a driving method of a pixel circuit provided by at least one embodiment of the present disclosure. The driving method of the pixel circuit 100 provided by the embodiment of the present disclosure will be described below in conjunction with the signal timing diagram shown in FIG. 8. It should be noted that the level of the potential of the signal timing diagram shown in FIG. 8 is only illustrative, and does not represent the true potential value or relative ratio. It corresponds to the embodiment of the present disclosure, and the high-level signal corresponds to the N-type transistor. The turn-on signal, and the low-level signal corresponds to the turn-off signal of the N-type transistor.

For example, the driving method of the pixel circuit includes: providing a data signal to the pixel circuit, so that the first light-emitting element and the second light-emitting element jointly display the gray scale to be displayed corresponding to the data signal. The following takes the pixel circuit shown in FIG. 3 (the pixel circuit shown in FIG. 3 is specifically implemented as the circuit structure shown in FIG. 5) as an example to describe the driving method of the pixel circuit in detail.

For example, as shown in FIG. 8, the driving method provided by this embodiment may include three phases, namely a reset phase t1, a data writing phase t2, and a light-emitting phase t3. FIG. 8 shows the status of each signal in each phase. Timing waveform.

In the reset phase t1, the second scan signal SN2 is input. At this time, the second scan signal SN2 is at an effective level (ie, a high level). The first reset circuit 160 and the second reset circuit 180 are both turned on, and the first reset circuit 160 and the second reset circuit 180 respectively reset the control terminal 111 of the first drive circuit 110 and the control terminal 121 of the second drive circuit 120.

For example, in the pixel circuit shown in FIG. 5, in the reset phase t1, the third switch transistor T3 and the fourth switch transistor T4 are both turned on by the high level of the second scan signal SN2; at the same time, the second switch transistor T2 is turned on The low level of the first scan signal SN1 is turned off. Since the second power supply voltage VSS provided by the second power supply terminal ELVSS is a low voltage (for example, it can be a ground voltage or other low voltages, such as zero voltage or negative voltage, etc.), the first storage capacitor Cs1 can pass through the third switching transistor T3 ( And the fourth switching transistor T4) are discharged, so that the potential of the first end of the first storage capacitor Cs1 and the gate of the first driving transistor M1 (that is, the first node P1) becomes VSS, and the second storage capacitor Cs2 can pass The fourth switching transistor T4 discharges, so that the potential of the first end of the second storage capacitor Cs2 and the gate of the second driving transistor M2 (that is, the second node P2) becomes VSS, that is, the potential of the first driving transistor M1 The gate and the gate of the second driving transistor M2 are reset. At this time, the first switching transistor T1 is turned off under the action of the second power supply voltage VSS.

In the data writing phase t2, the first scan signal SN1 is input. At this time, the first scan signal SN1 is at a high level, the input circuit 140 is turned on, and the data signal Vdata is written into the first storage circuit 150 through the input circuit 140; at the same time, The voltage regulation circuit 130 generates a control signal Vctrl according to the data signal Vdata, and writes the control signal Vctrl into the second storage circuit 170.

For example, in the pixel circuit shown in FIG. 5, in the data writing phase t2, the second switching transistor T2 is turned on by the high level of the first scan signal SN1, and the third switching transistor T3 and the fourth switching transistor T4 are both turned on. The low level of the second scan signal SN2 is turned off. The data signal terminal DATA charges the first terminal of the first storage capacitor Cs1 (ie, the first node P1) through the second switch transistor T2, so that the potential of the first terminal of the first storage capacitor Cs1 becomes Vdata. Since the first switching transistor T1 is in a diode connection mode, the first switching transistor T1 can be compared with the threshold voltage Vtht1 of the first switching transistor T1 according to the potential Vdata of the first node P1 (that is, the first end of the first storage capacitor Cs1) In relation to this, the control signal Vctrl is generated at the second node P2, and the control signal Vctrl is written into the second storage capacitor Cs2.

For example, when Vdata≤Vtht1, the first switching transistor T1 is turned off, and it can be considered that the control signal generated by it is Vctrl=0. At this time, the potential of the second node P2 remains at VSS, which can be considered as the control of the storage of the second storage capacitor Cs2 The signal is VSS, for example, VSS<Vth2, for example, VSS=0. When Vtht1<Vdata≤Vtht1+Vth2, the first switch transistor T1 is turned on, and the control signal it generates is Vctrl=Vdata-Vtht1, where Vctrl≤Vth2. At this time, the data signal terminal DATA passes through the second switch transistor T2 and the second switch transistor T2. A switch transistor T1 charges the first terminal (ie, the second node P2) of the second storage capacitor Cs2. When the potential of the second node P2 reaches Vctrl, the first switch transistor T1 is turned off and the charging process ends. When Vdata>Vtht1+Vth2, the first switch transistor T1 is turned on, and the generated control signal is Vctrl=Vdata-Vtht1, where Vctrl>Vth2, at this time, the data signal terminal DATA passes through the second switch transistor T2 and the first switch transistor T1 charges the first terminal (ie, the second node P2) of the second storage capacitor Cs2. When the potential of the second node P2 reaches Vctrl, the first switching transistor T1 is turned off, and the charging process ends.

In the light-emitting phase t3, the first driving circuit 110 generates a first driving current according to the data signal Vdata stored in the first storage circuit 150 to make the first light-emitting element 210 emit light, and the second driving circuit 120 according to the control signal stored in the second storage circuit 170 Vctrl generates a second driving current (for example, the second driving current may be 0), so that the second light-emitting element 220 emits light or does not emit light, and the superposition of the light-emitting brightness of the first light-emitting element 210 and the second light-emitting element 220 conforms to the data signal Vdata Corresponding to the requirements of the grayscale to be displayed.

For example, in the pixel circuit shown in FIG. 5, the first driving current can be expressed as:

The second drive current can be expressed as:

Among them, I ₁ represents the first drive current, I ₂ represents the second drive current, β ₁ represents a constant value related to the first drive circuit 110 (ie, the first drive transistor M1), and β ₂ represents a constant value related to the second drive circuit. 120 (ie, the second drive transistor M2) related constant value, Vth1 represents the threshold voltage of the first drive circuit 110 (ie the first drive transistor M1), Vth2 represents the threshold value of the second drive circuit 120 (ie, the second drive transistor M2) Voltage.

For example, in the pixel circuit shown in FIG. 5, in the light-emitting phase t3, the second switching transistor T2 is turned off by the low level of the first scanning signal SN1, and the third switching transistor T3 and the fourth switching transistor T4 are both scanned secondly. The low level of the signal SN2 is cut off. The first driving transistor M1 generates a first driving current under the control of the data signal Vdata stored in the first storage capacitor Cs1 to drive the first light emitting element L1 to emit light, and the second driving transistor M2 stores the control signal Vctrl in the second storage capacitor Cs2 The second driving current (for example, the second driving current may be 0) is generated under the control of, to drive or not drive the second light-emitting element L2 to emit light, and the superposition of the light-emitting brightness of the first light-emitting element L1 and the second light-emitting element L2 conforms to The data signal Vdata corresponds to the requirement of the gray scale to be displayed.

For example, in some examples, the gray scale range of the gray scale to be displayed includes a first gray scale range (for example, a low gray scale range, such as the aforementioned [0, n]) and a second gray scale range (for example, a high gray scale range). Range, such as the aforementioned (n,255]), the level range of the data signal Vdata includes a first range and a second range. For example, the first range of the data signal Vdata corresponds to the first grayscale range, for example, in the first range Where the data signal satisfies Vdata≦Vtht1+Vth2; for example, the second range of the data signal Vdata corresponds to the second grayscale range, for example, in the second range, the data signal satisfies Vdata>Vtht1+Vth2.

Therefore, when the gray scale to be displayed is in the first gray scale range, the data signal Vdata provided to the pixel circuit in the data writing stage should be in the first range, so that the control signal satisfies Vctrl≤Vth2, thus, The first light-emitting element L1 emits light (the first driving current is not 0) and the second light-emitting element L2 does not emit light (the second driving current is 0); at this time, the light-emitting brightness of the first light-emitting element L1 and the second light-emitting element L2 The superposition is the brightness of the first light emitting element L1, that is, the brightness of the first light emitting element L1 should meet the requirements of the gray scale to be displayed corresponding to the data signal Vdata. When the gray scale to be displayed is in the second gray scale range, the data signal Vdata provided to the pixel circuit during the data writing phase should be in the second range, so that the control signal satisfies Vctrl>Vth2, thus, the first Both the light-emitting element L1 and the second light-emitting element L2 emit light (the first driving current and the second driving current are not 0); at this time, the superimposition of the light-emitting brightness of the first light-emitting element L1 and the second light-emitting element L2 should satisfy the data signal Vdata corresponds to the requirements of the grayscale to be displayed.

It should be noted that the signal timing diagram shown in FIG. 8 is schematic. For the pixel circuit provided by the embodiment of the present disclosure, the signal timing during operation may be determined according to actual needs, and the present disclosure does not limit this. For example, in some examples, considering the influence of the voltage drop (IRDROP) of the data signal line and the actually provided first scan signal SN1 may not be a standard square wave signal, the actually provided data signal may be the dashed line as shown in Figure 8. Vdata_r shown (for clarity, Vdata_r shown in FIG. 8 is lower than Vdata, but in fact Vdata_r=Vdata), its falling edge is located in the light-emitting phase (that is, the falling edge of the data signal Vdata_r lags behind the first scan signal SN1 Even if there is a voltage drop or/and the actual provided first scan signal SN1 deviates from the standard square wave signal, at the end of the data writing phase, the first end of the first storage capacitor Cs1 is written The data signal can still be determined as Vdata.

It should also be noted that the division of the reset phase t1, the data writing phase t2, and the light-emitting phase t3 is for convenience of description. In practical applications, there may not be a clear time boundary between different phases. For example, in some examples, during the data writing phase, the first light-emitting element L1 may already start to emit light before the voltage of the first terminal of the first storage capacitor reaches Vdata. For example, in order to avoid this situation, on the basis of the pixel circuit provided by the embodiment of the present disclosure, a light emission control circuit may be added to enable the pixel circuit to have a light emission control function, which is not limited by the embodiment of the present disclosure.

For the technical effects of the driving method of the pixel circuit provided by the embodiment of the present disclosure, reference may be made to the corresponding description of the pixel circuit in the above-mentioned embodiment, which will not be repeated here.

At least one embodiment of the present disclosure also provides a display panel. FIG. 9 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 9, the display panel 10 includes a plurality of sub-pixels 50, a plurality of scan signal lines, and a plurality of data signal lines arranged in an array. It should be noted that only a part of the sub-pixels 50, scanning signal lines, and data signal lines are shown in FIG. 9. For example, G_N-1, G_N, G_N+1 and G_N+2 represent the scanning signal lines for the N-1th, Nth, N+1, and N+2th rows of the array, respectively, D_M and D_M +1 represents the data signal lines used for the Mth column and M+1th column of the array, respectively. Here, N is, for example, an integer greater than 1, and M is, for example, an integer greater than 1.

For example, each sub-pixel 50 includes a pixel circuit provided by any one of the foregoing embodiments of the present disclosure, such as the pixel circuit 100 shown in FIG. 2 or FIG. 3, but is not limited thereto.

For example, the input circuit 140 in the pixel circuit 100 of each row is connected to the scan signal line of the current row to receive the first scan signal SN1; the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 of each row are connected to the upper The scan signal lines of one row are connected to receive the second scan signal SN2. For another example, for the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 in the first row, there may be an additional scan signal line to provide the second scan signal SN2.

For example, each column of sub-pixels corresponds to one data signal line. For example, the input circuit 140 in the pixel circuit 100 of each column of sub-pixels is connected to the corresponding data signal line, so that the input circuit 140 in each pixel circuit 100 can be connected to The corresponding connected data signal line receives the data signal Vdata.

For the technical effects of the display panel 10 provided by at least one embodiment of the present disclosure, reference may be made to the corresponding description of the pixel circuit in the foregoing embodiment, which is not repeated here.

At least one embodiment of the present disclosure also provides a display device. FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 10, the display device 1 may include the display panel 10 provided by any of the foregoing embodiments of the present disclosure, and may also include a scan driving circuit 20 and a data driving circuit 30.

For example, the scan driving circuit 20 may be connected to a plurality of scan signal lines GL (that is, G_N-1, G_N, G_N+1, G_N+2, etc.) to provide scan signals (for example, the first scan signal SN1, the second scan signal SN2). It should be noted that the first scan signal SN1 and the second scan signal SN2 are relative terms. For example, the first scan signal SN1 of the pixel circuit 100 of a certain row may be the second scan signal of the pixel circuit 100 of the next row. SN2. For example, the scan driving circuit 20 may be implemented by a bonded integrated circuit driving chip, or the scan driving circuit 20 may be directly integrated on the display panel to form a GOA (Gate Driver On Array).

For example, the data driving circuit 30 may be connected to a plurality of data signal lines DL (ie, D_M, D_M+1, etc.) to provide the data signal Vdata. For example, the data driving circuit 30 may be implemented by a bonded integrated circuit driving chip.

The display device 1 may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc. These components may, for example, adopt conventional components or structures, which will not be repeated here.

For example, the display device 1 in this embodiment may be any product or component with a display function, such as a display, a TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator. It should be noted that the display device 1 may also include other conventional components or structures. For example, in order to realize the necessary functions of the display device, a person skilled in the art can set other conventional components or structures according to specific application scenarios. The embodiments of the present disclosure There is no restriction on this.

For the technical effects of the display device provided by at least one embodiment of the present disclosure, reference may be made to the corresponding description of the pixel circuit in the foregoing embodiment, which is not repeated here.

For this disclosure, the following points need to be explained:

(1) The drawings of the embodiments of the present disclosure only refer to the structures related to the embodiments of the present disclosure, and other structures can refer to the usual design.

(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above descriptions are only exemplary implementations of the present disclosure, and are not intended to limit the scope of protection of the present disclosure. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. Covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure is determined by the appended claims.

Claims

A pixel circuit, including a first driving circuit and a second driving circuit, wherein

The first driving circuit is configured to generate a first driving current for driving the first light-emitting element to emit light according to the data signal,

The second driving circuit is configured to generate a second driving current for driving the second light-emitting element to emit light according to a control signal, and the control signal is obtained according to the data signal and is different from the data signal.
The pixel circuit according to claim 1, further comprising a voltage adjustment circuit, wherein:

The voltage regulation circuit is configured to generate the control signal according to the data signal.
The pixel circuit according to claim 2, wherein the voltage regulation circuit includes a first switching transistor,

The gate and the first pole of the first switch transistor are both connected to the control terminal of the first drive circuit, and the second pole of the first switch transistor is connected to the control terminal of the second drive circuit to form Diode structure.
The pixel circuit according to claim 2, wherein the voltage regulating circuit includes a diode,

The first pole of the diode is connected to the control terminal of the first drive circuit, and the second pole of the diode is connected to the control terminal of the second drive circuit.
The pixel circuit according to any one of claims 1 to 4, further comprising the first light-emitting element, wherein:

The first pole of the first light-emitting element is connected to the first power terminal to receive the first power voltage,

The first driving circuit includes a first driving transistor,

The gate of the first driving transistor serves as the control terminal of the first driving circuit, the first electrode of the first driving transistor is connected to the second electrode of the first light-emitting element, and the The second pole is connected to the second power terminal to receive the second power voltage.
The pixel circuit according to any one of claims 1 to 5, further comprising the second light-emitting element, wherein:

The first pole of the second light-emitting element is connected to the first power terminal to receive the first power voltage,

The second driving circuit includes a second driving transistor,

The gate of the second driving transistor serves as the control terminal of the second driving circuit, the first electrode of the second driving transistor is connected to the second electrode of the second light-emitting element, and the second electrode of the second driving transistor is The second pole is connected to the second power terminal to receive the second power voltage.
The pixel circuit according to any one of claims 1 to 6, further comprising an input circuit, wherein:

The input circuit is configured to apply the data signal to the control terminal of the first driving circuit in response to a first scan signal.
The pixel circuit according to claim 7, wherein the input circuit includes a second switching transistor,

The gate of the second switch transistor is connected to the first scan signal terminal to receive the first scan signal, the first pole of the second switch transistor is connected to the data signal terminal to receive the data signal, the first The second pole of a switch transistor is connected to the control terminal of the first driving circuit.
7. The pixel circuit according to any one of claims 1-7, further comprising a first storage circuit and a first reset circuit, wherein,

The first storage circuit is configured to store the data signal,

The first reset circuit is configured to reset the control terminal of the first driving circuit in response to a second scan signal.
9. The pixel circuit according to claim 9, wherein the first storage circuit includes a first storage capacitor, and the first reset circuit includes a third switching transistor,

The first end of the first storage capacitor is coupled to the control end of the first drive circuit, the second end of the first storage capacitor is coupled to the control end of the second drive circuit, and the third The gate of the switching transistor is connected to the second scanning signal terminal to receive the second scanning signal, the first electrode of the third switching transistor is connected to the control terminal of the first driving circuit, and the third switching transistor The second pole is connected to the control terminal of the second drive circuit; or,

The first terminal of the first storage capacitor is coupled to the control terminal of the first drive circuit, the second terminal of the first storage capacitor is connected to the second power terminal, and the gate of the third switch transistor is connected to The second scan signal terminal is connected to receive the second scan signal, the first pole of the third switch transistor is connected to the control terminal of the first drive circuit, and the second pole of the third switch transistor is connected to the The second power terminal is connected.
The pixel circuit according to any one of claims 1-10, further comprising a second storage circuit and a second reset circuit, wherein,

The second storage circuit is configured to store the control signal,

The second reset circuit is configured to reset the control terminal of the second driving circuit in response to a second scan signal.
11. The pixel circuit of claim 11, wherein the second storage circuit includes a second storage capacitor, and the second reset circuit includes a fourth switching transistor,

The first terminal of the second storage capacitor is coupled to the control terminal of the second drive circuit, and the second terminal of the second storage capacitor is connected to the second power terminal,

The gate of the fourth switch transistor is connected to the second scan signal terminal to receive the second scan signal, the first pole of the fourth switch transistor is connected to the control terminal of the second drive circuit, and the first The second pole of the four-switch transistor is connected to the second power terminal.
The pixel circuit according to any one of claims 1-12, wherein the level range of the data signal includes a first range and a second range,

When the level of the data signal is in the first range, the first drive current is greater than zero, and the second drive current is equal to zero,

When the level of the data signal is in the second range, the first driving current and the second driving current are both greater than zero.
The pixel circuit according to claim 13, wherein the light emission color of the first light-emitting element and the second light-emitting element are the same, and the area of the light-emitting region of the first light-emitting element is smaller than that of the second light-emitting element. The area of the district.
A display panel includes a plurality of sub-pixels arranged in an array, wherein:

Each of the sub-pixels includes the pixel circuit according to any one of claims 1-14.
A display device comprising the display panel according to claim 15.
A method for driving a pixel circuit, wherein the pixel circuit includes a first driving circuit and a second driving circuit, the first driving circuit is configured to generate a first driving current for driving a first light-emitting element to emit light according to a data signal, and The second driving circuit is configured to generate a second driving current for driving the second light-emitting element to emit light according to a control signal, the control signal is obtained according to the data signal and is different from the data signal,

The driving method includes:

The data signal is provided to the pixel circuit, so that the first light-emitting element and the second light-emitting element jointly display the gray scale to be displayed corresponding to the data signal.
The driving method according to claim 17, wherein:

The gray scale range of the gray scale to be displayed includes a first gray scale range and a second gray scale range, and the level range of the data signal includes a first range and a second range;

When the gray scale to be displayed is within the first gray scale range, the pixel circuit is provided with the data signal in the first range, so that the first light-emitting element emits light and all The second light-emitting element does not emit light;

When the gray scale to be displayed is in the second gray scale range, the pixel circuit is provided with the data signal in the second range, so that the first light-emitting element and the The second light-emitting elements all emit light.