WO2020239835A1

WO2020239835A1 - Signal processing (e.g., for mixed-signal beamforming and down-conversion receiver)

Info

Publication number: WO2020239835A1
Application number: PCT/EP2020/064702
Authority: WO
Inventors: Wilhelm Keusgen; Friedel Gerfers
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 2019-05-27
Filing date: 2020-05-27
Publication date: 2020-12-03
Also published as: EP3977636A1

Abstract

There are provided techniques for signal processing (e.g., for a mixed-signal beamforming and/or down-conversion receiver). The techniques may be implemented in devices (e.g., circuit arrangements), systems, methods, and/or storage units. A circuit arrangement (460) may comprise: a hold stage (420), configured to selectively sample and/or hold, in a time- shifted manner, signal values of a plurality of analog input signals values (410a- 410c), to obtain held signal values (422a-422c); a combiner stage (424), configured to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a- 410c), to obtain a combined signal value (428), such that the held signal values (422a- 422c) which are combined by the combiner stage (424) represent signal values of the input signals (410a- 410c) associated with different times (T₁-T₃); and an analog-to-digital converter (434) configured to analog-to-digital convert the combined signal (428) value into a digital representation (436). In addiction or alternative, a circuit arrangement (460) may comprise: a hold stage (420), configured to selectively sample and/or hold signal values of a plurality of analog input signals values (410a- 410c), to obtain held signal values (422a- 422c); a combiner stage (424), configured to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a-410c), selectively using different gains, to obtain a combined signal value (428), such that the held signal values (422a-422c) which are combined by the combiner stage (424) represent signal values of the input signals (410a- 410c) associated with different times (T₁-T₃); and an analog-to-digital converter (434) configured to analog-to-digital convert the combined signal (428) value into a digital representation (436).

Description

Signal processing (e.g., for mixed-signal beamforminq and down-conversion receiver)

Technical field

The present invention refers to techniques for signal processing (e.g., for a mixed- signal beamforming and/or down-conversion receiver). The techniques may be implemented in devices (e.g., circuit arrangements), systems, methods, and storage units.

Background

Reference is made to Figs. 1 , 2, and 3, showing circuits (beamformer receivers) 100, 200, and 300 according to the prior art.

Communication receivers (e.g. for the 5th generation of mobile communication: 5G) or radar receivers will mostly rely to a large extend on multiple antenna techniques. A multiple antenna receiver can be implemented in principle as a beamforming receiver or as a multiple input multiple output, MIMO, receiver.

The circuits 100, 200, 300 provide digital values 136, 236, 336 associated to signals obtained at antenna arrays 101 , 201 , 301.

Fig. 1 shows a beamforming receiver 100 with amplitude (gain) and delay or phase shift 120 in the RF-domain (Radio Frequency domain) 185 (upstream of a downconverter 134 converting from the RF domain to the IF domain 186).

Fig. 2 shows a beamforming receiver 200 with amplitude (gain) and delay or phase shift 220 in the IF domain (Intermediate Frequency domain) 286 (downstream of a downconverter stage 234 converting from the RF domain 285 to the If domain 286).

Fig. 3 shows a beamforming receiver 300 with phase shift 320 in the LO domain (Local Oscillator domain) 387 (between a local oscillator 350 and a downconverter stage 334 converting from the RF domain 385 to the IF domain 386). Within a beamforming receiver the antenna signals are in general delayed in time or weighted in phase and potentially also in amplitude (gain) before being summed and digitized as shown in the circuits 100 of Fig. 1. In general, the weighting is necessarily done in the analogue domain, whereas it can be implemented with respect to the RF signals (Fig. 1), IF signals (Fig. 2) or LO signals (Fig. 3). If a beamforming receiver is implemented by means of changing LO signals (Fig. 3), just a phase shift and no delay or gain variation could be realized. If the beamforming operation is performed just with respect to phase or delay, the receiver reassembles a phased array receiver. The performance of a true time delay shift is superior to the performance of a phase shift especially for broadband signals as envisioned for 5G. The performance of a beamforming receiver incorporating amplitude (gain) variation is in general superior to that of a phased array receiver, since it enables a better control of the antenna beam, with respect to an antenna beam, being independent from changes in signal frequency.

Independent of the chosen architecture, it is characteristic for a beamforming receiver that it has one (digitized) output signal (or data stream). Within a beamforming receiver just one effective antenna beam per time instance is realized by the time shift resp. phase shift, weighting and the summation.

In contrast to a beamforming receiver, within a MIMO receiver each antenna signal is digitized directly at the antenna or after down-conversion, so that the number of digital data streams equals the number of antenna elements. This approach offers the possibility to perform beamforming with time delay or phase shift as well as amplitude control in the digital domain, whereas each of the data streams could be associated to one independent beam leading to multiple simultaneous beams. Therefore, the MIMO receiver has the highest flexibility and the capability to support multiple users and to increase the data rate by means of spatial multiplexing. The MIMO approach has the drawback of high-power consumption and massively increased data rates in the digital domain due to the high number of parallel analog to digital converters (ADC). Therefore, it has a poor scalability.

A combination of both approaches is called hybrid beamforming receiver, where within a MIMO receiver the number of digitized data-streams is reduced by the implementation of beamforming receivers or phased array receivers prior to digitizing. Currently there is a trend towards high signal bandwidth (up to 2 GHz) within mobile and fixed communication and radar systems. Those systems are intended to operate also at high carrier frequencies (up to 100 GHz i.e. mm-wave range). They are foreseen to incorporate a high number of antenna elements (up to several hundred), which makes a Ml MO receiver virtually infeasible. Therefore, beamforming as well as hybrid beamforming systems become more and more relevant especially for broadband and mm-wave systems.

Current beamforming architectures rely on an analogue frontend, incorporating analogue phase shifters or delay lines (e.g., at 120, 220, 320), variable gain amplifiers or variable attenuators (e.g., at 220 or 320) and a power combiner (summation element) 124, 224, 324, limiting a cost-effective implementation, miniaturization and scalability of these approaches mainly due to the power consumption, heat dissipation and the large required chip size [1 , 2]

Figures

Figs. 1-3 show techniques according to the prior art.

Fig. 4 shows a system according to examples.

Figs. 8a and 8b show methods according to examples,

Figs. 5-7, 9a, and 9b show elements of systems according to examples.

Figs. 10a and 10b show operation according to examples.

Figs. 10c and 10d show elements of systems according to examples.

Summary

In accordance to an aspect, there is provided a circuit arrangement comprising:

a hold stage which may be configured to selectively sample and/or hold, in a time- shifted manner, signal values of a plurality of analog input signals values, to obtain held signal values;

a combiner stage, which may be configured to combine the held signal values which are based on the plurality of analog input signals, to obtain a combined signal value, such that the held signal values which are combined by the combiner stage represent signal values of the input signals associated with different times; and an analog-to-digital converter which may be configured to analog-to-digital convert the combined signal value into a digital representation.

In accordance to an additional or alternative aspect, there is provided a circuit arrangement comprising:

a hold stage, which may be configured to selectively sample and/or hold signal values of a plurality of analog input signals values, to obtain held signal values;

a combiner stage, which may be configured to combine the held signal values which are based on the plurality of analog input signals, selectively using different gains, to obtain a combined signal value, such that the held signal values which are combined by the combiner stage represent signal values of the input signals associated with different times; and

an analog-to-digital converter which may be configured to analog-to-digital convert the combined signal value into a digital representation.

In accordance to an aspect, there is provided a method comprising at least one of the following steps:

a hold step to selectively sample and/or hold, in a time-shifted manner, signal values of a plurality of analog input signals values, to obtain held signal values;

a combiner step, to combine the held signal values which are based on the plurality of analog input signals, to obtain a combined signal value, such that the held signal values which are combined in the combiner step represent signal values of the input signals associated with different times; and

an analog-to-digital converter step to analog-to-digital convert the combined signal value into a digital representation.

In accordance to an additional or alternative aspect, there is provided a method comprising at least one of the following steps:

a hold step, to selectively sample and/or hold signal values of a plurality of analog input signals values, to obtain held signal values;

a combiner step, to combine the held signal values which are based on the plurality of analog input signals, selectively using different gains, to obtain a combined signal value, such that the held signal values which are combined by the combiner step represent signal values of the input signals associated with different times; and an analog-to-digital converter step to analog-to-digital convert the combined signal value into a digital representation.

Examples

Fig. 4 shows a circuit arrangement 460 (see also Figs. 9a and 9b) which may be included in a system 400.

The system 400 (which in this case may be used to receive and digitize a beam, but may also be used for other purposes in other examples) may comprise a plurality (e.g., three or more than three) of antennas 402a, 402b, 402c, and so on, which are grouped in one antenna array 401. Each of the antennas 402a, 402b, 402c may be impinged from a wavefront which is spatially slanted with respect to the disposition of the antennas. The antennas 402a, 402b, 402c may be, for example, spatially displaced in an array such as in a row or line. As the wavefront may be slanted with respect to the antenna array, the wavefront may impinge the different antenna elements 402a, 402b and 402c at different time instants.

The circuit arrangement 460 may permit to reconstruct the one single signal from the wavefront impinging the antenna elements 402a, 402b and 402c at different time instants. The circuit arrangement 460 may operate in beamforming. Each antenna element 402a, 402b, 402c may be in extremity of a signal line a, b, c, associated to the particular antenna 402a, 402b, 402c. As can be seen, several elements are repeated and indicated with letters a, b and c for each signal line.

The techniques discussed here do not necessarily refer to beamforming and to antenna arrays. It is possible, for example, to use the techniques here for all kinds of parallel signals, which need to be aligned in time to maximise the sum output (e.g., within cables having multiple parallel signal lines). It is also possible that the signals 403a-c have been previously saved in an analogic support, and not directly obtained from an antenna, and provided to the circuit arrangement 460 only subsequently.

Hereinafter, reference is principally made to radio frequency, RF, wireless transmissions (e.g., received by antenna elements 402a-c). However, it is possible to use the same examples for other transmissions (e.g. ultrasound transmissions), which may be wireless or non-wireless

As is shown in Fig. 4, the circuit arrangement 460 may include a hold stage 420 and/or a combiner stage 424. A digital output (digital representation) 436 may be provided (e.g., to a unit which will perform a decoding operation). The digital output 436 may represent the wavefront that has impinged the antenna elements 402a, 402b and 402c at different time instances.

Each received signal 403a-c may be filtered by a filter 404a-c. A filtered output 406a-c may therefore be obtained. The signal 406a-c may be amplified at a low noise amplifier, LNA, 408a-406c, to obtain an amplified signal 410a-c. The signals 4Q3a-c, 406a-c and/or 410a-c may be provided to the hold stage 420. The hold stage 420 may be configured to selectively sample and/or hold (e.g., in a time shifted manner, e.g., in a controlled fashion) signal values of a plurality of analog input signal values (e.g., 403a- c, 406a-c and/or 41 Oa-c). At the output of the hold stage 420, held signal values 422a- c may be provided. The hold stage 420 may sample and/or hold the input values (403a- c, 404a-c and/or 41 Oa-c) in a time shifted manner. In applications based on beamforming, the hold stage 420 may operate so that the input signals (403a-c, 404a- c and/or 41 Oa-c) are selectively delayed to have signals 422a, 422b and 422c associated to the same front wave as obtained at different times from the different antennas 402a, 402b and 402c. Therefore, ideally, the signals 422a, 422b and 422c should be the same or similar to each other (apart from noise).

The hold stage 420 may be a track and hold stage and/or a sample and hold stage. Examples of the hold stage 420 are provided in Figs. 5 and 7 (other implementations are notwithstanding possible).

The hold stage 420 may be controlled by a clock signal 452 (e.g., provided by a clock 450, which may implement an oscillator and/or a phase locked loop, PLL). In addition or alternative, a time shift control line 442 may be provided to control the hold stage 420. The time shift control line 442 may control the time shifting for different signal lines a, b, c (e.g., for different input signals 402a-402c, 406a-406c and/or 410a-410c). The time shift control line 442 may be implemented as an array of single control lines 442a, 442b, 442c (see for example Figs. 9a and 9b), each controlling one delay to be applied to a particular signal line a, b, c. The time shift control line 442 may be in output to a delay control unit 440a, which may be a part of a delay and gain control unit 440. The delay control unit 440a may, for example, generate a plurality of delay control signals or time shift control signals 442 (e.g., subdivided into delay control signals or time shift control signals 442a, 442c, 442c, each to control a signal line a, b, c, respectively) which may represent, in examples, delayed versions of the clock signal 452 (the delays may be associated to the orientation of the wavefront impinging the antenna elements, for example). An input to the delay control unit 440a may be the clock signal 452. The delay control unit 440a may include, for example, a phased lock loop, PLL, stage.

The circuit arrangement 460 may comprise a combiner stage 424 (e.g., summer, power combiner). The combiner stage 424 may be configured to combine the held signal values 422a-c as provided by the hold stage 420, to obtain a combined signal value 428. Accordingly, the held signal values 422a-422c may be combined so as to represent signal values of the input signals (403a-c, 406a-c, 410a-c) associated with different times (but associated to the same wavefront, in the case of beamforming). At the combiner stage 424, different gains may be used for different held signal values 422a, 422b and 422c. Accordingly, it is possible to obtain a combined signal value 428 which is the composition, according to different gains, of the held signals 422a, 422b, 422c.

A filter 430 may be provided (e.g., downstream of the combiner stage 424, for filtering the combined signal value 428). A filtered value 432 may be obtained. The circuit arrangement 460 may comprise an analog to digital converter, ADC, 434, which may provide a digital representation associated to the wave that has impinged the antenna elements 402a, 402b and 402c. The analog to digital converter 434 may be driven by a fraction of the clock signal 452 (by means of the frequency divider 456), to obtain a more coherent operation. The functional principle the system is not limited to a coherent operation of the analog to digital converter. Examples of elements of the circuit arrangement 460 are provided in Figs. 5-8, which show particular examples of the hold stage 420 and/or the combiner stage 424. Figs. 9a and 9b show the circuit arrangement 460, in which only the signal line a (e.g., associated to the antenna 402a) is shown for conciseness. As may be seen, the elements of Figs. 9a and 9b correspond to the elements of Figs. 4, 5 and 6. However, similar arrangements can be obtained by using the equipment shown in Fig. 7.

Fig. 5 shows an example 520 of the hold stage 420 of Fig. 4. Fig. 5 shows that, for each signal line a, b, c, at least one first switch 512a, 512b, 512c may be provided. At least one second switch 514a, 514b, 514c may also be provided (e.g., downstream of the first switch). Between the first and second switches 512a-c and 514a-c, a hold element (here identified with a capacitor 520a, 520b, 520c) may be provided for each signal line a-c. As can be understood by comparing Fig. 5 with Fig. 4 or from Figs. 9a and 9b, when the first switch 512a-c is closed and the second switch 514a-c is open, the signal (voltage) value 510a-c is the same as the respective input value 410a-c. The value 510a-c at the capacitor 520a-c is the same of the value 410a-c at the input of the hold stage 420 (520). For example, the capacitor 520a-c has a voltage (which may be used as a physical quantity for storing the signal) obtained from the input signal 410a-c. When the first switch 512a-c is closed and the second switch 514a-c is open at the same signal line, the signal 422a-c at the output of the hold stage 420 is that obtained from the charge of the capacitor 520a-c. Therefore:

- the signal 410a-c is tracked by the capacitor 520a-c when the switch 512a-c is closed and the second switch 514a-c is open;

- the signal 510a-c is held when the first switch 512a-c is open; and

the signal 510a-c is provided as delayed output of the hold stage 420 at the output 422a-c when the second switch 514a-c is subsequently closed.

As can be seen from Fig. 5, the first switches 512a, 512b and 512c of the different signal lines a, b, c are in general selectively activated (closed) and/or deactivated (opened) at different time instants. For example, the first switch 512a of the first signal line a may be opened at time instant xi. The first switch 512b of the second signal line b may be opened at the time instant X2. The first switch 512c of the third signal line c may be opened at time instant xs. In general terms, when a switch (e.g., interposed between a first, upstream capacitor and a second, downstream capacitor) is closed, the charge stored in the first upstream capacitor is provided to the second downstream capacitor. The control of the opening of the first switches 512a, 512b and 512c may be performed through the time shift control line 442 (442a-442c). In case of beamforming, such as control may follow the delay of the wavefront in impinging different antenna elements 402a, 402b and 402c.

Differently from the opening of the first switches 512a, 512b, 512c, the second switches 514a, 514b and 514c may be opened and/or closed simultaneously with each other or at different time instants, e.g., independently of the delays associated to ti, t₂, t3. Fig. 5 shows that the closing time instant is t₀ for all the three second switches 514a, 514b, 514c, even if this is not always strictly necessary. It is important that the three second switches 514a, 514b, 514c provide as output the values that have been obtained at different time instants and stored in the different hold elements (capacitors). In general terms, the second switches 514a, 514b and 514c may be controlled by the clock line 452 (see also Figs. 9a and 9b).

A variant to the hold stage 520 of Fig. 5, allowing for higher delays, is shown in the example 720 of Fig. 7, which shows a hold stage 720 divided into a first branch 720-1 and a second branch 720-2. The branches 720-1 and 720-2 may operate in time- interleaved manner (e.g., alternating manner). Each signal line a, b, c is divided into multiple signal sublines: e.g., the signal line may be subdivided into signal sublines a1 and a2; the signal line b into the signal sublines b1 and b2; the signal line c into the signal sublines into d and c2. Two signal sublines of the same signal line may be in parallel to each other.

The input 410a may be associated to:

- a couple of first switches 712a and 713a (respectively, the input 410b is associated to a couple of first switches 712b and 713b; and the input 410c is associated to a couple of first switches 712c and 713c), so that one first switch 712a pertains to the first branch 720-1 (signal subline a1) and one first switch 713a pertains to the first branch 720-2 (signal subline a2) (respectively, one first switch 712b pertains to the first branch 720-1 and one first switch 713b pertains to the second branch 720-2; one first switch 712c pertains to the first branch 720-1 and one first switch 713c pertains to the second branch 720-2);

- a couple of second switches 714a-c and 715a-c (respectively, the input 410b is associated to a couple of second switches 714b and 715b; and the input 410c is associated to a couple of second switches 714c and 715c), so that one second switch 714a pertains to the first branch 720-1 and one second switch 715a pertains to the second branch 720-2 (respectively, one second switch 714b pertains to the first branch 720-1 and one second switch 715b pertains to the second branch 720-2; one second switch 714c pertains to the first branch 720-1 and one second switch 715c pertains to the second branch 720-2); and

- a couple of capacitors 720a and 721a (or other types of storing elements), each placed between a first switch 712 (or 713) and a second switch 714 (or 715) (respectively, the input 410b is associated to a couple of capacitors 720b and 721 b; and the input 410c is associated to a couple of capacitors 720c and 721c), so that a capacitor 720a pertains to the first branch 720-1 and a capacitor 721a pertains to the second branch 720-2 (respectively, a capacitor 720b pertains to the first branch 720-1 and a capacitor 721 b pertains to the second branch 720- 2; a capacitor 720c pertains to the first branch 720-1 and a capacitor 721 c pertains to the second branch 720-2).

For example:

- the signal line a is subdivided among:

o a first signal subline a1 (with first switch 712a upstream to a capacitor 720a, which may be upstream to a second switch 714a), which pertains to the first branch 720-1 ; and

o a second subline a2 (with first switch 713a upstream to a capacitor 721a which may be upstream to a second switch 715a) which pertains to the first branch 720-2;

- the signal line b is subdivided among:

o a first signal subline b1 (with first switch 712b upstream to a capacitor 720b which may be upstream to a second switch 714b), which pertains to the first branch 720-1 ; and

o a second signal subline b2 (with first switch 713b upstream to a capacitor 721b which may be upstream to a second switch 715b); which pertains to the second branch 720-2; and

- the signal line c is subdivided among:

o a first signal subline d (with first switch 712c upstream to a capacitor 720c which may be upstream to a second switch 714c), which pertains to the first branch 720-1 ; and o a second signal subline c2 (with first switch 713c upstream to a capacitor 721c which may be upstream to a second switch 715c), which pertains to the second branch 720-2.

It is to be noted that, for each signal line a, b, c, the couple of first switches (e.g., 712a and 713a) are activated and/or deactivated alternative to each other (e.g., when the first switch 712a is closed, the first switch 713a is open, and/or when the first switch 712a is open, the first switch 713a is closed). The same applies to the second switches 714a and 715a. Accordingly, it is possible to increase the sample rate.

It is also possible to make use of more than two (e.g., three) signal sublines for each signal line. In that case.

Fig. 6 shows an example of a combiner stage 424. A plurality of signals 422a, 422b and 422c (e.g., as obtained by any of the hold stages discussed above) may be combined (e.g., power combined, or analogically summed) to obtain a combined signal 674. As shown in Fig. 6, the combined signal 674 may be stored in a storage element (e.g., capacitor or another dipole) 676. The combined signal value 674 may be obtained by an analog combination (e.g., addition, sum) of different values 670a, 670b and 670c which are obtained from the input 422a, 422b and 422c of the combiner stage. In particular, in this implementation the values 670a, 670b and 670c are stored in storage elements (e.g., capacitors) 668a, 668b and 668c, respectively. Upstream to each storage element 668a-c, a storage element (e.g., capacitor) 662a-c may be provided. Each signal line a, b, c may comprise switches 660a-c, 666a-c, 672a-c, which may be alternated to the storage elements 662a~c and 668a-c. (In some implementations, the storage elements 662a-c are not strictly necessary and may be avoided. In that case, the role of the storage elements 662 may be taken, for example, by the storage elements 520 of the whole stage 520, for example.)

The storage elements 668a, 668b and 668c may have different parameters (e.g., capacitances) which may have a role in the combination of the signals 670a, 670b and 670c. Accordingly, different gains may be obtained. The combined signal value 674 may therefore be obtained by a combination according to gains defined by the different capacitances of the capacitors (e.g., according to a relationship between each of the capacitors 668a-c and the corresponding capacitor 662a or respective storage elements in 520 of the same signal line). For example, if a capacitance is twice as much as another, the overall voltage and therefore the gain may be halved. This is because a parallel of two capacitors with the same capacitance results in the capability of a double amount of charge. It has been noted that this is an optimal technique for achieving gains in the amplitude of the signals when the gain is to be < 1. Other techniques, however, may be used.

As can be seen from Figs. 6, 9a and 9b, parameters (e.g., capacitances) of the storage elements 668a-c may be varied. For example, the storage elements 668a-c may be capacitors with variable capacitances. The variable capacitances may be obtained, for example, by adequately combining, in series or in parallel, arrays of capacitors. For example, a parallel of two capacitors with equal capacitance results into a “big capacitor” with double capacitance; a series of two capacitors with equal capacitance results into a “small capacitor” with half capacitance. Series/parallel connections between capacitors may therefore be obtained to opportunely modify the capacitance of the capacitors 668a-c. (An alternative may be obtained if the position of the second capacitors 668a-c is exchanged with the position of the first capacitors 664a-c. Further, it is also possible to modify also the capacitances of the first capacitors 662a-662c.)

A gain control unit 440b (which may be part of the unit 440) may be provided for selectively defining different gains (e.g., by modifying the capacitances of the capacitors 668a-668c). The control of the gains may follow the beamforming and may be associated to the different signals obtained by the different antennas 402a-402c.

As can be understood from Figs. 4-9b, at least some of the different switches may be operated synchronously, even if alternatively. For example, as can be seen from Fig. 9b, for each capacitor, the two switches close to it are alternatively closed and opened so as to permit that a signal value is copied in correspondence to each capacitor and is provided to the subsequent capacitor. Accordingly, a pipeline operation is obtained.

Operations

General operations Example of operations are provided here. These operations may be obtained, for example, with the equipment and/or the methods discussed above and/or below.

An input signal 403a-c is obtained (e.g., from a wavefront impinging three antenna elements 402a-c at different time instants, e.g., by virtue of the wavefront being slanted with respect to the displacement of the antenna elements 402a-c). It is intended to obtain a digital representation 436 associated to the input signal 403a-c. The digital representation 436 may be obtained by converting an analog value 428 (or its filtered version 432). The analog value 428 may be obtained as the combination, performed at the combiner stage 424, of a plurality of signals 422a-422c, each being obtained from a respective input signal 403a-c. In examples, the combiner stage 424 may apply different gains (e.g., each being less than 1) to the different signals 422a-422c (the different gains may be defined according to the beamforming). In examples, the signals 422a-422c input to the combiner stage 424 may be obtained from a hold stage 420. The hold stage 420 may delay each input signals 403a-c (or a processed version thereof, such as 410a-c) by applying delays (e.g. ti, t , t₃) to each of the input signals 403a-c. The delay may be defined according to the beamforming, for example.

Hold stage

Fig. 10a shows the operation of the hold stage 520 of Fig. 5 during a time interval T of the clock signal 452. It is possible to see how the hold stage 420 operates (reference is made, in particular, to the hold stage 520 of Fig. 5, even if the same is possible with other hold stages). In ordinate, time is shown. In abscissa, a binary logic value of different signals is shown (different heights are only for permitting to better distinguishing the different signals). A clock signal 452 (e.g., as provided by clock 450) is shown as a square signal with time interval T. Here, the duty cycle appears 50%, but a different duty cycle may be chosen.

Before the time instant 0, the status of the hold stage 520 is the following:

- the first switches 512a-512c are closed;

- the second switches 514a-514c are closed.

At the time instant 0, the second switches 514a-514c are opened. Hence, after instant 0: - the first switches 512a-512c remain closed;

- the second switches 514a-514c are open, hence preventing from any output to the combiner stage 424;

- accordingly, the values 51 Oa-51 Oc at the capacitors 520a-520c track the values of the input signals 41 Oa-41 Oc, although the tracked values 51 Oa-51 Oc are not provided to the output.

At the time instant t^ , the first switch 512a of the signal line a is opened, while the first switches 512b and 512c of the signal lines b and c and the second switches 514a-514c are maintained open. ti may be understood as the sample instant of the value 510a.

After ti:

- the first switch 512a is open;

- the remaining first switches 512b and 512c are maintained closed;

- the second switches 514a-514c are maintained open, hence preventing from any output to the combiner stage 424;

accordingly, the capacitor 520a holds, stored, the value 510a, which is the value of the input signal 410a as it was at the instant ti, although the stored value 510a is not output yet;

meanwhile, the capacitors 520b and 520c go on tracking the input signals 410b and 410c.

At T2, also the first switch 512b of the signal line b is opened, while the first switch 512a of the signal line a is maintained open and the first switch 512c of the signal line c is maintained closed. xz may be understood as the sample instant of the value 510b.

After X2.

- the first switches 512a and 512b are now open;

- the remaining first switch 512c is maintained closed;

- accordingly, while the capacitor 520a stores the value 510a (i.e., the value of the input signal 410a as it was at the instant ti), the capacitor 520b stores the value 510b, which is the value of the input signal 410b as it was at the instant meanwhile, the capacitor 520c goes on tracking the values of the input signals 410b and 410c.

At T3, also the first switch 514c of the signal line c is opened, while the first switches 512a and 512b of the signal lines a and b are maintained open. t₃ may be understood as the sample instant of the value 510c. After x₃:

- all the first switches 512a-512c are now open, hence storing the values of the input signals 410a-410c as they were at the time instants xi, t₂, t₃, respectively;

- the second switches 514a-514c are maintained open, hence preventing any provision of the output to the combiner stage 424.

At the time instant to, the held values 510a-510c to the outputs (combiner stage 424) are output (e.g., to the combiner stage 424), as the second switches 514a-514c are closed, while the first switches 512a-512c are marinated open.

The cycle will be repeated after the time instant T.

The sampling interval for all values 510a, 510b, 510c is the period T of the clock signal 452: in fact, the next sample instant will be T+xi for 510a; T +x₂ for 510b; and T+x₃ for 510b.

Notably, the delays t-i, x₂, x₃ are selected by a controller entity and may change with time. If Fig. 10a refers to a beamforming technique, the fact that xi < x₂ < X3 means that a wavefront reaches the first antenna element 402a before the second antenna element 402b, which in turn is impinged by the wavefront before the third antenna element 403c. In some examples, the controller entity selects the delays xi, x₂, x₃ according to a detected orientation of the impinging wavefront with respect to the antenna array 401. If, subsequently, the third antenna element 403c is reached by the wavefront before the second antenna element 402b (and the latter is impinged by the wavefront before the first antenna element 402a), the controller entity will select different delays, which in this case will verify xi > x₂ > x₃. The controller entity may comprise or control, for example, the control unit 440 and/or the delay control circuit 440a. It is not necessary that the duty cycle of the clock signal 542 is 50% (T_O=T/2). The duty cycle of the clock signal 542 may be varied for optimizing the electrical performance. In general terms, however, the length of T₀ cannot be so close to the length of the period T, as time is needed for permitting the signals to stabilize in the capacitors.

Moreover, it is not strictly necessary that all the second switches 514a-514c are opened simultaneously: it is sufficient that they are opened in time for the combiner 424 to receive them.

Accordingly, it is possible to track the plurality of analog input signals values 410a-410c up to different time instants T_I-T₃ and to selectively sample and/or hold the plurality of tracked analog input signals values 510a-510c for different hold time distances. In Fig. 9a, for example, the value 510a is held between the instant T_I and T_O; the value 510b is held between the instant T2 and T_O; and the value 510c is held between the instant T₃ and TO.

As can be seen from Fig. 10a, the lengths of each of the delays ti, T2, t₃ cannot be larger than to: this is because at T_O the second switches 514a-c are closed, and it is accordingly not possible any more to track a value for more time. The time for which a signal value 510a-510c of any of the input signal 410a-410c is held in a hold element 520a-520c is less than the sample interval or larger than a sample interval (or dock period) T.

However, it is possible to address this necessity with the hold stage of Fig. 7, which operates as in Fig. 10b. Each signal line a, b, c is divided among a first signal subline (a1 , b1 , c1) associated to the first stage 720-1 and a second signal subline (a2, b2, c2) associated to the second stage 720-2. Here, reference is only made to the signal line a for conciseness (the same explanation would be repeated for signal lines b and c). The signal line a is here subdivided among a first branch subline a1 (with first switch 712a, capacitor 720a, and second switch 714a), which pertains to the first branch 720- 1 , and a second branch subline a2 (with first switch 713a, capacitor 721 a, and second switch 715a), which pertains to the second branch 720-2. The sublines a1 and a2 may be controlled in alterative fashion. For example, when the first switch 712a of the first subline a1 is closed, the corresponding first switch 713a of the second subline a2 is opened. This effect may be obtained, for example, by adopting the technique shown in Fig. 10c. A control line 442a (meant at controlling both the first switches 712a and 712b) may be biforked into a direct control subline 442a1 which directly controls the first switch 712a, and a second, negated control subline 442a2, which controls the first switch 713a through a NOT connection 1002. A similar strategy may be applied to the clock line 452, which may directly control a second switch 714a, and controlling, a second switch 715a though a NOT connection 1004. The same may be repeated for the second and third signal lines b and c.

With the hold stage 720 of Fig. 7 (e.g., controlled as shown in Fig. 10c), the behaviour at the first signal subline a1 (pertaining to the first stage branch 720-1 ) is shown in the first graph of Fig. 10b, while the behaviour at the second signal subline a2 (pertaining to the second stage branch 720-2) is shown in the second graph. As explained above:

- the first signal subline a1 may be controlled by the direct clock control subline 452a 1 (for controlling the second switch 714a) and by the direct time shift control subline 442a1 (for controlling the delay to be applied to the first switch 712a); and

- the second signal subline a2 may be controlled by the negated clock control subline 452a2 (for controlling the second switch 715a) and by the negated clock control subline 442a2 (for controlling the delay ti’ to be applied to the first switch 712a).

At the time instant 0, the second switch 714a of the first signal subline a1 is closed, while the second switch 715a of the second signal subline a2 is opened. Meanwhile, the first switch 712a of the first signal subline a1 remains closed, and the first switch 713a of the second signal subline a2 remains open.

Hence, after instant 0, the value 710a of the capacitor 720a of the first signal subline a1 tracks the input signal 410a, while the capacitor 721 a of the second signal subline a2 holds a previously obtained value. At instant xi, the first switch 712a of the first signal subline a1 is opened, so that the value of the input signal 410a is stored (held) in the capacitor 720a as value 710a. Hence, ti is the sample instant for the value 710a. Meanwhile, the first switch 712a of the second signal subline a2 is closed, so that the input signal 410a is tracked by the value 711 a the capacitor 721a.

At instant xo, the second switch 714a of the first signal subline a1 is closed. Hence, the value 710a may be output to the combiner stage 424. Meanwhile, the second switch 715a of the second signal subline a2 is opened.

After the delay xi’, the second switch 715a of the second signal subline a2 is closed, while the second switch 714a of the first signal subline a1 is opened. At this instant, the value 71 1 a is sampled at the second signal subline a2. The value 711 a will be provided to the combiner stage 424 after the instant T, i.e., after the second switch 715a of the second signal subline a2 is closed.

It is now to be noted that, while the clock period of the clock signal 542 is T, the sample interval is now T/2: this is because, during one clock cycle, the input signal 410a is sampled twice (once by the first signal subline a1 and once by the second signal subline a2).

Accordingly, it is possible to increase the sampling rate while maintaining the same clock rate.

Moreover, it is possible to have delays (e.g., x-i, t₂, t₃) larger almost as one half of the clock interval T (and larger than the sample interval).

The time lengths of the steps of the clock signals 452 (e.g., from 0 to xo and from xo to T) and of the shift time signals 442 (Fig. 10a) may be of 100 fs or even less.

Combination

Operations, in particular at the combiner 424 (with particular reference to Figs. 6, 9a, 9b), are here explained. At the combiner 424, signals (e.g., the held signals 422a-c) obtained at different signal lines a-c may be combined (e.g., analogically summed, power combined, added to each other, etc.) to obtain one single line which provides a signal 674 (subsequently provided to the output as signal 428). When applying a beamforming technique, this permits to obtain a single value which gives information regarding the wavefront that has reached the antenna elements 402a-c at different time instants.

As shown in Fig. 6, each line a-c comprises none (no gain control) or at least one selectable element 668a-c (which may be a capacitor with selectable capacitance). (A combiner stage without a real-time gain control is also useful, e.g., for a phased array receiver. In some cases, however, an off-line gain control may be implemented anyway in a calibration stage.) The at least one selectable element 668a-c may present a selectable parameter (e.g., selectable capacitance) which may be controlled (e.g., in real time) so as to modify the gain at each line. By modifying the parameter (e.g., capacitance) with respect to a previous storage element (e.g., capacitor 662a~c in Figs. 6 and 9b or capacitor 520a-c in Fig. 9a) the value of the signal may be selectively modified for each spinal line a-c. In the case of using capacitances, the obtained gains follow the relationships between the selected capacitances of the capacitors 668a-668c with the capacitances of the preceding capacitors 662a-662c (or 520a-c in Fig. 9a).

Fig. 10d shows an example of a selectable capacitor 668a which may be selected between a first, low capacitance C 1, and a second, high capacitance C2. In this case, the selectable capacitor 668a may comprise a plurality of capacitors (e.g., 668a1 and 668a2), at least one of which may be selectively activated and deactivated through switches (e.g., 668a3). The capacitors may be in series and/or in parallel to each other. The control of the switches (e.g., 668a3) may be performed by an activation line 441a (which may be part of the gain control line 444 shown in Fig. 4) controlled by the gain control unit 440b. Fig. 10d only shows two capacitors 668a 1 and 668a2, but a multiplicity thereof may be implemented. A permanent capacitor 668a 1 with capacitance C is shown, while a non-permanent capacitor 668a2 (here with capacitance C) is also present (and connectable in parallel). When the capacitor 668a2 is activated (e.g., by closing the switch 668a3), the capacitance of the capacitor 668a is 2C (by virtue of the parallel of the capacitors). When the capacitor 668a2 is deactivated (e.g., by opening the switch 668a3), the capacitance of the capacitor 668a is C (by virtue of the deactivation of the capacitor 668a3). While Fig. 10d shows a parallel of two capacitors with same capacitance C, it is also possible to:

- use capacitors with different capacitances; and/or

- use multiple capacitors; and/or

- use multiple activations/deactivations; and/or

- use series of capacitors or other kinds of connections.

- use different elements (e.g., inductors).

In other cases, it is possible to use different elements, such as inductors, in which the values are stored in currents and not in voltages. Combinations of capacitors and inductors may also be implemented.

The combiner 424 may comprise storage elements (e.g., capacitors) 662a-c, 668a-c, 676 interposed to each other though switches 660a-c, 666a-c, 672a-c. Figs. 9a and 9b show that the switches may be controlled, for example, through the clock line 452. NOT connections 1010 and 1012 may be used for ensuring that two consecutive switches in the same signal line are not simultaneously closed.

The combiner 424 may be understood as operating as a pipeline, in which each value (e.g., 410a-c, 510a-c, 422a-c, 664a-v, 670a-c, 674, 428) (e.g., stored in a storage element such as a capacitor 520a-c, 662a-c, 668a-c, 676) is provided to a subsequent step at the closing of a respective switch (e.g., 660a-c, 666a-c, 672a-c). Notably, the pipeline operation permits to speed up the provision of the signal 428, as the combination of the held signals at the combiner 424 may be performed simultaneously to the holding operations at the hold stage 420.

A step-by-step operation of the combiner stage 424 is now shown with reference to Fig. 6.

At an instant t_6bo, the switches 660a-c are closed, to provide the held stage to a storage element 662a-c (e.g., a capacitor), while the switches 666a-c are open. Therefore, the capacitor 662a-c stores (as charge or voltage) a value associated to the held signal At a subsequent instant X666, the switches 666a-c are closed, to provide the held stage to a storage element 668a-c (e.g., a selectable capacitor with variable capacitance), while the switches 660a-c and 672a-c are opened. Therefore, the capacitor 668a-c stores (as charge or voltage) a value 670a-c associated to the held signal 422a-c. However, the value 670a-c is also subjected to the relationship between the capacitance 668a-c with the capacitance 662a-c of the same signal line (e.g., the capacitors 662a and 668a are now in parallel to each other, and the charge is distributed according to the respective capacitances). Hence, the signal is modified according to a gain as define by the gain-controlled 440b. This is repeated for each of the signal lines a, b, c, even if the gains are not necessarily the same: the gain controller 440b modifies the capacitances of each of the selectable capacitors 672a-672c differently.

At a subsequent instant X672, the switches 666a-c are opened, while the switch 677 is opened. Hence, at the capacitor 676 (which is unique for all the signal lines a, b, c) the charge is obtained as the combination of the charges at the selectable capacitors 672a- 672c. Accordingly, an analog addition (combination) is obtained.

At a subsequent instant X677, the switch 677 is closed and the analog value 428 (resulting from the analog value 674) is provided to the ADC 434 (e.g., through the filter 420).

Downconversion

It has been understood that the present examples may operate to achieve an appropriated downconversion (subsampling) into a reduced frequency, e.g., from RF to a lower frequency (e.g., IF). In this case, up to the hold stage 420, the circuit 460 operates in RF domain; and downstream to the hold stage 420, the circuit 460 may operate in IF domain.

With reference to the hold stage 520 of Fig. 5, by reducing the opening rate of the switches 512a-c and 514a-c (e.g., by reducing the frequency of the time shift control line 442), the sample rate of the values 51 Oa-c will be reduced. Just to give an example, if the delay control unit 440a may define a different period (longer) for the time shift control signal at time shift control line 442. In that case, even if the clock signal maintains its period T (and its clock rate f), the time shift control signal may have a different period (e.g., 10^*T), which causes a reduction of frequency to f/10 (IF).

In order to address this goal, the filters 404a-404c may be defined as passband filters (e.g., around the frequency f), so as to avoid aliasing. In general terms, it is possible to perform an undersampling for performing the downconversion, if there is the bandpass filtering by filters 404a-c.

The hold stage 420 may apply a sample period which is less than twice the maximum signal frequency of the input signal 402a-c, so as to obtain downconversion (e.g., to the IF domain). In this case, the bandpass filters 404a-404c are to be used. To the ADC 434, a reduction of the frequency by a factor N (identified by block 456) may be implemented. For example, if N=10, it means that RF is ten times greater than the IF.

Systems

An application of the circuit arrangement 460 and/or the system 400 is now discussed. The system 400 may be a radar system for ranging a target object. The radar system 400 may, for example, transmit a beam from the antenna array 401 and receive a reflected version of the beam at the antenna array 401. The reflected beam may be embodied by a plurality of signals 403a-c obtained by each antenna element 402a- 402c. The circuit arrangement 460 may provide a digital representation 436 of the reflected beam so that the distance of the target object may be detected (e.g., on the basis of the delay, the intensity, etc.). The system 400 may know the direction of the received reflected beam on the basis of other knowledge (e.g., the direction of the transmitted beam, or another direction obtained by inferring the position of the target object, and/or basis of previous evaluations, and/or on the basis of sensor(s), and /or predefined knowledge and/or signalling etc.) and may adopt particular delays xi, X2, X3, to be applied to the signal lines a, b, c, respectively, at the hold stage 420. The delays xi, X2, X3 may follow the direction of the received reflected signal, so that the lowest delay is awarded to the antenna element which is reached by the beam first, and the longest delay is awarded to the last antenna element reached by the beam. By using appropriate weights (e.g., at the combiner stage 424) the spatial selectivity of the beam may be increased by reducing the unwanted sidelobes. The ranging operated by the system 400 is fast and reliable, and permits an optimal downconversion (if needed) and a preferable gain provision. Notably, the system 400 may be a system for ranging

The same applies to the circuit arrangement 460 and/or the system 400 when referring to a reception of a signal (e.g., for mobile communications, such as LTE, 5G, etc.). Main differences are that, in this case, the received beam is not a reflected beam and in that the digital representation 436 is decoded (e.g., as voice or data stream).

The circuit arrangement 460 and/or the system 400 may be applied in case of communications via cable (not necessarily wireless).

The circuit arrangement 460 and/or the system 400 may be applied to a hybrid beamforming communication system, for example.

Calibration

It is not, in general, ensured that the elements constituting the circuit arrangement 460 ad/or 400 have always their nominal values. While a capacitor may have a nominal capacitance of C, its real value may be within a range of a given percentage (e.g. , 20%). In general terms, this could give non-preferable results. Consequently, the gains provided by the selectable capacitors 670a-670c could be impaired by errors. The same could apply to the circuitry of the delay control unit 440a and of the gain control unit 440b, which may in principle provide incorrect delays n, r_¾ T₃ (the same applies to the clock 450).

It has been understood, however, that it is possible to use calibration techniques for achieving optimal operations. Therefore, a calibration session (to be performed before the normal operations of the system 400 and/or the circuit arrangement 460) may be performed on the basis of test signals with known values. At the calibration session, obtained values 428 and/or 436 may be compared with expected values, so as to adapt values of gains, delays, capacitances, etc., to the particular hardware. During the calibration session, a lookup table, LUT, may be generated, which may be used during the normal operation for using correct values of gains, delays, capacitances, etc. During the calibration session, it is possible to compare the values of the signals at different signal lines (e.g., in case of test signal based on a non-slanted beam arriving at different antenna elements 402a-c simultaneously). If, for example, it is detected that in the hold stage 420 the hold signal 422a is incorrectly delayed more than the hold signals 422b and 422c, this information will be reported into the LUT (e.g., the LUT will have a value of the observed delay impairing the hold signal 422a with respect to the hold signals 422b and 422c). During the subsequent normal operations, the delay n will be increased of a quantity associated to the observed delay (as stored in the LUT).

With similar strategies, also the selectable capacitances of the capacitors 668a-668c may be calibrated.

Methods

Even if the present techniques are mainly discussed in terms of structural features and functional features, it is also possible to implement the invention with different hardware but using method steps which follow the operations presented above. In general terms, it is possible to understand that the blocks above (e.g., the blocks in Fig. 4) may be constituted by functional blocks (which, in some cases, may be independent of the hardware discussed above).

Fig. 8a shows a method 800a which may be performed by equipment and/or functions discussed above and/or below. The method 800a may include at least one of the following steps: one step S420a (e.g., performed by stage 420) to selectively sample and/or hold, in a time-shifted manner, signal values of a plurality of analog input signals values, to obtain held signal values

- one step S424a (e.g., performed by stage 424) to combine the held signal values which are based on the plurality of analog input signals, to obtain a combined signal value, such that the held signal values which are combined in the combiner step represent signal values of the input signals associated with different times - one step S434a (e.g., performed by stage 434) to analog-to-digital convert the combined signal value into a digital representation.

Fig. 8b shows a method 800b which may be performed by equipment and/or functions discussed above and/or below. The method 800b may include at least one of the following steps:

- one step S420b (e.g., performed by stage 420) to selectively sample and/or hold signal values of a plurality of analog input signals values, to obtain held signal values)

- one step S424b (e.g., performed by stage 424) to combine the held signal values which are based on the plurality of analog input signals, selectively using different gains, to obtain a combined signal value, such that the held signal values which are combined by the combiner step represent signal values of the input signals associated with different times

- one step S434b (e.g., performed by stage 434) to analog-to-digital convert the combined signal value into a digital representation.

Storing units

Methods, units, and/or functions as above and/or below may also be implemented, at least for some parts, into instructions stored in a storage unit (e.g., ROM), which, when executed by a processor, cause the processor to control said methods, units, and/or functions.

Discussion

Fig. 4 shows an example of a proposed architecture of direct sampling beamforming receiver (circuit arrangement 460), incorporating a delay-controlled track and hold stage (e.g., at stage 420, 520, 720, 820, etc.) and/or a gain-controlled combiner stage (e.g., 424) prior to a direct sampling analogue to digital converter (ADC) 434. Within the stage 420, 520, 720, 820, etc., the antenna signals 403a-403c (or processed versions thereof such as those indicated with numerals 406a~406c, 410a-410c, etc.) are changed in delay individually, similar to the beamforming network implemented in the RF domain (Fig. 1).

In addition or alternative, the hold stage 424 (track and hold stage) may perform subsampling from the RF domain 485 to into the IF domain 486, such that the hold stage 424 acts as a down-converter. Within the gain-controlled combiner 424 stage the antennas signals (in therein versions 422a-422c) may be changed individually in amplitude before being summed (similar to the beamforming in the RF-domain or IF- domain, as in Figs. 1 and 2). The summed antenna signal 428 is then digitized by an analogue-to-digital converter, ADC, 434 within the IF-domain or RF-domain (depending if the hold stage 420 has reassembled down-conversion or not). At least one of the hold stage 420 and the combiner stage 424 may be based on fast switched-capacitor technology.

Fig. 5 shows a proposed implementation of a delay-controlled hold stage 520 (which may embody the stage 420 of Fig. 4) for an exemplarily number of three antennas 402a, 402b, 402c. The hold stage 520 may be driven by a clock (e.g., clock 450 shown in Fig. 4). The hold stage 520 may implement a sample-and-hold architecture (e.g., a standard sample-and-hold architecture), where (in contrast to the prior art implementations), the clock signal 452 for the first switch could be delayed by a certain value of Ti, which is a fraction of the sample period T. The delay Ti is realized by means of a delay control circuit 440, whereas step sizes of <100fs may be achieved (e.g., using equipment discussed in [3, 4]). If the first switch 512a is closed, the hold element (capacitor) 520a stores the current signal value 510a, which is read out periodically by closing the second switch 514a (whereas the first switch 512a is open). This operation may be performed for the other signals 410b and 410c, as well, wherein different delays T₂ and T3 are selectively chosen. By adjusting the delay values of the switches512a-512c and 514a-514c precisely, the antenna signals 410a-410c may be consequently sampled with certain delay shifts (TI , T₂, T3) and the desired individual delay per each antenna signal may be accomplished. In contrast, with a prior art delay stage, the antenna signals, which impinge the antenna array first, would be delayed by means of additional transmission lines until the last signal has arrived (which is here not present). In the proposed implementation the first signal is sampled first and its signal value is stored until the last signal is also sampled. The delays across the antenna array, introduced by an (slanted) incident wavefront have been compensated for, such that at the power combiner 424 all antenna signals 422a, 422b, 422c add up coherently resulting in maximum received power. With the proposed architecture, a delay of at least one half of the clock period T can be achieved.

If the hold stage 420 (sample and hold stage) is operated with a clock rate of twice the maximum signal frequency the output signals 422a, 422b, 422c remains in the RF domain 485 (hence, the IF domain 486 of Fig. 4 is not reached). If the sample rate is lower than twice the maximum signal frequency, the stage 420 works in subsampling mode and acts as a down-converter to IF domain 485. In this case the antenna signals (in the version of 406a, 406b, 406c) are preferably bandpass-filtered in advance (e.g., at filters 404a, 404b, 404c) to the hold stage 420, to prevent aliasing effects.

Fig. 6 shows an architecture of a combiner stage 424 (e.g., passive gain-controlled combiner circuit). It may work as a multiple sample and hold stage, operating coherently with the clock period T obtained from the clock 450. In the first stage the first switch 660a is closed and the first capacitor 662a“reads” the signal value 422a obtained from the preceding hold stage 420. If then the second switch 666a is closed (whereas the first switch 660a is open), the stored signal value (charge) 664a is distributed between the first capacitor 662a and the second, variable capacitor 668a according to the ratio of the capacitance values of the first and the second capacitors 662a and 668a. Thus, the magnitude of the signal value 670a can be controlled (e.g., diminished) by the ratio of the two capacitances, The variable capacitor 668a can be realized by switching different small capacitors in parallel. In a third step the third switch 672a is closed (whereas the second switch 666a is open and the first switch 660a is closed again). This process is repeated for each of the signals 422a, 422b, and 422c. The stored signal values (voltages) 670a, 670b, 670c of all antenna signals are added up, to obtain a single value 674, in the third, common capacitor 676, which is finally“read” by closing a fourth switch 677. The whole stage is controlled by a digital gain-control block (e.g., 440 in Fig. 4).

Subsequently, the combined signal 428 (e.g., its filtered version 432) may be digitized into discrete magnitude steps by means of a digital-to-analogue converter 434 (Fig. 4). If the hold stage 420 implements down-conversion to a lower IF frequency, the sample- rate of the digital-to-analogue converter could be reduced by a factor of N (see Fig. 4).

The whole setup may be operated as a“pipeline”, whereas signal values (voltages) may proceed from the antenna elements 401 a-401 c to the analogue to digital converter 434 continuously.

Within the digital delay and gain control blocks 420, 424, an appropriate calibration technique may be implemented e.g. by a look-up-table, to ensure, that the given gain and delay values are compensated to the actual hardware imperfections. For that, defined test signals may be used to be applied to the different antenna ports, to enable a measurement of the actual hardware impairments.

The present solution is beneficial compared to the current prior art due to its capability to be integrated in current high-speed CMOS processes and therefore due to its massive cost and power consumption reduction. Furthermore, it enables fully digital control of delay and gain as well it is capable of integrated calibration and compensation procedures. Finally, it leads to an almost complete reduction of analogue RF circuitry by supporting RF or IF sampling, making this approach very versatile with respect to carrier frequency and signal bandwidth and being an implementation of the software- defined radio concept.

Fig. 7 shows an architecture of a hold stage 720 (which may embody the hold stage 420), which may be a delay-controlled sample and hold stage. The hold stage 720 may enable delays being larger than one half of a clock period (e.g., n > T/2) by using two or more hold stages (branches) 720-1 and 720-2 in parallel and driving them time- interleaved (alternating).

The hold stage 420 may perform down-conversion by bandpass-filtering of the antenna signals and by reducing the clock frequency.

Further embodiments and examples

Generally, examples may be implemented as a computer program product with program instructions, the program instructions being operative for performing one of the methods when the computer program product runs on a computer. The program instructions may for example be stored on a machine readable medium.

Other examples comprise the computer program for performing one of the methods described herein, stored on a machine-readable carrier.

In other words, an example of method is, therefore, a computer program having program instructions for performing one of the methods described herein, when the computer program runs on a computer.

A further example of the methods is, therefore, a data carrier medium (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier medium, the digital storage medium or the recorded medium are tangible and/or nontransitionary, rather than signals which are intangible and transitory.

A further example of the method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may for example be transferred via a data communication connection, for example via the Internet.

A further example comprises a processing means, for example a computer, or a programmable logic device performing one of the methods described herein.

A further example comprises a computer having installed thereon the computer program for performing one of the methods described herein.

A further example comprises an apparatus or a system transferring (for example, electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may, for example, be a computer, a mobile device, a memory device or the like. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver.

In some examples, a programmable logic device (for example, a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some examples, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein. Generally, the methods may be performed by any appropriate hardware apparatus. The above described examples are merely illustrative for the principles discussed above. It is understood that modifications and variations of the arrangements and the details described herein will be apparent. It is the intent, therefore, to be limited by the scope of the impending claims and not by the specific details presented by way of description and explanation of the examples herein.

Equal or equivalent elements or elements with equal or equivalent functionality are denoted in the following description by equal or equivalent reference numerals even if occurring in different figures.

References

[1] R. Mendez-Rial, C. Rusu, N. Gonzalez-Prelcic, A. Alkhateeb and R. W. Heath, "Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?," in IEEE Access, vol. 4, no. , pp. 247-267, 2016.

[2] Osth, J.; Karlsson, M.; Serban, A.; Gong, S. "A Comparative Study of Single- Ended vs. Differential Six-Port Modulators for Wireless Communications", Circuits and Systems I: Regular Papers, IEEE Transactions on, On page(s): 564

- 570 Volume: 62, Issue: 2, Feb. 2015.

[3] L. Kull et al., "Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 51 , no. 3, pp. 636-648, March 2016.

[4] M. Brandolini et al., "26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS," 2015 IEEE International Solid-State Circuits Conference

- (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3.

Claims

1. A circuit arrangement (460), comprising:

- a hold stage (420), configured to selectively sample and/or hold, in a time- shifted manner, signal values of a plurality of analog input signals values (410a- 410c), to obtain held signal values (422a-422c);

- a combiner stage (424), configured to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a- 410c), to obtain a combined signal value (428), such that the held signal values (422a- 422c) which are combined by the combiner stage (424) represent signal values of the input signals (410a- 410c) associated with different times (T_I-T₃); and an analog-to-digital converter (434) configured to analog-to-digital convert the combined signal (428) value into a digital representation (436).

2. A circuit arrangement (460), comprising:

- a hold stage (420), configured to selectively sample and/or hold signal values of a plurality of analog input signals values (410a- 410c), to obtain held signal values (422a- 422c);

a combiner stage (424), configured to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a-410c), selectively using different gains, to obtain a combined signal value (428), such that the held signal values (422a-422c) which are combined by the combiner stage (424) represent signal values of the input signals (410a- 410c) associated with different times (T_I-T₃); and

- an analog-to-digital converter (434) configured to analog-to-digital convert the combined signal (428) value into a digital representation (436).

3. The circuit arrangement (460) of any of claims 1 and 2, wherein the hold stage (420, 720, 520) is configured to track the plurality of analog input signals values (410a- 410c) up to different time instants (T_I-T₃) and to selectively hold the plurality of tracked analog input signals values (510a-510c, 710a-710c, 711 a-711c) for different hold time distances.

4. The circuit arrangement (460) of any of the preceding claims, wherein the hold stage (420, 520, 720) is configured to obtain a plurality of samples (510a-510c, 710a- 710c, 711 a-71 1 c) from the plurality of analog input signals (410a-410c) at different times (T1-T3) and to selectively hold the plurality of obtained samples (510a-510c, 710a- 710c, 711 a-71 1 c) for different hold time distances.

5. The circuit arrangement (460) of any of the preceding claims, wherein the hold stage (720) is configured so that the time for which a signal value (710a, 711a) of a given input signal (410a) is held in a hold element (720a, 721 a) is longer than half of the sample interval or longer than a sample interval.

6. The circuit arrangement (460) of any of the preceding claims, wherein the hold stage (720) includes a plurality of hold elements (720a, 721 a) for each input signal (410a), wherein the hold elements (720a, 721 a) of the same plurality are coupled to the respective input signal (410a) in an alternating manner and vice versa.

7. The circuit arrangement (460) of claim 6, wherein a first and a second hold elements (720a, 721 a) of the same plurality are coupled to a time shift control line (442), wherein one of the first and second hold elements (720a, 721 a) is directly controlled by the time shift control line (442), and the other one of the first and/or second hold elements (720a, 721 a) is controlled by the time shift control line (442) through a NOT connection (1002, 1004).

8. The circuit arrangement of any of the preceding claims, wherein the hold stage (420, 520, 720) includes at least one capacitor (520a, 720a, 721 a) operating as hold element for holding a respective input signal value (510a, 710a, 71 1 a).

9. The circuit arrangement of any of the preceding claims, wherein the hold stage (420, 520, 720) comprises at least one first switch (512a, 712a, 713a) for selectively obtaining a respective input signal (410a) and/or for selectively holding the respective input signal (410a).

10. The circuit arrangement of any of the preceding claims, wherein the hold stage (420) comprises at least one second switch (514a, 714a, 715a) for selectively providing the held signal values (510a, 710a, 711a) towards the combiner stage (424) and/or for selectively holding the respective input signal (410a).

11. The circuit arrangement of any of the preceding claims, further comprising at least one time shift control line (442), configured to provide at least one hold signal (442a-442c) for each of the plurality of analog input signals (410a- 410c), for selectively shifting or delaying the different times (T1-T3) at which the signal values (510a-510c) of the input signals (410a-410c) are to be held and/or sampled.

12. The circuit arrangement of claim 1 1 , wherein the at least one time shift control line (442) is an adjustable delay line to provide at least one hold signal for selectively shifting or delaying the different times (T1-T3) at which the signal values (510a-510c) of the input signals (410a-410c) are to be held.

13. The circuit arrangement of claim 11 or 12, wherein the at least one time shift control line (442) is controlled so as to adjust the time shifting in accordance with a desired antenna beam direction.

14. The arrangement of any of the preceding claims, wherein the at least one time shift control line (442) is controlled so that the held signal values (510a-510c) are sampled at different time instants and/or held for different hold time distances associated to the different timing arrivals of wavelength signals which have arrived at antenna elements (402a-402c) or an antenna array (401).

15. The arrangement of any of the preceding claims, wherein the hold stage (420) is configured to provide at least two held values (422a-422c) per period of the maximum-frequency component of the input signal (410a-410c).

16. The arrangement of any of the preceding claims, wherein the hold stage (420) is configured to selectively provide less than two held values (422a-422c) per period of the of the input signal (410a-410c).

17. The arrangement of any of the preceding claims, further comprising a bandpass filter (404a-404c) for bandpass filtering the input signal (403a-403c) so as to provide a bandpass-filtered input signal (410a-410c) as the input signal for the hold stage (420).

18. The arrangement of any of the preceding claims, further configured to perform an under-sampling (404a-404c) of the input signal (403a-403c) so as to provide an under-sampled input signal version (410a-410c) of the input signal to the hold stage (420).

19. The circuit arrangement of any of the preceding claims, wherein the combiner stage (424) is configured to combine the held signal values (422a-422c) by summing the held signal values (422a-422c) selectively using different gains.

20. The circuit arrangement of any of the preceding claims, wherein each of the gains is < 1.

21. The circuit arrangement of any of the preceding claims, wherein the combiner stage (424) includes, for a determined held signal (422a), at least one selectable element (668a) with a selectable electric parameter which controls the gain.

22. The circuit arrangement of claim 21 , wherein the at least one selectable element (668a-c) includes a selectable capacitor with selectable capacitance to control the gain.

23. The circuit arrangement of claim 21 or 22, wherein the at least one selectable element (668a) includes a plurality of capacitors selectively connectable in series and/or in parallel with each other to select a capacitance which controls the gain.

24. The circuit arrangement of any of claims 21-23, further comprising at least one fixed-parameter element (662a) selectively connectable to and disconnectable from: an input from the hold stage (420), so as to obtain the held signal value (422a); and

the at least one selectable element (668a), so as to weight the held signal value (422a) through the selected electric parameter of the at least one selectable element (668a).

25. The circuit arrangement of any of claims 21-24, wherein the at least one selectable element (668a) selectively connectable to and disconnectable from:

an input from the hold stage (420), so as to obtain the held signal value (422a); and

26. The circuit arrangement of any of claims 21-25, wherein the at least one selectable element (668a) is selectively connectable to and disconnectable from: a combiner element (676), so as to provide a weighted version (670a) of the held signal value (422a) to the combiner element (676) by combining a plurality of weighted held signals.

27. A method comprising: a hold step to selectively sample and/or hold, in a time-shifted manner, signal values of a plurality of analog input signals values (410a-410c), to obtain held signal values (422a-422c);

a combiner step, to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a- 410c), to obtain a combined signal value (428), such that the held signal values (422a-422c) which are combined in the combiner step represent signal values of the input signals (410a- 410c) associated with different times (T1-T3).

28. A method comprising:

a hold step, to selectively sample and/or hold signal values of a plurality of analog input signals values (410a- 410c), to obtain held signal values (422a- 422c);

a combiner step, to combine the held signal values (422a- 422c) which are based on the plurality of analog input signals (410a-410c), selectively using different gains, to obtain a combined signal value (428), such that the held signal values (422a-422c) which are combined by the combiner step (424) represent signal values of the input signals (410a- 410c) associated with different times (TI-T₃).

29. A non-transitory storage unit storing instructions which, when executed by a processor, cause the processor to perform the method of claim 27 or 28.