WO2020238704A1 - Method for multiplexing earphone seat and usb otg function - Google Patents
Method for multiplexing earphone seat and usb otg function Download PDFInfo
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- WO2020238704A1 WO2020238704A1 PCT/CN2020/091116 CN2020091116W WO2020238704A1 WO 2020238704 A1 WO2020238704 A1 WO 2020238704A1 CN 2020091116 W CN2020091116 W CN 2020091116W WO 2020238704 A1 WO2020238704 A1 WO 2020238704A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
- H04R1/1041—Mechanical or electronic switches, or control elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R2201/00—Details of transducers, loudspeakers or microphones covered by H04R1/00 but not provided for in any of its subgroups
- H04R2201/10—Details of earpieces, attachments therefor, earphones or monophonic headphones covered by H04R1/10 but not provided for in any of its subgroups
Definitions
- the present invention relates to the technical field of OTG functions, and in particular to a method for using an earphone socket and USB OTG function multiplexing.
- USB Universal Serial Bus
- USB Universal Serial Bus
- a plug with a plug on one side and a receptacle on the other.
- a socket on a computer is a female connector
- a USB device uses a male connector to connect to the computer.
- USB hardware interfaces There are currently three types of USB hardware interfaces. The type used on ordinary computers is called Type; the original interface used in Nokia's feature phone era is Mini USB; and the current Micro USB used in Android phones.
- USB OTG is the abbreviation of USB On-The-Go, which is a technology developed in recent years. On The Go, this is a form introduced in USB 2.0, and a new concept called Host Negotiation Protocol (Host Negotiation Protocol) is proposed, which allows two devices to negotiate who will be the Host.
- the OTG controller can be used as a host or a device. The role of the controller is generally determined by the USB ID level.
- USB socket is reserved only for the earphone holder, which cannot realize the USB software burning, and the USB OTG function cannot be used during debugging.
- the industry's approach is to increase the miniUSB or mircoUSB interface, so the use cost is high, not to promote.
- a method of using the headset socket and USB OTG function multiplexing including:
- Step S1 Provide a multiplexing circuit, and the multiplexing circuit is respectively connected to a headphone holder and a control chip;
- Step S2 The control chip is used to detect the level state of the earphone holder, and the external device inserted into the earphone holder is determined through the multiplexing circuit.
- the multiplexing circuit further includes a switching unit, and the switching unit is respectively connected to the control chip and the earphone holder.
- the earphone holder includes:
- a first pin connected to a first power terminal
- a second pin connected to the right channel power terminal of the switching unit
- a third pin connected to the first data pin of the control chip through a first resistor
- a fourth pin connected to the left channel power terminal of the switching unit
- a fifth pin connected to the ground terminal.
- control chip includes:
- a first data pin which is used to implement the earphone detection pin
- a second data pin used to implement USB audio switching pins
- a third data pin used to realize the USB power pin
- One data acquisition pin used to realize USB audio detection pin
- An ID pin used to implement the USB ID pin
- a data negative signal pin used to realize the USB OTG negative voltage pin
- One data positive signal pin used to realize the USB OTG positive voltage pin
- An audio second output pin used to implement the audio right channel.
- the switching unit further includes:
- a first switching pin connected to the second data pin
- a positive voltage terminal connected to the data positive signal pin
- a negative voltage terminal connected to the data negative signal pin
- a left channel pin connected to the first audio output pin
- a right channel pin is connected to the second audio output pin.
- the multiplexing circuit includes:
- a first power terminal providing a first power voltage
- a second power terminal providing a second power voltage
- a third power supply terminal providing a third power supply voltage
- a fourth power supply terminal providing a fourth power supply voltage
- a multiplexing unit is respectively connected to the first voltage terminal, the second power terminal, the third power terminal, the fourth voltage terminal, the control chip and the earphone socket between.
- the multiplexing unit includes:
- a triode the emitter of the triode is connected to the third data pin, and the base of the triode is connected to the second voltage terminal through a second resistor;
- a MOS tube the gate of the MOS tube is connected to the collector of the triode through a third resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the earphone
- the first pin of the socket
- a fourth resistor connected between the fourth power terminal and the data acquisition pin through a diode
- a fifth resistor connected between the first pin of the earphone socket and the data collection pin
- a sixth resistor connected between the data acquisition pin and the ground terminal
- a seventh resistor connected between the third power terminal and the collector of the triode
- a ninth resistor connected between the first data pin and the second power terminal
- a tenth resistor connected between the fourth pin of the earphone holder and the ground terminal;
- a first capacitor connected between the first power terminal and the ground terminal
- a second capacitor is connected between the third power terminal and the gate of the MOS transistor.
- the step S2 includes:
- Step S20 Judge whether the first data pin has a level change, and when the first data pin has a level change, go to step S21;
- Step S21 Detect the voltage value of the data collection pin to determine the external device inserted into the earphone socket.
- step S21 when it is detected that the voltage value of the data collection pin is a first preset value, it is determined that the earphone socket is inserted into the earphone cable;
- the first preset value is 0.64V;
- the second preset value is 0.80V
- the third preset value is 1.67V.
- the beneficial effect of the technical solution of the present invention is to provide a method for multiplexing the functions of the earphone socket and USB OTG.
- the control chip is used to detect the level state of the earphone socket, and the external equipment inserted into the earphone socket is determined by the multiplexing circuit. Communicate and connect with earphone cable, USB host device, and USB external device to realize the multiplexing of earphone function and OTG function.
- the circuit structure is simple, which is convenient for software engineers to debug and promote.
- FIG. 1 is a flowchart of steps of a method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention
- step S2 is a flowchart of step S2 of the method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention
- Fig. 3 is a circuit connection diagram of the multiplexing circuit of the embodiment of the present invention.
- the present invention includes a method for multiplexing the functions of an earphone holder and USB OTG, including:
- Step S1 Provide a multiplexing circuit, which is connected to an earphone jack AJ1 and a control chip SOC respectively;
- Step S2 The control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is determined through the multiplexing circuit.
- control chip SOC can be used as a host device or an external device.
- the role of the control chip SOC is generally determined by the level of the USB ID.
- USB ID is the input signal, defined by the USB OTG protocol, and used to identify the default role of the device connected to the headset jack AJ1, that is, host mode or external device mode.
- the USB ID is pulled up by default and is in the state of an external device. If the headphone jack AJ1 needs to be in host mode, the control chip 3 will short USB_ID to the ground, that is, when the input is 0, it means that the headphone jack AJ1 is in host mode and communicates with USB external devices.
- control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function.
- Multiplexing with OTG functions simple circuit structure, convenient for software engineers to debug and promote.
- the multiplexing circuit further includes a switching unit U1, and the switching unit U1 is respectively connected to the control chip SOC and the earphone socket AJ1.
- the switching unit U1 further includes:
- a first switching pin ASEL connected to the second data pin GPIOA_1;
- a positive voltage terminal D+ connected to the data positive signal pin USB_DP;
- a negative voltage terminal D- connected to the data negative signal pin USB_DM;
- One left channel pin L connected to the first audio output pin AUDIO_L;
- a right channel pin R is connected to the second audio output pin AUDIO_R.
- control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
- the earphone holder AJ1 includes:
- a first pin AJ10 is connected to a first power terminal S1;
- a second pin AJ11 connected to the right channel power terminal DR+ of the switching unit U1;
- a third pin AJ12 is connected to the first data pin GPIOA_0 of the control chip SOC through a first resistor R1;
- a fourth pin AJ13 connected to the left channel power terminal DL- of the switching unit U1;
- a fifth pin AJ14 is connected to the ground terminal GND.
- the resistance value of the first resistor R1 is 1K ohms
- the control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is judged by the multiplexing circuit, which can be connected to the earphone cable and USB
- the host device and the USB external device are connected for communication to realize the multiplexing of the earphone function and the OTG function.
- the circuit structure is simple, which is convenient for software engineers to debug and promote.
- control chip SOC includes:
- a first data pin GPIOA_0 used to implement the headphone detection pin HP_DET;
- a data acquisition pin SARADC_CH0 used to realize the USB audio detection pin USB_AUDIO_DET;
- USB_ID used to implement the USB ID pin USB_ID
- USB_DM used to realize the USB OTG negative voltage pin USB OTG_B_DM
- USB_DP used to realize the USB OTG positive voltage pin USB OTG_B_DP;
- An audio first output pin AUDIO_L used to realize the left audio channel AUDIO_L;
- An audio second output pin AUDIO_R is used to implement the audio right channel AUDIO_R.
- the first data pin GPIOA_0 is used to detect the level state of the headphone detection pin HP_DET.
- the first data pin GPIOA_0 detects the level state of the headphone detection pin HP_DET from low to high, it means The headphone detection pin HP_DET has an external device inserted, and then the data acquisition pin SARADC_CH0 detects the voltage value of the USB audio detection pin USB_AUDIO_DET.
- the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.64V, it means that the headphone cable is inserted.
- USB_AUDIO_DET When the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.80V, it means that the USB host device is inserted, and when the voltage value of the USB audio detection pin USB_AUDIO_DET is 1.67V, it means that the USB external device is inserted.
- control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function.
- Multiplexing with OTG functions simple circuit structure, convenient for software engineers to debug and promote.
- the multiplexing circuit includes:
- a second power supply terminal S2 providing a second power supply voltage VCC2;
- a fourth power supply terminal S4 providing a fourth power supply voltage VCC4;
- a multiplexing unit is respectively connected between the first voltage terminal S1, the second power terminal S2, the third power terminal S3, the fourth voltage terminal S4, the control chip SOC and the earphone socket AJ1.
- the first power supply voltage VCC1 is 5V
- the second power supply voltage VCC2 is 3.3V
- the third power supply voltage VCC3 is 5V
- the fourth power supply voltage VCC4 is 1.8V.
- the multiplexing unit includes:
- a triode Q1 the emitter of the triode Q1 is connected to the third data pin GPIOA_2, and the base of the triode Q1 is connected to the second voltage terminal S2 through a second resistor R2;
- a MOS tube Q2 the gate of the MOS tube Q2 is connected to the collector of the transistor Q1 through a third resistor R3, the source of the MOS tube Q2 is connected to the third power terminal S3, and the drain of the MOS tube Q2 is connected to the first terminal of the earphone socket AJ1 Pin AJ10;
- a fourth resistor R4 is connected between the fourth power terminal S4 and the data acquisition pin SARADC_CH0 through a diode D1;
- a seventh resistor R7 connected between the third power terminal S3 and the collector of the transistor Q1;
- a ninth resistor R9 connected between the first data pin GPIOA_0 and the second power terminal S2;
- a tenth resistor R10 connected between the fourth pin AJ13 of the earphone jack AJ1 and the ground terminal GND;
- a first capacitor C1 connected between the first power terminal S1 and the ground terminal GND;
- a second capacitor C2 is connected between the third power terminal S3 and the gate of the MOS transistor Q1.
- the transistor Q1 is an NPN transistor
- the MOS transistor Q2 is an N-type MOS transistor
- the resistance value of the second resistor R2 is 47K ohms
- the resistance value of the third resistor R3 is 100K ohms
- the resistance value of the fourth resistor R4 is 10K.
- the resistance of the fifth resistor R5 is 20K ohms
- the resistance of the sixth resistor R6 is 10K ohms
- the resistance of the seventh resistor R7 is 47K ohms
- the resistance of the eighth resistor R8 is 10K ohms
- the resistance of the ninth resistor R9 The resistance value of is 10K ohms, where the fourth resistor R4 and the sixth resistor R6 form a voltage divider resistor, connected to GPIOA_1 from the voltage divider node, the capacitance value of the first capacitor C1 is 22uF, and the capacitance value of the second capacitor C2 is 0.1uF .
- step S2 includes:
- Step S20 Judge whether the first data pin GPIOA_0 has a level change, and when the first data pin GPIOA_0 has a level change, go to step S21;
- Step S21 Detect the voltage value of the data collection pin SARADC_CH0 to determine the external device inserted into the earphone jack AJ1.
- step S21 when it is detected that the voltage value of the data collection pin SARADC_CH0 is a first preset value, it is determined that the earphone jack AJ1 is inserted into the earphone cable;
- the first preset value is 0.64V
- the second preset value is 0.80V
- the third preset value is 1.67V.
- the third pin AJ3 of the headphone socket AJ1 is grounded when the headphone cable is inserted.
- the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER to turn off the transistor Q1, and the MOS transistor Q2 is also turned off.
- the third pin AJ3 of the headphone holder AJ1 is in a floating state when the USB host device is inserted.
- the third data pin GPIOA_2 outputs a low-level USB power pin USB_POWER to turn on the transistor Q1, and the MOS tube Q2 also turns on the first power terminal S1 at this time.
- the first pin of the socket AJ1 which is the connected power pin USBOTG_B_5V, outputs a 5V voltage.
- the third pin AJ3 of the earphone holder AJ1 is in an external 5V state.
- the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER turns off the transistor Q1, and the MOS tube Q2 turns off the first power terminal S1 at this time.
- the first pin of AJ1 the connected power pin USBOTG_B_5V has no output, the ID pin USB_ID pulls up the USB power pin USB_POWER through the eighth resistor R8 to input high level, and the second data pin GPIOA_1 outputs low level USB audio
- control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
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Abstract
Description
Claims (10)
- 一种使用耳机座与USB OTG功能复用的方法,其特征在于,包括:A method for using a headset socket and USB OTG function multiplexing, which is characterized in that it includes:步骤S1、提供一复用电路,所述复用电路分别连接一耳机座及一控制芯片;Step S1: Provide a multiplexing circuit, and the multiplexing circuit is respectively connected to an earphone holder and a control chip;步骤S2、采用所述控制芯片检测所述耳机座的电平状态,通过所述复用电路判断出插入所述耳机座的外接设备。Step S2: Use the control chip to detect the level state of the earphone holder, and determine the external device inserted into the earphone holder through the multiplexing circuit.
- 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用电路还包括一切换单元,所述切换单元分别连接所述控制芯片与所述耳机座。The method for multiplexing the functions of an earphone socket and USB OTG according to claim 1, wherein the multiplexing circuit further comprises a switching unit, and the switching unit is respectively connected to the control chip and the earphone socket.
- 根据权利要求2所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述耳机座包括:The method for using the earphone socket and USB OTG function multiplexing according to claim 2, wherein the earphone socket comprises:一第一引脚,连接一第一电源端;A first pin connected to a first power terminal;一第二引脚,连接所述切换单元的右通道电源端;A second pin connected to the right channel power terminal of the switching unit;一第三引脚,通过一第一电阻连接所述控制芯片的第一数据引脚;A third pin connected to the first data pin of the control chip through a first resistor;一第四引脚,连接所述切换单元的左通道电源端;A fourth pin connected to the left channel power terminal of the switching unit;一第五引脚,连接接地端。A fifth pin, connected to the ground terminal.
- 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述控制芯片包括:The method for using the headset socket and USB OTG function multiplexing according to claim 1, wherein the control chip comprises:一第一数据引脚,用于实现耳机检测引脚;A first data pin, which is used to implement the earphone detection pin;一第二数据引脚,用于实现USB音频切换引脚;A second data pin, used to implement USB audio switching pins;一第三数据引脚,用于实现USB电源引脚;A third data pin, used to realize the USB power pin;一数据采集引脚,用于实现USB音频检测引脚;One data acquisition pin, used to realize USB audio detection pin;一ID引脚,用于实现USB ID引脚;An ID pin, used to realize the USB ID pin;一数据负信号引脚,用于实现USB OTG负电压引脚;A data negative signal pin, used to realize the USB OTG negative voltage pin;一数据正信号引脚,用于实现USB OTG正电压引脚;One data positive signal pin, used to realize the USB OTG positive voltage pin;一音频第一输出引脚,用于实现音频左通道;An audio first output pin for realizing the left audio channel;一音频第二输出引脚,用于实现音频右通道。An audio second output pin, used to implement the audio right channel.
- 根据权利要求4所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述切换单元还包括:The method for using the headset socket and USB OTG function multiplexing according to claim 4, wherein the switching unit further comprises:一第一切换引脚,连接所述第二数据引脚;A first switching pin connected to the second data pin;一正电压端,连接所述数据正信号引脚;A positive voltage terminal connected to the data positive signal pin;一负电压端,连接所述数据负信号引脚;A negative voltage terminal connected to the data negative signal pin;一左通道引脚,连接所述音频第一输出引脚;A left channel pin connected to the first audio output pin;一右通道引脚,连接所述音频第二输出引脚。A right channel pin is connected to the second audio output pin.
- 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用电路包括:The method for multiplexing the functions of an earphone holder and USB OTG according to claim 1, wherein the multiplexing circuit comprises:一第一电源端,提供一第一电源电压;A first power terminal, providing a first power voltage;一第二电源端,提供一第二电源电压;A second power terminal providing a second power voltage;一第三电源端,提供一第三电源电压;A third power supply terminal, providing a third power supply voltage;一第四电源端,提供一第四电源电压;A fourth power supply terminal, providing a fourth power supply voltage;一复用单元,所述复用单元分别连接于所述第一电压端、所述第二电源端、所述第三电源端、所述第四电压端、所述控制芯片及所述耳机座之间。A multiplexing unit, the multiplexing unit is respectively connected to the first voltage terminal, the second power terminal, the third power terminal, the fourth voltage terminal, the control chip and the earphone socket between.
- 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用单元包括:The method for multiplexing the functions of a headset and USB OTG according to claim 6, wherein the multiplexing unit comprises:一三极管,所述三极管的发射极连接所述第三数据引脚,所述三极管的基极通过一第二电阻连接所述第二电压端;A triode, the emitter of the triode is connected to the third data pin, and the base of the triode is connected to the second voltage terminal through a second resistor;一MOS管,所述MOS管的栅极通过一第三电阻连接所述三极管的集电极,所述MOS管的源极连接所述第三电源端,所述MOS管的漏极连接所述耳机座的第一引脚;A MOS tube, the gate of the MOS tube is connected to the collector of the triode through a third resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the earphone The first pin of the socket;一第四电阻,通过一二极管连接于所述第四电源端与所述数据采集引脚之间;A fourth resistor, connected between the fourth power terminal and the data acquisition pin through a diode;一第五电阻,连接于所述耳机插座的第一引脚与所述数据采集引脚之间;A fifth resistor connected between the first pin of the earphone socket and the data collection pin;一第六电阻,连接于所述数据采集引脚与接地端之间;A sixth resistor connected between the data collection pin and the ground terminal;一第七电阻,连接于所述第三电源端与所述三极管的集电极之间;A seventh resistor connected between the third power terminal and the collector of the triode;一第八电阻,连接于所述ID引脚与所述三极管的发射极之间;An eighth resistor, connected between the ID pin and the emitter of the triode;一第九电阻,连接于所述第一数据引脚与所述第二电源端之间;A ninth resistor connected between the first data pin and the second power terminal;一第十电阻,连接于所述耳机座的第四引脚与接地端之间;A tenth resistor, connected between the fourth pin of the earphone holder and the ground terminal;一第一电容,连接于所述第一电源端与接地端之间;A first capacitor connected between the first power terminal and the ground terminal;一第二电容,连接于所述第三电源端与所述MOS管的栅极之间。A second capacitor is connected between the third power terminal and the gate of the MOS transistor.
- 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述步骤S2包括:The method for using the headset socket and USB OTG function multiplexing according to claim 6, wherein the step S2 comprises:步骤S20、判断所述第一数据引脚是否有电平变化,并在所述第一数据引脚有电平变化时转向步骤S21;Step S20: Judge whether the level of the first data pin changes, and when the level of the first data pin changes, go to step S21;步骤S21、检测所述数据采集引脚的电压值,以判断出所述耳机座插入的外接设备。Step S21: Detect the voltage value of the data collection pin to determine the external device inserted into the earphone socket.
- 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,于所述步骤S21中,检测所述数据采集引脚的电压值为一第一预设值时,判断出所述耳机座插入耳机线;The method for using the earphone socket and USB OTG function multiplexing according to claim 6, wherein in the step S21, when the voltage value of the data collection pin is detected as a first preset value, it is determined Insert the earphone cable out of the earphone socket;检测所述数据采集引脚的电压值为一第二预设值时,判断出所述耳机座插入USB主机设备;When detecting that the voltage value of the data collection pin is a second preset value, it is determined that the earphone holder is inserted into the USB host device;检测所述数据采集引脚的电压值为一第三预设值时,判断出所述耳机座插入USB外接设备。When detecting that the voltage value of the data collection pin is a third preset value, it is determined that the earphone holder is inserted into a USB external device.
- 根据权利要求9所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述第一预设值为0.64V;The method for using a headset socket and USB OTG function multiplexing according to claim 9, wherein the first preset value is 0.64V;所述第二预设值为0.80V;The second preset value is 0.80V;所述第三预设值为1.67V。The third preset value is 1.67V.
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CN201910452656.XA CN110312180A (en) | 2019-05-28 | 2019-05-28 | A method of using earphone base and USB OTG multiplexing functions |
CN201910452656.X | 2019-05-28 |
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PCT/CN2020/091116 WO2020238704A1 (en) | 2019-05-28 | 2020-05-19 | Method for multiplexing earphone seat and usb otg function |
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CN110312180A (en) * | 2019-05-28 | 2019-10-08 | 晶晨半导体(上海)股份有限公司 | A method of using earphone base and USB OTG multiplexing functions |
Citations (4)
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CN104035357A (en) * | 2014-06-27 | 2014-09-10 | 广东欧珀移动通信有限公司 | Headset, charging and OTG equipment circuit design based on USB socket |
CN105635885A (en) * | 2016-03-21 | 2016-06-01 | 青岛海信移动通信技术股份有限公司 | USB interface multiplex circuit, mobile terminal and earphone |
US20170271894A1 (en) * | 2016-03-21 | 2017-09-21 | Microsoft Technology Licensing, Llc | Regulating charging port attach and detach |
CN110312180A (en) * | 2019-05-28 | 2019-10-08 | 晶晨半导体(上海)股份有限公司 | A method of using earphone base and USB OTG multiplexing functions |
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CN105573946B (en) * | 2016-03-01 | 2019-03-01 | Oppo广东移动通信有限公司 | The method and device of Universal Serial Bus Interface multiplexing |
CN206975633U (en) * | 2017-06-27 | 2018-02-06 | 深圳市有方科技股份有限公司 | A kind of multiplex circuit of OTG, USB function |
CN109039316A (en) * | 2018-10-17 | 2018-12-18 | 歌尔科技有限公司 | Earphone jack multiplex circuit, method and intelligent wearable device |
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- 2019-05-28 CN CN201910452656.XA patent/CN110312180A/en active Pending
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Publication number | Priority date | Publication date | Assignee | Title |
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CN104035357A (en) * | 2014-06-27 | 2014-09-10 | 广东欧珀移动通信有限公司 | Headset, charging and OTG equipment circuit design based on USB socket |
CN105635885A (en) * | 2016-03-21 | 2016-06-01 | 青岛海信移动通信技术股份有限公司 | USB interface multiplex circuit, mobile terminal and earphone |
US20170271894A1 (en) * | 2016-03-21 | 2017-09-21 | Microsoft Technology Licensing, Llc | Regulating charging port attach and detach |
CN110312180A (en) * | 2019-05-28 | 2019-10-08 | 晶晨半导体(上海)股份有限公司 | A method of using earphone base and USB OTG multiplexing functions |
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