WO2020238704A1 - Method for multiplexing earphone seat and usb otg function - Google Patents

Method for multiplexing earphone seat and usb otg function Download PDF

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Publication number
WO2020238704A1
WO2020238704A1 PCT/CN2020/091116 CN2020091116W WO2020238704A1 WO 2020238704 A1 WO2020238704 A1 WO 2020238704A1 CN 2020091116 W CN2020091116 W CN 2020091116W WO 2020238704 A1 WO2020238704 A1 WO 2020238704A1
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Prior art keywords
pin
usb
earphone
data
multiplexing
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PCT/CN2020/091116
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French (fr)
Chinese (zh)
Inventor
陈斯伟
张坤
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晶晨半导体(上海)股份有限公司
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Publication of WO2020238704A1 publication Critical patent/WO2020238704A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00Details of transducers, loudspeakers or microphones
    • H04R1/10Earpieces; Attachments therefor ; Earphones; Monophonic headphones
    • H04R1/1041Mechanical or electronic switches, or control elements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2201/00Details of transducers, loudspeakers or microphones covered by H04R1/00 but not provided for in any of its subgroups
    • H04R2201/10Details of earpieces, attachments therefor, earphones or monophonic headphones covered by H04R1/10 but not provided for in any of its subgroups

Definitions

  • the present invention relates to the technical field of OTG functions, and in particular to a method for using an earphone socket and USB OTG function multiplexing.
  • USB Universal Serial Bus
  • USB Universal Serial Bus
  • a plug with a plug on one side and a receptacle on the other.
  • a socket on a computer is a female connector
  • a USB device uses a male connector to connect to the computer.
  • USB hardware interfaces There are currently three types of USB hardware interfaces. The type used on ordinary computers is called Type; the original interface used in Nokia's feature phone era is Mini USB; and the current Micro USB used in Android phones.
  • USB OTG is the abbreviation of USB On-The-Go, which is a technology developed in recent years. On The Go, this is a form introduced in USB 2.0, and a new concept called Host Negotiation Protocol (Host Negotiation Protocol) is proposed, which allows two devices to negotiate who will be the Host.
  • the OTG controller can be used as a host or a device. The role of the controller is generally determined by the USB ID level.
  • USB socket is reserved only for the earphone holder, which cannot realize the USB software burning, and the USB OTG function cannot be used during debugging.
  • the industry's approach is to increase the miniUSB or mircoUSB interface, so the use cost is high, not to promote.
  • a method of using the headset socket and USB OTG function multiplexing including:
  • Step S1 Provide a multiplexing circuit, and the multiplexing circuit is respectively connected to a headphone holder and a control chip;
  • Step S2 The control chip is used to detect the level state of the earphone holder, and the external device inserted into the earphone holder is determined through the multiplexing circuit.
  • the multiplexing circuit further includes a switching unit, and the switching unit is respectively connected to the control chip and the earphone holder.
  • the earphone holder includes:
  • a first pin connected to a first power terminal
  • a second pin connected to the right channel power terminal of the switching unit
  • a third pin connected to the first data pin of the control chip through a first resistor
  • a fourth pin connected to the left channel power terminal of the switching unit
  • a fifth pin connected to the ground terminal.
  • control chip includes:
  • a first data pin which is used to implement the earphone detection pin
  • a second data pin used to implement USB audio switching pins
  • a third data pin used to realize the USB power pin
  • One data acquisition pin used to realize USB audio detection pin
  • An ID pin used to implement the USB ID pin
  • a data negative signal pin used to realize the USB OTG negative voltage pin
  • One data positive signal pin used to realize the USB OTG positive voltage pin
  • An audio second output pin used to implement the audio right channel.
  • the switching unit further includes:
  • a first switching pin connected to the second data pin
  • a positive voltage terminal connected to the data positive signal pin
  • a negative voltage terminal connected to the data negative signal pin
  • a left channel pin connected to the first audio output pin
  • a right channel pin is connected to the second audio output pin.
  • the multiplexing circuit includes:
  • a first power terminal providing a first power voltage
  • a second power terminal providing a second power voltage
  • a third power supply terminal providing a third power supply voltage
  • a fourth power supply terminal providing a fourth power supply voltage
  • a multiplexing unit is respectively connected to the first voltage terminal, the second power terminal, the third power terminal, the fourth voltage terminal, the control chip and the earphone socket between.
  • the multiplexing unit includes:
  • a triode the emitter of the triode is connected to the third data pin, and the base of the triode is connected to the second voltage terminal through a second resistor;
  • a MOS tube the gate of the MOS tube is connected to the collector of the triode through a third resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the earphone
  • the first pin of the socket
  • a fourth resistor connected between the fourth power terminal and the data acquisition pin through a diode
  • a fifth resistor connected between the first pin of the earphone socket and the data collection pin
  • a sixth resistor connected between the data acquisition pin and the ground terminal
  • a seventh resistor connected between the third power terminal and the collector of the triode
  • a ninth resistor connected between the first data pin and the second power terminal
  • a tenth resistor connected between the fourth pin of the earphone holder and the ground terminal;
  • a first capacitor connected between the first power terminal and the ground terminal
  • a second capacitor is connected between the third power terminal and the gate of the MOS transistor.
  • the step S2 includes:
  • Step S20 Judge whether the first data pin has a level change, and when the first data pin has a level change, go to step S21;
  • Step S21 Detect the voltage value of the data collection pin to determine the external device inserted into the earphone socket.
  • step S21 when it is detected that the voltage value of the data collection pin is a first preset value, it is determined that the earphone socket is inserted into the earphone cable;
  • the first preset value is 0.64V;
  • the second preset value is 0.80V
  • the third preset value is 1.67V.
  • the beneficial effect of the technical solution of the present invention is to provide a method for multiplexing the functions of the earphone socket and USB OTG.
  • the control chip is used to detect the level state of the earphone socket, and the external equipment inserted into the earphone socket is determined by the multiplexing circuit. Communicate and connect with earphone cable, USB host device, and USB external device to realize the multiplexing of earphone function and OTG function.
  • the circuit structure is simple, which is convenient for software engineers to debug and promote.
  • FIG. 1 is a flowchart of steps of a method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention
  • step S2 is a flowchart of step S2 of the method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention
  • Fig. 3 is a circuit connection diagram of the multiplexing circuit of the embodiment of the present invention.
  • the present invention includes a method for multiplexing the functions of an earphone holder and USB OTG, including:
  • Step S1 Provide a multiplexing circuit, which is connected to an earphone jack AJ1 and a control chip SOC respectively;
  • Step S2 The control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is determined through the multiplexing circuit.
  • control chip SOC can be used as a host device or an external device.
  • the role of the control chip SOC is generally determined by the level of the USB ID.
  • USB ID is the input signal, defined by the USB OTG protocol, and used to identify the default role of the device connected to the headset jack AJ1, that is, host mode or external device mode.
  • the USB ID is pulled up by default and is in the state of an external device. If the headphone jack AJ1 needs to be in host mode, the control chip 3 will short USB_ID to the ground, that is, when the input is 0, it means that the headphone jack AJ1 is in host mode and communicates with USB external devices.
  • control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function.
  • Multiplexing with OTG functions simple circuit structure, convenient for software engineers to debug and promote.
  • the multiplexing circuit further includes a switching unit U1, and the switching unit U1 is respectively connected to the control chip SOC and the earphone socket AJ1.
  • the switching unit U1 further includes:
  • a first switching pin ASEL connected to the second data pin GPIOA_1;
  • a positive voltage terminal D+ connected to the data positive signal pin USB_DP;
  • a negative voltage terminal D- connected to the data negative signal pin USB_DM;
  • One left channel pin L connected to the first audio output pin AUDIO_L;
  • a right channel pin R is connected to the second audio output pin AUDIO_R.
  • control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
  • the earphone holder AJ1 includes:
  • a first pin AJ10 is connected to a first power terminal S1;
  • a second pin AJ11 connected to the right channel power terminal DR+ of the switching unit U1;
  • a third pin AJ12 is connected to the first data pin GPIOA_0 of the control chip SOC through a first resistor R1;
  • a fourth pin AJ13 connected to the left channel power terminal DL- of the switching unit U1;
  • a fifth pin AJ14 is connected to the ground terminal GND.
  • the resistance value of the first resistor R1 is 1K ohms
  • the control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is judged by the multiplexing circuit, which can be connected to the earphone cable and USB
  • the host device and the USB external device are connected for communication to realize the multiplexing of the earphone function and the OTG function.
  • the circuit structure is simple, which is convenient for software engineers to debug and promote.
  • control chip SOC includes:
  • a first data pin GPIOA_0 used to implement the headphone detection pin HP_DET;
  • a data acquisition pin SARADC_CH0 used to realize the USB audio detection pin USB_AUDIO_DET;
  • USB_ID used to implement the USB ID pin USB_ID
  • USB_DM used to realize the USB OTG negative voltage pin USB OTG_B_DM
  • USB_DP used to realize the USB OTG positive voltage pin USB OTG_B_DP;
  • An audio first output pin AUDIO_L used to realize the left audio channel AUDIO_L;
  • An audio second output pin AUDIO_R is used to implement the audio right channel AUDIO_R.
  • the first data pin GPIOA_0 is used to detect the level state of the headphone detection pin HP_DET.
  • the first data pin GPIOA_0 detects the level state of the headphone detection pin HP_DET from low to high, it means The headphone detection pin HP_DET has an external device inserted, and then the data acquisition pin SARADC_CH0 detects the voltage value of the USB audio detection pin USB_AUDIO_DET.
  • the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.64V, it means that the headphone cable is inserted.
  • USB_AUDIO_DET When the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.80V, it means that the USB host device is inserted, and when the voltage value of the USB audio detection pin USB_AUDIO_DET is 1.67V, it means that the USB external device is inserted.
  • control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function.
  • Multiplexing with OTG functions simple circuit structure, convenient for software engineers to debug and promote.
  • the multiplexing circuit includes:
  • a second power supply terminal S2 providing a second power supply voltage VCC2;
  • a fourth power supply terminal S4 providing a fourth power supply voltage VCC4;
  • a multiplexing unit is respectively connected between the first voltage terminal S1, the second power terminal S2, the third power terminal S3, the fourth voltage terminal S4, the control chip SOC and the earphone socket AJ1.
  • the first power supply voltage VCC1 is 5V
  • the second power supply voltage VCC2 is 3.3V
  • the third power supply voltage VCC3 is 5V
  • the fourth power supply voltage VCC4 is 1.8V.
  • the multiplexing unit includes:
  • a triode Q1 the emitter of the triode Q1 is connected to the third data pin GPIOA_2, and the base of the triode Q1 is connected to the second voltage terminal S2 through a second resistor R2;
  • a MOS tube Q2 the gate of the MOS tube Q2 is connected to the collector of the transistor Q1 through a third resistor R3, the source of the MOS tube Q2 is connected to the third power terminal S3, and the drain of the MOS tube Q2 is connected to the first terminal of the earphone socket AJ1 Pin AJ10;
  • a fourth resistor R4 is connected between the fourth power terminal S4 and the data acquisition pin SARADC_CH0 through a diode D1;
  • a seventh resistor R7 connected between the third power terminal S3 and the collector of the transistor Q1;
  • a ninth resistor R9 connected between the first data pin GPIOA_0 and the second power terminal S2;
  • a tenth resistor R10 connected between the fourth pin AJ13 of the earphone jack AJ1 and the ground terminal GND;
  • a first capacitor C1 connected between the first power terminal S1 and the ground terminal GND;
  • a second capacitor C2 is connected between the third power terminal S3 and the gate of the MOS transistor Q1.
  • the transistor Q1 is an NPN transistor
  • the MOS transistor Q2 is an N-type MOS transistor
  • the resistance value of the second resistor R2 is 47K ohms
  • the resistance value of the third resistor R3 is 100K ohms
  • the resistance value of the fourth resistor R4 is 10K.
  • the resistance of the fifth resistor R5 is 20K ohms
  • the resistance of the sixth resistor R6 is 10K ohms
  • the resistance of the seventh resistor R7 is 47K ohms
  • the resistance of the eighth resistor R8 is 10K ohms
  • the resistance of the ninth resistor R9 The resistance value of is 10K ohms, where the fourth resistor R4 and the sixth resistor R6 form a voltage divider resistor, connected to GPIOA_1 from the voltage divider node, the capacitance value of the first capacitor C1 is 22uF, and the capacitance value of the second capacitor C2 is 0.1uF .
  • step S2 includes:
  • Step S20 Judge whether the first data pin GPIOA_0 has a level change, and when the first data pin GPIOA_0 has a level change, go to step S21;
  • Step S21 Detect the voltage value of the data collection pin SARADC_CH0 to determine the external device inserted into the earphone jack AJ1.
  • step S21 when it is detected that the voltage value of the data collection pin SARADC_CH0 is a first preset value, it is determined that the earphone jack AJ1 is inserted into the earphone cable;
  • the first preset value is 0.64V
  • the second preset value is 0.80V
  • the third preset value is 1.67V.
  • the third pin AJ3 of the headphone socket AJ1 is grounded when the headphone cable is inserted.
  • the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER to turn off the transistor Q1, and the MOS transistor Q2 is also turned off.
  • the third pin AJ3 of the headphone holder AJ1 is in a floating state when the USB host device is inserted.
  • the third data pin GPIOA_2 outputs a low-level USB power pin USB_POWER to turn on the transistor Q1, and the MOS tube Q2 also turns on the first power terminal S1 at this time.
  • the first pin of the socket AJ1 which is the connected power pin USBOTG_B_5V, outputs a 5V voltage.
  • the third pin AJ3 of the earphone holder AJ1 is in an external 5V state.
  • the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER turns off the transistor Q1, and the MOS tube Q2 turns off the first power terminal S1 at this time.
  • the first pin of AJ1 the connected power pin USBOTG_B_5V has no output, the ID pin USB_ID pulls up the USB power pin USB_POWER through the eighth resistor R8 to input high level, and the second data pin GPIOA_1 outputs low level USB audio
  • control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Headphones And Earphones (AREA)
  • Stereophonic Arrangements (AREA)

Abstract

The present invention relates to the technical field of OTG functions, in particular relates to a method for multiplexing an earphone seat and a USB OTG function. The method comprises: step S1, providing a multiplexing circuit, wherein the multiplexing circuit is respectively connected to an earphone seat and a control chip; and step S2, using the control chip to detect a level state of the earphone seat, and determining, by means of the multiplexing circuit, an external device which is inserted into the earphone seat. The technical solution of the present invention has the beneficial effects that the level state of the earphone seat is detected by using the control chip, and the external device which is inserted into the earphone seat is determined by means of the multiplexing circuit and can be respectively in communication connection with an earphone wire, a USB host device and a USB external device, such that multiplexing of an earphone function and an OTG function is realized, the circuit structure is simple, debugging performed by a software engineer is facilitated, and popularization is facilitated.

Description

一种使用耳机座与USB OTG功能复用的方法A method of using the headphone socket and USB OTG function multiplexing 技术领域Technical field
本发明涉及OTG功能技术领域,尤其涉及一种使用耳机座与USB OTG功能复用的方法。The present invention relates to the technical field of OTG functions, and in particular to a method for using an earphone socket and USB OTG function multiplexing.
背景技术Background technique
USB(Universal Serial Bus,通用串行总线)是一种数据通信方式,也是一种数据总线,而且是最复杂的总线之一。硬件上,它是用插头连接,一边是公头(plug),一边是母头(receptacle)。例如,计算机上的插座就是母头,USB设备使用公头与计算机连接。目前USB硬件接口分三种,普通计算机上使用的叫Type;原来诺基亚功能机时代的接口为Mini USB;目前Android手机使用的Micro USB。USB (Universal Serial Bus) is a data communication method, it is also a data bus, and it is one of the most complex buses. In terms of hardware, it is connected by a plug, with a plug on one side and a receptacle on the other. For example, a socket on a computer is a female connector, and a USB device uses a male connector to connect to the computer. There are currently three types of USB hardware interfaces. The type used on ordinary computers is called Type; the original interface used in Nokia's feature phone era is Mini USB; and the current Micro USB used in Android phones.
USB OTG是USB On-The-Go的缩写,是近年发展起来的技术。On The Go,这是在USB2.0引入的一种形式,提出了一个新的概念叫主机协商协议(HostNegotiation Protocol),允许两个设备间商量谁去当Host。OTG控制器可以做host,也能做device,控制器的角色一般由USB ID电平来决定。USB OTG is the abbreviation of USB On-The-Go, which is a technology developed in recent years. On The Go, this is a form introduced in USB 2.0, and a new concept called Host Negotiation Protocol (Host Negotiation Protocol) is proposed, which allows two devices to negotiate who will be the Host. The OTG controller can be used as a host or a device. The role of the controller is generally determined by the USB ID level.
由于智能音响产品设计外观已经取消USB插座只留耳机座,其中耳机座无法实现USB软件烧录,在调试的时候无法使用USB OTG功能。业界的做法都是增加miniUSB或mircoUSB接口,这样使用成本较高,不予推广。Since the design and appearance of smart audio products has been cancelled, the USB socket is reserved only for the earphone holder, which cannot realize the USB software burning, and the USB OTG function cannot be used during debugging. The industry's approach is to increase the miniUSB or mircoUSB interface, so the use cost is high, not to promote.
发明内容Summary of the invention
针对现有技术中存在的上述问题,现提供一种使用耳机座与USB OTG功能复用的方法。In view of the above-mentioned problems existing in the prior art, a method for multiplexing the functions of a headset and USB OTG is provided.
具体技术方案如下:The specific technical solutions are as follows:
一种使用耳机座与USB OTG功能复用的方法,其中包括:A method of using the headset socket and USB OTG function multiplexing, including:
步骤S1、提供一复用电路,复用电路分别连接一耳机座及一控制芯片;Step S1: Provide a multiplexing circuit, and the multiplexing circuit is respectively connected to a headphone holder and a control chip;
步骤S2、采用控制芯片检测耳机座的电平状态,通过复用电路判断出插入耳机座的外接设备。Step S2: The control chip is used to detect the level state of the earphone holder, and the external device inserted into the earphone holder is determined through the multiplexing circuit.
优选的,复用电路还包括一切换单元,切换单元分别连接控制芯片与耳机座。Preferably, the multiplexing circuit further includes a switching unit, and the switching unit is respectively connected to the control chip and the earphone holder.
优选的,耳机座包括:Preferably, the earphone holder includes:
一第一引脚,连接一第一电源端;A first pin connected to a first power terminal;
一第二引脚,连接切换单元的右通道电源端;A second pin, connected to the right channel power terminal of the switching unit;
一第三引脚,通过一第一电阻连接控制芯片的第一数据引脚;A third pin, connected to the first data pin of the control chip through a first resistor;
一第四引脚,连接切换单元的左通道电源端;A fourth pin, connected to the left channel power terminal of the switching unit;
一第五引脚,连接接地端。A fifth pin, connected to the ground terminal.
优选的,控制芯片包括:Preferably, the control chip includes:
一第一数据引脚,用于实现耳机检测引脚;A first data pin, which is used to implement the earphone detection pin;
一第二数据引脚,用于实现USB音频切换引脚;A second data pin, used to implement USB audio switching pins;
一第三数据引脚,用于实现USB电源引脚;A third data pin, used to realize the USB power pin;
一数据采集引脚,用于实现USB音频检测引脚;One data acquisition pin, used to realize USB audio detection pin;
一ID引脚,用于实现USB ID引脚;An ID pin, used to implement the USB ID pin;
一数据负信号引脚,用于实现USB OTG负电压引脚;A data negative signal pin, used to realize the USB OTG negative voltage pin;
一数据正信号引脚,用于实现USB OTG正电压引脚;One data positive signal pin, used to realize the USB OTG positive voltage pin;
一音频第一输出引脚,用于实现音频左通道;An audio first output pin for realizing the left audio channel;
一音频第二输出引脚,用于实现音频右通道。An audio second output pin, used to implement the audio right channel.
优选的,所述切换单元还包括:Preferably, the switching unit further includes:
一第一切换引脚,连接所述第二数据引脚;A first switching pin connected to the second data pin;
一正电压端,连接所述数据正信号引脚;A positive voltage terminal connected to the data positive signal pin;
一负电压端,连接所述数据负信号引脚;A negative voltage terminal connected to the data negative signal pin;
一左通道引脚,连接所述音频第一输出引脚;A left channel pin, connected to the first audio output pin;
一右通道引脚,连接所述音频第二输出引脚。A right channel pin is connected to the second audio output pin.
优选的,所述复用电路包括:Preferably, the multiplexing circuit includes:
一第一电源端,提供一第一电源电压;A first power terminal, providing a first power voltage;
一第二电源端,提供一第二电源电压;A second power terminal, providing a second power voltage;
一第三电源端,提供一第三电源电压;A third power supply terminal, providing a third power supply voltage;
一第四电源端,提供一第四电源电压;A fourth power supply terminal, providing a fourth power supply voltage;
一复用单元,所述复用单元分别连接于所述第一电压端、所述第二电源端、所述第三电源端、所述第四电压端、所述控制芯片及所述耳机座之间。A multiplexing unit, the multiplexing unit is respectively connected to the first voltage terminal, the second power terminal, the third power terminal, the fourth voltage terminal, the control chip and the earphone socket between.
优选的,所述复用单元包括:Preferably, the multiplexing unit includes:
一三极管,所述三极管的发射极连接所述第三数据引脚,所述三极管的基极通过一第二电阻连接所述第二电压端;A triode, the emitter of the triode is connected to the third data pin, and the base of the triode is connected to the second voltage terminal through a second resistor;
一MOS管,所述MOS管的栅极通过一第三电阻连接所述三极管的集电极,所述MOS管的源极连接所述第三电源端,所述MOS管的漏极连接所述耳机座的第一引脚;A MOS tube, the gate of the MOS tube is connected to the collector of the triode through a third resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the earphone The first pin of the socket;
一第四电阻,通过一二极管连接于所述第四电源端与所述数据采集引脚之间;A fourth resistor, connected between the fourth power terminal and the data acquisition pin through a diode;
一第五电阻,连接于所述耳机插座的第一引脚与所述数据采集引脚之间;A fifth resistor connected between the first pin of the earphone socket and the data collection pin;
一第六电阻,连接于所述数据采集引脚与接地端之间;A sixth resistor connected between the data acquisition pin and the ground terminal;
一第七电阻,连接于所述第三电源端与所述三极管的集电极之间;A seventh resistor, connected between the third power terminal and the collector of the triode;
一第八电阻,连接于所述ID引脚与所述三极管的发射极之间;An eighth resistor, connected between the ID pin and the emitter of the triode;
一第九电阻,连接于所述第一数据引脚与所述第二电源端之间;A ninth resistor connected between the first data pin and the second power terminal;
一第十电阻,连接于所述耳机座的第四引脚与接地端之间;A tenth resistor, connected between the fourth pin of the earphone holder and the ground terminal;
一第一电容,连接于所述第一电源端与接地端之间;A first capacitor connected between the first power terminal and the ground terminal;
一第二电容,连接于所述第三电源端与所述MOS管的栅极之间。A second capacitor is connected between the third power terminal and the gate of the MOS transistor.
优选的,所述步骤S2包括:Preferably, the step S2 includes:
步骤S20、判断所述第一数据引脚是否有电平变化,并在所述第一数据引脚有电平变化时转向步骤S21;Step S20: Judge whether the first data pin has a level change, and when the first data pin has a level change, go to step S21;
步骤S21、检测所述数据采集引脚的电压值,以判断出所述耳机座插入的外接设备。Step S21: Detect the voltage value of the data collection pin to determine the external device inserted into the earphone socket.
优选的,于所述步骤S21中,检测所述数据采集引脚的电压值为一第一预设值时,判断出所述耳机座插入耳机线;Preferably, in the step S21, when it is detected that the voltage value of the data collection pin is a first preset value, it is determined that the earphone socket is inserted into the earphone cable;
检测所述数据采集引脚的电压值为一第二预设值时,判断出所述耳机座插入USB主机设备;When detecting that the voltage value of the data collection pin is a second preset value, it is determined that the earphone holder is inserted into the USB host device;
检测所述数据采集引脚的电压值为一第三预设值时,判断出所述耳机座插入USB外接设备。When detecting that the voltage value of the data collection pin is a third preset value, it is determined that the earphone holder is inserted into a USB external device.
优选的,所述第一预设值为0.64V;Preferably, the first preset value is 0.64V;
所述第二预设值为0.80V;The second preset value is 0.80V;
所述第三预设值为1.67V。The third preset value is 1.67V.
本发明的技术方案有益效果在于:提供一种使用耳机座与USB OTG功能复用的方法,采用控制芯片检测耳机座的电平状态,通过复用电路判断出插入耳机座的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。The beneficial effect of the technical solution of the present invention is to provide a method for multiplexing the functions of the earphone socket and USB OTG. The control chip is used to detect the level state of the earphone socket, and the external equipment inserted into the earphone socket is determined by the multiplexing circuit. Communicate and connect with earphone cable, USB host device, and USB external device to realize the multiplexing of earphone function and OTG function. The circuit structure is simple, which is convenient for software engineers to debug and promote.
附图说明Description of the drawings
参考所附附图,以更加充分的描述本发明的实施例。然而,所附附图仅 用于说明和阐述,并不构成对本发明范围的限制。With reference to the attached drawings, the embodiments of the present invention are described more fully. However, the attached drawings are only for illustration and illustration, and do not constitute a limitation on the scope of the present invention.
图1为本发明的实施例的使用耳机座与USB OTG功能复用的方法的步骤流程图;FIG. 1 is a flowchart of steps of a method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention;
图2为本发明的实施例的使用耳机座与USB OTG功能复用的方法的步骤S2的步骤流程图;2 is a flowchart of step S2 of the method for multiplexing the functions of an earphone holder and USB OTG according to an embodiment of the present invention;
图3为本发明的实施例的复用电路的电路连接图。Fig. 3 is a circuit connection diagram of the multiplexing circuit of the embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
需要说明的是,在不冲突的情况下,本发明中的实施例及实施例中的特征可以相互组合。It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other if there is no conflict.
下面结合附图和具体实施例对本发明作进一步说明,但不作为本发明的限定。The present invention will be further described below with reference to the drawings and specific embodiments, but it is not a limitation of the present invention.
本发明包括一种使用耳机座与USB OTG功能复用的方法,其中包括:The present invention includes a method for multiplexing the functions of an earphone holder and USB OTG, including:
步骤S1、提供一复用电路,复用电路分别连接一耳机座AJ1及一控制芯片SOC;Step S1: Provide a multiplexing circuit, which is connected to an earphone jack AJ1 and a control chip SOC respectively;
步骤S2、采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备。Step S2: The control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is determined through the multiplexing circuit.
通过上述使用耳机座与USB OTG功能复用的方法的技术方案,结合图1、3所示,首先识别耳机座AJ1的耳机功能与USB OTG功能的状态识别, 通过控制芯片SOC检测耳机座AJ1的电平状态,结合复用电路判断插入耳机座AJ1的外接设备的电压来判断插入耳机座AJ1的设备,其中可以检测到外界设备有耳机线、USB主机设备及USB外接设备。Through the above-mentioned technical solution using the method of multiplexing the headphone holder and USB OTG function, combined with Figures 1 and 3, first identify the headphone function of the headphone holder AJ1 and the status recognition of the USB OTG function, and detect the headphone holder AJ1's status through the control chip SOC. The level status is combined with the multiplexing circuit to determine the voltage of the external device plugged into the headphone socket AJ1 to determine the device plugged into the headphone socket AJ1. The external devices can be detected as headphone cables, USB host devices and USB external devices.
进一步地,控制芯片SOC可以做主机设备,也可以做外接设备,控制芯片SOC的角色一般是由USB ID的电平来决定。其中,USB ID为输入信号,由USB OTG协议定义,用于识别耳机插座AJ1所接设备的默认角色,即主机模式或外接设备模式。USB ID默认上拉,处于外接设备状况。如果需要耳机插座AJ1为主机模式,则控制芯片3将USB_ID短接到地,即输入为0时,说明耳机插座AJ1为主机模式,与USB外接设备通信。Further, the control chip SOC can be used as a host device or an external device. The role of the control chip SOC is generally determined by the level of the USB ID. Among them, USB ID is the input signal, defined by the USB OTG protocol, and used to identify the default role of the device connected to the headset jack AJ1, that is, host mode or external device mode. The USB ID is pulled up by default and is in the state of an external device. If the headphone jack AJ1 needs to be in host mode, the control chip 3 will short USB_ID to the ground, that is, when the input is 0, it means that the headphone jack AJ1 is in host mode and communicates with USB external devices.
进一步地,采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。Further, the control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function. Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
在一种较优的实施例中,复用电路还包括一切换单元U1,切换单元U1分别连接控制芯片SOC与耳机座AJ1。In a preferred embodiment, the multiplexing circuit further includes a switching unit U1, and the switching unit U1 is respectively connected to the control chip SOC and the earphone socket AJ1.
上述技术方案中,切换单元U1还包括:In the above technical solution, the switching unit U1 further includes:
一第一切换引脚ASEL,连接第二数据引脚GPIOA_1;A first switching pin ASEL, connected to the second data pin GPIOA_1;
一正电压端D+,连接数据正信号引脚USB_DP;A positive voltage terminal D+, connected to the data positive signal pin USB_DP;
一负电压端D-,连接数据负信号引脚USB_DM;A negative voltage terminal D-, connected to the data negative signal pin USB_DM;
一左通道引脚L,连接音频第一输出引脚AUDIO_L;One left channel pin L, connected to the first audio output pin AUDIO_L;
一右通道引脚R,连接音频第二输出引脚AUDIO_R。A right channel pin R is connected to the second audio output pin AUDIO_R.
进一步地,采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。Further, the control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
在一种较优的实施例中,耳机座AJ1包括:In a preferred embodiment, the earphone holder AJ1 includes:
一第一引脚AJ10,连接一第一电源端S1;A first pin AJ10 is connected to a first power terminal S1;
一第二引脚AJ11,连接切换单元U1的右通道电源端DR+;A second pin AJ11 connected to the right channel power terminal DR+ of the switching unit U1;
一第三引脚AJ12,通过一第一电阻R1连接控制芯片SOC的第一数据引脚GPIOA_0;A third pin AJ12 is connected to the first data pin GPIOA_0 of the control chip SOC through a first resistor R1;
一第四引脚AJ13,连接切换单元U1的左通道电源端DL-;A fourth pin AJ13, connected to the left channel power terminal DL- of the switching unit U1;
一第五引脚AJ14,连接接地端GND。A fifth pin AJ14 is connected to the ground terminal GND.
其中,第一电阻R1的阻值为1K欧姆,进一步地,采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。Among them, the resistance value of the first resistor R1 is 1K ohms, and further, the control chip SOC is used to detect the level state of the earphone socket AJ1, and the external device inserted into the earphone socket AJ1 is judged by the multiplexing circuit, which can be connected to the earphone cable and USB The host device and the USB external device are connected for communication to realize the multiplexing of the earphone function and the OTG function. The circuit structure is simple, which is convenient for software engineers to debug and promote.
在一种较优的实施例中,控制芯片SOC包括:In a preferred embodiment, the control chip SOC includes:
一第一数据引脚GPIOA_0,用于实现耳机检测引脚HP_DET;A first data pin GPIOA_0, used to implement the headphone detection pin HP_DET;
一第二数据引脚GPIOA_1,用于实现USB音频切换引脚USB_AUDIO_SW;A second data pin GPIOA_1, used to implement the USB audio switching pin USB_AUDIO_SW;
一第三数据引脚GPIOA_2,用于实现USB电源引脚USB_POWER;A third data pin GPIOA_2, used to implement the USB power pin USB_POWER;
一数据采集引脚SARADC_CH0,用于实现USB音频检测引脚USB_AUDIO_DET;A data acquisition pin SARADC_CH0, used to realize the USB audio detection pin USB_AUDIO_DET;
一ID引脚USB_ID,用于实现USB ID引脚USB_ID;An ID pin USB_ID, used to implement the USB ID pin USB_ID;
一数据负信号引脚USB_DM,用于实现USB OTG负电压引脚USB OTG_B_DM;A data negative signal pin USB_DM, used to realize the USB OTG negative voltage pin USB OTG_B_DM;
一数据正信号引脚USB_DP,用于实现USB OTG正电压引脚USB OTG_B_DP;A data positive signal pin USB_DP, used to realize the USB OTG positive voltage pin USB OTG_B_DP;
一音频第一输出引脚AUDIO_L,用于实现音频左通道AUDIO_L;An audio first output pin AUDIO_L, used to realize the left audio channel AUDIO_L;
一音频第二输出引脚AUDIO_R,用于实现音频右通道AUDIO_R。An audio second output pin AUDIO_R is used to implement the audio right channel AUDIO_R.
具体地,采用第一数据引脚GPIOA_0检测耳机检测引脚HP_DET的电 平状态,当第一数据引脚GPIOA_0检测耳机检测引脚HP_DET的电平状态从低电平变为高电平时,即表示耳机检测引脚HP_DET有外接设备插入,然后通过数据采集引脚SARADC_CH0检测开始USB音频检测引脚USB_AUDIO_DET的电压值,当USB音频检测引脚USB_AUDIO_DET的电压值为0.64V时,表示插入耳机线,当USB音频检测引脚USB_AUDIO_DET的电压值为0.80V时,表示插入USB主机设备,USB音频检测引脚USB_AUDIO_DET的电压值为1.67V时,表示插入USB外接设备。Specifically, the first data pin GPIOA_0 is used to detect the level state of the headphone detection pin HP_DET. When the first data pin GPIOA_0 detects the level state of the headphone detection pin HP_DET from low to high, it means The headphone detection pin HP_DET has an external device inserted, and then the data acquisition pin SARADC_CH0 detects the voltage value of the USB audio detection pin USB_AUDIO_DET. When the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.64V, it means that the headphone cable is inserted. When the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.80V, it means that the USB host device is inserted, and when the voltage value of the USB audio detection pin USB_AUDIO_DET is 1.67V, it means that the USB external device is inserted.
进一步地,采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。Further, the control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is judged by the multiplexing circuit, which can communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function. Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
在一种较优的实施例中,复用电路包括:In a preferred embodiment, the multiplexing circuit includes:
一第一电源端S1,提供一第一电源电压VCC1;A first power terminal S1, providing a first power voltage VCC1;
一第二电源端S2,提供一第二电源电压VCC2;A second power supply terminal S2, providing a second power supply voltage VCC2;
一第三电源端S3,提供一第三电源电压VCC3;A third power terminal S3, providing a third power voltage VCC3;
一第四电源端S4,提供一第四电源电压VCC4;A fourth power supply terminal S4, providing a fourth power supply voltage VCC4;
一复用单元,复用单元分别连接于第一电压端S1、第二电源端S2、第三电源端S3、第四电压端S4、控制芯片SOC及耳机座AJ1之间。A multiplexing unit, the multiplexing unit is respectively connected between the first voltage terminal S1, the second power terminal S2, the third power terminal S3, the fourth voltage terminal S4, the control chip SOC and the earphone socket AJ1.
其中,第一电源电压VCC1为5V,第二电源电压VCC2为3.3V,第三电源电压VCC3为5V,第四电源电压VCC4为1.8V。Among them, the first power supply voltage VCC1 is 5V, the second power supply voltage VCC2 is 3.3V, the third power supply voltage VCC3 is 5V, and the fourth power supply voltage VCC4 is 1.8V.
上述技术方案中,复用单元包括:In the above technical solution, the multiplexing unit includes:
一三极管Q1,三极管Q1的发射极连接第三数据引脚GPIOA_2,三极管Q1的基极通过一第二电阻R2连接第二电压端S2;A triode Q1, the emitter of the triode Q1 is connected to the third data pin GPIOA_2, and the base of the triode Q1 is connected to the second voltage terminal S2 through a second resistor R2;
一MOS管Q2,MOS管Q2的栅极通过一第三电阻R3连接三极管Q1的集电极,MOS管Q2的源极连接第三电源端S3,MOS管Q2的漏极连接耳机座AJ1的第一引脚AJ10;A MOS tube Q2, the gate of the MOS tube Q2 is connected to the collector of the transistor Q1 through a third resistor R3, the source of the MOS tube Q2 is connected to the third power terminal S3, and the drain of the MOS tube Q2 is connected to the first terminal of the earphone socket AJ1 Pin AJ10;
一第四电阻R4,通过一二极管D1连接于第四电源端S4与数据采集引脚SARADC_CH0之间;A fourth resistor R4 is connected between the fourth power terminal S4 and the data acquisition pin SARADC_CH0 through a diode D1;
一第五电阻R5,连接于耳机插座AJ1的第一引脚AJ10与数据采集引脚SARADC_CH0之间;A fifth resistor R5, connected between the first pin AJ10 of the earphone jack AJ1 and the data acquisition pin SARADC_CH0;
一第六电阻R6,连接于数据采集引脚SARADC_CH0与接地端GND之间;A sixth resistor R6, connected between the data acquisition pin SARADC_CH0 and the ground terminal GND;
一第七电阻R7,连接于第三电源端S3与三极管Q1的集电极之间;A seventh resistor R7, connected between the third power terminal S3 and the collector of the transistor Q1;
一第八电阻R8,连接于ID引脚USB_ID与三极管Q1的发射极之间;An eighth resistor R8, connected between the ID pin USB_ID and the emitter of the transistor Q1;
一第九电阻R9,连接于第一数据引脚GPIOA_0与第二电源端S2之间;A ninth resistor R9, connected between the first data pin GPIOA_0 and the second power terminal S2;
一第十电阻R10,连接于耳机座AJ1的第四引脚AJ13与接地端GND之间;A tenth resistor R10, connected between the fourth pin AJ13 of the earphone jack AJ1 and the ground terminal GND;
一第一电容C1,连接于第一电源端S1与接地端GND之间;A first capacitor C1 connected between the first power terminal S1 and the ground terminal GND;
一第二电容C2,连接于第三电源端S3与MOS管Q1的栅极之间。A second capacitor C2 is connected between the third power terminal S3 and the gate of the MOS transistor Q1.
具体地,三极管Q1为NPN型三极管,MOS管Q2为N型MOS管,第二电阻R2的阻值为47K欧姆,第三电阻R3的阻值为100K欧姆,第四电阻R4的阻值为10K欧姆,第五电阻R5的阻值为20K欧姆,第六电阻R6的阻值为10K欧姆,第七电阻R7的阻值为47K欧姆,第八电阻R8的阻值为10K欧姆,第九电阻R9的阻值为10K欧姆,其中,第四电阻R4与第六电阻R6组成分压电阻,自分压节点连接至GPIOA_1,第一电容C1的容值为22uF,第二电容C2的容值为0.1uF。Specifically, the transistor Q1 is an NPN transistor, the MOS transistor Q2 is an N-type MOS transistor, the resistance value of the second resistor R2 is 47K ohms, the resistance value of the third resistor R3 is 100K ohms, and the resistance value of the fourth resistor R4 is 10K. Ohm, the resistance of the fifth resistor R5 is 20K ohms, the resistance of the sixth resistor R6 is 10K ohms, the resistance of the seventh resistor R7 is 47K ohms, the resistance of the eighth resistor R8 is 10K ohms, and the resistance of the ninth resistor R9 The resistance value of is 10K ohms, where the fourth resistor R4 and the sixth resistor R6 form a voltage divider resistor, connected to GPIOA_1 from the voltage divider node, the capacitance value of the first capacitor C1 is 22uF, and the capacitance value of the second capacitor C2 is 0.1uF .
在一种较优的实施例中,如图2所示,步骤S2包括:In a preferred embodiment, as shown in FIG. 2, step S2 includes:
步骤S20、判断第一数据引脚GPIOA_0是否有电平变化,并在第一数据引脚GPIOA_0有电平变化时转向步骤S21;Step S20: Judge whether the first data pin GPIOA_0 has a level change, and when the first data pin GPIOA_0 has a level change, go to step S21;
步骤S21、检测数据采集引脚SARADC_CH0的电压值,以判断出耳机座AJ1插入的外接设备。Step S21: Detect the voltage value of the data collection pin SARADC_CH0 to determine the external device inserted into the earphone jack AJ1.
上述技术方案中,于步骤S21中,检测数据采集引脚SARADC_CH0的 电压值为一第一预设值时,判断出耳机座AJ1插入耳机线;In the above technical solution, in step S21, when it is detected that the voltage value of the data collection pin SARADC_CH0 is a first preset value, it is determined that the earphone jack AJ1 is inserted into the earphone cable;
检测数据采集引脚SARADC_CH0的电压值为一第二预设值时,判断出耳机座AJ1插入USB主机设备;When detecting that the voltage value of the data acquisition pin SARADC_CH0 is a second preset value, it is determined that the earphone holder AJ1 is inserted into the USB host device;
检测数据采集引脚SARADC_CH0的电压值为一第三预设值时,判断出耳机座AJ1插入USB外接设备。When detecting that the voltage value of the data acquisition pin SARADC_CH0 is a third preset value, it is determined that the earphone jack AJ1 is inserted into the USB external device.
上述技术方案中,第一预设值为0.64V;In the above technical solution, the first preset value is 0.64V;
第二预设值为0.80V;The second preset value is 0.80V;
第三预设值为1.67V。The third preset value is 1.67V.
具体地,耳机座AJ1处于耳机线状态时,插入耳机线时耳机座AJ1第三引脚AJ3是接地状态,此时,USB音频检测引脚USB_AUDIO_DET的电压值为0.64V,即0.64V=[(1.8-0.2)/(R4+R6//R5)]*(R6//R5),第三数据引脚GPIOA_2输出高平USB电源引脚USB_POWER关掉三极管Q1,同时MOS管Q2也关掉,第二数据引脚GPIOA_1输出高电平USB音频切换引脚USB_AUDIO_SW=1时,切换单元U1切换到L,R道路耳机输出。Specifically, when the headphone socket AJ1 is in the headphone cable state, the third pin AJ3 of the headphone socket AJ1 is grounded when the headphone cable is inserted. At this time, the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.64V, that is, 0.64V=[( 1.8-0.2)/(R4+R6//R5)]*(R6//R5), the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER to turn off the transistor Q1, and the MOS transistor Q2 is also turned off. The second When the data pin GPIOA_1 outputs a high-level USB audio switching pin USB_AUDIO_SW=1, the switching unit U1 switches to L, R road headphone output.
进一步地,耳机座AJ1处于USB主机设备状态时,插入USB主机设备时耳机座AJ1第三引脚AJ3是悬空状态,此时,USB音频检测引脚USB_AUDIO_DET的电压值为0.8V,即0.8V=[(1.8-0.2)/(R4+R6)]*R6,第三数据引脚GPIOA_2输出低电平USB电源引脚USB_POWER开启三极管Q1,同时MOS管Q2也开启第一电源端S1,此时耳机座AJ1的第一引脚,即连接的电源引脚USBOTG_B_5V输出5V电压,ID引脚USB_ID通过第八电阻R8下拉USB电源引脚USB_POWER输入低电平,此时,第二数据引脚GPIOA_1输出低电平USB音频切换引脚USB_AUDIO_SW=0时,切换单元U1切换到USB道路检测USB host外设。Further, when the headphone holder AJ1 is in the USB host device state, the third pin AJ3 of the headphone holder AJ1 is in a floating state when the USB host device is inserted. At this time, the voltage value of the USB audio detection pin USB_AUDIO_DET is 0.8V, that is, 0.8V= [(1.8-0.2)/(R4+R6)]*R6, the third data pin GPIOA_2 outputs a low-level USB power pin USB_POWER to turn on the transistor Q1, and the MOS tube Q2 also turns on the first power terminal S1 at this time. The first pin of the socket AJ1, which is the connected power pin USBOTG_B_5V, outputs a 5V voltage. The ID pin USB_ID pulls down the USB power pin USB_POWER through the eighth resistor R8 to input low level. At this time, the second data pin GPIOA_1 outputs low When the level USB audio switching pin USB_AUDIO_SW=0, the switching unit U1 switches to the USB road detection USB host peripheral.
进一步地,耳机座AJ1处于USB主机设备状态时,插入USB外接设备时耳机座AJ1第三引脚AJ3是外接5V的状态,此时,USB音频检测引脚USB_AUDIO_DET的电压值为1.67V,即1.67V=[5/(R4+R5)]*R6,第三数据 引脚GPIOA_2输出高电平USB电源引脚USB_POWER关掉三极管Q1,同时MOS管Q2关掉第一电源端S1,此时耳机座AJ1的第一引脚,即连接的电源引脚USBOTG_B_5V无输出,ID引脚USB_ID通过第八电阻R8上拉USB电源引脚USB_POWER输入高电平,第二数据引脚GPIOA_1输出低电平USB音频切换引脚USB_AUDIO_SW=0时切换单元U1切换到USB道路检测USB外接设备。Further, when the earphone holder AJ1 is in the USB host device state, when the USB external device is inserted, the third pin AJ3 of the earphone holder AJ1 is in an external 5V state. At this time, the voltage value of the USB audio detection pin USB_AUDIO_DET is 1.67V, which is 1.67 V=[5/(R4+R5)]*R6, the third data pin GPIOA_2 outputs a high-level USB power pin USB_POWER turns off the transistor Q1, and the MOS tube Q2 turns off the first power terminal S1 at this time. The first pin of AJ1, the connected power pin USBOTG_B_5V has no output, the ID pin USB_ID pulls up the USB power pin USB_POWER through the eighth resistor R8 to input high level, and the second data pin GPIOA_1 outputs low level USB audio When the switching pin USB_AUDIO_SW=0, the switching unit U1 switches to the USB road detection USB external device.
进一步地,采用控制芯片SOC检测耳机座AJ1的电平状态,通过复用电路判断出插入耳机座AJ1的外接设备,分别可以与耳机线、USB主机设备、USB外接设备通信连接,以实现耳机功能与OTG功能的复用,电路结构简单,方便软件工程师调试,便于推广。Further, the control chip SOC is used to detect the level status of the earphone holder AJ1, and the external device inserted into the earphone holder AJ1 is determined by the multiplexing circuit, which can respectively communicate with the earphone cable, the USB host device, and the USB external device to realize the earphone function Multiplexing with OTG functions, simple circuit structure, convenient for software engineers to debug and promote.
以上所述仅为本发明较佳的实施例,并非因此限制本发明的实施方式及保护范围,对于本领域技术人员而言,应当能够意识到凡运用本发明说明书及图示内容所作出的等同替换和显而易见的变化所得到的方案,均应当包含在本发明的保护范围内。The above descriptions are only preferred embodiments of the present invention, and do not limit the implementation and protection scope of the present invention. For those skilled in the art, they should be able to realize that any equivalent made by using the description and illustrations of the present invention The solutions obtained by substitutions and obvious changes should all be included in the protection scope of the present invention.

Claims (10)

  1. 一种使用耳机座与USB OTG功能复用的方法,其特征在于,包括:A method for using a headset socket and USB OTG function multiplexing, which is characterized in that it includes:
    步骤S1、提供一复用电路,所述复用电路分别连接一耳机座及一控制芯片;Step S1: Provide a multiplexing circuit, and the multiplexing circuit is respectively connected to an earphone holder and a control chip;
    步骤S2、采用所述控制芯片检测所述耳机座的电平状态,通过所述复用电路判断出插入所述耳机座的外接设备。Step S2: Use the control chip to detect the level state of the earphone holder, and determine the external device inserted into the earphone holder through the multiplexing circuit.
  2. 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用电路还包括一切换单元,所述切换单元分别连接所述控制芯片与所述耳机座。The method for multiplexing the functions of an earphone socket and USB OTG according to claim 1, wherein the multiplexing circuit further comprises a switching unit, and the switching unit is respectively connected to the control chip and the earphone socket.
  3. 根据权利要求2所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述耳机座包括:The method for using the earphone socket and USB OTG function multiplexing according to claim 2, wherein the earphone socket comprises:
    一第一引脚,连接一第一电源端;A first pin connected to a first power terminal;
    一第二引脚,连接所述切换单元的右通道电源端;A second pin connected to the right channel power terminal of the switching unit;
    一第三引脚,通过一第一电阻连接所述控制芯片的第一数据引脚;A third pin connected to the first data pin of the control chip through a first resistor;
    一第四引脚,连接所述切换单元的左通道电源端;A fourth pin connected to the left channel power terminal of the switching unit;
    一第五引脚,连接接地端。A fifth pin, connected to the ground terminal.
  4. 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述控制芯片包括:The method for using the headset socket and USB OTG function multiplexing according to claim 1, wherein the control chip comprises:
    一第一数据引脚,用于实现耳机检测引脚;A first data pin, which is used to implement the earphone detection pin;
    一第二数据引脚,用于实现USB音频切换引脚;A second data pin, used to implement USB audio switching pins;
    一第三数据引脚,用于实现USB电源引脚;A third data pin, used to realize the USB power pin;
    一数据采集引脚,用于实现USB音频检测引脚;One data acquisition pin, used to realize USB audio detection pin;
    一ID引脚,用于实现USB ID引脚;An ID pin, used to realize the USB ID pin;
    一数据负信号引脚,用于实现USB OTG负电压引脚;A data negative signal pin, used to realize the USB OTG negative voltage pin;
    一数据正信号引脚,用于实现USB OTG正电压引脚;One data positive signal pin, used to realize the USB OTG positive voltage pin;
    一音频第一输出引脚,用于实现音频左通道;An audio first output pin for realizing the left audio channel;
    一音频第二输出引脚,用于实现音频右通道。An audio second output pin, used to implement the audio right channel.
  5. 根据权利要求4所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述切换单元还包括:The method for using the headset socket and USB OTG function multiplexing according to claim 4, wherein the switching unit further comprises:
    一第一切换引脚,连接所述第二数据引脚;A first switching pin connected to the second data pin;
    一正电压端,连接所述数据正信号引脚;A positive voltage terminal connected to the data positive signal pin;
    一负电压端,连接所述数据负信号引脚;A negative voltage terminal connected to the data negative signal pin;
    一左通道引脚,连接所述音频第一输出引脚;A left channel pin connected to the first audio output pin;
    一右通道引脚,连接所述音频第二输出引脚。A right channel pin is connected to the second audio output pin.
  6. 根据权利要求1所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用电路包括:The method for multiplexing the functions of an earphone holder and USB OTG according to claim 1, wherein the multiplexing circuit comprises:
    一第一电源端,提供一第一电源电压;A first power terminal, providing a first power voltage;
    一第二电源端,提供一第二电源电压;A second power terminal providing a second power voltage;
    一第三电源端,提供一第三电源电压;A third power supply terminal, providing a third power supply voltage;
    一第四电源端,提供一第四电源电压;A fourth power supply terminal, providing a fourth power supply voltage;
    一复用单元,所述复用单元分别连接于所述第一电压端、所述第二电源端、所述第三电源端、所述第四电压端、所述控制芯片及所述耳机座之间。A multiplexing unit, the multiplexing unit is respectively connected to the first voltage terminal, the second power terminal, the third power terminal, the fourth voltage terminal, the control chip and the earphone socket between.
  7. 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述复用单元包括:The method for multiplexing the functions of a headset and USB OTG according to claim 6, wherein the multiplexing unit comprises:
    一三极管,所述三极管的发射极连接所述第三数据引脚,所述三极管的基极通过一第二电阻连接所述第二电压端;A triode, the emitter of the triode is connected to the third data pin, and the base of the triode is connected to the second voltage terminal through a second resistor;
    一MOS管,所述MOS管的栅极通过一第三电阻连接所述三极管的集电极,所述MOS管的源极连接所述第三电源端,所述MOS管的漏极连接所述耳机座的第一引脚;A MOS tube, the gate of the MOS tube is connected to the collector of the triode through a third resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the earphone The first pin of the socket;
    一第四电阻,通过一二极管连接于所述第四电源端与所述数据采集引脚之间;A fourth resistor, connected between the fourth power terminal and the data acquisition pin through a diode;
    一第五电阻,连接于所述耳机插座的第一引脚与所述数据采集引脚之间;A fifth resistor connected between the first pin of the earphone socket and the data collection pin;
    一第六电阻,连接于所述数据采集引脚与接地端之间;A sixth resistor connected between the data collection pin and the ground terminal;
    一第七电阻,连接于所述第三电源端与所述三极管的集电极之间;A seventh resistor connected between the third power terminal and the collector of the triode;
    一第八电阻,连接于所述ID引脚与所述三极管的发射极之间;An eighth resistor, connected between the ID pin and the emitter of the triode;
    一第九电阻,连接于所述第一数据引脚与所述第二电源端之间;A ninth resistor connected between the first data pin and the second power terminal;
    一第十电阻,连接于所述耳机座的第四引脚与接地端之间;A tenth resistor, connected between the fourth pin of the earphone holder and the ground terminal;
    一第一电容,连接于所述第一电源端与接地端之间;A first capacitor connected between the first power terminal and the ground terminal;
    一第二电容,连接于所述第三电源端与所述MOS管的栅极之间。A second capacitor is connected between the third power terminal and the gate of the MOS transistor.
  8. 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述步骤S2包括:The method for using the headset socket and USB OTG function multiplexing according to claim 6, wherein the step S2 comprises:
    步骤S20、判断所述第一数据引脚是否有电平变化,并在所述第一数据引脚有电平变化时转向步骤S21;Step S20: Judge whether the level of the first data pin changes, and when the level of the first data pin changes, go to step S21;
    步骤S21、检测所述数据采集引脚的电压值,以判断出所述耳机座插入的外接设备。Step S21: Detect the voltage value of the data collection pin to determine the external device inserted into the earphone socket.
  9. 根据权利要求6所述的使用耳机座与USB OTG功能复用的方法,其特征在于,于所述步骤S21中,检测所述数据采集引脚的电压值为一第一预设值时,判断出所述耳机座插入耳机线;The method for using the earphone socket and USB OTG function multiplexing according to claim 6, wherein in the step S21, when the voltage value of the data collection pin is detected as a first preset value, it is determined Insert the earphone cable out of the earphone socket;
    检测所述数据采集引脚的电压值为一第二预设值时,判断出所述耳机座插入USB主机设备;When detecting that the voltage value of the data collection pin is a second preset value, it is determined that the earphone holder is inserted into the USB host device;
    检测所述数据采集引脚的电压值为一第三预设值时,判断出所述耳机座插入USB外接设备。When detecting that the voltage value of the data collection pin is a third preset value, it is determined that the earphone holder is inserted into a USB external device.
  10. 根据权利要求9所述的使用耳机座与USB OTG功能复用的方法,其特征在于,所述第一预设值为0.64V;The method for using a headset socket and USB OTG function multiplexing according to claim 9, wherein the first preset value is 0.64V;
    所述第二预设值为0.80V;The second preset value is 0.80V;
    所述第三预设值为1.67V。The third preset value is 1.67V.
PCT/CN2020/091116 2019-05-28 2020-05-19 Method for multiplexing earphone seat and usb otg function WO2020238704A1 (en)

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