WO2020234185A1 - Procédé de marquage de bits, procédé de décodage de bits, dispositif de marquage de bits, décodeur, récepteur et puce - Google Patents

Procédé de marquage de bits, procédé de décodage de bits, dispositif de marquage de bits, décodeur, récepteur et puce Download PDF

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WO2020234185A1
WO2020234185A1 PCT/EP2020/063701 EP2020063701W WO2020234185A1 WO 2020234185 A1 WO2020234185 A1 WO 2020234185A1 EP 2020063701 W EP2020063701 W EP 2020063701W WO 2020234185 A1 WO2020234185 A1 WO 2020234185A1
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bits
decoding
decoder
sequence
marking
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PCT/EP2020/063701
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Gabriele LIGA
Alireza SHEIKH
Alex Enrique Alvarado SEGOVIA
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Technische Universiteit Eindhoven
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6325—Error control coding in combination with demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • a method of marking bits a method of decoding bits, a bit marking device, a decoder, a receiver and a chip.
  • the present disclosure generally relates to the field of decoding technologies and, more specifically, to a method of marking bits to be decoded by a decoder, a method of decoding marked bits, a marking device, a decoder, a receiver comprising a decoder and a chip comprising a receiver.
  • FEC Forward Error Correction
  • communication system such as optical communication systems
  • FEC Error detection and correction or error control techniques like FEC, are used in the area of telecommunication to enable reliable delivery of digital data over unreliable communication channels.
  • FEC is a process of adding redundant data such as an error-correcting code, ECC, to a message so that the message can be recovered by a receiver even when a number of errors were introduced during the transmission over the communication channel.
  • ECC error-correcting code
  • a product code constructed on a (n; k) component code is a set of square arrays of size n*n where any row and column of each array is a valid codeword in the component code.
  • BCH Bose-Chaudhuri-Hocquenghem
  • Reed- Solomon codes are used as a component code.
  • PCs based on BCH codes are typically decoded using iterative algebraic decoding methods such as iterative bounded distance decoding, BDD, which can lead to substantial coding gains.
  • a decoding failure is declared when a received vector of bits is not within a correction capability of a component code.
  • a miscorrection instead occurs when the received vector is successfully decoded, but mapped into codeword different from the transmitted one.
  • a method of marking a sequence of bits to be decoded at a decoding iteration by a decoder the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the method comprising the steps of:
  • each of the reliability measures being based on a combination of a first indicator indicating whether a corresponding output bit is successfully decoded and a second indicator indicating a reliability of the corresponding output bit based on soft information available from a medium influencing the corresponding output bit;
  • the present disclosure is based on the insight that marking a sequence of bits output from a previous decoding iteration or stage of a decoder, with reference to reliability measures respectively calculated for each of the output bits which take into consideration both potential decoding failures and possible miscorrections of the output bits, can effectively facilitate more reliable decoding of the sequence of output bits.
  • a reliability measure of an output bit is essentially a combination of two indicators or parameters, the first indicator takes one of a set of different values reflecting decoding correctness of the bit output from the previous decoding stage, while the second indicator indicates how reliable the output bit can be considered, by relying on soft information available from a medium that can influence the output bit.
  • a medium as used in the context of the present disclosure may refer to for example a communication channel in optical or wireless communication networks over which signals or data are transmitted, a storage medium having information stored thereon, for example related to magnetic, optical and solid state/flash based devices, or devices in security fields.
  • the reliability measures are then used to mark the output bits, to yield or generate a new or further sequence of marked bits, which will then be decoded by the decoder at the present decoding iteration or stage.
  • the reliability measures calculated according to the above method are simple to implement and will not jeopardize the simple-complexity of the HD decoding algorithm used to decode the bits marked with reference to the reliability measures.
  • the reliability measures are updated based on a decision made by the decoder at a previous decoding iteration, thereby allowing the output bits to be decoded at the present iteration to be re-marked, facilitating the generation of a further decoding decision.
  • the method of the present disclosure tackles both miscorrections and decoding failures, based on decoding decision from the previous decoding iteration and soft-information from for example the communication channel. It is demonstrated that decoding gains achieved by decoding the output bits marked using this new scheme are unprecedented for a decoder which still preserves its core HD decoding structure, such as a bounded distance decoder, BDD. As a result, it is possible to achieve decoding performance closer to soft decision, SD, decoding schemes, while still keeping decoding complexity and data-flow orders of magnitude below that of SD decoding schemes.
  • the first one is a medium for communicating data, e.g. a communication channel and the second one is a medium for storing data, for example a storage medium which stores data.
  • a medium for communicating data e.g. a communication channel
  • the second one is a medium for storing data, for example a storage medium which stores data.
  • the first indicator is an indication value selected from a predetermined set comprising values assigned respectively to correctly and incorrectly decoded bits, the indication value is further scaled with a scaling factor.
  • the decoder can, at each iteration, output or provide such as quantized a-posteriori information that indicates whether the output bits are correctly decoded.
  • quantized a-posteriori information indicates whether the output bits are correctly decoded.
  • values -1 and +1 may be assigned for successfully decoded bits 0 and 1 , respectively, while a value of 0 will be assigned to the first indicator when a decoding failure occurs.
  • Such indicator information is simple and straightforward and requires little extra computation or storage resources. The introduction of this indicator therefore will not substantially increase decoding complexity of the core HD decoding algorithm of the decoder.
  • the scaling factor is a real-valued weight optimized for the decoding iteration using a bit error rate as a cost function to be minimized.
  • the scaling factor may be optimized based on an estimate for a bit error rate, BER, for a fixed signal-to-noise ratio.
  • all scaling factors may be jointly optimized using Monte-Carlo estimates of the BER for the fixed as the optimization criterion.
  • optimization of the scaling factor is performed numerically and different values are found for each decoding iteration.
  • the optimal values of the scaling factors can also be optimally derived using a maximum-a-posteriori criterion.
  • the second indicator is a log-likelihood ratio, LLR, of an output bit.
  • the second indicator can be soft quantities or reliabilities extracted from for example the communication channel.
  • One specific example is the LLR calculated as a bit reliability measure for the output bit.
  • the marking is simply made with reference to absolute values of LLRs.
  • the LLR is used together with the first indicator to arrive at a more sophisticated reliability measure, which will be used to mark the corresponding bit.
  • the step of marking comprising one of:
  • an output bit can be marked as either a (highly) reliable bit, HRB, if its reliability measure is greater than or equal to the marking threshold.
  • HRB a reliable bit
  • HUB a unreliable bit
  • the new marked bit will be passed to for example a decoding module of the decoder for further decoding.
  • the marking threshold is scaled with the scaling factor.
  • the marking threshold may be a fixed value. However, to further improve the decoding accuracy, the marking threshold can also be scaled with the scaling factor at each decoding iteration. A rationale behind this choice is minimising the probability of wrong miscorrection detection or non-detected miscorrection. The bit marking as a result is more reliable.
  • the decoding may be performed according to HD-FEC algorithms known to those skilled in the art, which means the bit marking may be used together with different HD decoding schemes to improve the decoding performance.
  • the decoding method provides a new attractive tradeoff between performance and decoding complexity in the context of high-speed HD-FEC schemes such as PCs and SCCs, for example.
  • the decoding method further comprises the step of calculating a further plurality of first indicators, each indicating whether a further output bit is successfully decoded, for a next decoding iteration.
  • the decoder When the output bits are remarked and decoded again at the present iteration, the decoder generates a further plurality of first indicators based on the decoding decision, which in turn will be used in a next decoding iteration for updating the reliability measures. This is beneficial as decoding at each iteration is performed using updated reliability measures.
  • the step of decoding comprising a step of flipping at least one of the further sequence of bits prior to the decoding step.
  • Bit flipping is used to facilitate the success of an additional decoding attempt.
  • the decoder can never flip a bit from a previously successfully decoded codeword (zero-syndrome codeword); HRBs can never be flipped either. When either a failure occurs or a miscorrection is detected, a new decoding attempt is performed after bit flipping.
  • the output bits are set equal to the decoder input and passed to a next decoding stage or iteration. This process is performed for a few iterations.
  • a marking device for marking a sequence of bits to be decoded at a decoding iteration by a decoder, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the marking device comprising:
  • a receive module configured for receiving, from the previous decoding iteration, a plurality of reliability measures calculated respectively for the output bits, each of the reliability measure being based on a combination of a first indicator indicating whether a corresponding output bit is successfully decoded and a second indicator indicating a reliability of the corresponding output bit based on soft information available from a medium influencing the corresponding output bit; and a marking module configured for marking the output bits with reference to the received reliability measures to generate a further sequence of bits to be decoded at the decoding iteration.
  • the marking device may function as a marking module in a decoder to mark a sequence of bits to be decoded at the present iteration with reference to correctness and reliability of the bits output from the previous decoding iteration.
  • marked bits will be decoded by the decoder in a decoding attempt or iteration further to the previous decoding iteration, improving the overall decoding performance.
  • a decoder for decoding a sequence of bits marked by the marking device according to the third aspect of the present disclosure at a decoding iteration, the sequence of bits being output bits from a previous decoding iteration of the decoder, the decoder employing hard decision forward-error correction decoding calculations, the decoder comprising:
  • a receiving module configured for receiving the marked further sequence of bits; a decoding module configured for decoding the further sequence of bits to generate a sequence of further output bits to be decoded at a next decoding iteration.
  • a receiver at a receiving end of a communication channel in a communication system comprising a decoder according to the fourth aspect of the present disclosure.
  • a chip comprising the receiver according to the fifth aspect of the present disclosure.
  • a seventh aspect of the present disclosure there is presented computer program product, comprising a computer readable storage medium storing instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to the first aspect of the present disclosure.
  • Fig. 1 schematically illustrates a system model for a SABM scheme implemented in an exemplary receiver, in comparison with a standard HD decoding receiver.
  • Fig. 2 is a diagram schematically illustrating a workflow of a SABM algorithm for marking bits in comparison with a standard BDD algorithm without SABM.
  • Fig. 3 schematically illustrates how bit reliability measures are updated at each iteration for both row and column decoding.
  • Fig. 4 schematically illustrates numerical results for a Product Codes, PCs, of rate ⁇ ° ⁇ 78 , respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR-ST algorithm.
  • Fig. 5 schematically illustrates numerical results for a Product Codes, PCs, of rate ⁇ 0 87 , respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR-ST algorithm.
  • Fig. 6 schematically illustrates a receiver implementing the algorithm for bit marking and decoding according to the present disclosure.
  • Iterative decoding is based on the idea of breaking up a decoding problem into a sequence of stages or iterations, such that each stage or iteration utilizes an output from previous decoding stages or iterations to formulate its own result.
  • Simple but powerful hard-decision FEC, HD-FEC, codes, such as product codes, PCs, and staircase codes, SCCs, are currently receiving consideration attention in their application to optical transport networks, OTNs.
  • PC has been adopted, as an inner code, in the subclass 1.5 of ITU-T Recommendation G.975.1
  • SCC is part of the 400ZR Implementation Agreement, as an outer code, in the Optical Internetworking Forum.
  • SCC is also recommended for 100G optical transport unit, OUT, order 4 for long-reach applications in the ITU-T Recommendation G.709.2/Y.1331.2.
  • Iterative BDD as an iterative decoding algorithm, when applied to decode PCs, can lead to substantial coding gains.
  • the error-correcting capability of BDD that is, a number of incorrectly decoded bit f, is limited to where do is a the minimum Humming distance, MHD, of a component code. This limited error-correcting capability of BDD may lead decoding failures and miscorrections, which is considered as main performance limitation of BDD.
  • BDD is used to decode, in Hamming space, a received bit sequence r for a component code C comprising codewords c.
  • the MHD do of C must satisfy d 0 3 2t + 1.
  • every codeword c in the code C can be associated to a sphere of radius t. Within such a sphere, no other codewords exist. If the received bit sequence rfalls inside one of these spheres, BDD will decode r to the corresponding codeword c. Otherwise, BDD will declare a failure.
  • H(G, C) is the Hamming distance between r and c.
  • BDD is a syndrome-based decoder that uses syndromes to estimate the error pattern e. If the syndromes are all zeros, no errors are present. For the first two cases in equation (1), BDD will declare decoding success. In the second case, although BDD will still return an error pattern e, this case corresponds to a miscorrection. The third case is considered as decoding failure, and the received bit sequence r is output as the codeword.
  • SABM soft-aided bit-marking
  • Figure 1 schematically illustrates a system model 10 of a receiver implementing a SABM scheme, in comparison with a standard HD decoding receiver.
  • the receiver may be an optical receiver or an optical transponder comprising a receiver module.
  • the receiver 10 may further comprise at least optical front end components, a digital signal processor, DSP, which provides digital signal input to a decoder, such as a FEC decoder in which a decoding algorithm as herein described is implemented.
  • DSP digital signal processor
  • the decoder may be implemented on, for example, a chip along with the DSP and other components of the receiver. It can be contemplated by those skilled in the art that the algorithm of the present disclosure may also be implementable in a non-optical system.
  • the algorithm provides lower complexity, lower gate count in the chip, thereby lowering overall power consumption. Data flow within the chip is made more efficient by using the algorithm as disclosed herein, which contributes to lower power consumption.
  • the receiver will be a module or device comprising a decoder for decoding received bits.
  • the bit-to-symbol mapping may be for example a binary reflected Gray code.
  • FIG. 1 The upper part of Figure 1 within a dashed box illustrates a standard HD receiver 1 1 comprising a decoder 1 12.
  • a received signal y is input to an HD-based demapper 1 11 , which estimates code bits of the received signal. The estimated bits are then fed to the decoder 1 12 for decoding.
  • the received signal is also input to a bit reliability calculation module 1 13, which uses partial soft information from a medium influencing the received signal, such as a communication channel for transmitting the received signal, to determine reliabilities of bits of the received signal.
  • bit marking module 1 14 a sequence of bits marked by a bit marking module 1 14 will also be made available to the decoder 1 12.
  • These marked bits can be marked as highly reliable bits, HRBs, highly unreliable bits, HUBs, or neither.
  • the marking is made based on the absolute value of the LLRs i k v.
  • a bit with a LLR higher than or equal to a preset threshold will be marked as a HRB, while a bit with a LLR smaller than the preset threshold will be marked as HUB.
  • Figure 2 is a diagram 20 schematically illustrating a workflow of a SABM algorithm for marking bits in comparison with a standard BDD algorithm without SABM.
  • a successful BDD decoding does not always guarantee that the transmitted codeword c is correctly recovered. If more than t errors are introduced by a communication channel over which the codeword c is transmitted, and r is within t positions from a codeword c' 1 c, the decoder will select c' as opposed to c, resulting in a so called miscorrection. Miscorrections often result in the decoder adding more errors than the ones introduced by the channel, thus leading to a deterioration of the BDD performance.
  • SABM tackles both decoding failures and miscorrections via a twofold action: miscorrection detection and bit flipping. This approach is enabled by the use of soft quantities or reliabilities extracted from the channel.
  • LLRs are used as a bit reliability measure.
  • bits are marked as HRBs, when they fall above such a threshold.
  • HUBs Two rules are adopted to prevent a miscorrection: i) the BDD decoder can never flip a bit from a previously successfully decoded codeword; ii) HRBs can never be flipped. When either a failure occurs or a miscorrection is detected, a new decoding attempt is performed after bit flipping, as illustrated in Figure 2.
  • bit flipping is performed to produce a new received bit sequence r’.
  • a new decoding attempt such as by BDD, is performed at block 250, to produce a new decoded codeword ⁇ ' with optionally an error pattern e’.
  • the received sequence r is output at step 290.
  • Bit flipping is used to facilitate an additional decoding attempt.
  • the LLRs of bits of the received sequence are ordered based on their magnitudes and the least reliable bit is flipped in the case of a failure.
  • the least dmn ⁇ t ⁇ w hi( e ) are flipped, where are the minimum Hamming distance of the component code and the error Hamming weight, respectively.
  • the decoder output is set equal to the decoder input and passed to the next BDD decoding stage. This process is performed for a few iterations.
  • bit marking occurs only once and is based on the channel LLRs. The same marking is then used over a certain number of iterations. This approach is, however, sub-optimal as the marking mask loses its validity after bits are updated at every iteration by the BDD decoder.
  • the present disclosure discloses a bit marking method that re-marks the output bits at each BDD iteration by defining a reliability measure for the outbound BDD decisions.
  • This reliability measure combines the BDD decisions linearly with the channels LLRs.
  • the BDD output can provide at each iteration (quantized) a-posteriori information by assigning values -1 , and +1 for successfully decoded bits 0 and 1 , respectively.
  • the output of the BDD will instead be identically set to 0.
  • Figure 3 schematically illustrates how bit reliabilities are updated at each iteration for both row and column decoding.
  • FIG. 3 refers to one generic decoding iteration of a decoder applied to a PC.
  • Each decoding iteration is illustrated to comprise two soft-aided bit-marking decoders.
  • Each decoder deals with row decoding and column decoding, respectively.
  • a scaled reliability Y ⁇ ] , SR 33, after row decoding at each iteration may be defined or calculated 34 as:
  • ⁇ are optimised real-valued weights and are for example the LLRs.
  • Block 34 may be implemented using operational gates of for example an Integrated Chip.
  • the SR 33 can be used to update a SABM marking stage 35. This approach is therefore referred as SABM-SR.
  • a bit marking block takes as an input the SRs 33 from a previous (column) decoding stage or iteration, and yields a new set of marked bits Yu 36. The new marked bits 36 are then passed to a SABM row decoder
  • the reliability information at each iteration is used merely used to re-mark the bits at the input of the next BDD decoding iteration, and the BDD output D ' 7 is still used as the input of the next BDD decoder.
  • the first indicator Ul is a parameter generated for the bit sequence based on whether the bits are successfully decoded, and the second indicator reflects reliabilities of the bits.
  • a variant of the SABM-SR decoder described above may include adjustable marking thresholds to account for SRs scaling over multiple iterations. The rationale behind this choice is minimising the probability of wrong miscorrection detection or of not detecting a miscorrection.
  • This variant of the SABM-SR decoding approach is referred to as SABM-SR-ST, where“ST” stands for“scaled threshold”.
  • the reliability threshold is also scaled accordingly.
  • the decoding process improved with the bit-marking method in accordance with the present disclosure is numerically assessed in an additive white Gaussian noise channel with binary antipodal modulation, 2PAM, and noise power spectral density .
  • Figure 4 is a graph 40 that schematically illustrates numerical results for a set of PCs of rate ⁇ 0 78 (extended BCH (7,2, 1)), respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR- ST algorithm.
  • Figure 5 is a graph 50 that schematically illustrates numerical results for a PCs of rate ⁇ 0 87 (extended BCH (8,2, 1)), respectively decoded using a standard BDD algorithm, a SABM algorithm, a SABM-SR algorithm, and a SABM-SR- ST algorithm.
  • E b /N 0 ou tp U t of the SABM-SR and SABM-SR-ST decoders are illustrated respectively as lines 41 and 42.
  • Other decoding algorithms are also shown as a reference. These include a line 43 for iBDD, an ideal miscorrection-free iBDD, a line 44 for SABM, and a line 45 for turbo-product decoder, TPD, which adopts the so-called Chase-Pyndiah algorithm.
  • TPD can be considered a“fully-fledged” SD decoder and therefore of a much higher complexity than all other HD algorithms presented.
  • the present disclosure provides a simple and effective algorithm to improve the decoding of PCs as well as SCCs, without significantly increasing the decoding complexity, latency and decoder data-flow. Therefore, the present disclosure can be advantageously used many application involving HD decoders, in particular for example to relax the requirements on the optical transceivers or boost the transmission data rates in the 100G/400G or beyond OTNs.
  • Techniques used in this present disclosure are also suitable for other hard-decision codes that the optical communication community is interested in.
  • the method can be applied to concatenation coding schemes based on Hamming codes, BCH codes and Reed-Solomon codes for example.
  • the algorithm could in principle boost the performance of all these codes.
  • SCCs have also attracted much attention from the security fields, e.g., using SCCs to construct threshold changeable secret sharing. It can be contemplated by those skilled in the art the present disclosure is also applicable to security field as it can improve the performance significantly.
  • Figure 6 schematically illustrates a receiver 60 implementing the algorithm for bit marking and decoding according to the present disclosure.
  • the receiver 60 may comprises, among others, a bit marking device 61 , and a decoder 62. Although illustrated as two separate devices, in practice the bit marking device 61 may be an integral part of the decoder 62.
  • the bit marking device 61 may comprise a bit reliability calculation module 63 configured for computing reliability measures for bits output from a previous decoding iteration based on information 64 received the previous decoding iteration, and sending the computed reliability measures to a bit marking module 65.
  • a bit reliability calculation module 63 configured for computing reliability measures for bits output from a previous decoding iteration based on information 64 received the previous decoding iteration, and sending the computed reliability measures to a bit marking module 65.
  • the bit marking module 65 is configured for marking the output bits based on the received reliability measures.
  • the marked bits are then fed to the decoder 62.
  • the decoder 62 therefore may comprise a bit receiving module 66, and among others, a bit flipping module 67 and a decoding module 68.
  • the received marked bits may be flipped by the bit flipping module 67 and then decoded at the decoding module 68.
  • decoded bits and indication information for calculation of reliability measures for the decoded bits are output 69 to a next stage or iteration.
  • Figure 6 is for illustrative purpose only and shows only a decoding stage of the receiver.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un procédé de marquage d'une séquence de bits à décoder à une itération de décodage par un décodeur au niveau d'une extrémité de réception d'un canal de communication dans un système de communication. La séquence de bits est des bits de sortie provenant d'une itération de décodage précédente du décodeur, le décodeur utilise des calculs de décodage de correction d'erreur directe de décision dure. Le procédé utilise des mesures de fiabilité calculées respectivement pour chacun des bits de sortie qui prennent en considération à la fois des défaillances de décodage potentielles et des erreurs possibles des bits de sortie pour marquer la séquence de bits, ce qui permet au décodeur d'effectuer une ou d'autres itérations de décodage qui aident à assurer un décodage correct de la séquence de bits.
PCT/EP2020/063701 2019-05-17 2020-05-15 Procédé de marquage de bits, procédé de décodage de bits, dispositif de marquage de bits, décodeur, récepteur et puce WO2020234185A1 (fr)

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