WO2020233575A1 - Procédé de réalisation de fonction usb otg - Google Patents

Procédé de réalisation de fonction usb otg Download PDF

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Publication number
WO2020233575A1
WO2020233575A1 PCT/CN2020/091115 CN2020091115W WO2020233575A1 WO 2020233575 A1 WO2020233575 A1 WO 2020233575A1 CN 2020091115 W CN2020091115 W CN 2020091115W WO 2020233575 A1 WO2020233575 A1 WO 2020233575A1
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WO
WIPO (PCT)
Prior art keywords
usb
pin
power
socket
mode
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Application number
PCT/CN2020/091115
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English (en)
Chinese (zh)
Inventor
陈斯伟
张坤
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晶晨半导体(上海)股份有限公司
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Publication of WO2020233575A1 publication Critical patent/WO2020233575A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of OTG functions, in particular to a method for realizing USB OTG functions.
  • USB Universal Serial Bus
  • USB Universal Serial Bus
  • a plug with a plug on one side and a receptacle on the other.
  • a socket on a computer is a female connector
  • a USB device uses a male connector to connect to the computer.
  • USB hardware interfaces There are currently three types of USB hardware interfaces. The type used on ordinary computers is called Type; the original interface used in Nokia's feature phone era is Mini USB; and the current Micro USB used in Android phones.
  • USB OTG is the abbreviation of USB On-The-Go, which is a technology developed in recent years. On The Go, this is a form introduced in USB 2.0, and a new concept called Host Negotiation Protocol (Host Negotiation Protocol) is proposed, which allows two devices to negotiate who will be the Host.
  • the OTG controller can be used as a host or a device. The role of the controller is generally determined by the USB ID level.
  • USB_ID switch As the design and appearance require more and more structures to reserve only one USB socket, the reserved USB can only be used for software burning and host functions, and cannot be used for USB OTG use and cannot be opened during debugging.
  • the industry's approach is to increase the miniUSB or mircoUSB interface, add a small hole in the structure to lead to the USB_ID switch. Such an operation mode needs to improve the structure of the USB socket, which makes the cost higher.
  • a method for implementing USB OTG functions including:
  • Step S1 Provide a detection circuit, which is respectively connected to a USB socket and a USB control chip;
  • Step S2 The detection circuit is used to identify the working mode of the USB socket, and the working mode of the USB socket is set to a working mode adapted to an external device through the USB control chip.
  • the USB socket is a type A socket, and the USB socket includes at least eight pins.
  • the detection circuit includes:
  • a first power terminal providing a first power voltage
  • a second power terminal providing a second power voltage
  • a third power supply terminal providing a third power supply voltage
  • a detection unit the detection unit is respectively connected between the first voltage terminal, the second power terminal, the third power terminal, the USB control chip and the USB socket.
  • the USB control chip includes:
  • a first data pin used to implement the USB power pin
  • a second data pin used to implement USB OTG detection pin
  • An ID pin used to realize the USB ID pin
  • a data negative signal pin used to realize the USB OTG negative voltage pin
  • a data positive signal pin used to realize the USB OTG positive voltage pin.
  • the detection unit includes:
  • a triode the emitter of the triode is connected to the first data pin, and the base of the triode is connected to the second voltage terminal through a third resistor;
  • a MOS tube the gate of the MOS tube is connected to the collector of the triode through a fourth resistor, the source of the MOS tube is connected to the third power terminal, and the drain of the MOS tube is connected to the USB The power pin of the socket;
  • a fifth resistor connected to the power pin and the second data pin of the USB socket
  • a sixth resistor connected between the second data pin and the ground terminal
  • a seventh resistor connected between the third power terminal and the collector of the triode
  • a first capacitor connected between the first power terminal and the ground terminal
  • a second capacitor is connected between the third power terminal and the gate of the MOS transistor.
  • the step S2 includes:
  • Step S20 the first data pin outputs a high level within a preset time, so that the power pin of the USB socket has no power mode
  • Step S21 Detect whether the USB OTG detection pin is in a low level mode through the second data pin;
  • USB socket enters the host mode and goes to step S22;
  • USB socket If not, the USB socket enters the external device mode
  • Step S22 Determine whether the USB socket communication is successful
  • the preset time is set to at least 100 ms.
  • the communication with the host device is completed.
  • step S22 when the USB socket enters the host mode, communication with the external device is completed.
  • the beneficial effect of the technical solution of the present invention is to provide a method for realizing the USB OTG function, by adopting a detection circuit to identify the external device mode and the host mode of the USB socket, so that the USB socket is switched between the external device mode and the host mode, respectively Communicate with host device or external device to realize OTG function.
  • the circuit structure is simple, and the test function can be displayed, which is convenient for promotion.
  • FIG. 1 is a flowchart of steps of a method for implementing USB OTG functions according to an embodiment of the present invention
  • step S2 is a flowchart of step S2 of the method for implementing USB OTG function according to an embodiment of the present invention
  • Fig. 3 is a circuit connection diagram of the detection circuit of the embodiment of the present invention.
  • the present invention includes a method for realizing USB OTG function, including:
  • Step S1 Provide a detection circuit, which is respectively connected to a USB socket J and a USB control chip U;
  • Step S2 The detection circuit is used to identify the working mode of the USB socket J, and the working mode of the USB socket J is set to a working mode adapted to the external device through the USB control chip U.
  • the detection circuit is used to identify the external device mode and the host mode of the USB socket J, so that the USB socket J is switched between the external device mode and the host mode, respectively Communicate with host device or external device to realize OTG function.
  • the detection circuit detects that there is voltage
  • the USB socket J is in the external device mode to complete communication with the host device
  • the detection circuit does not detect voltage
  • the USB socket J is in the host mode and communicates with the external device.
  • the USB socket J enters the external device mode, it completes the communication with the host device, and when the USB socket J enters the host mode, it completes the communication with the external device.
  • USB control chip U can be used as a host device or an external device.
  • the role of the USB control chip U is generally determined by the level of the USB ID.
  • USB ID is the input signal, defined by the USB OTG protocol, and used to identify the default role of the device connected to the USB socket J, that is, the host mode or the external device mode.
  • the USB ID is pulled up by default and is in the state of an external device. If the USB socket J needs to be in host mode, the control chip 3 will short the USB_ID to the ground, that is, when the input is 0, it means that the USB socket J is in host mode and communicates with the external device.
  • the USB socket is switched between the external device mode and the host mode, and communicates with the host device or the external device respectively to realize the OTG function.
  • the circuit structure is simple , Can display test function, easy to promote.
  • the USB socket J is a type A socket, and the USB socket J includes at least eight pins.
  • the eight pins include the power supply pin USB_OTG_5V, the positive voltage pin D+, the negative voltage pin D-, and the remaining four pins are connected to the ground terminal GND.
  • the most critical pin of the USB socket J is the power pin USB_OTG_5V.
  • the USB OTG detection pin USB OTG_DET of the USB control chip U is connected to the power pin USB_OTG_5V of the control USB socket J.
  • USB socket J When it is detected that the power pin USB_OTG_5V has voltage, Then the USB socket J is in the external device mode to complete the communication with the host device; when it is detected that the power pin USB_OTG_5V does not detect a voltage, the USB socket J is in the host mode and communicates with the external device.
  • the USB socket J is switched between the external device mode and the host mode, and communicates with the host device or the external device respectively to realize the OTG function.
  • the structure is simple, and the test function can be displayed, which is convenient for promotion.
  • the detection circuit includes:
  • a second power supply terminal S2 providing a second power supply voltage VCC2;
  • a detection unit the detection unit is respectively connected between the first voltage terminal S1, the second power terminal S2, the third power terminal S3, the USB control chip U and the USB socket J.
  • the first power supply voltage VCC1 is 5V
  • the second power supply voltage VCC2 is 3.3V
  • the third power supply voltage VCC3 is 5V
  • the first power supply S1 is connected to the power pin USB_OTG_5V of the USB socket J.
  • the detection unit mainly detects
  • the power pin USB_OTG_5V uses a detection unit to identify the external device mode and host mode of the USB socket J, so that the USB socket J switches between the external device mode and the host mode, and communicates with the host device or external device respectively to realize the OTG function ,
  • the circuit structure is simple, and the test function can be displayed, which is convenient for promotion.
  • the USB control chip U includes:
  • a first data pin GPIOA_0 used to realize the USB power pin USB_POWER;
  • USB_ID used to implement the USB ID pin USB_ID
  • a data negative signal pin USB_DM used to realize the USB OTG negative voltage pin USB OTG_B_DM, connected to the negative voltage pin D- of the USB socket J through the first resistor R1;
  • a data positive signal pin USB_DP is used to implement the USB OTG positive voltage pin USB OTG_B_DP, which is connected to the positive voltage pin D+ of the USB socket J through the second resistor R2.
  • the USB OTG detection pin USB OTG_DET is essentially the power pin USB_OTG_5V connected to the USB socket J, and the USB control chip U passes the detection
  • the voltage control of the power pin USB_OTG_5V of the USB socket J sets the working mode of the USB socket J to a working mode adapted to the external device.
  • the detection unit includes:
  • a triode Q1 the emitter of the triode Q1 is connected to the first data pin GPIOA_0, and the base of the triode Q1 is connected to the second voltage terminal S2 through a third resistor R3;
  • a MOS tube Q2 the gate of the MOS tube Q2 is connected to the collector of the transistor Q1 through a fourth resistor R4, the source of the MOS tube Q2 is connected to the third power terminal S3, and the drain of the MOS tube Q2 is connected to the power source of the USB socket J Pin USB_OTG_5V;
  • a seventh resistor R7 connected between the third power terminal S3 and the collector of the transistor Q1;
  • a first capacitor C1 connected between the first power terminal S1 and the ground terminal GND;
  • a second capacitor C2 is connected between the third power terminal S2 and the gate of the MOS transistor Q2.
  • the detection unit further includes a first voltage regulator tube D1 connected between the data positive signal pin USB_DP and the ground terminal, a second voltage regulator tube D2 connected between the data negative signal pin USB_DM and the ground terminal, and a transistor Q1 It is an NPN transistor, the MOS transistor Q2 is an N-type MOS transistor, the resistance of the third resistor R3 is 47K ohms, the resistance of the fourth resistor R4 is 100K ohms, and the resistance of the fifth resistor R5 is 5.1K ohms.
  • the resistance value of the resistor R6 is 10K ohms, the resistance value of the seventh resistor R7 is 47K ohms, and the resistance value of the eighth resistor R8 is 10K ohms.
  • the fifth resistor R5 and the sixth resistor R6 form a voltage dividing resistor, which is self-dividing node Connect to the USB OTG detection pin USB OTG_DET.
  • step S2 includes:
  • Step S20 Output a high level at the first data pin GPIOA_0 within a preset time, so that the power pin USB_OTG_5V of the USB socket J has no power mode;
  • Step S21 Detect whether the USB OTG detection pin USB OTG_DET is in low level mode through the second data pin GPIOA_1;
  • USB socket J enters the host mode, and goes to step S22;
  • USB socket J If not, the USB socket J enters the external device mode
  • Step S22 Judge whether the USB communication is successful
  • the preset time is set to at least 100 ms.
  • the working mode of the USB socket J in order to realize the USB OTG function, the working mode of the USB socket J must first be identified. Specifically, the first data pin GPIOA_0 outputs high every 100ms. The level makes the power pin USBOTG_B_5V of the USB socket J have no power mode, and the second data pin GPIOA_1 starts to detect the high and low level mode of the USB OTG detection pin USBOTG_DET, and enters when the USBOTG detection pin USBOTG_DET is high In the external device mode, when the USB OTG detection pin USB OTG_DET is low, it is necessary to determine whether to enter the host mode for external device communication, and if the communication fails, it will return to the mode recognition.
  • the power pin USBOTG_B_5V of the USB socket J introduces 5V power from the external device, and the voltage is divided by the fifth resistor R5 and the sixth resistor R6 to 3.3V to the second data pin GPIOA_1, when it is detected that the USB OTG detection pin USB OTG_DET is high, the first data pin GPIOA_0 outputs a high-level USB power pin USB_POWER to turn off the transistor Q1, and the MOS transistor Q2 is also turned off, and the USB power pin USB_POWER passes The eighth resistor R8 pulls up the USB_ID pin USB_ID so that the USB control chip U controls the USB socket J to enter the external device mode to communicate with the host device.
  • the power pin USB OTG_B_5V of the USB socket J has no power mode, and the sixth resistor R6 is pulled down to the ground terminal GND.
  • the second data pin GPIOA_1 detects the USB OTG detection pin USB OTG_DET is low level, and the first data pin GPIOA_0 outputs low level.
  • the USB power pin USB_POWER turns on the transistor Q1, and the MOS transistor Q2 is also turned on.
  • the USB power pin USB_POWER pulls down the USB_ID pin USB_ID through the eighth resistor R8.
  • the USB control chip U controls the USB socket J to enter the host mode to communicate with external devices.
  • the USB socket J is switched between the external device mode and the host mode, and communicates with the host device or the external device respectively to realize the OTG function.
  • the structure is simple, and the test function can be displayed, which is convenient for promotion.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Power Sources (AREA)

Abstract

L'invention concerne un procédé de réalisation d'une fonction USB OTG. Le procédé comprend les étapes suivantes : étape S1, fournir un circuit de détection, le circuit de détection étant respectivement connecté à une prise USB (J) et à une puce de commande USB (U) ; et étape S2, identifier un mode de fonctionnement de la prise USB (J) en utilisant le circuit de détection, et définir, au moyen de la puce de commande USB (U), le mode de fonctionnement de la prise USB (J) pour qu'il soit un mode de fonctionnement adaptatif par rapport à un dispositif externe. En utilisant un circuit de détection, un mode de dispositif externe et un mode d'hôte d'une prise USB (J) sont identifiés, de sorte que la prise USB (J) soit commutée entre le mode de dispositif externe et le mode d'hôte et communique respectivement avec un dispositif hôte ou un dispositif externe pour réaliser une fonction OTG ; de plus, la structure du circuit est simple, une fonction de test peut être affichée, et la popularisation est facilitée.
PCT/CN2020/091115 2019-05-21 2020-05-19 Procédé de réalisation de fonction usb otg WO2020233575A1 (fr)

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CN201910425274.8 2019-05-21

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CN110297789B (zh) * 2019-05-21 2023-07-28 晶晨半导体(上海)股份有限公司 一种实现usb otg功能的方法

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CN106571657A (zh) * 2016-09-28 2017-04-19 上海创功通讯技术有限公司 终端、转换器以及连接转换系统和方法
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