WO2020232681A1

WO2020232681A1 - Level shift circuit and electronic device

Info

Publication number: WO2020232681A1
Application number: PCT/CN2019/088030
Authority: WO
Inventors: 周佳
Original assignee: 华为技术有限公司
Priority date: 2019-05-22
Filing date: 2019-05-22
Publication date: 2020-11-26
Also published as: CN113767572A; CN113767572B

Abstract

The present application provides a level shift circuit and an electronic device. The level shift circuit comprises: a first current source, a second current source, and a voltage-variable circuit. The voltage-variable circuit comprises: a resistor and a transistor coupled. A drain of the transistor is coupled to a first end of the resistor, a second end of the resistor is coupled to the first current source, a source of the transistor is coupled to the second current source, and a gate of the transistor is coupled to the first end or second end of the resistor. Therefore, the impedance in the level shift process is reduced, the noise performance of the level shift circuit is optimized, and the linearity loss of the level shift circuit is reduced.

Description

Level conversion circuit and electronic equipment

Technical field

This application relates to the field of electronic technology, and in particular to a level conversion circuit and electronic equipment.

Background technique

In the process of analog signal processing, it is usually necessary to boost or step down the direct current (DC) voltage or common mode voltage of the analog signal. In this process, it is necessary to preserve the original characteristics of the analog signal as much as possible For example, from DC to high frequency bandwidth range of signal amplitude, signal linearity, signal noise, etc., at the same time, it is also necessary to reduce power consumption as much as possible.

The level conversion circuit can realize the conversion of DC voltage or common mode voltage. For example, the level conversion circuit can adopt a resistor and capacitor (RC) structure, and can convert the input voltage value (such as DC level) to the target value, and then use a push-pull input buffer to perform the input voltage Buffer and input so that the amplitude of input voltage and output voltage remain basically unchanged. For another example, the level conversion circuit can adopt the structure of pure resistance, and use the circuit with common mode feedback to detect whether the output voltage (such as the common mode voltage) is the target value, and perform the access amplitude of the pure resistance according to the detection result. Dynamic adjustment to achieve level conversion.

However, the currently used level conversion circuit not only has high noise and poor linearity, but also easily causes adverse effects on the previous circuit.

Summary of the invention

The application provides a level conversion circuit and electronic equipment to improve the problems of large noise and poor linearity caused by the existing level conversion circuit, reduce the impedance of the level conversion process, and optimize the level conversion circuit The noise performance reduces the linearity loss of the level conversion circuit.

In the first aspect, the present application provides a level conversion circuit, including: a first current source, a second current source, and a transformer circuit. The transformer circuit includes a resistor and a transistor, wherein the drain of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, the source of the transistor is coupled to the second current source, and the gate of the transistor is coupled to The first end of the resistor or the second end of the resistor.

Among them, the field effect transistor (field effect transistor, FET). For example, the field effect transistor may include junction field-effect transistor (JFET), metal oxide semiconductor field-effect transistor (metal oxide semiconductor FET, MOSFET), and V-groove field effect transistor (V-groove metal -oxide semiconductor FET, VMOSFET), MOSFET can include N-type metal oxide semiconductor field effect transistor (NMOSFET, referred to as NMOS tube) and P-type metal oxide semiconductor field effect transistor (PMOSFET, referred to as PMOS tube).

With the level conversion circuit provided by the first aspect, the drain of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, the source of the transistor is coupled to the second current source, and the gate of the transistor is The pole is coupled to the first end of the resistor or the second end of the resistor, so that the first current source, the transformer circuit, and the second current source form a loop. Thus, the first current source and the second current source can adjust the current flowing through the transformer circuit, so that the transformer circuit can convert the received input voltage into an output voltage. In this application, since the transformer circuit includes coupled resistors and transistors, the existing pure resistance structure is replaced with a resistor and transistor structure, which reduces the impedance of the level conversion circuit and optimizes the noise performance of the level conversion circuit. Reduce the linearity loss of the level conversion circuit.

In a possible design, the transistor is a first NMOS tube, and the gate of the first NMOS tube is coupled to the second end of the resistor.

In order to realize the step-up process of the transformer circuit, the source of the first NMOS tube is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the gate of the first NMOS tube is the output terminal of the transformer circuit, which can be used to output output Voltage.

In order to realize the step-down process of the transformer circuit, the gate of the first NMOS tube is the input terminal of the transformer circuit, which can be used to receive input voltage, and the source of the first NMOS tube is the output terminal of the transformer circuit, which can be used to output output Voltage.

The level conversion circuit provided by this embodiment adopts the structure of a resistor and a first NMOS transistor to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the first NMOS transistor, that is, the diode (Diode) coupling mode, the first current source and the second current source adjust the current flowing through the first NMOS tube so that the first NMOS tube works in a linear region. In this way, the transformer circuit converts the input voltage The output voltage whose amplitude is the target value is more effective.

In a possible design, the transistor is a second NMOS tube, and the gate of the second NMOS tube is coupled to the first end of the resistor.

In order to realize the boost process of the transformer circuit, the source of the second NMOS tube is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the second end of the resistor is the output terminal of the transformer circuit, which can be used to output the output voltage. .

In order to realize the step-down process of the transformer circuit, the second terminal of the resistor is the input terminal of the transformer circuit, which can be used to receive input voltage, and the source of the second NMOS tube is the output terminal of the transformer circuit, which can be used to output output voltage. .

The level conversion circuit provided by this embodiment adopts a resistor and a second NMOS tube structure to replace the existing pure resistance structure, wherein the two ends of the resistor are coupled to the gate and drain of the second NMOS tube respectively, that is, Diode The first current source and the second current source adjust the current flowing through the second NMOS tube so that the second NMOS tube works in the saturation region or the sub-threshold region. In this way, the transformer circuit converts the input voltage into an amplitude The output voltage of the target value is more effective.

In a possible design, the transistor is a first PMOS tube, and the gate of the first PMOS tube is coupled to the second end of the resistor.

In order to realize the step-up process of the transformer circuit, the gate of the first PMOS tube is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the source of the first PMOS tube is the output terminal of the transformer circuit, which can be used to output output Voltage.

In order to realize the step-up process of the transformer circuit, the source of the first PMOS tube is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the gate of the first PMOS tube is the output terminal of the transformer circuit, which can be used to output output Voltage.

The level conversion circuit provided by this embodiment uses a resistor and a first PMOS tube structure to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the first PMOS tube, that is, Diode The first current source and the second current source adjust the current flowing through the first PMOS tube to make the first PMOS tube work in the linear region. In this way, the transformer circuit converts the input voltage into a target value The output voltage effect is better.

In a possible design, the transistor is a second PMOS tube, and the gate of the second PMOS tube is coupled to the first end of the resistor.

In order to realize the step-up process of the transformer circuit, the second end of the resistor is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the source of the second PMOS tube is the output terminal of the transformer circuit, which can be used to output the output voltage. .

In order to realize the step-down process of the transformer circuit, the source of the second PMOS tube is the input terminal of the transformer circuit, which can be used to receive the input voltage, and the second end of the resistor is the output terminal of the transformer circuit, which can be used to output the output voltage. .

The level conversion circuit provided by this embodiment uses a resistor and a second PMOS structure to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the second PMOS, that is, the coupling of the diode In this way, the first current source and the second current source adjust the current flowing through the second PMOS so that the second PMOS works in the saturation region or the sub-threshold region. In this way, the transformer circuit converts the input voltage into a target value The output voltage effect is better.

In a possible design, the transformer circuit further includes a capacitor, which is coupled in parallel between the input terminal and the output terminal of the transformer circuit to obtain better noise performance and high frequency performance.

In a possible design, the first current source and the second current source are used to adjust the current of the first current source and the current of the second current source respectively, so that the current of the first current source and the second current source The currents of the current sources are equal. Thus, the first current source and the second current source can adjust the current flowing through the transformer circuit.

Generally, when the amplitude of the output voltage is greater than the target value, the first current source and the second current source can reduce the current flowing through the transformer circuit, so that the amplitude of the output voltage becomes smaller to adjust to the target value. When the amplitude of the output voltage is less than the target value, the first current source and the second current source can increase the current flowing through the transformer circuit, so that the amplitude of the output voltage becomes larger to adjust to the target value. When the amplitude of the output voltage is equal to the target value, the first current source and the second current source do not need to adjust the current flowing through the transformer circuit, so that the transformer circuit can output the output voltage with the amplitude of the target value.

In a possible design, the first current source is used to adjust the current of the first current source according to the received first feedback signal, and the first feedback signal is used to indicate that the amplitude of the output voltage is not the target value. The second current source is used to adjust the current of the second current source according to the received second feedback signal, and the second feedback signal is used to indicate that the amplitude of the output voltage is not the target value. Wherein, the first feedback signal and the second feedback signal are usually voltages of different amplitudes. Thus, the adjustment process of the current flowing through the transformer circuit is realized.

In this application, the implementation of the first current source and the second current source may adopt adjustable resistors, or may adopt MOS transistors or bipolar junction transistors (BJT), etc., and may also be a combination of resistors and MOS transistors. It can also be a combination of resistance and BJT, or a combination of resistance, MOS tube and BJT, this application is not limited to this, as long as the first current source and the second current source can adjust the current flowing through the transformer circuit OK.

In a possible design, the level conversion circuit further includes: a first control circuit. The input terminal of the first control circuit is coupled to the output terminal of the transformer circuit, the first output terminal of the first control circuit is coupled to the first current source, and the second output terminal of the first control circuit is coupled to the second current source. The first control circuit is used to receive the output voltage from the transformer circuit. The first control circuit is also used to send a first feedback signal to the first current source and a second feedback signal to the second current source when it is determined that the amplitude of the output voltage is not the target value.

In a possible design, the first current source includes a third PMOS tube, the second current source includes a third NMOS tube, and the first control circuit includes a voltage feedback circuit, a fourth PMOS tube, and a fourth NMOS tube.

Wherein, the source of the third PMOS tube is coupled with the power supply level, the drain of the third PMOS tube is coupled to the second end of the resistor, and the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube. The drain of the third NMOS tube is coupled to the source of the transistor, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is coupled to the gate of the fourth NMOS tube. The source of the fourth PMOS tube is coupled with the supply voltage, the gate and drain of the fourth PMOS tube are both coupled to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is grounded, and the gate of the fourth NMOS tube is also The input terminal of the voltage feedback circuit is the input terminal of the first control circuit, and the input terminal of the voltage feedback circuit is coupled to the output terminal of the transformer circuit.

In this application, the voltage feedback circuit is used to receive the output voltage from the transformer circuit and judge whether the current amplitude of the output voltage is the target value. The voltage feedback circuit is also used to send an adjustment signal to the fourth NMOS tube when the amplitude of the output voltage is not the target value. The adjustment signal is used for the fourth PMOS tube to send the first feedback signal to the third PMOS tube, and the fourth The NMOS tube sends the second feedback signal to the third NMOS tube.

Among them, the fourth PMOS tube in the first control circuit can be used as the current mirror of the third PMOS tube, the fourth PMOS tube sends the first feedback signal to the third PMOS tube, and the fourth NMOS tube in the first control circuit can be used as The current mirror of the third NMOS tube sends the second feedback signal from the fourth NMOS tube to the third NMOS tube.

On the one hand, the adjustment signal can send the first feedback signal to the third PMOS transistor via the fourth NMOS tube and the fourth PMOS tube to adjust the current of the third PMOS tube.

On the other hand, the adjustment signal can send a second feedback signal to the third NMOS tube through the fourth NMOS tube to adjust the current of the third NMOS tube, and to ensure the current of the third PMOS tube and the current of the third NMOS tube. On an equal basis, the adjustment of the current flowing through the transformer circuit is realized.

In a possible design, the level conversion circuit further includes: M first current sources, M second current sources, M transformer circuits, and second control circuits, where M is a positive integer. Among them, M+1 first current sources, M+1 second current sources and M+1 transformer circuits are coupled in a one-to-one correspondence, and M+1 input terminals of the second control circuit are coupled with M+1 transformer circuits. The output terminals of the circuit are coupled in one-to-one correspondence, the M+1 first output terminals of the second control circuit are coupled to the M+1 first current sources in one-to-one correspondence, and the M+1 second output terminals of the second control circuit are coupled with The M+1 second current sources are coupled in a one-to-one correspondence. The second control circuit is used to receive an output voltage from each transformer circuit. The second control circuit is also used to send a first feedback signal to each first current source and a second feedback to each second current source when the average value of the amplitude of the M+1 output voltages is not the target value signal.

In this application, the M+1 first current source and the M+1 second current source can adjust the current flowing through the transformer circuit corresponding to the first current source and the second current source, so that the M+1 transformer The average value of the amplitude of the output voltage output by each circuit is the target value, which can improve the accuracy of the output voltage and make the level conversion process more effective.

It should be noted that the level conversion circuit can not only adopt a structure including a first current source, a second current source, a transformer circuit, and a first control circuit, but also a structure that includes M+1 first The structure of the current source, M+1 second current source, M+1 transformer circuit, and second control circuit. In addition, a circuit (or unit or device or electronic device) can be integrated with multiple level conversion circuits such as any one of the above methods or including two of the above methods, which can convert one or more input voltages into different amplitudes. Value of the output voltage can also realize the process of step-up and step-down at the same time, providing various possibilities for the level conversion process and improving the processing efficiency of the circuit.

In a possible design, the second control circuit includes any one of a processor, a comparator with common mode feedback, or a comparator with common mode feedback and a buffer. Furthermore, the level conversion circuit provided by the present application can control the output common mode. By adjusting the two current sources at the same time, the driving capability requirements of the signal source can be reduced, and the process of common mode feedback can be realized. The matching problem makes the output common mode controllable, eliminates the DC current of the level conversion circuit to the previous circuit, and reduces the impact on the previous circuit.

In a possible design, the transistors in the second control circuit are of the same type as the transistors in the transformer circuit, which can reduce the influence of process-voltage-temperature (process-voltage-temperature, PVT) on the output common mode.

In a second aspect, the present application provides a level conversion circuit including: a first current source, a second current source, and a transformer circuit. The transformer circuit includes a resistor and a transistor, wherein the collector of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, the emitter of the transistor is coupled to the second current source, and the base of the transistor is coupled To the first end of the resistor or the second end of the resistor.

Among them, the transistors in the present application can also be of other types, such as transistors, which can include two types: PNP type transistors and NPN type transistors.

With the level conversion circuit provided in the second aspect, the collector of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, the emitter of the transistor is coupled to the second current source, and the base of the transistor is The pole is coupled to the first end of the resistor or the second end of the resistor, so that the first current source, the transformer circuit, and the second current source form a loop. Thus, the first current source and the second current source can adjust the current flowing through the transformer circuit, so that the transformer circuit can convert the received input voltage into an output voltage. In this application, since the transformer circuit includes coupled resistors and transistors, the existing pure resistance structure is replaced with a resistor and transistor structure, which reduces the impedance of the level conversion circuit and optimizes the noise performance of the level conversion circuit. Reduce the linearity loss of the level conversion circuit.

In one possible design, the transistor is a first NPN, and the base of the first NPN is coupled to the second end of the resistor.

In order to realize the step-up process of the transformer circuit, the transmitter of the first NPN can be used to receive the input voltage, and the base electrode of the first NPN can be used to output the output voltage.

In order to realize the voltage step-down process of the transformer circuit, the base of the first NPN can be used to receive the input voltage, and the emitter of the first NPN can be used to output the output voltage.

The level conversion circuit provided by this embodiment replaces the existing pure resistance structure with a resistor and a first NPN structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the first NPN, that is, the coupling of Diode In this way, the first current source and the second current source adjust the current flowing through the first NPN so that the first NPN works in the linear region. In this way, the transformer circuit converts the input voltage into the output voltage with the amplitude of the target value. Better.

In one possible design, the transistor is a second NPN, and the base of the second NPN is coupled to the first end of the resistor.

In order to realize the step-up process of the transformer circuit, the transmitter of the second NPN can be used to receive the input voltage, and the second end of the resistor is the output terminal of the transformer circuit and can be used to output the output voltage.

In order to realize the voltage step-down process of the transformer circuit, the second end of the resistor is the input terminal of the transformer circuit and can be used to receive the input voltage, and the emitter of the second NPN is the output terminal of the transformer circuit and can be used to output the output voltage.

The level conversion circuit provided by this embodiment adopts a resistor and a second NPN structure to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the second NPN, that is, the coupling of Diode In this way, the first current source and the second current source adjust the current flowing through the second NPN so that the second NPN works in the saturation region or the sub-threshold region. In this way, the voltage transformer circuit converts the input level to the target value. The output voltage effect is better.

In one possible design, the transistor is a first PNP, and the base of the first PNP is coupled to the second end of the resistor.

In order to realize the step-up process of the transformer circuit, the base of the first PNP can be used to receive the input voltage, and the emitter of the first PNP can be used to output the output voltage.

In order to realize the step-up process of the transformer circuit, the transmitter of the first PNP can be used to receive the input voltage, and the base electrode of the first PNP can be used to output the output voltage.

The level conversion circuit provided by this embodiment adopts a resistor and a first PNP structure to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the first PNP, that is, the coupling of Diode In this way, the first current source and the second current source adjust the current flowing through the first PNP so that the first PNP works in the linear region. In this way, the transformer circuit converts the input voltage into the output voltage with the amplitude of the target value. Better.

In one possible design, the transistor is a second PNP, and the base of the second PNP is coupled to the first end of the resistor.

In order to realize the step-up process of the transformer circuit, the second terminal of the resistor is the input terminal of the transformer circuit and can be used to receive the input voltage, and the emitter of the second PNP is the output terminal of the transformer circuit and can be used to output the output voltage.

In order to realize the voltage step-down process of the transformer circuit, the transmitter of the second PNP is the input terminal of the transformer circuit and can be used to receive the input voltage, and the second end of the resistor is the output terminal of the transformer circuit and can be used to output the output voltage.

The level conversion circuit provided by this embodiment adopts a resistor and a second PNP structure to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the second PNP, that is, the coupling of Diode In this way, the first current source and the second current source adjust the current flowing through the second PNP so that the second PNP works in the saturation region or the sub-threshold region. In this way, the transformer circuit converts the input voltage into a target value of amplitude The output voltage effect is better.

In a possible design, the level conversion circuit further includes: a first control circuit. The input terminal of the first control circuit is coupled to the output terminal of the transformer circuit, the first output terminal of the first control circuit is coupled to the first current source, and the second output terminal of the first control circuit is coupled to the second current source. The first control circuit is used to receive the output voltage from the transformer circuit. The first control circuit is further configured to send a first feedback signal to the first current source and a second feedback signal to the second current source when it is determined that the amplitude of the output voltage is not the target value.

In a possible design, the transistors in the second control circuit are of the same type as the transistors in the transformer circuit, which can reduce the influence of process-voltage-temperature on the output common mode.

In a third aspect, the present application provides an electronic device, including: an input end circuit, an output end circuit, and at least one possible implementation manner as in the above first aspect and the first aspect and/or at least one as in the above second aspect and The level conversion circuit of each possible implementation of the second aspect. Wherein, the level conversion circuit is coupled to the input terminal circuit and is used to receive the input voltage from the input terminal circuit. The level conversion circuit is coupled to the output terminal circuit and used for sending the output voltage to the output terminal circuit.

For the electronic equipment provided in the above-mentioned third aspect and each possible design of the above-mentioned third aspect, the beneficial effects can be referred to the above-mentioned first aspect and each possible implementation manner of the first aspect and/or the above-mentioned second aspect and second aspect The beneficial effects brought by each possible implementation manner of the aspect are not repeated here.

Description of the drawings

FIG. 1a is a schematic structural diagram of a level conversion circuit provided by this application;

FIG. 1b is a schematic structural diagram of a level conversion circuit provided by this application;

2 is a schematic circuit diagram of a level conversion circuit provided by this application;

3 is a schematic circuit diagram of a level conversion circuit provided by this application;

4 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 5 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 6 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 7 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 8 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 9 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 10 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 11 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 12 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 13 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 14 is a schematic circuit diagram of a level conversion circuit provided by this application;

15 is a schematic circuit diagram of a level conversion circuit provided by this application;

16 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 17 is a schematic circuit diagram of a level conversion circuit provided by this application;

18 is a schematic structural diagram of a level conversion circuit provided by this application;

FIG. 19 is a schematic circuit diagram of a level conversion circuit provided by this application;

FIG. 20 is a schematic diagram of an equivalent small signal model of a level conversion circuit provided by this application;

FIG. 21 is a schematic diagram of a current-voltage (I-V) curve and its DC resistance and AC resistance curves of a transistor in a level conversion circuit provided by this application;

FIG. 22 is a schematic structural diagram of a level conversion circuit provided by this application;

FIG. 23 is a schematic structural diagram of a level conversion circuit provided by this application;

FIG. 24 is a schematic structural diagram of a level conversion circuit provided by this application;

FIG. 25 is a schematic structural diagram of an electronic device provided by this application.

Reference signs:

10-level conversion circuit; 11-first current source; 12-second current source;

13—Transformer circuit; 14—First control circuit; 15—Second control circuit;

20—input circuit; 30—output circuit.

Detailed ways

The technical solutions in this application will be described below in conjunction with the drawings in this application. Among them, in the description of this application, unless otherwise specified, "/" means or, for example, A/B can mean A or B; "and/or" in this document is only an association describing the associated object Relationship means that there can be three kinds of relationships. For example, A and/or B can mean that: A alone exists, A and B exist at the same time, and B exists alone. Also, in the description of this application, unless otherwise specified, "plurality" means two or more than two. In addition, in order to facilitate a clear description of the technical solutions of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and order of execution, and words such as "first" and "second" do not limit the difference.

In this application, the coupling may be direct contact coupling or indirect coupling, which is not limited in this application.

Figures 1a and 1b show schematic structural diagrams of the level conversion circuit provided by the present application. As shown in FIGS. 1a and 1b, the level shifter (LS) of the present application may include: a first current source 11, a second current source 12, and a transformer circuit 13. Among them, the level conversion circuit 10 can be applied to, but not limited to, various scenarios where a direct current (DC) signal or a common mode signal in an analog signal is raised or lowered.

In this application, the transformer circuit 13 may include a resistor and a transistor. In Figures 1a and 1b, the resistor is identified by the letter "R", the first end of the resistor is identified by the number "1", the second end of the resistor is identified by the number "2", and the transistor is identified by the letter "Q".

Generally, a transistor has three electrodes. The resistor and at least one electrode of the transistor can be connected in series, in parallel, or in series and parallel. This application does not limit this, as long as the coupled resistor and the transistor jointly realize voltage conversion . In addition, this application does not limit the number and types of resistors and transistors.

Hereinafter, the coupling relationship between the resistor and the transistor will be described in detail with reference to FIGS. 1a and 1b.

In Figure 1a, the transistor can be a FET. For example, FET may include three types of JFET, MOSFET, and VMOSFET, and MOSFET may include two types of NMOS tube and PMOS tube.

As shown in Figure 1a, the drain of the transistor is coupled to the first end of the resistor, and the second end of the resistor is coupled to the first end of the first current source 11 (identified by the number "1" in Figure 1a). The source of the transistor is Coupled to the first terminal of the second current source 12 (identified by the number "1" in FIG. 1a), the gate of the transistor is coupled to the first terminal of the resistor or the second terminal of the resistor.

In addition, in FIG. 1b, the transistor may also be a transistor, and the transistor may include two types: a PNP type transistor and an NPN type transistor.

As shown in Figure 1b, the collector of the transistor is coupled to the first end of the resistor, and the second end of the resistor is coupled to the first end of the first current source 11 (identified by the number "1" in Figure 1a), and the emitter of the transistor Coupled to the first end of the second current source 12 (identified by the number "1" in FIG. 1a), the base of the transistor is coupled to the first end of the resistor or the second end of the resistor.

It should be noted that the embodiments shown in FIGS. 1a and 1b are only partial illustrations of the coupling relationship between the resistor and the transistor. Wherein, when the number and/or type of transistors are changed, the names of the three electrodes of the transistors correspondingly change, and the specific corresponding relationship can be determined according to the working principle of the transistors.

In the present application, the implementation of the first current source 11 and the second current source 12 may adopt adjustable resistors, MOS transistors or BJTs, a combination of resistors and MOS transistors, or a combination of resistors and BJTs. It can also be a combination of resistors, MOS transistors and BJTs. This application is not limited to this, as long as the first current source 11 and the second current source 12 can adjust the current flowing through the transformer circuit 13.

In this application, the power supply terminal of the first current source 11 is coupled with a power supply voltage (the power supply voltage can be set according to actual conditions), and the first terminal of the first current source 11 is coupled to the resistor and transistor in the transformer circuit 13 , The first terminal of the second current source 12 is coupled with the resistor and transistor in the transformer circuit 13, and the ground terminal of the second current source 12 is grounded. In this way, the first current source 11, the transformer circuit 13 and the second current The source 12 can form a loop, so that the first current source 11 and the second current source 12 can adjust the current flowing through the transformer circuit 13.

In the present application, the first current source 11 and the second current source 12 can adjust the current flowing through the transformer circuit 13 according to the amplitude of the output voltage output by the transformer circuit 13. Generally, when the amplitude of the output voltage is greater than the target value, the first current source 11 and the second current source 12 can reduce the current flowing through the transformer circuit 13 so that the amplitude of the output voltage becomes smaller to adjust to the target value. value. When the amplitude of the output voltage is smaller than the target value, the first current source 11 and the second current source 12 can increase the current flowing through the transformer circuit 13 so that the amplitude of the output voltage becomes larger to adjust to the target value. When the amplitude of the output voltage is equal to the target value, the first current source 11 and the second current source 12 may not need to adjust the current flowing through the transformer circuit 13 so that the transformer circuit 13 can output the output voltage with the amplitude of the target value.

Those skilled in the art can understand that when the current flowing through the transformer circuit 13 changes, and the amplitude of the input voltage received by the transformer circuit 13 remains unchanged, the amplitude of the output voltage will change. Moreover, since the amplitude of the voltage required by the output circuit is usually fixed (ie, the target value), the transformer circuit 13 needs to convert the input voltage into an output voltage with the amplitude of the target value.

Among them, the specific amplitudes of the input voltage and the output voltage can be set according to actual conditions, which are not limited in this application.

Based on the foregoing, on the one hand, the first current source 11 and the second current source 12 can keep the current flowing through the transformer circuit 13 unchanged when the amplitude of the output voltage is the target value, that is, there is no need to adjust the current flowing through the transformer circuit. The current of 13 allows the transformer circuit 13 to directly output an output voltage with a target value.

On the other hand, the first current source 11 and the second current source 12 can adjust the current flowing through the transformer circuit 13 when the amplitude of the output voltage is not the target value, so that the transformer circuit 13 can output the target amplitude. Value of the output voltage.

In this way, the step-up or step-down of the level conversion circuit 10 is completed, and the level conversion circuit 10 can output the voltage required by the output circuit (that is, the output voltage whose amplitude is the target value), so as to facilitate the output circuit to perform subsequent steps. The corresponding operation.

In the level conversion circuit provided by the present application, the drain of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, the source of the transistor is coupled to the second current source, and the gate of the transistor is coupled To the first end of the resistor or the second end of the resistor, the first current source, the transformer circuit and the second current source form a loop. Thus, the first current source and the second current source can adjust the current flowing through the transformer circuit, so that the transformer circuit can convert the received input voltage into an output voltage. In this application, since the transformer circuit includes coupled resistors and transistors, the existing pure resistance structure is replaced with a resistor and transistor structure, which reduces the impedance of the level conversion circuit and optimizes the noise performance of the level conversion circuit. Reduce the linearity loss of the level conversion circuit.

In this application, the transistors in the transformer circuit 13 may be various types of transistors. For ease of description, in Figure 2-17, the first current source 11 is identified by the letter "I1", the second current source 12 is identified by the letter "I2", the resistance is identified by the letter "R", and the input voltage is identified by the letter "Vin" Mark, the output voltage is marked with the letter "Vout".

When the transistor is a field effect tube, on the basis of the embodiment shown in FIG. 1a and in conjunction with FIG. 2 to FIG. 9, the following four feasible implementation manners are used to describe the specific structure of the level conversion circuit 10.

In a possible implementation manner, as shown in FIGS. 2 and 3, when the transistor is a first NMOS tube, the gate of the first NMOS tube is coupled to the second end of the resistor.

Among them, this application does not limit the specific number of the first NMOS transistors. For ease of description, in FIG. 2 and FIG. 3, the first NMOS transistor is one and is identified by the letter "M1".

On the one hand, as shown in FIG. 2, in order to realize the boost process of the transformer circuit 13, the source of the first NMOS transistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the gate of the first NMOS transistor is The output terminal of the voltage circuit 13 can be used to output an output voltage.

On the other hand, as shown in FIG. 3, in order to achieve the step-down process of the transformer circuit 13, the gate of the first NMOS transistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage. The source of the first NMOS transistor The output terminal of the transformer circuit 13 can be used to output an output voltage.

In this application, the structure of the resistor and the first NMOS tube is used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the first NMOS tube, that is, the Diode coupling method, the first current The source 11 and the second current source 12 adjust the current flowing through the first NMOS tube so that the first NMOS tube works in the linear region. In this way, the transformer circuit 13 converts the input voltage into an output voltage with a target value. Better.

In another feasible implementation manner, as shown in FIGS. 4 and 5, when the transistor is a second NMOS tube, the gate of the second NMOS tube is coupled to the first end of the resistor.

Among them, this application does not limit the specific number of the second NMOS transistors. For ease of description, in FIGS. 4 and 5, the second NMOS transistor is one and is identified by the letter "M2".

On the one hand, as shown in FIG. 4, in order to realize the step-up process of the transformer circuit 13, the source of the second NMOS tube is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the second end of the resistor is the transformer. The output terminal of the circuit 13 can be used to output the output voltage.

On the other hand, as shown in Figure 5, in order to achieve the step-down process of the transformer circuit 13, the second end of the resistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage. The source of the second NMOS transistor is changed. The output terminal of the voltage circuit 13 can be used to output an output voltage.

In this application, the structure of the resistor and the second NMOS tube is used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the second NMOS tube, that is, the coupling method of Diode, the first current The source 11 and the second current source 12 adjust the current flowing through the second NMOS tube to make the second NMOS tube work in the saturation region or the sub-threshold region. In this way, the voltage transformer circuit 13 converts the input voltage into a target value. The output voltage effect is better.

In another feasible implementation manner, as shown in FIGS. 6 and 7, when the transistor is a first PMOS tube, the gate of the first PMOS tube is coupled to the second end of the resistor.

Among them, this application does not limit the specific number of the first PMOS transistors. For ease of description, in FIG. 6 and FIG. 7, the first PMOS transistor is one and is identified by the letter "M3".

On the one hand, as shown in FIG. 6, in order to realize the step-up process of the transformer circuit 13, the gate of the first PMOS tube is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the source of the first PMOS tube is changed. The output terminal of the voltage circuit 13 can be used to output an output voltage.

On the other hand, as shown in FIG. 7, in order to realize the boosting process of the transformer circuit 13, the source of the first PMOS tube is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the gate of the first PMOS tube is The output terminal of the transformer circuit 13 can be used to output an output voltage.

In this application, the structure of the resistor and the first PMOS tube is used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the gate and drain of the first PMOS tube, that is, the coupling method of Diode, the first current The source 11 and the second current source 12 adjust the current flowing through the first PMOS tube to make the first PMOS tube work in the linear region. In this way, the transformer circuit 13 converts the input voltage into an output voltage with a target value. Better.

In another feasible implementation manner, as shown in FIGS. 8 and 9, when the transistor is a second PMOS tube, the gate of the second PMOS tube is coupled to the first end of the resistor.

Among them, this application does not limit the specific number of the second PMOS transistors. For ease of description, in FIGS. 8 and 9, there is one second PMOS transistor and is identified by the letter "M4".

On the one hand, as shown in FIG. 8, in order to realize the step-up process of the transformer circuit 13, the second end of the resistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage. The source of the second PMOS transistor is the transformer The output terminal of the circuit 13 can be used to output the output voltage.

On the other hand, as shown in Figure 9, in order to achieve the step-down process of the transformer circuit 13, the source of the second PMOS tube is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the second end of the resistor is the transformer. The output terminal of the voltage circuit 13 can be used to output an output voltage.

In this application, the resistor and the second PMOS structure are used to replace the existing pure resistor structure, wherein the two ends of the resistor are respectively coupled to the gate and the drain of the second PMOS, that is, the Diode coupling mode, the first current source 11 And the second current source 12 adjusts the current flowing through the second PMOS so that the second PMOS works in the saturation region or the sub-threshold region. In this way, the transformer circuit 13 converts the input voltage into an output voltage with a target value. Better.

When the transistor is a transistor, on the basis of the embodiment shown in FIG. 1b and in conjunction with FIGS. 10-17, the following four feasible implementation modes are used to describe the specific structure of the level conversion circuit 10.

In a feasible implementation manner, as shown in FIGS. 10 and 11, when the transistor is the first NPN, the base of the first NPN is coupled to the second end of the resistor.

Among them, this application does not limit the specific number of the first NPN. For ease of description, in FIGS. 10 and 11, the first NPN is one and is identified by the letter "N1". In addition, the base of the first NPN is usually coupled with a resistor, which is not shown in FIGS. 10 and 11.

On the one hand, as shown in FIG. 10, in order to realize the step-up process of the transformer circuit 13, the transmitter of the first NPN can be used to receive the input voltage of the transformer circuit 13, and the base of the first NPN is the transformer circuit The output terminal of 13 can be used to output the output voltage.

On the other hand, as shown in FIG. 11, in order to realize the step-down process of the transformer circuit 13, the base of the first NPN is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the transmitter of the first NPN is transformer. The output terminal of the circuit 13 can be used to output the output voltage.

In this application, the structure of the resistor and the first NPN is used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the first NPN, that is, the coupling method of Diode, the first current source 11 And the second current source 12 adjusts the current flowing through the first NPN so that the first NPN works in the linear region. In this way, the transformer circuit 13 has a better effect of converting the input level into the output voltage with the amplitude of the target value.

In another feasible implementation manner, as shown in FIGS. 12 and 13, when the transistor is the second NPN, the base of the second NPN is coupled to the first end of the resistor.

Among them, this application does not limit the specific number of the second NPN. For ease of description, in FIGS. 12 and 13, the second NPN is one and is identified by the letter "N2". In addition, the base of the second NPN is usually coupled with a resistor, which is not shown in FIGS. 12 and 13.

On the one hand, as shown in FIG. 12, in order to realize the step-up process of the transformer circuit 13, the transmitter of the second NPN is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the second end of the resistor is the transformer circuit The output terminal of 13 can be used to output the output voltage.

On the other hand, as shown in Figure 13, in order to achieve the step-down process of the transformer circuit 13, the second end of the resistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage. The transmitter of the second NPN is extremely transformer The output terminal of the circuit 13 can be used to output the output voltage.

In this application, the resistor and the second NPN structure are used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the second NPN, that is, the coupling method of Diode, the first current source 11 And the second current source 12 adjusts the current flowing through the second NPN so that the second NPN works in the saturation region or the sub-threshold region. In this way, the transformer circuit 13 converts the input voltage into an output voltage with a target value. Better.

In another feasible implementation manner, as shown in FIGS. 14 and 15, when the transistor is a first PNP, the base of the first PNP is coupled to the second end of the resistor.

Among them, this application does not limit the specific number of the first PNP. For ease of description, in FIG. 14 and FIG. 15, the first PNP is one and is identified by the letter "N3". In addition, the base of the first PNP is usually coupled with a resistor, which is not shown in FIGS. 14 and 15.

On the one hand, as shown in FIG. 14, in order to realize the step-up process of the transformer circuit 13, the base of the first PNP is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the transmitter of the first PNP is the transformer circuit The output terminal of 13 can be used to output the output voltage.

On the other hand, as shown in Fig. 15, in order to realize the step-up process of the transformer circuit 13, the transmitter of the first PNP can be used to receive the input voltage. The base electrode of the first PNP can be used to transform the voltage. The output terminal of the circuit 13 can be used to output the output voltage.

In this application, the structure of the resistor and the first PNP is used to replace the existing pure resistance structure, wherein the two ends of the resistor are respectively coupled to the base and collector of the first PNP, that is, the coupling method of Diode, the first current source 11 And the second current source 12 adjusts the current flowing through the first PNP so that the first PNP works in the linear region. In this way, the transformer circuit 13 has a better effect of converting the input voltage into the output voltage with the amplitude of the target value.

In another feasible implementation manner, as shown in FIGS. 16 and 17, when the transistor is a second PNP, the base of the second PNP is coupled to the first end of the resistor.

Among them, this application does not limit the specific number of the second PNP. For ease of description, in FIG. 16 and FIG. 17, the second PNP is one and is identified by the letter "N4". In addition, the base of the second PNP is usually coupled with a resistor, which is not shown in FIGS. 16 and 17.

On the one hand, as shown in FIG. 16, in order to realize the boost process of the transformer circuit 13, the second end of the resistor is the input terminal of the transformer circuit 13, which can be used to receive the input voltage. The transmitter of the second PNP is the transformer circuit The output terminal of 13 can be used to output the output voltage.

On the other hand, as shown in Figure 17, in order to achieve the step-down process of the transformer circuit 13, the emitter of the second PNP is the input terminal of the transformer circuit 13, which can be used to receive the input voltage, and the second end of the resistor is the transformer. The output terminal of the circuit 13 can be used to output an output voltage.

In this application, the existing pure resistance structure is replaced by the structure of the resistor and the second PNP. The two ends of the resistor are respectively coupled to the base and collector of the second PNP, that is, the coupling method of Diode, the first current source 11 And the second current source 12 adjusts the current flowing through the second PNP so that the second PNP works in the saturation region or the sub-threshold region. In this way, the transformer circuit 13 converts the input level into an output voltage whose amplitude is the target value. The effect is better.

It should be noted that the above-mentioned embodiments are only partial implementations of the transformer circuit 13, and the transformer circuit 13 in this application can also adopt other methods, as long as the transformer circuit 13 includes coupled resistors and transistors.

Further, on the basis of the embodiment shown in FIGS. 2-17, the transformer circuit 13 may also include a capacitor (the capacitor is identified by the letter "C" in FIGS. 2-17), and the capacitor is coupled in parallel to the transformer circuit 13 Between the input end and the output end to obtain better noise performance and high frequency performance.

Exemplarily, on the basis of the above-mentioned embodiments in FIGS. 1a and 1b-17, the second end of the first current source 11 is used to receive the first feedback signal, and the second end of the second current source 12 is used to receive the first feedback signal. 2. Feedback signal. Wherein, the first feedback signal and the second feedback signal are usually voltages of different amplitudes.

In this application, since the first feedback signal and the second feedback signal are used to indicate that the amplitude of the output voltage is not the target value, the first current source 11 and the second current source 12 can adjust their own currents respectively to achieve the Adjustment of the current of the transformer circuit 13.

Optionally, the first current source 11 adjusts the current of the first current source 11 according to the first feedback signal, so that the current of the first current source 11 and the current of the second current source 12 are equal. The second current source 12 adjusts the current of the second current source 12 according to the second feedback signal, so that the current of the second current source 12 is equal to the current of the first current source 11. The process of adjusting its own current by the first current source 11 and the process of adjusting its own current by the second current source 12 can be performed simultaneously, in no particular order in time sequence.

The level conversion circuit provided by the present application can form a loop through the first current source, the resistors and transistors in the transformer circuit, and the second current source, so that the first current source and the second current source can adjust the flow through the transformer circuit The current, so that the transformer circuit can convert the received input voltage into an output voltage. When the amplitude of the output voltage is the target value, the first current source and the second current source maintain the current flowing through the transformer circuit, without adjusting the current flowing through the transformer circuit, the transformer circuit can directly output the amplitude to the target value Value of the output voltage. When the amplitude of the output voltage is not the target value, the first current source and the second current source can adjust the current flowing through the transformer circuit through the coupling with the resistor and the transistor, so that the transformer circuit can output the target amplitude Value of the output voltage to achieve the step-up or step-down of the level conversion circuit. In this application, since the transformer circuit includes coupled resistors and transistors, the existing pure resistance structure is replaced with a resistor and transistor structure, which reduces the impedance of the level conversion circuit and optimizes the noise performance of the level conversion circuit. Reduce the linearity loss of the level conversion circuit.

FIG. 18 is a schematic diagram of the level conversion circuit 10 of the present application based on the structure shown in FIG. 1a. As shown in FIG. 18, the level conversion circuit 10 may further include: a first control circuit 14. The input terminal of the first control circuit 14 is coupled to the output terminal of the transformer circuit 13, the output terminal of the transformer circuit 13 is used to output an output voltage, and the first output terminal of the first control circuit 14 is coupled to the first current source 11 Two terminals, the second output terminal of the first control circuit 14 is coupled to the second terminal of the second current source 12.

For ease of description, in FIG. 18, the output terminal of the transformer circuit 13 samples the number "1", the second terminal of the first current source 11 uses the number "2", and the second terminal of the second current source 12 uses the number " 2" identification, the input terminal of the first control circuit 14 adopts the number “1” identification, the first output terminal of the first control circuit 14 adopts the number “2” identification, and the second output terminal of the first control circuit 14 adopts the number “3” "Identification.

In this application, the first control circuit 14 may receive the output voltage from the transformer circuit 13, and then determine whether the current amplitude of the output voltage is the target value. Furthermore, when the current amplitude of the output voltage is not the target value, the first control circuit 14 may send a first feedback signal to the first current source 11 and a second feedback signal to the second current source 12, so that the first current The source 11 can adjust its own current according to the first feedback signal. At the same time, the second current source 12 can adjust its own circuit according to the second feedback signal, so that the current of the first current source 11 and the current of the second current source 12 are the same. In this way, the adjustment of the current flowing through the transformer circuit 13 is jointly realized, so that the transformer circuit 13 can output an output voltage whose amplitude is the target value.

In addition, when the current amplitude of the output voltage is the target value, the first control circuit 14 may respectively provide the first current source 11 and the second current source 12 with the first feedback signal and the first feedback signal indicating that the amplitude of the output voltage is the target value. Two feedback signals, so that the first current source 11 and the second current source 12 do not need to adjust the current flowing through the transformer circuit 13 and continue to maintain the current, so that the transformer circuit 13 can directly output an output with a target amplitude Voltage, it is also possible not to output the first feedback signal and the second feedback signal to the first current source 11 and the second current source 12 respectively, so that the first current source 11 and the second current source 12 have not received the voltage after the preset time When the first feedback signal and the second feedback signal are reached, the current flowing through the transformer circuit 13 can be maintained without adjusting the current, so that the transformer circuit 13 can output an output voltage with a target amplitude. Among them, the preset duration can be set according to actual experience values, which is not limited in this application.

It should be noted that the present application can also combine the structure shown in FIG. 1b and the first control circuit 14 to form the level conversion circuit 10 of the present application. For the specific working principle, refer to the description shown in FIG. 18, which will not be repeated here.

Wherein, when the first current source 11 and the second current source 12 adopt transistors, the transistors in the first current source 11, the second current source 12, and the first control circuit 14 may be of the same type, or may be of different types. It can be one or multiple, which is not limited in this application.

Optionally, in conjunction with FIG. 19, the first current source 11, the second current source 12, and the first control circuit 14 are exemplarily illustrated by using a current mirror implementation. As shown in FIG. 19, the first current source 11 includes: a third PMOS tube, the second current source 12 includes: a third NMOS tube, and the first control circuit 14 includes: a voltage feedback circuit, a fourth PMOS tube, and a fourth NMOS tube . Wherein, the voltage feedback circuit may be a component such as a processor, which is not limited in this application.

For ease of description, in FIG. 19, the transformer circuit 13 is illustrated with the structure shown in FIG. 2 as an example. The third PMOS tube is a PMOS tube as an example, and the letter "Q1" is used to identify the third NMOS tube. For example, the letter "Q2" is used for identification, the fourth PMOS tube is identified by a PMOS tube with the letter "Q3", and the fourth NMOS tube is identified by an NMOS tube with the letter "Q4".

Wherein, the source of the third PMOS tube is coupled with a power supply level, that is, the power supply level on the power supply terminal of the first current source 11, the drain of the third PMOS tube is coupled to the second end of the resistor, and the power supply level of the third PMOS tube is The gate is the second end of the first current source 11, and the gate of the third PMOS transistor is coupled to the gate of the fourth PMOS transistor.

The drain of the third NMOS transistor is coupled to the source of the transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is the second end of the second current source 12, and the gate of the third NMOS transistor is coupled to the The grid of four NMOS tubes.

The source of the fourth PMOS tube is coupled with a power supply voltage (the power supply voltage is the same as the power supply voltage coupled to the source of the third PMOS tube), and the gate and drain of the fourth PMOS tube are both coupled to the drain of the fourth NMOS tube , The source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is also coupled to the output terminal of the voltage feedback circuit, the input terminal of the voltage feedback circuit is the input terminal of the first control circuit 14, and the input terminal of the voltage feedback circuit is coupled To the output terminal of the transformer circuit 13.

In this application, the voltage feedback circuit may receive the output voltage from the output terminal of the transformer circuit 13, and then determine whether the current amplitude of the output voltage is the target value. Furthermore, when the current amplitude of the output voltage is not the target value, the voltage feedback circuit can send an adjustment signal to the fourth NMOS tube (in Figure 19, the letter "Vctrl" is used for identification).

Among them, the fourth PMOS tube in the first control circuit 14 can be used as the current mirror of the third PMOS tube, the fourth PMOS tube sends the first feedback signal to the third PMOS tube, and the fourth NMOS tube in the first control circuit 14 It can be used as a current mirror of the third NMOS tube, and the fourth NMOS tube sends the second feedback signal to the third NMOS tube.

On the other hand, the adjustment signal can send a second feedback signal to the third NMOS tube through the fourth NMOS tube to adjust the current of the third NMOS tube, and to ensure the current of the third PMOS tube and the current of the third NMOS tube. On an equal basis, the adjustment of the current flowing through the transformer circuit 13 is realized.

Among them, this application does not limit the number of fourth PMOS transistors and fourth NMOS transistors. In addition, the fourth PMOS tube and the fourth NMOS tube may be integrated with the voltage feedback circuit, or may be provided separately from the voltage feedback circuit, which is not limited in this application.

Further, in order to analyze the process of reducing the impedance of the level conversion circuit 10 of the present application, the impedance of the level conversion circuit 10 of the present application and the impedance of the level conversion circuit adopting a pure resistance structure are analyzed in conjunction with FIG. 20 and FIG. 21. comparative analysis.

FIG. 20 shows an equivalent small signal model of the level conversion circuit 10 of the present application. For ease of description, in the level conversion circuit 10 of the present application shown in FIG. 20, the first current source 11, the second current source 12, and the transformer The voltage circuit 13 is illustrated by taking the structure shown in FIG. 2 as an example.

As shown in FIG. 20, the equivalent impedance R _eq (excluding the capacitor and current source) of the level conversion circuit 10 of the present application is calculated by the following formula:

g _m r _ds ≈1

Among them, g _m is the transconductance of M1, r _ds is the small signal impedance of M1, and R _eq is the equivalent impedance (ie, AC impedance).

According to the following formula, for the level conversion circuit adopting the pure resistance structure, the resistance value R'required to generate the output voltage conversion with the target value is calculated as:

I _D ＝K(V _GS -V _TH ) V _DS ＝K(V _GS -V _TH )(V _GS -I _D R)

Among them, I _D is the current flowing through the level conversion circuit using a pure resistance structure, K is a constant, V _GS is the voltage difference of the level conversion circuit using a pure resistance structure or the level conversion circuit 10 of the present application, and V _TH is The threshold voltage of the transistor in the level shift circuit 10 of the present application (the transistor is a MOS transistor as an example), V _DS is the voltage difference between the source and drain of the MOS transistor in the level shift circuit 10 of the present application, and R'is the voltage of the pure resistance structure. The equivalent impedance (ie, DC impedance) of the level conversion circuit 10.

The transfer function from the input voltage (that is, the input signal) to the output voltage (the output signal) is:

Among them, v _in is the input signal, v _out is the output signal, R _{ls is} the impedance of the level conversion circuit 10 of the application, and R _tail is the current source impedance. Since the current source is usually a MOS tube, the impedance R _{tail of the} MOS tube will change with the change of the signal. Therefore, the smaller the R _ls , the better the linearity.

Based on the above content, comparing the equivalent impedance R _{eq of the} level conversion circuit 10 of the present application in FIG. 20 with the resistance value _{R'of the} level conversion circuit adopting a pure resistance structure, R _eq is about half of R', so the present application The linearity of the level conversion circuit 10 is better, and the noise contribution brought by the smaller impedance will be smaller.

21 shows the current-voltage curve of the transistor in the level conversion circuit 10 of the present application and its DC resistance and AC resistance curves. The abscissa _IDS of the curve is the current flowing through the level conversion circuit 10 of the present application, and the ordinate V _{GS is} the voltage difference of the level conversion circuit 10 of this application. For ease of description, in the level conversion circuit 10 of the present application shown in FIG. 21, the first current source 11, the second current source 12, and the transformer circuit 13 take the structure shown in FIG. 4 as an example, and the transistor adopts a MOS tube as an example. Give a gesture.

Using the following formula, the equivalent impedance R _eq of the level conversion circuit 10 of the present application is calculated as:

Based on the above content, the resistance value R'of the level conversion circuit with pure resistance structure is calculated as:

R'=R+r _ds

As shown in FIG. 21, since the MOS tube is working in the saturation region or the sub-threshold region, the IV curve of the second NMOS tube in FIG. 4 is similar to an exponential curve. Obviously, the AC impedance of the second MOS tube is smaller than the DC impedance. Also, since the equivalent impedance R _eq of the level conversion circuit 10 of the present application is equal to the AC impedance of the MOS tube, and the resistance value R′ of the level conversion circuit adopting a pure resistance structure is equal to the DC impedance of the second MOS tube, R _eq Less than R'. Therefore, compared with a level conversion circuit adopting a pure resistance structure, the level conversion circuit 10 of the present application has better linearity and less noise contribution.

Exemplarily, on the basis of the embodiment shown in FIG. 1a or FIG. 1b, as shown in FIG. 22, the level conversion circuit 10 of the present application may further include: M first current sources 11, M second current sources 12. M transformer circuits 13 and second control circuit 15, M is a positive integer. For ease of description, FIG. 22 only illustrates the level conversion circuit 10 on the basis of FIG. 1a.

In the present application, in any pair of M+1 first current source 11, M+1 second current source 12, and M+1 transformer circuit 13, the first current source 11, the second current source 12, and The specific implementation of the transformer circuit 13 can be referred to the description of the embodiments shown in FIG. 1a, FIG. 1b-FIG. 21 in this application, and will not be repeated here.

In this application, the M+1 input terminals of the second control circuit 15 (identified by the letter "IN(i)" in FIG. 22, 1≤i≤M, and i is a positive integer) pass through and M+1 transformers The output terminals of the circuit 13 (identified by the letter "OUT" in Figure 22) are coupled in a one-to-one correspondence, and can receive an output voltage from each transformer circuit 13 to obtain the M+1 output voltage, and then determine the M+1 output voltage Whether the mean amplitude is the target value.

Among them, the second control circuit 15 can first sum the amplitudes of the M+1 output voltages, and then take the average value to obtain the average amplitude of the M+1 output voltages, or other algorithms (such as taking M+1 The arithmetic square root of the amplitude of the output voltage) calculates the mean value of the amplitude of the M+1 output voltages, which is not limited in this application.

Generally, when the average value of the amplitude of the output voltage is greater than the target value, the second control circuit 15 can reduce the current flowing through the transformer circuit 13 through the first current source 11 and the second current source 12, so that the amplitude of the output voltage is The average value becomes smaller to adjust to the target value. When the average amplitude of the output voltage is less than the target value, the second control circuit 15 can increase the current flowing through the transformer circuit 13 through the first current source 11 and the second current source 12, so that the average amplitude of the output voltage changes Large to adjust to the target value. When the average value of the output voltage amplitude is equal to the target value, the second control circuit 15 can maintain the current flowing through the transformer circuit 13 through the first current source 11 and the second current source 12, so that the transformer circuit 13 can output amplitude. The average value is the output voltage of the target value.

In this application, the M+1 first output terminals of the second control circuit 15 (identified by the letter "OUT1(i)" in FIG. 22, 1≤i≤M, and i is a positive integer) pass through and M+1 The second terminal of the first current source 11 (identified by the letter "ADJ" in FIG. 22) is coupled in one-to-one correspondence, and the M+1 second output terminal of the second control circuit 15 (the letter "OUT2(i) in FIG. 22) ”Mark, 1≤i≤M, and i is a positive integer) through a one-to-one correspondence coupling with the second end of the M+1 second current source 12 (identified by the letter “ADJ” in Fig. 22), in M+1 When the average value of the output voltage is not the target value, the first feedback signal can be sent to each first current source 11, and the second feedback signal can be sent to each second current source 12, that is, M+1 first The current sources 11 will all receive the first feedback signal, and the M+1 second current sources 12 will all receive the second feedback signal.

Wherein, the first feedback signal and the second feedback signal here are used to indicate that the average value of the amplitude of the M+1 output voltage is not the target value.

In this application, for any pair of the first current source 11, the second current source 12, and the transformer circuit 13, the first current source 11 receives the first feedback signal and the second current source 12 receives the second feedback When signal is generated, the first current source 11 and the second current source 12 can adjust the current flowing through the transformer circuit 13, so that the average value of the output voltage output by the M+1 transformer circuits 13 is the target value, Improve the accuracy of output voltage.

Among them, the application does not limit the specific implementation of the second control circuit 15. Optionally, the second control circuit 15 includes any one of a processor, a comparator with common mode feedback, or a comparator with common mode feedback and a buffer.

Next, in conjunction with FIG. 23 and FIG. 24, the second control circuit 15 uses a comparator with common mode feedback (Sense Amplifier) and a level conversion circuit 10 with a comparator with common mode feedback and a buffer respectively to illustrate Gesture. For ease of description, in FIGS. 23 and 24, the first current source 11, the second current source 12, and the transformer circuit 13 are illustrated by taking the structure shown in FIG. 2 as an example. The first current source 11, the second current source 12 and The number M of the transformer circuit 13 is 2. Among them, one transistor is identified by the letter "Mp", correspondingly, the input voltage is identified by the "Vinp", the output voltage is identified by the "Voutp", and the other transistor is identified by the letter "Mn" , Correspondingly, the input voltage adopts the "Vinn" label, and the output voltage adopts the "Voutn" label.

When the second control circuit 15 is a comparator with common mode feedback, as shown in FIG. 23, the level conversion circuit 10 is a differential LS with common mode feedback. The output voltages (Voutp and Voutn) output by LS are Feedback comparator, the comparator with common mode feedback compares the average value of the output voltage amplitude (such as the average value of Voutp and Voutn) with the reference voltage (marked by the letter "Vref" in Figure 23, the amplitude is the target value) Generate two pairs of first feedback signal and second feedback signal, and output the corresponding first feedback signal to each first current source 11 and output the corresponding second feedback signal to each second current source 12 , So that any one of the first current source 11 and the corresponding second current source 12 adjusts the corresponding current flowing through the transformer circuit 13 to achieve the purpose of common mode feedback.

When the second control circuit 15 is a comparator with common mode feedback and a buffer, as shown in FIG. 24, the level conversion circuit 10 is a differential LS with common mode feedback and a buffer. The output voltage (Voutp and Voutn ) Through the buffer, the buffer can adopt a source follower structure, and the MOS tube in the buffer and the MOS tube in the transformer circuit 13 usually adopt the same type, which can reduce the process-voltage-temperature (Process-Voltage- Temperature, PVT) influence on output common mode.

Furthermore, the Buffer outputs the output common mode to the comparator with common mode feedback, and the comparator with common mode feedback compares the output voltage with the reference voltage (in Figure 24, it is marked with the letter "Vref" and the amplitude is the target value). The magnitude of the amplitude, two pairs of the first feedback signal and the second feedback signal are generated, and the corresponding first feedback signal is output to each first current source 11 and the corresponding second feedback signal is output to each second current source 12, Make any one of the first current source 11 and each corresponding second current source 12 adjust the corresponding current flowing through the transformer circuit 13, so as to achieve the purpose of common mode feedback and solve the problem of buffer input/output common mode mismatch , And at the same time reduce the adverse effects of LS to a relatively low level.

Furthermore, the level conversion circuit 10 in Fig. 23 and Fig. 24 can control the output common mode. By adjusting the two current sources at the same time, the driving capability requirement of the signal source can be reduced, and the common mode feedback process can be realized. Solve the problem of input and output common mode mismatch, make the output common mode controllable, eliminate the DC current of the level conversion circuit 10 to the previous circuit, and reduce the impact on the previous circuit.

In this application, the level conversion circuit 10 can not only adopt a structure including a first current source 11, a second current source 12, a transformer circuit 13 and a first control circuit 14 as shown in FIG. 1a or FIG. 1b. The structure shown in FIG. 22 including M+1 first current sources 11, M+1 second current sources 12, M+1 transformer circuits 13 and second control circuit 15 can also be adopted. In addition, a circuit (or unit or device or electronic device) can be integrated with multiple level conversion circuits 10 such as any one of the above methods or including the above two methods, which can convert one or more input voltages into different The amplitude of the output voltage can also realize the process of step-up and step-down at the same time, which provides various possibilities for the level conversion process and improves the processing efficiency of the circuit.

Exemplarily, on the basis of the embodiments shown in FIG. 1a and FIG. 1b-24, the present application also provides an electronic device. FIG. 25 is a schematic structural diagram of an electronic device provided by this application. As shown in FIG. 25, the electronic device may include: an input terminal circuit 20, an output terminal circuit 30, and at least one level conversion circuit 10.

Wherein, the level conversion circuit 10 is coupled to the input terminal circuit 20 for receiving the input voltage from the input terminal circuit 20. The level conversion circuit 10 is coupled to the output terminal circuit 30 for sending an output voltage to the output terminal circuit 30.

Among them, the input terminal circuit and the output terminal circuit may include various forms, and the structure of the level conversion circuit 10 can refer to the description in the above-mentioned embodiment, which is not repeated here.

Wherein, the level conversion circuit 10 can be integrated with the input circuit 20, can also be integrated with the output circuit 30, or can be separately provided, which is not limited in this application.

Among them, electronic devices may include, but are not limited to: terminal devices such as mobile phones, tablet computers, desktop computers, notebooks, etc., logic operation chips, high and low voltage switching phase locked loop (Phase Locked Loop, PLL) phase detectors and differential Signal level converter, etc.

The above embodiments, structural diagrams or simulation diagrams are only for schematically illustrating the technical solutions of the present application, and the size ratios and simulation values therein do not constitute a limitation on the protection scope of the technical solutions. Anything in the spirit and principles of the above embodiments Modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the technical solution.

Claims

A level conversion circuit, which is characterized by comprising: a first current source, a second current source and a transformer circuit;

The transformer circuit includes a resistor and a transistor, wherein the drain of the transistor is coupled to the first end of the resistor, the second end of the resistor is coupled to the first current source, and the source of the transistor is coupled To the second current source, the gate of the transistor is coupled to the first end of the resistor or the second end of the resistor.
3. The circuit of claim 1, wherein the transistor is a first N-type metal oxide semiconductor NMOS tube, and the gate of the first NMOS tube is coupled to the second end of the resistor;

Wherein the source of the first NMOS tube is the input terminal of the transformer circuit, and the gate of the first NMOS tube is the output terminal of the transformer circuit; or, the gate of the first NMOS tube is the The input terminal of the transformer circuit, and the source of the first NMOS tube is the output terminal of the transformer circuit.
4. The circuit of claim 1, wherein the transistor is a second NMOS tube, and the gate of the second NMOS tube is coupled to the first end of the resistor;

The source of the second NMOS tube is the input terminal of the transformer circuit, and the second terminal of the resistor is the output terminal of the transformer circuit; or, the second terminal of the resistor is the input terminal of the transformer circuit. The input terminal, the source of the second NMOS tube is the output terminal of the transformer circuit.
3. The circuit of claim 1, wherein the transistor is a first P-type metal oxide semiconductor PMOS tube, and the gate of the first PMOS tube is coupled to the second end of the resistor;

Wherein the gate of the first PMOS tube is the input terminal of the transformer circuit, and the source of the first PMOS tube is the output terminal of the transformer circuit; or, the source of the first PMOS tube is the The input terminal of the transformer circuit, and the gate of the first PMOS tube is the output terminal of the transformer circuit.
The circuit according to claim 1, wherein the transistor is a second PMOS tube, and the gate of the second PMOS tube is coupled to the first end of the resistor;

The second end of the resistor is the input end of the transformer circuit, and the source of the second PMOS transistor is the output end of the transformer circuit; or, the source of the second PMOS transistor is the transformer. The input terminal of the voltage transformer circuit, and the second terminal of the resistor is the output terminal of the transformer circuit.
The circuit according to any one of claims 1-5, wherein the voltage transformation circuit further comprises: a capacitor, and the capacitor is coupled in parallel between the input terminal and the output terminal of the voltage transformation circuit.
The circuit according to any one of claims 1-6, wherein:

The first current source and the second current source are used to adjust the current of the first current source and the current of the second current source respectively, so that the current of the first current source and the second current source The currents of the current sources are equal.
The circuit according to claim 7, wherein:

The first current source is used to adjust the current of the first current source according to the received first feedback signal, and the first feedback signal is used to indicate that the amplitude of the output voltage output by the transformer circuit is different. Is the target value;

The second current source is used to adjust the current of the second current source according to the received second feedback signal, and the second feedback signal is used to indicate that the amplitude of the output voltage is not a target value.
8. The circuit of claim 8, wherein the level conversion circuit further comprises: a first control circuit;

The input terminal of the first control circuit is coupled to the output terminal of the transformer circuit, the first output terminal of the first control circuit is coupled to the first current source, and the second output of the first control circuit is Terminal coupled to the second current source;

The first control circuit is configured to receive an output voltage from the transformer circuit;

The first control circuit is further configured to send the first feedback signal to the first current source and send all the signals to the second current source when it is determined that the amplitude of the output voltage is not a target value. The second feedback signal.
The circuit according to claim 9, wherein the first current source comprises: a third PMOS tube, the second current source comprises: a third NMOS tube, and the first control circuit comprises: a voltage feedback circuit , The fourth PMOS tube and the fourth NMOS tube;

Wherein, the source of the third PMOS transistor is coupled with a power supply level, the drain of the third PMOS transistor is coupled to the second end of the resistor, and the gate of the third PMOS transistor is coupled to the second end of the resistor. The grid of four PMOS tubes;

The drain of the third NMOS tube is coupled to the source of the transistor, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is coupled to the gate of the fourth NMOS tube;

The source of the fourth PMOS tube is coupled with the supply voltage, the gate and drain of the fourth PMOS tube are both coupled to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is Grounded, the gate of the fourth NMOS tube is also coupled to the output terminal of the voltage feedback circuit, the input terminal of the voltage feedback circuit is the input terminal of the first control circuit, and the input terminal of the voltage feedback circuit Coupled to the output terminal of the transformer circuit;

The voltage feedback circuit is configured to receive the output voltage from the transformer circuit;

The voltage feedback circuit is further configured to send an adjustment signal to the fourth NMOS tube when the amplitude of the output voltage is not a target value, and the adjustment signal is used for the fourth PMOS tube to send an adjustment signal to the first NMOS transistor. Three PMOS transistors send the first feedback signal, and the fourth NMOS transistor sends the second feedback signal to the third NMOS transistor.
The circuit according to any one of claims 1-7, wherein the level conversion circuit further comprises: M first current sources, M second current sources, M transformer circuits, and second control Circuit, M is a positive integer;

Wherein, M+1 said first current sources, M+1 said second current sources and M+1 said transformer circuits are coupled in one-to-one correspondence, and M+1 inputs of said second control circuit Terminals are coupled to the output terminals of the M+1 transformer circuits in a one-to-one correspondence, and the M+1 first output terminals of the second control circuit are coupled in a one-to-one correspondence with the M+1 first current sources, The M+1 second output terminals of the second control circuit are coupled to the M+1 second current sources in a one-to-one correspondence;

The second control circuit is configured to receive one output voltage from each transformer circuit;

The second control circuit is further configured to send a first feedback signal to each first current source and to each second current source when the average value of the amplitude of the M+1 output voltages is not the target value A second feedback signal, where the first feedback signal and the second feedback signal are used to indicate that the average value of the amplitude of the output voltage is not a target value.
The circuit according to claim 11, wherein the second control circuit comprises any one of a processor, a comparator with common mode feedback, or a comparator with common mode feedback and a buffer.
The circuit according to claim 12, wherein the transistors in the second control circuit and the transistors in the transformer circuit are of the same type.
An electronic device, characterized by comprising: an input end circuit, an output end circuit and at least one level conversion circuit according to any one of claims 1-13;

Wherein, the level conversion circuit is coupled to the input end circuit and is used to receive the input voltage from the input end circuit; the level conversion circuit is coupled to the output end circuit and is used to transmit the input voltage to the output end circuit. Send output voltage.