WO2020227923A1 - Nano-scale transistor and preparation method therefor - Google Patents

Nano-scale transistor and preparation method therefor Download PDF

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WO2020227923A1
WO2020227923A1 PCT/CN2019/086823 CN2019086823W WO2020227923A1 WO 2020227923 A1 WO2020227923 A1 WO 2020227923A1 CN 2019086823 W CN2019086823 W CN 2019086823W WO 2020227923 A1 WO2020227923 A1 WO 2020227923A1
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insulating layer
electrode
gate dielectric
dielectric layer
layer
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PCT/CN2019/086823
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French (fr)
Chinese (zh)
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卢年端
李泠
耿玓
刘明
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中国科学院微电子研究所
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Priority to PCT/CN2019/086823 priority Critical patent/WO2020227923A1/en
Publication of WO2020227923A1 publication Critical patent/WO2020227923A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the technical field of nano-scale transistor devices, in particular to a nano-scale transistor and a preparation method thereof.
  • Semiconductor materials are electronic materials that have semiconductor properties, and their conductivity is between conductors and insulators, and can be used to make semiconductor devices and integrated circuits.
  • semiconductor materials With the continuous advancement of technology, many new low-dimensional materials have been developed and widely used, for example, graphene, nanotubes, nanowires, etc.
  • the main characteristic of low-dimensional materials is the high mobility of electrons on them.
  • new low-dimensional materials are widely used in semiconductors due to their superior optical, electrical and thermal properties. On the device.
  • the present invention provides a nano-scale transistor and a preparation method thereof, so as to at least partially solve the above-mentioned technical problems.
  • a nano-scale transistor including:
  • Insulating layer substrate Insulating layer supporting column, active layer, drain electrode, gate dielectric layer, source electrode and gate electrode;
  • the insulating layer support column is located above the insulating layer substrate, the active layer is wrapped around the insulating layer support column, and the drain electrode, the gate dielectric layer, and the source electrode are wrapped in order from the bottom to the top. Outside the source layer, the gate electrode is wrapped outside the gate dielectric layer; wherein, the active layer is a nanotube formed of a semiconductor material.
  • the insulating layer substrate is a glass substrate with a thickness of 1 ⁇ m-10 ⁇ m.
  • the insulating layer support column is a glass cylinder with a height of 100 nm-500 nm, and a diameter of the inner diameter of the active layer.
  • the source electrode and the drain electrode are circular columns formed of Pt, Au, Cu or Ag, and the height of the source electrode and the drain electrode is 20nm-50nm, and the wall thickness is 10nm-100nm.
  • the gate dielectric layer is a circular column formed of Al 2 O 3 or SiO 2 with a height of 100 nm to 300 nm and a wall thickness of 10 nm to 100 nm.
  • the gate electrode is a circular column formed by at least one of Mo, Pt, Au, Cu, and Ag, with a height of 50nm-250nm and a wall thickness of 50nm-500nm.
  • a method for manufacturing a nanoscale transistor as described above comprising:
  • a gate electrode is grown outside the gate dielectric layer.
  • the insulating layer support column is prepared by wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.
  • the drain electrode, the source electrode and the gate electrode are all prepared by an electron beam evaporation method; the gate dielectric layer is prepared by a chemical deposition method.
  • the materials of the drain electrode and the source electrode are both Pt, Au, Cu or Ag; the material of the gate dielectric layer is Al 2 O 3 or SiO 2 ; the material of the gate electrode is Mo, At least one of Pt, Au, Cu and Ag; the shape of the drain electrode, the source electrode, the gate dielectric layer and the gate electrode are all circular pillars.
  • nanoscale transistor and its preparation method provided by the present invention use nanotubes as the active layer, and the insulating layer, active layer, source and drain electrodes are tightly combined, which not only reduces the overall size of the transistor, but also Moreover, a relatively strong nanoscale transistor is obtained, which can be extended to all nanotube devices with semiconductor characteristics;
  • the nano-scale transistor and the preparation method thereof provided by the present invention use semiconductor nanotubes as the active layer and metal or metal compound materials to form other components in the transistor, thereby obtaining van der Waals contacts.
  • Fig. 1 is a schematic diagram of a conventional transistor structure
  • Figure 2 is a schematic diagram of the structure of a nanoscale transistor of the present invention.
  • Figure 3 is a flow chart of the method for preparing a nanoscale transistor of the present invention.
  • FIG. 4 is a schematic diagram of a manufacturing process of a nanoscale transistor provided by an embodiment of the present invention.
  • the nanoscale transistor includes:
  • the active layer 3 is a nanotube formed of a semiconductor material, and the material of the nanotube may be materials such as boron nitride (BN) or molybdenum disulfide (MoS 2 ).
  • the nano-level transistor provided by the present invention uses nanotubes as the active layer, and closely combines the insulating layer, the active layer, the source and drain electrodes, etc., which not only reduces the overall size of the transistor, but also obtains greater strength Nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.
  • the insulating layer substrate 1 is a glass substrate with a thickness of 1 ⁇ m-10 ⁇ m;
  • the insulating layer support column 2 is a glass cylinder with a height of 200 nm-500 nm, because the active layer 3, that is, nanotubes need to be nested It is outside the insulating layer supporting column 2, so the diameter of the insulating layer supporting column 2 is the inner diameter of the active layer 3, that is, the nanotube.
  • the source electrode 6 and the drain electrode 4 are circular cylinders formed of Pt, Au, Cu or Ag, with a height of 20nm-50nm and a wall thickness of 10nm-100nm; the gate electrode 7 is made of Mo, Pt, Au, Cu And a circular column composed of at least one of Ag, with a height of 50nm-250nm and a wall thickness of 50nm-500nm; and the gate dielectric layer 5 is a circular column formed of Al 2 O 3 or SiO 2 with a height of 100nm-300nm, wall thickness is 10nm-100nm.
  • the drain electrode 4, the gate dielectric layer 5, the gate electrode 7 and the source electrode 6 can also have other shapes, such as a rectangular column or a square column.
  • the nanoscale transistor uses semiconductor nanotubes as the active layer, and other structures are metals or metal compounds to obtain a nanoscale transistor with van der Waals contact.
  • the nanotube material and the metal The contact resistance is very small when in contact, thereby reducing the resistance of carrier injection.
  • a method for preparing a nanoscale transistor includes the following steps:
  • Step S101 preparing an insulating layer support column on the insulating layer substrate
  • Step S102 transferring the nanotubes as the active layer to the insulating layer support column;
  • Step S103 growing a drain electrode on the outer wall of the nanotube
  • Step S104 growing a gate dielectric layer on the outer wall of the nanotube and along the upper part of the drain electrode;
  • Step S105 growing a source electrode on the outer wall of the nanotube and along the upper part of the gate dielectric layer;
  • Step S106 growing a gate electrode outside the gate dielectric layer.
  • the method for preparing a nanoscale transistor provided by the present invention uses nanotubes as the active layer, and closely combines the insulating layer, the active layer, the source and drain electrodes, etc., which not only reduces the overall size of the transistor, but also obtains a better High-strength nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.
  • the insulating layer support column can be prepared by wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering; the drain electrode, source electrode, and gate electrode can be prepared by the electron beam evaporation method; and the chemical deposition method can be used Prepare the gate dielectric layer.
  • wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering is used to prepare a thickness of 200nm-500nm on an insulating layer substrate with a thickness of 1 ⁇ m-10 ⁇ m, that is, a glass substrate.
  • the insulating layer support column is a glass cylinder, and the nanotube is transferred as the active layer to the outside of the insulating layer support column, where the diameter of the insulating layer support column is required to be the same as the inner diameter of the nanotube; then the electron beam evaporation is used on the outer wall of the nanotube
  • the method grows a drain electrode circular column with a wall thickness of 10nm-100nm and a height of 20nm-50nm.
  • the material is Pt, Au, Cu or Ag.
  • the wall thickness is grown on the outer wall of the nanotube and along the upper part of the drain electrode by chemical deposition.
  • the circular column with a height of 10nm-100nm and a height of 100nm-300nm is used as the gate dielectric layer.
  • the material of the circular column gate dielectric layer can be Al 2 O 3 or SiO 2.
  • the electron beam evaporation method is used on the outer wall of the nanotube and along the gate.
  • the growth wall thickness of the upper part of the dielectric layer is 10nm-100nm, and the ring pillars of Pt, Au, Cu or Ag with the height of 20nm-50nm are used as the source electrode; finally, Mo, Mo, Au, Cu, or Ag are grown on the outside of the gate dielectric layer by electron beam evaporation method.
  • the overall shape is circular cylinders, and the source electrode, drain electrode, and gate dielectric layer are directly prepared on the nanotubes. While reducing the overall size, the performance of the transistor can be made more stable.
  • the method for preparing nanoscale transistors uses semiconductor nanotubes as the active layer and other structures as metals or metal compounds to obtain nanoscale transistors with van der Waals contacts.
  • the nanotube material in the nanoscale transistor is When in contact with metal, its contact resistance is very small, thereby reducing the resistance of carrier injection.
  • the preparation process of a nanoscale transistor is as follows: first, a wire drawing process is used to prepare a glass column with a height of 500 nm and a diameter equal to the inner diameter of the nanotube as an insulating layer support on a glass substrate.
  • the BN nanotube is transferred to the insulating layer support column by the transfer method; then the Au ring column with the thickness of 50nm and the height of 100nm is grown on the outer wall of the BN nanotube along the bottom of the substrate by the electron beam evaporation method as the transistor
  • the drain electrode a SiO 2 circular column with a thickness of 50 nm and a height of 250 nm is grown on the outer wall of the nanotube along the bottom electrode by chemical deposition as the gate dielectric layer, and then the gate dielectric is deposited on the outer wall of the BN nanotube by the electron beam evaporation method.
  • An Au ring column with a thickness of 50 nm and a height of 100 nm is grown at the layer as the source electrode of the transistor; finally, an electron beam evaporation method is used to grow a Pt ring column with a thickness of 100 nm and a height of 150 nm on the outside of the gate dielectric layer as the gate electrode.
  • nanotubes are used as the active layer, and the insulating layer, active layer, source and drain electrodes are tightly combined, which not only reduces the overall size of the transistor, but also obtains Higher strength nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.

Abstract

The present invention relates to the technical field of nano-scale transistor devices, and provides a nano-scale transistor and preparation method therefor. The nano-scale transistor comprises an insulating layer substrate, an insulating layer support column, an active layer, a drain electrode, a gate dielectric layer, a source electrode, and a gate electrode. The insulating layer support column is located above the insulating layer substrate. The active layer wraps the outer side of the insulating layer support column. The drain electrode, the gate dielectric layer, and the source electrode sequentially wrap the outer side of the active layer from bottom to top. The gate electrode wraps the outer side of the gate dielectric layer. The active layer is a nanotube formed by a semiconductor material. By using a nanotube as an active layer and closely combining an insulating layer, the active layer, and source and drain electrodes, the present invention not only reduces the overall size of a transistor, but also obtains a nano-scale transistor having a great strength, and thus can be generalized to all nanotube devices having semiconductor characteristics.

Description

纳米级晶体管及其制备方法Nano-level transistor and preparation method thereof 技术领域Technical field
本发明涉及纳米级晶体管器件技术领域，尤其涉及一种纳米级晶体管及其制备方法。The invention relates to the technical field of nano-scale transistor devices, in particular to a nano-scale transistor and a preparation method thereof.
背景技术Background technique
半导体材料是一类具有半导体性能，其导电能力介于导体与绝缘体之间，可用来制作半导体器件和集成电路的电子材料。随着技术的不断进步，许多新型低维材料被开发并广泛应用，例如，石墨烯，纳米管，纳米线等。低维材料由于最主要的特性是电子在其上传输的迁移率高；另外，相对于传统的块体材料，新型的低维材料由于其优越的光，电及热等特性被广泛应用于半导体器件上。Semiconductor materials are electronic materials that have semiconductor properties, and their conductivity is between conductors and insulators, and can be used to make semiconductor devices and integrated circuits. With the continuous advancement of technology, many new low-dimensional materials have been developed and widely used, for example, graphene, nanotubes, nanowires, etc. The main characteristic of low-dimensional materials is the high mobility of electrons on them. In addition, compared with traditional bulk materials, new low-dimensional materials are widely used in semiconductors due to their superior optical, electrical and thermal properties. On the device.
随着器件尺寸的不断缩小，晶体管的体积必然会缩小才能适应新的技术要求。但是，现有的MoS 2、BN、黑磷等薄膜材料的尺寸缩小到纳米带尺寸时，其半导体特性将消失，即二维材料的纳米带带隙为零。因此，二维材料的纳米带材料将不再适合制备晶体管。与二维材料相比，一维纳米管具有良好的特性及非零带隙，因此可以作为晶体管器件的有源层。当前虽然有利用纳米管作为有源层的晶体管，但是其结构与传统的晶体管结构相似，如图1所示为现有的晶体管结构(图1中01为石墨烯，02为纳米线)，晶体管结构的整体体积较大，难以实现真正的纳米级器件的要求。同时，现有的利用纳米管作为有源层制备的晶体管器件中的各组成较为分散，晶体管强度较差。 As the size of devices continues to shrink, the size of transistors will inevitably shrink to meet new technical requirements. However, when the size of the existing thin film materials such as MoS 2 , BN, and black phosphorous is reduced to the size of the nanoribbon, its semiconductor characteristics will disappear, that is, the nanoband band gap of the two-dimensional material is zero. Therefore, nanoribbons of two-dimensional materials will no longer be suitable for making transistors. Compared with two-dimensional materials, one-dimensional nanotubes have good characteristics and non-zero band gap, so they can be used as the active layer of transistor devices. Although there are transistors that use nanotubes as the active layer, their structure is similar to that of traditional transistors. Figure 1 shows the existing transistor structure (01 is graphene and 02 is nanowire). The overall volume of the structure is large, and it is difficult to achieve the requirements of a true nano-level device. At the same time, the components of the existing transistor devices prepared by using nanotubes as the active layer are relatively dispersed, and the transistor strength is poor.
发明内容Summary of the invention
(一)要解决的技术问题(1) Technical problems to be solved
本发明提供了一种纳米级晶体管及其制备方法，以至少部分解决以上所提出的技术问题。The present invention provides a nano-scale transistor and a preparation method thereof, so as to at least partially solve the above-mentioned technical problems.
(二)技术方案(2) Technical solution
根据本发明的一个方面，提供了一种纳米级晶体管，包括：According to one aspect of the present invention, there is provided a nano-scale transistor including:
绝缘层衬底、绝缘层支撑柱、有源层、漏电极、栅介质层、源电极以及栅电极；Insulating layer substrate, insulating layer supporting column, active layer, drain electrode, gate dielectric layer, source electrode and gate electrode;
所述绝缘层支撑柱位于所述绝缘层衬底上方，所述有源层包裹于所述绝缘层支撑柱外部，所述漏电极、栅介质层以及源电极从下至上依次包裹于所述有源层外部，所述栅电极包裹于所述栅介质层外部；其中，所述有源层为半导体材料形成的纳米管。The insulating layer support column is located above the insulating layer substrate, the active layer is wrapped around the insulating layer support column, and the drain electrode, the gate dielectric layer, and the source electrode are wrapped in order from the bottom to the top. Outside the source layer, the gate electrode is wrapped outside the gate dielectric layer; wherein, the active layer is a nanotube formed of a semiconductor material.
在一些实施例中，所述绝缘层衬底为玻璃衬底，厚度为1μm-10μm。In some embodiments, the insulating layer substrate is a glass substrate with a thickness of 1 μm-10 μm.
在一些实施例中，所述绝缘层支撑柱为玻璃圆柱体，高度为100nm-500nm，直径为所述有源层的内径尺寸。In some embodiments, the insulating layer support column is a glass cylinder with a height of 100 nm-500 nm, and a diameter of the inner diameter of the active layer.
在一些实施例中，所述源电极和漏电极为材料Pt、Au、Cu或者Ag形成的圆环柱，所述源电极和漏电极的高度为20nm-50nm，壁厚为10nm-100nm。In some embodiments, the source electrode and the drain electrode are circular columns formed of Pt, Au, Cu or Ag, and the height of the source electrode and the drain electrode is 20nm-50nm, and the wall thickness is 10nm-100nm.
在一些实施例中，所述栅介质层为采用材料Al 2O 3或SiO 2形成的圆环柱，其高度为100nm-300nm，壁厚为10nm-100nm。 In some embodiments, the gate dielectric layer is a circular column formed of Al 2 O 3 or SiO 2 with a height of 100 nm to 300 nm and a wall thickness of 10 nm to 100 nm.
在一些实施例中，所述栅电极为材料Mo、Pt、Au、Cu以及Ag中至少一种形成的圆环柱，其高度为50nm-250nm，壁厚为50nm-500nm。In some embodiments, the gate electrode is a circular column formed by at least one of Mo, Pt, Au, Cu, and Ag, with a height of 50nm-250nm and a wall thickness of 50nm-500nm.
根据本发明的另一个方面，提供了一种如上所述的纳米级晶体管的制备方法，所述方法包括：According to another aspect of the present invention, there is provided a method for manufacturing a nanoscale transistor as described above, the method comprising:
在绝缘层衬底上制备绝缘层支撑柱；Preparing insulating layer support pillars on the insulating layer substrate;
将纳米管作为有源层转移到绝缘层支撑柱上；Transfer the nanotubes as the active layer to the insulating layer support column;
在所述纳米管外壁生长漏电极；Growing a drain electrode on the outer wall of the nanotube;
在所述纳米管外壁并沿着所述漏电极的上部生长栅介质层；Growing a gate dielectric layer on the outer wall of the nanotube and along the upper part of the drain electrode;
在所述纳米管外壁并沿着所述栅介质层上部生长源电极；Growing a source electrode on the outer wall of the nanotube and along the upper part of the gate dielectric layer;
在所述栅介质层外部生长栅电极。A gate electrode is grown outside the gate dielectric layer.
在一些实施例中，采用拉丝、化学气相沉积、脉冲激光沉积、原子层沉积或者磁控溅射方法制备所述绝缘层支撑柱。In some embodiments, the insulating layer support column is prepared by wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.
在一些实施例中，所述漏电极、源电极以及栅电极均采用电子束蒸发方法制备；所述栅介质层采用化学沉积方法制备。In some embodiments, the drain electrode, the source electrode and the gate electrode are all prepared by an electron beam evaporation method; the gate dielectric layer is prepared by a chemical deposition method.
在一些实施例中，所述漏电极和源电极的材料均为Pt、Au、Cu或者Ag；所述栅介质层的材料为Al 2O 3或SiO 2；所述栅电极的材料为Mo、Pt、Au、Cu以及Ag中的至少一种；所述漏电极、源电极、栅介质层以及栅电极的形状均为圆环柱。 In some embodiments, the materials of the drain electrode and the source electrode are both Pt, Au, Cu or Ag; the material of the gate dielectric layer is Al 2 O 3 or SiO 2 ; the material of the gate electrode is Mo, At least one of Pt, Au, Cu and Ag; the shape of the drain electrode, the source electrode, the gate dielectric layer and the gate electrode are all circular pillars.
(三)有益效果(3) Beneficial effects
从上述技术方案可以看出，本发明纳米级晶体管及其制备方法至少具有以下有益效果其中之一或其中一部分：It can be seen from the above technical solutions that the nanoscale transistor and the preparation method thereof of the present invention have at least one or part of the following beneficial effects:
(1)本发明提供的纳米级晶体管及其制备方法，以纳米管作为有源层，且绝缘层，有源层，源、漏电极等紧密结合在一起，不仅将晶体管的整体尺寸减小，而且得到了较大强度的纳米级晶体管，可以推广到所有具有半导体特性的纳米管器件中；(1) The nanoscale transistor and its preparation method provided by the present invention use nanotubes as the active layer, and the insulating layer, active layer, source and drain electrodes are tightly combined, which not only reduces the overall size of the transistor, but also Moreover, a relatively strong nanoscale transistor is obtained, which can be extended to all nanotube devices with semiconductor characteristics;
(2)本发明提供的纳米级晶体管及其制备方法，以半导体纳米管为有源层，以金属或者金属化合物材料形成晶体管中的其它组成，由此得到有范德华尔(van der Waals)接触的纳米级晶体管，该纳米级晶体管中纳米管材料与金属接触时其接触电阻很小，从而减小了载流子注入的阻力。(2) The nano-scale transistor and the preparation method thereof provided by the present invention use semiconductor nanotubes as the active layer and metal or metal compound materials to form other components in the transistor, thereby obtaining van der Waals contacts. A nano-scale transistor, in which the contact resistance of the nanotube material in contact with the metal is small, thereby reducing the resistance of carrier injection.
附图说明Description of the drawings
构成本发明的一部分的附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and the description thereof are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:
图1为现有的晶体管结构示意图；Fig. 1 is a schematic diagram of a conventional transistor structure;
图2为本发明纳米级晶体管的结构示意图；Figure 2 is a schematic diagram of the structure of a nanoscale transistor of the present invention;
图3为本发明纳米级晶体管制备方法流程图；Figure 3 is a flow chart of the method for preparing a nanoscale transistor of the present invention;
图4为本发明实施例提供的纳米级晶体管制备过程示意图。FIG. 4 is a schematic diagram of a manufacturing process of a nanoscale transistor provided by an embodiment of the present invention.
<现有技术><Existing Technology>
01-石墨烯，02-纳米线。01-graphene, 02-nanowire.
<本发明><The present invention>
1-绝缘层衬底；2-绝缘层支撑柱；3-有源层；4-漏电极；5-栅介质层；6-源电极；7-栅电极。1-Insulating layer substrate; 2-Insulating layer supporting column; 3-active layer; 4-drain electrode; 5-gate dielectric layer; 6-source electrode; 7-gate electrode.
具体实施方式Detailed ways
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
根据本发明的一个方面，提供了一种纳米级晶体管，如图2所示，该纳米级晶体管包括：According to one aspect of the present invention, a nanoscale transistor is provided. As shown in FIG. 2, the nanoscale transistor includes:
绝缘层衬底1、绝缘层支撑柱2、有源层3、漏电极4、栅介质层5、源电极6以及栅电极7；绝缘层支撑柱2位于绝缘层衬底1上方，有源层3包裹于绝缘层支撑柱2外部，所述漏电极4、栅介质层5以及源电极6从下至上依次包裹于有源层3外部，栅电极7包裹于栅介质层5外部，由此将绝缘层，有源层，源、漏电极等紧密结合在一起。其中，有源层3为半导体材料形成的纳米管，该纳米管的材料可以是氮化硼(BN)或者二硫化钼(MoS 2)等材料。 The insulating layer substrate 1, the insulating layer supporting column 2, the active layer 3, the drain electrode 4, the gate dielectric layer 5, the source electrode 6, and the gate electrode 7; the insulating layer supporting column 2 is located above the insulating layer substrate 1, and the active layer 3 Wrapped outside the insulating layer support column 2, the drain electrode 4, the gate dielectric layer 5, and the source electrode 6 are sequentially wrapped outside the active layer 3 from bottom to top, and the gate electrode 7 is wrapped outside the gate dielectric layer 5, thereby The insulating layer, the active layer, the source and drain electrodes are tightly integrated. Wherein, the active layer 3 is a nanotube formed of a semiconductor material, and the material of the nanotube may be materials such as boron nitride (BN) or molybdenum disulfide (MoS 2 ).
本发明提供的纳米级晶体管，以纳米管作为有源层，且将绝缘层，有源层，源、漏电极等紧密结合在一起，不仅将晶体管的整体尺寸减小，同时得到了较大强度的纳米级晶体管，可以推广到所有具有半导体特性的纳米管器件中。The nano-level transistor provided by the present invention uses nanotubes as the active layer, and closely combines the insulating layer, the active layer, the source and drain electrodes, etc., which not only reduces the overall size of the transistor, but also obtains greater strength Nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.
具体的，所述绝缘层衬底1为玻璃衬底，厚度为1μm-10μm；所述绝缘层支撑柱2为玻璃圆柱体，高度为200nm-500nm，因为有源层3即纳米管需要嵌套于绝缘层支撑柱2外，所以绝缘层支撑柱2的直径为有源层3即纳米管的内径尺寸。Specifically, the insulating layer substrate 1 is a glass substrate with a thickness of 1 μm-10 μm; the insulating layer support column 2 is a glass cylinder with a height of 200 nm-500 nm, because the active layer 3, that is, nanotubes need to be nested It is outside the insulating layer supporting column 2, so the diameter of the insulating layer supporting column 2 is the inner diameter of the active layer 3, that is, the nanotube.
所述源电极6和漏电极4为材料Pt、Au、Cu或者Ag形成的圆环柱，其高度为20nm-50nm，壁厚为10nm-100nm；栅电极7为材料Mo、Pt、Au、Cu以及Ag中至少一种组成的圆环柱，其高度为50nm-250nm，壁厚为50nm-500nm；而栅介质层5为采用材料Al 2O 3或SiO 2形成的圆环柱，其高度为100nm-300nm，壁厚为10nm-100nm。其中，漏电极4、栅介质层5、栅电极7以及源电极6也可以是其他形状，如长方形柱体或正方形柱体，但是由于纳米管为圆环柱，相对于其他形状，用圆柱体可以使器件更稳定。本发明提供的纳米级晶体管，以半导体纳米管为有源层，其他结构为金属或者金属化合物，得到有范德华尔(van der Waals)接触的纳米级晶体管，该纳米级晶体管中纳米管材料与金属接触时其接触电阻很小，从而 减小了载流子注入的阻力。 The source electrode 6 and the drain electrode 4 are circular cylinders formed of Pt, Au, Cu or Ag, with a height of 20nm-50nm and a wall thickness of 10nm-100nm; the gate electrode 7 is made of Mo, Pt, Au, Cu And a circular column composed of at least one of Ag, with a height of 50nm-250nm and a wall thickness of 50nm-500nm; and the gate dielectric layer 5 is a circular column formed of Al 2 O 3 or SiO 2 with a height of 100nm-300nm, wall thickness is 10nm-100nm. Among them, the drain electrode 4, the gate dielectric layer 5, the gate electrode 7 and the source electrode 6 can also have other shapes, such as a rectangular column or a square column. However, because the nanotube is a circular column, compared to other shapes, a cylindrical Can make the device more stable. The nanoscale transistor provided by the present invention uses semiconductor nanotubes as the active layer, and other structures are metals or metal compounds to obtain a nanoscale transistor with van der Waals contact. In the nanoscale transistor, the nanotube material and the metal The contact resistance is very small when in contact, thereby reducing the resistance of carrier injection.
根据本发明的另一个方面，提供了一种纳米级晶体管的制备方法，如图3所示，该方法包括如下步骤：According to another aspect of the present invention, a method for preparing a nanoscale transistor is provided. As shown in FIG. 3, the method includes the following steps:
步骤S101，在绝缘层衬底上制备绝缘层支撑柱；Step S101, preparing an insulating layer support column on the insulating layer substrate;
步骤S102，将纳米管作为有源层转移到绝缘层支撑柱上；Step S102, transferring the nanotubes as the active layer to the insulating layer support column;
步骤S103，在纳米管外壁生长漏电极；Step S103, growing a drain electrode on the outer wall of the nanotube;
步骤S104，在纳米管外壁并沿着漏电极的上部生长栅介质层；Step S104, growing a gate dielectric layer on the outer wall of the nanotube and along the upper part of the drain electrode;
步骤S105，在纳米管外壁并沿着栅介质层上部生长源电极；Step S105, growing a source electrode on the outer wall of the nanotube and along the upper part of the gate dielectric layer;
步骤S106，在栅介质层外部生长栅电极。Step S106, growing a gate electrode outside the gate dielectric layer.
本发明提供的纳米级晶体管制备方法，以纳米管作为有源层，且将绝缘层，有源层，源、漏电极等紧密结合在一起，不仅将晶体管的整体尺寸减小，也得到了较大强度的纳米级晶体管，可以推广到所有具有半导体特性的纳米管器件中。The method for preparing a nanoscale transistor provided by the present invention uses nanotubes as the active layer, and closely combines the insulating layer, the active layer, the source and drain electrodes, etc., which not only reduces the overall size of the transistor, but also obtains a better High-strength nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.
具体的，可以采用拉丝、化学气相沉积、脉冲激光沉积、原子层沉积或者磁控溅射等方法制备绝缘层支撑柱；采用电子束蒸发方法制备漏电极、源电极以及栅电极；采用化学沉积方法制备栅介质层。Specifically, the insulating layer support column can be prepared by wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering; the drain electrode, source electrode, and gate electrode can be prepared by the electron beam evaporation method; and the chemical deposition method can be used Prepare the gate dielectric layer.
更具体而言，首先在厚度为1μm-10μm的绝缘层衬底即玻璃衬底上采用拉丝、化学气相沉积、脉冲激光沉积、原子层沉积或者磁控溅射等方法制备高度为200nm-500nm的绝缘层支撑柱即玻璃圆柱体，并将纳米管作为有源层转移到绝缘层支撑柱外上，其中要求绝缘层支撑柱的直径与纳米管的内径相同；然后在纳米管外壁采用电子束蒸发方法生长壁厚为10nm-100nm，高度为20nm-50nm的漏电极圆环柱，其材料为Pt、Au、Cu或者Ag，通过化学沉积方法在纳米管外壁并沿着漏电极的上部生长壁厚为10nm-100nm和高度为100nm-300nm的圆环柱作为栅介质层，该圆环柱栅介质层材料可以是Al 2O 3或SiO 2，通过电子束蒸发方法在纳米管外壁并沿着栅介质层上部生长壁厚为10nm-100nm，高度为20nm-50nm的Pt、Au、Cu或Ag等的圆环柱作为源电极；最后通过电子束蒸发方法在栅介质层圆环柱外部生长Mo、Pt、Au、Cu及Ag中的至少一种组成的圆环柱，其高度为50nm-250nm，厚度为50nm-500nm，作为栅电极。 More specifically, firstly, wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering is used to prepare a thickness of 200nm-500nm on an insulating layer substrate with a thickness of 1μm-10μm, that is, a glass substrate. The insulating layer support column is a glass cylinder, and the nanotube is transferred as the active layer to the outside of the insulating layer support column, where the diameter of the insulating layer support column is required to be the same as the inner diameter of the nanotube; then the electron beam evaporation is used on the outer wall of the nanotube The method grows a drain electrode circular column with a wall thickness of 10nm-100nm and a height of 20nm-50nm. The material is Pt, Au, Cu or Ag. The wall thickness is grown on the outer wall of the nanotube and along the upper part of the drain electrode by chemical deposition. The circular column with a height of 10nm-100nm and a height of 100nm-300nm is used as the gate dielectric layer. The material of the circular column gate dielectric layer can be Al 2 O 3 or SiO 2. The electron beam evaporation method is used on the outer wall of the nanotube and along the gate. The growth wall thickness of the upper part of the dielectric layer is 10nm-100nm, and the ring pillars of Pt, Au, Cu or Ag with the height of 20nm-50nm are used as the source electrode; finally, Mo, Mo, Au, Cu, or Ag are grown on the outside of the gate dielectric layer by electron beam evaporation method. A circular column composed of at least one of Pt, Au, Cu and Ag, with a height of 50nm-250nm and a thickness of 50nm-500nm, serves as a gate electrode.
在本实施例中，因为采用纳米管作为有源层，而且纳米管为圆环柱，因此整体形状为圆环柱体，并且在纳米管上直接制备源电极、漏电极以及栅介质层，在减小整体尺寸的同时，可以使晶体管的性能更加稳定。In this embodiment, because nanotubes are used as the active layer, and the nanotubes are circular cylinders, the overall shape is circular cylinders, and the source electrode, drain electrode, and gate dielectric layer are directly prepared on the nanotubes. While reducing the overall size, the performance of the transistor can be made more stable.
本发明提供的纳米级晶体管制备方法，以半导体纳米管为有源层，其他结构为金属或者金属化合物，得到有范德华尔(van der Waals)接触的纳米级晶体管，该纳米级晶体管中纳米管材料与金属接触时其接触电阻很小，从而减小了载流子注入的阻力。The method for preparing nanoscale transistors provided by the present invention uses semiconductor nanotubes as the active layer and other structures as metals or metal compounds to obtain nanoscale transistors with van der Waals contacts. The nanotube material in the nanoscale transistor is When in contact with metal, its contact resistance is very small, thereby reducing the resistance of carrier injection.
在一具体实施例中，如图4所示，纳米级晶体管的制备过程为：首先，采用拉丝工艺，在玻璃衬底上制备出高500nm，直径与纳米管内径相等的玻璃柱作为绝缘层支撑柱，采用转移的方法将BN纳米管转移到绝缘层支撑柱上；然后通电子束蒸发方法在BN纳米管外壁沿着衬底底部生长厚度为50nm，高为100nm的Au圆环柱作为晶体管的漏电极，通过化学沉积方法在纳米管外壁沿着下电极处生长厚度为50nm，高为250nm的SiO 2圆环柱作为栅介质层，再通过电子束蒸发方法在BN纳米管外壁沿着栅介质层处生长厚度为50nm，高为100nm的Au圆环柱作为晶体管的源电极；最后采用电子束蒸发方法在栅介质层外部生长厚度为100nm，高为150nm的Pt圆环柱作为栅电极。 In a specific embodiment, as shown in FIG. 4, the preparation process of a nanoscale transistor is as follows: first, a wire drawing process is used to prepare a glass column with a height of 500 nm and a diameter equal to the inner diameter of the nanotube as an insulating layer support on a glass substrate. Column, the BN nanotube is transferred to the insulating layer support column by the transfer method; then the Au ring column with the thickness of 50nm and the height of 100nm is grown on the outer wall of the BN nanotube along the bottom of the substrate by the electron beam evaporation method as the transistor For the drain electrode, a SiO 2 circular column with a thickness of 50 nm and a height of 250 nm is grown on the outer wall of the nanotube along the bottom electrode by chemical deposition as the gate dielectric layer, and then the gate dielectric is deposited on the outer wall of the BN nanotube by the electron beam evaporation method. An Au ring column with a thickness of 50 nm and a height of 100 nm is grown at the layer as the source electrode of the transistor; finally, an electron beam evaporation method is used to grow a Pt ring column with a thickness of 100 nm and a height of 150 nm on the outside of the gate dielectric layer as the gate electrode.
本发明实施例提供的纳米级晶体管制备方法，以纳米管作为有源层，把绝缘层，有源层，源、漏电极等紧密结合在一起，不仅将晶体管的整体尺寸减小，同时得到了较大强度的纳米级晶体管，可以推广到所有具有半导体特性的纳米管器件中。In the method for preparing nanoscale transistors provided by the embodiments of the present invention, nanotubes are used as the active layer, and the insulating layer, active layer, source and drain electrodes are tightly combined, which not only reduces the overall size of the transistor, but also obtains Higher strength nano-scale transistors can be extended to all nanotube devices with semiconductor characteristics.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Within the spirit and principle of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (10)

  1. 一种纳米级晶体管，其特征在于，包括：A nano-scale transistor, characterized in that it comprises:
    绝缘层衬底、绝缘层支撑柱、有源层、漏电极、栅介质层、源电极以及栅电极；Insulating layer substrate, insulating layer supporting column, active layer, drain electrode, gate dielectric layer, source electrode and gate electrode;
    所述绝缘层支撑柱位于所述绝缘层衬底上方，所述有源层包裹于所述绝缘层支撑柱外部，所述漏电极、栅介质层以及源电极从下至上依次包裹于所述有源层外部，所述栅电极包裹于所述栅介质层外部；其中，所述有源层为半导体材料形成的纳米管。The insulating layer support column is located above the insulating layer substrate, the active layer is wrapped around the insulating layer support column, and the drain electrode, the gate dielectric layer, and the source electrode are wrapped in order from the bottom to the top. Outside the source layer, the gate electrode is wrapped outside the gate dielectric layer; wherein, the active layer is a nanotube formed of a semiconductor material.
  2. 根据权利要求1所述的纳米级晶体管，其特征在于，所述绝缘层衬底为玻璃衬底，厚度为1μm-10μm。The nanoscale transistor according to claim 1, wherein the insulating layer substrate is a glass substrate with a thickness of 1 μm-10 μm.
  3. 根据权利要求1所述的纳米级晶体管，其特征在于，所述绝缘层支撑柱为玻璃圆柱体，高度为100nm-500nm，直径为所述有源层的内径尺寸。The nanoscale transistor according to claim 1, wherein the insulating layer support column is a glass cylinder with a height of 100 nm to 500 nm, and a diameter of the inner diameter of the active layer.
  4. 根据权利要求1所述的纳米级晶体管，其特征在于，所述源电极和漏电极为材料Pt、Au、Cu或者Ag形成的圆环柱，所述源电极和漏电极的高度为20nm-50nm，壁厚为10nm-100nm。The nano-scale transistor according to claim 1, wherein the source electrode and the drain electrode are circular columns formed of Pt, Au, Cu or Ag, and the height of the source electrode and the drain electrode is 20nm-50nm, The wall thickness is 10nm-100nm.
  5. 根据权利要求1所述的纳米级晶体管，其特征在于，所述栅介质层为采用材料Al 2O 3或SiO 2形成的圆环柱，其高度为100nm-300nm，壁厚为10nm-100nm。 The nanoscale transistor according to claim 1, wherein the gate dielectric layer is a circular column formed of Al 2 O 3 or SiO 2 with a height of 100 nm-300 nm and a wall thickness of 10 nm-100 nm.
  6. 根据权利要求1所述的纳米级晶体管，其特征在于，所述栅电极为材料Mo、Pt、Au、Cu以及Ag中至少一种形成的圆环柱，其高度为50nm-250nm，壁厚为50nm-500nm。The nanoscale transistor according to claim 1, wherein the gate electrode is a circular column formed by at least one of Mo, Pt, Au, Cu, and Ag, the height of which is 50nm-250nm, and the wall thickness is 50nm-500nm.
  7. 一种如权利要求1至6中任一项所述的纳米级晶体管的制备方法，其特征在于，所述方法包括：A method for preparing a nanoscale transistor according to any one of claims 1 to 6, wherein the method comprises:
    在绝缘层衬底上制备绝缘层支撑柱；Preparing insulating layer support pillars on the insulating layer substrate;
    将纳米管作为有源层转移到绝缘层支撑柱上；Transfer the nanotubes as the active layer to the insulating layer support column;
    在所述纳米管外壁生长漏电极；Growing a drain electrode on the outer wall of the nanotube;
    在所述纳米管外壁并沿着所述漏电极的上部生长栅介质层；Growing a gate dielectric layer on the outer wall of the nanotube and along the upper part of the drain electrode;
    在所述纳米管外壁并沿着所述栅介质层上部生长源电极；Growing a source electrode on the outer wall of the nanotube and along the upper part of the gate dielectric layer;
    在所述栅介质层外部生长栅电极。A gate electrode is grown outside the gate dielectric layer.
  8. 根据权利要求7所述的方法，其特征在于，采用拉丝、化学气相沉积、脉冲激光沉积、原子层沉积或者磁控溅射方法制备所述绝缘层支撑柱。8. The method according to claim 7, wherein the insulating layer support column is prepared by wire drawing, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering.
  9. 根据权利要求7所述的方法，其特征在于，所述漏电极、源电极以及栅电极均采用电子束蒸发方法制备；所述栅介质层采用化学沉积方法制备。8. The method according to claim 7, wherein the drain electrode, the source electrode and the gate electrode are all prepared by an electron beam evaporation method; and the gate dielectric layer is prepared by a chemical deposition method.
  10. 根据权利要求7所述的方法，其特征在于，所述漏电极和源电极的材料均为Pt、Au、Cu或者Ag；所述栅介质层的材料为Al 2O 3或SiO 2；所述栅电极的材料为Mo、Pt、Au、Cu以及Ag中的至少一种；所述漏电极、源电极、栅介质层以及栅电极的形状均为圆环柱。 7. The method according to claim 7, wherein the materials of the drain electrode and the source electrode are both Pt, Au, Cu or Ag; the material of the gate dielectric layer is Al 2 O 3 or SiO 2 ; The material of the gate electrode is at least one of Mo, Pt, Au, Cu, and Ag; the shape of the drain electrode, the source electrode, the gate dielectric layer and the gate electrode are all circular pillars.
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