WO2020224389A1

WO2020224389A1 - Array substrate, display panel and display device

Info

Publication number: WO2020224389A1
Application number: PCT/CN2020/084544
Authority: WO
Inventors: 郝学光; 吴新银; 乔勇
Original assignee: 京东方科技集团股份有限公司; 北京京东方技术开发有限公司
Priority date: 2019-05-05
Filing date: 2020-04-13
Publication date: 2020-11-12
Also published as: CN209434190U

Abstract

Disclosed are an array substrate, a display panel and a display device. The array substrate comprises: a base substrate 10; a plurality of sub-pixels arranged in an array on the base substrate 10, wherein at least one of the plurality of sub-pixels comprises: a pixel circuit; a plurality of scanning lines, wherein pixel circuits in a row of sub-pixels are electrically connected to at least one scanning line, and the scanning lines extend in the row direction of the sub-pixels and are arranged in the column direction of the sub-pixels; and a plurality of transmission signal lines electrically connected to the pixel circuits, wherein the plurality of transmission signal lines extend in the column direction and are arranged in the row direction, and at least one of the plurality of transmission signal lines has a multilayer wiring structure where layers are electrically connected to one another.

Description

Array substrate, display panel and display device

Cross references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 201920631110.6, and the application name is "an array substrate, display panel and display device" on May 05, 2019, the entire content of which is incorporated by reference In this application.

Technical field

The present disclosure relates to the field of flexible display technology, and in particular to an array substrate, a display panel and a display device.

Background technique

Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED) and other electroluminescent diodes have the advantages of self-luminescence, low energy consumption, etc., which are the most important in the application research field of electroluminescent display panels. One of the hot spots has received widespread attention.

Summary of the invention

The array substrate provided by the embodiment of the present disclosure includes:

Base substrate

A plurality of sub-pixels are arranged in an array on the base substrate, and at least one of the plurality of sub-pixels includes: a pixel circuit;

A plurality of scan lines, the pixel circuits in a row of the sub-pixels are electrically connected to at least one of the scan lines, and the scan lines extend along the row direction of the sub-pixels and are arranged along the column direction of the sub-pixels;

A plurality of transmission signal lines are electrically connected to the pixel circuit, and the plurality of transmission signal lines extend in the column direction and are arranged in the row direction;

Wherein, at least one of the plurality of transmission signal lines has a multilayer wiring structure electrically connected to each other.

In some embodiments, the array substrate further includes:

A plurality of power signal lines, the power signal lines are located in a gap between two adjacent sub-pixel columns, and the power signal lines are electrically connected to the pixel circuit;

A plurality of detection signal lines, the detection signal line is located in the gap between two adjacent sub-pixel columns, and the detection signal line is insulated from the power signal line, and the detection signal line is electrically connected to the pixel circuit connection;

The transmission signal line includes: at least one of the plurality of detection signal lines and the plurality of power signal lines.

In some embodiments, the array substrate further includes a plurality of first connection wires and a plurality of second connection wires; the first connection wires and the second connection wires are insulated; wherein, the first connection wires The extension direction of the power signal line crosses the extension direction of the power signal line, and the extension direction of the second connection line crosses the extension direction of the detection signal line;

Some of the pixel circuits are electrically connected to one of the power signal lines through a first connection line, and some of the pixel circuits are electrically connected to one of the detection signal lines through a second connection line;

At least one of the plurality of first connecting lines and the plurality of second connecting lines has a multilayer wiring structure electrically connected to each other.

In some embodiments, the array substrate further includes:

The light-shielding metal layer is located on the base substrate;

The first insulating layer is located on the side of the light-shielding metal layer away from the base substrate;

A semiconductor layer located on the side of the first insulating layer away from the base substrate;

A second insulating layer located on the side of the semiconductor layer away from the base substrate;

A gate conductive layer located on a side of the second insulating layer away from the base substrate, and the gate conductive layer includes the plurality of scan lines;

A third insulating layer located on the side of the gate conductive layer away from the base substrate;

The source-drain conductive layer is located on the side of the third insulating layer away from the base substrate, and the source-drain conductive layer includes the plurality of power signal lines and the plurality of detection signal lines;

The multilayer wiring structure includes at least any two layers of the light-shielding conductive layer, the gate conductive layer, and the source-drain conductive layer; and the same multilayer wiring structure passes through the multilayer wiring structure. The multiple via holes of the insulating layer between the wire structures are electrically connected.

In some embodiments, the gate conductive layer further includes a plurality of first auxiliary portions, and the first auxiliary portions are insulated from the scan line; wherein, one of the power signal lines passes through a plurality of first vias Electrically connected to at least one of the first auxiliary parts, and the first via hole penetrates the third insulating layer;

The power signal line and the first auxiliary part that are electrically connected to each other form a multilayer wiring structure of the power signal line.

In some embodiments, the orthographic projection of the power signal line on the base substrate covers the orthographic projection of the first auxiliary part of the electrical connection on the base substrate.

In some embodiments, the power signal line has a gap at the edge of the orthographic projection of the base substrate and the electrically connected first auxiliary part at the edge of the orthographic projection of the base substrate, and the power signal line The cross section perpendicular to the extension direction of the power signal line is in the shape of a "several".

In some embodiments, the gate conductive layer further includes a plurality of second auxiliary portions, and the second auxiliary portions are insulated from the scan line; wherein, one detection signal line passes through a plurality of second via holes Electrically connected to at least one of the second auxiliary portions, and the second via hole penetrates the third insulating layer;

The detection signal line and the second auxiliary part electrically connected to each other form a multilayer wiring structure of the detection signal line.

In some embodiments, the orthographic projection of the detection signal line on the base substrate covers the orthographic projection of the second auxiliary part of the electrical connection on the base substrate.

In some embodiments, the detection signal line has a gap at the edge of the orthographic projection of the base substrate and the second auxiliary part electrically connected to the edge of the orthographic projection of the base substrate, and the detection signal line The cross section perpendicular to the extending direction of the detection signal line is in the shape of a "several".

In some embodiments, the gate conductive layer further includes a plurality of third auxiliary parts, and the third auxiliary parts are insulated from the scan line; wherein, one of the first connecting lines passes through a plurality of third passing parts. The hole is electrically connected to at least one of the third auxiliary parts, and the third via hole penetrates the third insulating layer;

The first connection line and the third auxiliary part electrically connected to each other form a multilayer wiring structure of the first connection line.

In some embodiments, the orthographic projection of the first connecting line on the base substrate covers the orthographic projection of the third auxiliary part of the electrical connection on the base substrate.

In some embodiments, the gate conductive layer further includes a plurality of fourth auxiliary parts, and the fourth auxiliary parts are insulated from the scan line; wherein, one of the second connecting lines passes through a plurality of fourth passing parts. The hole is electrically connected to at least one of the fourth auxiliary parts, and the fourth via hole penetrates the third insulating layer;

The second connecting line and the fourth auxiliary part electrically connected to each other form a multilayer wiring structure of the second connecting line.

In some embodiments, the orthographic projection of the second connecting line on the base substrate covers the orthographic projection of the fourth auxiliary part of the electrical connection on the base substrate.

In some embodiments, the gap between two adjacent sub-pixel columns where the power signal line and the detection signal line are located is different.

The display panel provided by the embodiment of the present disclosure includes the above-mentioned array substrate.

The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.

Description of the drawings

FIG. 1 is a schematic structural diagram of some array substrates provided by embodiments of the disclosure;

2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure;

3 is a schematic diagram of specific structures of some array substrates provided by embodiments of the disclosure;

4 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG. 3 along the AA' direction;

5 is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 3 along the BB' direction;

6a is a schematic diagram of specific structures of still other array substrates provided by the embodiments of the disclosure;

6b is a schematic cross-sectional structure view of the array substrate shown in FIG. 6a along the AA' direction;

FIG. 7a is a schematic diagram of specific structures of still other array substrates provided by the embodiments of the disclosure;

FIG. 7b is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 7a along the AA' direction;

FIG. 8 is a schematic diagram of specific structures of still other array substrates provided by the embodiments of the disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. And in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, and are only intended to illustrate the present disclosure. And the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions.

As the pixel resolution of the display panel becomes higher and higher, the wiring area in the display panel becomes smaller and smaller. Generally, a variety of signal lines are provided in the display panel to transmit signals. As signal lines are gradually becoming thinner and more refined, this will cause the resistance of the signal lines to become larger and larger, especially for some important signal lines (such as power signal lines, detection signal lines). The power consumption of the display panel has increased significantly. However, in order to reduce the resistance of the signal line, it can be solved in the following two ways: (1) Widen the width of the signal line. However, due to the limited wiring space, the contribution of this method to reducing the power consumption of the display panel is limited. (2) Thicken the signal line. However, due to the limitation of process factors, the use of this method is limited by the exposure ability. When the thickness of the signal line reaches more than 8000 angstroms, it is easy to cause residual photoresist and cause poor display.

The embodiments of the present disclosure provide some array substrates. By setting the signal lines in a multilayer wiring structure that is electrically connected to each other, it is equivalent to making the signal lines consist of at least two signal lines in parallel, which can be arranged in a multilayer wiring structure. The resistance of the signal line is reduced, so that the power consumption of the display panel where the array substrate is located can be reduced, which satisfies the customer's requirements for low power consumption.

In addition, the array substrate provided by the embodiments of the present disclosure can also reduce the wiring space of the signal lines, and can avoid the problem of photoresist residue caused by increasing the thickness of the signal lines and causing poor display.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 1, the array substrate may include: a base substrate 10 and a plurality of pixel units PX. The pixel unit PX may include multiple sub-pixels spx. These sub-pixel spx arrays are arranged on the base substrate 10.

Exemplarily, as shown in FIG. 1 and FIG. 2, at least one sub-pixel spx in the plurality of sub-pixels may include: a pixel circuit and an electroluminescent diode L. Among them, the pixel circuit has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode of the electroluminescent diode. In addition, a corresponding voltage is applied to the cathode of the electroluminescent diode to drive the electroluminescent diode to emit light.

Exemplarily, as shown in FIG. 2, the pixel circuit may include a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. Wherein, the gate of the switching transistor T2 is electrically connected to the scan line GA, the first electrode (for example, the source) of the switching transistor T2 is electrically connected to the data line DA, and the second electrode (for example, the drain) of the switching transistor T2 is electrically connected to the driving transistor T1. The grid is electrically connected. The first electrode (for example, the source) of the driving transistor T1 is electrically connected to the power signal line Vdd, the second electrode (for example, the drain) of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode L, and the cathode of the electroluminescent diode L It is electrically connected to the low-voltage signal line VSS. The gate of the sensing transistor T3 is electrically connected to the scan line GA, the first electrode (such as the source) of the sensing transistor T3 is electrically connected to the second electrode (such as the drain) of the driving transistor T1, and the second electrode of the sensing transistor T3 is electrically connected. The pole (for example, the drain) is electrically connected to the detection signal line SL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the second electrode of the storage capacitor Cst is electrically connected to the second electrode (for example, the drain) of the driving transistor T1.

The switching transistor T2 is controlled to be turned on by the signal transmitted on the scan line GA to write the data voltage transmitted on the data line DA into the gate of the driving transistor T1, and the driving transistor T1 is controlled to generate a working current to drive the electroluminescent diode L to emit light. . And the sensing transistor T3 is controlled to turn on by the signal transmitted on the scan line GA, so as to output the operating current generated by the driving transistor T1 to the detection signal line SL to charge the detection signal line SL. After that, the voltage on each detection signal line SL is detected, and compensation calculation is performed according to the detected voltage to obtain the data voltage corresponding to each sub-pixel in the row for display.

Exemplarily, the power signal line Vdd may transmit a constant first voltage, which is a positive voltage; and the low voltage signal line VSS may transmit a constant second voltage, which is a negative voltage. Alternatively, in some examples, the low voltage signal line VSS may also be grounded.

It should be noted that, in the embodiment of the present disclosure, the pixel circuit may be a structure including other numbers of transistors and capacitors in addition to the structure shown in FIG. 2, which is not limited in the embodiment of the present disclosure.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 1, the display panel may further include: a plurality of scan lines GA, a plurality of detection signal lines SL, a plurality of data lines DA, and a power signal line Vdd. Among them, the scan line GA, the detection signal line SL, the data line DA, and the power signal line Vdd are insulated from each other. Among them, the pixel circuit in a column of sub-pixels is electrically connected to a data line DA. Pixel circuits in one column of pixel units and one detection signal line SL. The pixel circuits in a row of sub-pixels are electrically connected to at least one scan line. For example, the pixel circuits in a row of sub-pixels are electrically connected to one scan line.

Exemplarily, the scan lines extend along the row direction F2 of the sub-pixels and are arranged along the column direction F1 of the sub-pixels. The data lines DA extend along the column direction F1 and are arranged along the row direction F2, the power signal lines Vdd extend along the column direction F1 and are arranged along the row direction F2, and the detection signal lines SL extend along the column direction F1 and are arranged along the row direction F2. In addition, the power signal line Vdd is located in the gap between two adjacent sub-pixel columns, and the power signal line Vdd is electrically connected to the driving transistor T1 in the pixel circuit. The detection signal line SL is located in the gap between two adjacent sub-pixel columns, and the detection signal line SL is electrically connected to the sensing transistor T3 in the pixel circuit. Exemplarily, the gap between two adjacent sub-pixel columns where the power signal line Vdd and the detection signal line SL are located is different.

In specific implementation, in the embodiment of the present disclosure, the array substrate has a plurality of transmission signal lines electrically connected to the pixel circuit. Wherein, at least one of the multiple transmission signal lines has a multilayer wiring structure electrically connected to each other. Exemplarily, each transmission signal line may have a multilayer wiring structure electrically connected to each other. This can reduce the resistance of the transmission signal line, reduce the signal delay, and improve the display effect.

In specific implementation, the transmission signal line may include at least one of a plurality of detection signal lines SL and a plurality of power signal lines Vdd. For example, as shown in FIGS. 3 and 4, the transmission signal line may include a plurality of detection signal lines SL. In this way, the detection signal line SL can be composed of signal lines located on at least two different conductive layers, stacked and connected to each other, which is equivalent to that the detection signal line SL is composed of at least two signal lines in parallel. Since the equivalent resistance of the two signal lines of the detection signal line SL in parallel is smaller than the resistance of any one of the signal lines, the resistance of the detection signal line SL can be effectively reduced, thereby reducing the power consumption of the display panel where the array substrate is located. It satisfies the requirements of customers for low power consumption. In addition, adopting the design disclosed in the embodiment of the present disclosure not only reduces the wiring space of the detection signal line SL, but also avoids the problem of photoresist residue caused by increasing the thickness of the detection signal line SL, resulting in poor display.

In specific implementation, as shown in FIGS. 3 and 4, the transmission signal line may also include multiple power signal lines Vdd. In this way, the power signal line Vdd can be composed of at least two different conductive layers, stacked and connected with each other, which is equivalent to that the power signal line Vdd is composed of at least two signal lines in parallel. Since the equivalent resistance of the two signal lines of the power signal line Vdd in parallel is smaller than the resistance of any one of the signal lines, the resistance of the power signal line Vdd can be effectively reduced, thereby reducing the power consumption of the display panel where the array substrate is located. It satisfies the requirements of customers for low power consumption. In addition, adopting the design disclosed in the embodiment of the present disclosure not only reduces the wiring space of the power signal line Vdd, but also avoids the problem of photoresist residue caused by increasing the thickness of the power signal line Vdd and causing poor display.

Exemplarily, one electroluminescent diode and one pixel circuit may be provided in each sub-pixel. Exemplarily, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In this way, red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited here.

In the following, the pixel unit includes red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels as an example. As shown in FIG. 3, the red sub-pixel may include a pixel circuit R, the green sub-pixel may include a pixel circuit G, the blue sub-pixel may include a pixel circuit B, and the white sub-pixel may include a pixel circuit W. Exemplarily, a plurality of pixel circuits (R, G, B, W) may be arranged on the base substrate 10 in an array. It should be noted that the reference signs R, G, B, and W in FIG. 3 indicate the pixel circuit in each sub-pixel, and Vdd indicates the power signal line Vdd electrically connected to the pixel circuit (R, G, B, W) (FIG. 3 Two power signal lines Vdd are taken as an example for description), SL represents the detection signal line SL electrically connected to the pixel circuit (R, G, B, W) (in Figure 3, a detection signal line SL is taken as an example for description) .

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 3 to 5, the array substrate may further include: a light-shielding metal layer on the base substrate 10; and a side of the light-shielding metal layer away from the base substrate 10. The first insulating layer 210; the semiconductor layer 60 on the side of the first insulating layer 210 away from the base substrate 10; the second insulating layer 220 on the side of the semiconductor layer 60 away from the base substrate 10; the second insulating layer 220 away from the liner The gate conductive layer 30 on the side of the base substrate 10; the third insulating layer 230 on the side of the gate conductive layer 30 away from the base substrate 10; the source-drain conductive layer 40 on the side of the third insulating layer 230 away from the base substrate 10. Wherein, the light-shielding metal layer includes a plurality of first connecting wires 110 and a plurality of second connecting wires 120 arranged in an insulated manner. The semiconductor layer 60 includes an active layer having a channel region and a conductive region of the aforementioned transistor. The gate conductive layer 30 includes a plurality of scan lines and the gates of the aforementioned transistors. The source-drain conductive layer 40 includes a plurality of power signal lines Vdd and a plurality of detection signal lines SL, and the source and drain of the above-mentioned transistors. In some embodiments, the multilayer wiring structure may include at least any two layers of the light-shielding metal layer, the gate conductive layer 30, and the source-drain conductive layer 40; and the same multilayer wiring structure may pass through the multilayer wiring The multiple vias of the insulating layer between the structures are electrically connected.

In specific implementation, take each power signal line Vdd as an example. In the embodiment of the present disclosure, as shown in FIGS. 3 to 5, the gate conductive layer 30 may further include a plurality of first auxiliary parts 310, and the first auxiliary parts 310 are insulated from the scan lines; among them, one power signal line Vdd The plurality of first vias 01 are electrically connected to at least one first auxiliary portion 310, and the first via 01 penetrates the third insulating layer 230. The power signal line Vdd and the first auxiliary part 310 electrically connected to each other form a multilayer wiring structure of the power signal line Vdd. It can also be said that the power signal line Vdd and the first auxiliary part 310 that are electrically connected to each other form a double-layer wiring structure. This is equivalent to making each power signal line Vdd be composed of two different conductive layers, stacked and connected to each other.

Exemplarily, as shown in FIG. 3, the first auxiliary part 310 has a gap between the orthographic projection of the base substrate 10 and the orthographic projection of the scan line on the base substrate 10. This can prevent the first auxiliary part 310 from occupying an additional area.

Exemplarily, as shown in FIG. 3, each power signal line Vdd may be electrically connected to a plurality of first auxiliary parts 310 through a plurality of first vias 01. This can further reduce the resistance of the power signal line Vdd.

Exemplarily, as shown in FIGS. 3 to 5, the orthographic projection of the power signal line Vdd on the base substrate 10 may cover the orthographic projection of the electrically connected first auxiliary part 310 on the base substrate 10. Further, the power signal line Vdd may have a gap at the edge of the orthographic projection of the base substrate 10 and the electrically connected first auxiliary portion 310 at the edge of the orthographic projection of the base substrate 10, and the power signal line Vdd may be perpendicular to the power source. The cross section in the extending direction of the signal line Vdd is in the shape of "several". By arranging the power signal line Vdd located in the source-drain conductive layer 40 to have a cross section perpendicular to the extension direction of the power signal line Vdd in the shape of a "several", the slope angle of the source-drain conductive layer 40 can be reduced, and the subsequent formation The passivation layer 90 is not easy to break at the slope angle, causing other film layers in the subsequent process to break, affecting signal transmission and other problems.

In specific implementation, take each detection signal line SL as an example. In the embodiment of the present disclosure, as shown in FIGS. 3 to 5, the gate conductive layer 30 may further include a plurality of second auxiliary parts 320, and the second auxiliary parts 320 are insulated from the scan lines; among them, one detection signal line SL The plurality of second via holes 02 is electrically connected to at least one second auxiliary portion 320, and the second via holes 02 penetrate the third insulating layer 230. In addition, the detection signal line SL and the second auxiliary portion 320 electrically connected to each other form a multilayer wiring structure of the detection signal line SL. It can also be said that the detection signal line SL and the second auxiliary portion 320 electrically connected to each other form a double-layer wiring structure. This is equivalent to making each detection signal line SL consist of signal lines located on two different conductive layers, stacked and connected to each other.

Exemplarily, as shown in FIG. 3, the second auxiliary part 320 has a gap between the orthographic projection of the base substrate 10 and the orthographic projection of the scan line on the base substrate 10. This can prevent the second auxiliary part 320 from occupying an additional area.

Exemplarily, as shown in FIG. 3, each detection signal line SL may be electrically connected to a plurality of second auxiliary parts 320 through a plurality of second via holes 02. This can further reduce the resistance of the detection signal line SL.

Exemplarily, as shown in FIGS. 3 to 5, the orthographic projection of the detection signal line SL on the base substrate 10 may cover the orthographic projection of the electrically connected second auxiliary part 320 on the base substrate 10. Further, the detection signal line SL may have a gap between the edge of the orthographic projection of the base substrate 10 and the electrically connected second auxiliary part 320 on the edge of the orthographic projection of the base substrate 10, and the detection signal line SL may be perpendicular to the detection The cross section in the extending direction of the signal line SL has a "several" shape. By arranging the detection signal line SL located in the source-drain conductive layer 40 to have a cross section perpendicular to the extension direction of the detection signal line SL in a "several" shape, the slope angle of the source-drain conductive layer 40 can be reduced, and the subsequent formation The passivation layer 90 is not easy to break at the slope angle, causing other film layers in the subsequent process to break, affecting signal transmission and other problems.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 3 to 5, the extension direction of the first connection line 110 crosses the extension direction of the power signal line Vdd, and part of the pixel circuit passes through a first connection line. 110 is electrically connected to a power signal line Vdd. Exemplarily, in FIG. 3, two power signal lines Vdd are respectively located on both sides of the pixel circuit R and the pixel circuit B. The pixel circuit R and the pixel circuit B can be electrically connected to the corresponding power signal line Vdd, and the pixel circuit G and the pixel circuit W cannot be directly electrically connected to the corresponding power signal line Vdd, which requires a first connection line 110 electrically connected to the corresponding power signal line Vdd, so that the pixel circuit G and the pixel circuit W pass through the first connection line 110 is electrically connected to the corresponding power signal line Vdd.

Exemplarily, the first connection line 110 may be configured as a single-layer wiring structure. Alternatively, the first connection line 110 may also have a multilayer wiring structure electrically connected to each other to reduce the resistance of the first connection line 110. For example, as shown in FIG. 6a, FIG. 6b, and FIG. 8, the gate conductive layer 30 may further include a plurality of third auxiliary portions 330, and the third auxiliary portions 330 are insulated from the scan line; wherein, one first connection line 110 passes through The plurality of third via holes 03 are electrically connected to at least one third auxiliary portion 330, and the third via holes 03 penetrate the third insulating layer 230. In addition, the first connecting line 110 and the third auxiliary part 330 electrically connected to each other form a multilayer wiring structure of the first connecting line 110. It can also be said that the first connecting line 110 and the third auxiliary part 330 electrically connected to each other form a double-layer wiring structure. This is equivalent to making each first connection line 110 consist of two different conductive layers, stacked and mutually connected signal lines. That is to say, the first connection line 110 is composed of two signal lines and signal lines in parallel. The equivalent resistance of the two signal lines and signal lines of the first connection line 110 in parallel is less than the resistance of any one of the signal lines, so it can be effective Reducing the resistance of the first connecting line 110 can further reduce the power consumption of the display panel where the array substrate is located, and better meet the requirements of customers for low power consumption.

In the specific implementation, in the embodiment of the present disclosure, in conjunction with FIG. 6a, FIG. 6b and FIG. 8, the orthographic projection of the first connection line 110 on the base substrate 10 can cover the third auxiliary part 330 of the electrical connection on the liner. The orthographic projection of the base substrate 10. This can prevent the third auxiliary part 330 from occupying additional area.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 3 to 5, the extension direction of the second connection line 120 crosses the extension direction of the detection signal line SL, and part of the pixel circuit passes through a second connection line. 120 is electrically connected to a detection signal line SL. Exemplarily, in FIG. 3, a detection signal line SL is located between the pixel circuit G and the pixel circuit W, the pixel circuit G and the pixel circuit W may be electrically connected to the detection signal line SL, and the pixel circuit R and the pixel circuit B It cannot be directly electrically connected to the detection signal line SL, which requires a second connection line 120 electrically connected to the detection signal line SL, so that the pixel circuit R and the pixel circuit B are electrically connected to the detection signal line SL through the second connection line 120.

Exemplarily, the second connection line 120 may be configured as a single-layer wiring structure. Alternatively, the second connecting line 120 may also have a multilayer wiring structure electrically connected to each other to reduce the resistance of the second connecting line 120. For example, as shown in FIG. 7a, FIG. 7b, and FIG. 8, the gate conductive layer 30 further includes a plurality of fourth auxiliary portions 340, and the fourth auxiliary portion 340 is insulated from the scan line; wherein, one second connecting line 120 passes through the multiple The fourth via 04 is electrically connected to at least one fourth auxiliary portion 340, and the fourth via 04 penetrates the third insulating layer 230. In addition, the second connecting line 120 and the fourth auxiliary part 340 electrically connected to each other form a multilayer wiring structure of the second connecting line 120. It can also be said that the second connection line 120 and the fourth auxiliary part 340 that are electrically connected to each other form a double-layer wiring structure. This is equivalent to making each second connection line 120 be composed of two different conductive layers, stacked and mutually connected signal lines. That is to say, the second connecting line 120 is composed of two signal lines and signal lines in parallel. The equivalent resistance of the two signal lines and signal lines of the second connecting line 120 in parallel is less than the resistance of any signal line, so it can be effective Reducing the resistance of the second connecting wire 120 can further reduce the power consumption of the display panel where the array substrate is located, and better meet the customer's requirements for low power consumption.

In specific implementation, in the embodiment of the present disclosure, in conjunction with FIG. 7a, FIG. 7b, and FIG. 8, the orthographic projection of the second connection line 120 on the base substrate 10 can cover the fourth auxiliary part 340 of the electrical connection on the backing The orthographic projection of the base substrate 10. This can prevent the fourth auxiliary part 340 from occupying an extra area.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, in order to minimize the power consumption of the display panel on which the array substrate is located, as shown in FIG. 8, each power signal line Vdd, each detection signal line SL, each first connection line 110, and each second connection line 120 may have a multilayer wiring structure. For example, each power signal line Vdd, each detection signal line SL, each first connection line 110, and each second connection line 120 may have the above-mentioned double-layer wiring structure. Since the power signal line Vdd, the first connection line 110, the detection signal line SL, and the second connection line 120 are relatively important signal lines in the array substrate, if the resistance of the four signal lines is large, the power consumption of the display panel will increase. Therefore, the embodiments of the present disclosure reduce the resistance of the four signal lines, so as to minimize the power consumption of the display panel as much as possible.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, the first auxiliary layer may also be located on the light-shielding metal layer, which is not limited herein.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, the second auxiliary layer may also be located on the light-shielding metal layer, which is not limited herein.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, the third auxiliary layer may also be located in the source-drain conductive layer 40, which is not limited herein.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, the fourth auxiliary layer may also be located in the source-drain conductive layer 40, which is not limited herein.

It should be noted that the materials of the light-shielding metal layer, the gate conductive layer 30 and the source-drain conductive layer 40 may be metal materials. For example, gold, silver, copper, aluminum, molybdenum, etc. In actual applications, it can be designed and determined according to actual application requirements, which is not limited here.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, there is an insulating layer between two different conductive layers and stacked signal lines; the stacked signal lines pass through the insulating layer. A plurality of vias arranged in an array are electrically connected. Specifically, as shown in FIGS. 3 and 4, the first connection line 110 may be electrically connected to the power signal line Vdd through a plurality of fifth via holes 05. The second connection line 120 may be electrically connected to the detection signal line SL through a plurality of sixth via holes 06. The fifth via 05 and the sixth via 06 penetrate the first insulating layer 210, the second insulating layer 220, and the third insulating layer 230, respectively. In addition, the first via 01 and the second via 02 respectively penetrate the third insulating layer 230. The third via 03 and the fourth via 04 penetrate the first insulating layer 210 and the second insulating layer 220, respectively.

Specifically, as shown in FIGS. 3 to 8, since the array substrate includes scan lines GA and data lines DA that are arranged crosswise, among the above signal lines, each of the signal lines located in the gate conductive layer 30 is insulated from the scan lines. In the specific manufacturing process, the signal lines that need to be insulated and the signal lines that need to be insulated and the scanning lines can be spaced apart by the patterning process. In the above-mentioned signal lines, the signal lines in the source and drain conductive layer 40 are insulated from the data lines. In the specific manufacturing process, the patterning process can be used to separate the signal lines that need to be insulated and between the signal lines and the data lines that need to be insulated. The patterning process belongs to a technology well-known to those skilled in the art and will not be detailed here. Narrated.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIGS. 3 to 8, the extension directions of the power signal line Vdd and the detection signal line SL are the same, and the power signal line Vdd and the detection signal line SL extend in the same direction. The extending direction of the signal line SL is the same as the extending direction of the data line DA.

Further, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIGS. 3 to 8, the power signal line Vdd and the detection signal line SL are located between different adjacent columns of pixel circuits. This can prevent signal crosstalk between the power signal line Vdd and the detection signal line SL.

Based on the same inventive concept, embodiments of the present disclosure also provide a display panel, including any of the aforementioned array substrates provided by the embodiments of the present disclosure. The problem-solving principle of the display panel is similar to that of the aforementioned array substrate. Therefore, the implementation of the display panel can refer to the implementation of the aforementioned array substrate, and the repetitive parts will not be repeated here.

Based on the same inventive concept, an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure. The principle of solving the problems of the display device is similar to that of the aforementioned array substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetitive points will not be repeated here. The display device can also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

In the array substrate, display panel and display device provided by the embodiments of the present disclosure, the signal lines are arranged in a multilayer wiring structure electrically connected to each other, which is equivalent to making the signal lines consist of at least two signal lines in parallel, which can be arranged as The resistance of the signal line of the multilayer wiring structure is reduced, thereby reducing the power consumption of the display panel where the array substrate is located, which satisfies the customer's low power requirements. In addition, the embodiments of the present disclosure can also reduce the wiring space of the signal line, and can avoid the problem of photoresist residue caused by the increase of the thickness of the signal line, which causes poor display.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

An array substrate, which includes:

Base substrate

A plurality of sub-pixels are arranged in an array on the base substrate, and at least one of the plurality of sub-pixels includes: a pixel circuit;

A plurality of scan lines, the pixel circuits in a row of the sub-pixels are electrically connected to at least one of the scan lines, and the scan lines extend along the row direction of the sub-pixels and are arranged along the column direction of the sub-pixels;

A plurality of transmission signal lines are electrically connected to the pixel circuit, and the plurality of transmission signal lines extend in the column direction and are arranged in the row direction;

Wherein, at least one of the plurality of transmission signal lines has a multilayer wiring structure electrically connected to each other.
5. The array substrate of claim 1, wherein the array substrate further comprises:

A plurality of power signal lines, the power signal lines are located in a gap between two adjacent sub-pixel columns, and the power signal lines are electrically connected to the pixel circuit;

A plurality of detection signal lines, the detection signal line is located in the gap between two adjacent sub-pixel columns, and the detection signal line is insulated from the power signal line, and the detection signal line is electrically connected to the pixel circuit connection;

The transmission signal line includes: at least one of the plurality of detection signal lines and the plurality of power signal lines.
3. The array substrate according to claim 2, wherein the array substrate further comprises a plurality of first connection lines and a plurality of second connection lines; the first connection lines and the second connection lines are insulated; wherein, The extension direction of the first connection line crosses the extension direction of the power signal line, and the extension direction of the second connection line crosses the extension direction of the detection signal line;

Some of the pixel circuits are electrically connected to one of the power signal lines through a first connection line, and some of the pixel circuits are electrically connected to one of the detection signal lines through a second connection line;

At least one of the plurality of first connecting lines and the plurality of second connecting lines has a multilayer wiring structure electrically connected to each other.
5. The array substrate of claim 2 or 3, wherein the array substrate further comprises:

The light-shielding metal layer is located on the base substrate;

The first insulating layer is located on the side of the light-shielding metal layer away from the base substrate;

A semiconductor layer located on the side of the first insulating layer away from the base substrate;

A second insulating layer located on the side of the semiconductor layer away from the base substrate;

A gate conductive layer located on a side of the second insulating layer away from the base substrate, and the gate conductive layer includes the plurality of scan lines;

A third insulating layer located on the side of the gate conductive layer away from the base substrate;

The source-drain conductive layer is located on the side of the third insulating layer away from the base substrate, and the source-drain conductive layer includes the plurality of power signal lines and the plurality of detection signal lines;

The multilayer wiring structure includes at least any two layers of the light-shielding conductive layer, the gate conductive layer, and the source-drain conductive layer; and the same multilayer wiring structure passes through the multilayer wiring structure. The multiple via holes of the insulating layer between the wire structures are electrically connected.
The array substrate of claim 4, wherein the gate conductive layer further comprises a plurality of first auxiliary parts, and the first auxiliary parts are insulated from the scan line; wherein one of the power signal lines passes through A plurality of first via holes are electrically connected to at least one of the first auxiliary portions, and the first via holes penetrate the third insulating layer;

The power signal line and the first auxiliary part that are electrically connected to each other form a multilayer wiring structure of the power signal line.
5. The array substrate of claim 5, wherein the orthographic projection of the power signal line on the base substrate covers the orthographic projection of the first auxiliary portion of the electrical connection on the base substrate.
7. The array substrate according to claim 6, wherein the power signal line has a gap at the edge of the orthographic projection of the base substrate and the first auxiliary part electrically connected to the edge of the orthographic projection of the base substrate, And the cross section of the power signal line perpendicular to the extension direction of the power signal line is in the shape of a "several".
7. The array substrate according to any one of claims 4-7, wherein the gate conductive layer further comprises a plurality of second auxiliary parts, and the second auxiliary parts are insulated from the scan line; The detection signal line is electrically connected to at least one of the second auxiliary parts through a plurality of second via holes, and the second via hole penetrates the third insulating layer;

The detection signal line and the second auxiliary part electrically connected to each other form a multilayer wiring structure of the detection signal line.
8. The array substrate according to claim 8, wherein the orthographic projection of the detection signal line on the base substrate covers the orthographic projection of the second auxiliary part of the electrical connection on the base substrate.
9. The array substrate according to claim 9, wherein the detection signal line has a gap at the edge of the orthographic projection of the base substrate and the second auxiliary part electrically connected to the edge of the orthographic projection of the base substrate, In addition, the cross section of the detection signal line perpendicular to the extension direction of the detection signal line is in the shape of a "several".
7. The array substrate according to any one of claims 4-10, wherein the gate conductive layer further comprises a plurality of third auxiliary parts, and the third auxiliary parts are insulated from the scan line; The first connection line is electrically connected to at least one of the third auxiliary parts through a plurality of third via holes, and the third via hole penetrates the third insulating layer;

The first connection line and the third auxiliary part electrically connected to each other form a multilayer wiring structure of the first connection line.
11. The array substrate according to claim 11, wherein the orthographic projection of the first connection line on the base substrate covers the orthographic projection of the third auxiliary part of the electrical connection on the base substrate.
The array substrate according to any one of claims 4-12, wherein the gate conductive layer further comprises a plurality of fourth auxiliary parts, and the fourth auxiliary parts are insulated from the scan line; The second connection line is electrically connected to at least one of the fourth auxiliary parts through a plurality of fourth via holes, and the fourth via hole penetrates the third insulating layer;

The second connecting line and the fourth auxiliary part electrically connected to each other form a multilayer wiring structure of the second connecting line.
13. The array substrate of claim 13, wherein the orthographic projection of the second connecting line on the base substrate covers the orthographic projection of the fourth auxiliary part of the electrical connection on the base substrate.
14. The array substrate according to any one of claims 2-14, wherein the gap between two adjacent sub-pixel columns where the power signal line and the detection signal line are located is different.
A display panel, which comprises the array substrate according to any one of claims 1-15.
A display device comprising the display panel according to claim 16.