WO2020224386A1

WO2020224386A1 - Data decoding method and apparatus

Info

Publication number: WO2020224386A1
Application number: PCT/CN2020/084420
Authority: WO
Inventors: 郑晨; 唐成君; 马亮; 魏岳军
Original assignee: 华为技术有限公司
Priority date: 2019-05-08
Filing date: 2020-04-13
Publication date: 2020-11-12
Also published as: CN111917419B; CN111917419A

Abstract

Provided are a data decoding method and apparatus, wherein same are used for lowering the decoding complexity, shortening a decoding delay and improving the decoding accuracy by means of performing disturbance processing on an LLR sequence. The method comprises: acquiring a first log-likelihood ratio (LLR) sequence corresponding to transmitted data; performing disturbance processing on one or more LLRs in the first LLR sequence to obtain one or more groups of second LLR sequences; and decoding the one or more groups of second LLR sequences to obtain first decoded data that has been successfully checked.

Description

Method and device for data decoding

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 08, 2019, with the application number 201910381356.7 and the application name "A method and device for data decoding", the entire content of which is incorporated herein by reference Applying.

Technical field

This application relates to the field of communications, and in particular to a method and device for data decoding.

Background technique

In various communication systems, when transmitting data between a sending device and a receiving device, it is usually necessary to encode the sending data. Low density parity check code (LDPC) is a linear block code, which can be uniquely determined by the check matrix or the Tanner graph corresponding to the check matrix. LDPC codes can be used for coding in communication systems. For example, in the fifth-generation mobile communication technology (5th-Generation, 5G) system, LDPC codes can be used to encode data.

Therefore, after receiving the transmitted data, the receiving device needs to perform LDPC decoding on the data. In the existing scheme, after the previous confidence propagation (BP) algorithm fails to decode, the variable nodes (VN) that do not satisfy the check equation are determined to form a VN set, and then the VN set Select a part of the VN, saturate the value of the log-likelihood ratio (LLR) of the original channel corresponding to the part of the VN, and saturate to the maximum positive and negative maximum, and then saturate the LLR to generate The sequence is input to the decoder for decoding, and the above steps are repeated until the preset condition is met, that is, a legal codeword is output. And determine a group from the output legal code words as the final decoded data.

However, in the existing solution, the decoding process is a serial process, that is, after the previous decoding is completed, the next level of decoding process is performed, and each level of decoding needs to perform the next level of VN The choice is more complicated and the delay is longer.

Summary of the invention

This application provides a method and device for data decoding, which are used to reduce decoding complexity, reduce decoding delay, and improve decoding accuracy by perturbing LLR sequences.

In view of this, the first aspect of the present application provides a data decoding method, including:

Obtain the transmission data; determine the first log-likelihood ratio LLR sequence according to the transmission data; perform perturbation processing on one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences; Group the second LLR sequence to decode to obtain the first decoded data. In the embodiment of the present application, one or more first LLRs in the first LLR sequence are disturbed to obtain one or more sets of second LLR sequences, and then the one or more sets of second LLR sequences are translated Code to obtain the first decoded data. Therefore, by perturbing one or more LLRs in the first LLR sequence, a new LLR sequence, that is, the second LLR sequence, can be obtained, and then the new LLR sequence is used for decoding, which improves the decoding success. The accuracy of the code data. And for the obtained multiple sets of new second LLR sequences, parallel decoding can be realized, and the complexity and time delay of LDPC decoding can be reduced, and the decoding efficiency can be improved.

Optionally, in some possible implementation manners, decoding one or more sets of second LLR sequences to obtain first decoded data may include:

Perform LDPC iterative decoding on a group of second LLR sequences; if the decoded data of a group of second LLR sequences is successfully checked, then the decoded data of the second LLR sequence is used as the first decoded data. In the embodiment of the present application, the second LLR sequence can be decoded iteratively by LDPC. If the decoded data obtained by the LDPC iterative decoding of a group of second LLR sequences is successfully checked, the second LLR sequence can be The decoded data serves as the first decoded data. Therefore, the second LLR sequence obtained after perturbing the first LLR sequence can be used to perform LDPC iterative decoding to obtain decoded data with successful verification.

Perform LDPC iterative decoding on each group of second LLR sequences in one or more groups of second LLR sequences to obtain one or more groups of successfully verified decoded data; according to preset rules, check from one or more groups A group of decoded data is determined as the first decoded data from the decoded data that is successfully verified.

In the embodiment of the present application, LDPC iterative decoding can be performed on each group of second LLR sequences in one or more groups of second LLR sequences to obtain one or more groups of successfully verified decoded data, and then according to preset The rule determines a set of decoded data as the first decoded data from one or more sets of decoded data successfully verified. When there is only one group of successfully decoded decoded data, this group of decoded data is regarded as the first decoded data. When there are multiple groups of successfully decoded decoded data, the decoded data can be decoded from the multiple groups according to preset rules. One group of code data is selected as the first decoded data, and therefore, successfully decoded decoded data can be obtained.

Optionally, in some possible implementation manners, determining a set of decoded data from one or more sets of successfully verified decoded data as the first decoded data according to a preset rule may include:

A group of decoded data whose Euclidean metric between the first LLR sequence and the first LLR sequence is less than or equal to a threshold is determined from one or more sets of decoded data successfully verified as the first decoded data. In the embodiment of the present application, after one or more sets of decoded data with successful verification are determined, it can be determined from the one or more sets of decoded data that the Euclidean metric with the first LLR sequence is less than A group of decoded data equal to or equal to the threshold is used as the first decoded data. By filtering the one or more sets of decoded data through the Euclidean metric, more accurate decoded data can be obtained.

Optionally, in some possible implementation manners, performing LDPC iterative decoding on a group of second LLR sequences may include:

Perform N iterative decoding on a set of second LLR sequences, and update the information R _ij [k] transmitted by the i-th check node to the j-th variable node in the k-th LDPC iterative decoding among them, and pass The second LLR sequence updates the information Q _ji [k] transmitted by the j-th variable node to the i-th check node, 1≤k≤N, and N is less than or equal to the preset number of iterations; among them, a group of the second LLR sequence The decoded data of the k-th iterative decoding includes R _ij [k] and Q _ji [k].

In the embodiment of the present application, in each iteration of decoding, variable nodes and check nodes can be alternately updated to complete the decoding of the second LLR sequence to obtain accurate decoded data.

Optionally, in some possible implementation manners, updating the information R _ij [k] transmitted by the i-th check node to the j-th variable node may include:

Update the information R _ij [k] transmitted from the i-th check node to the j-th variable node through at least one preset correction value. In the embodiment of the present application, the information transmitted from the i-th check node to the j-th variable node can be updated by the correction value, and the correction value can be used to improve the decoding performance, compensate for calculation errors, and improve the accuracy of decoding.

Optionally, in some possible implementation manners, updating the information Q _ji [k] transmitted from the j-th variable node to the i-th check node through the second LLR sequence may include:

The information Q _ji [k] transmitted from the j-th variable node to the i-th check node is updated by the preset weight value and the second LLR sequence.

In the embodiment of this application, the information transmitted from the j-th variable node to the i-th check node can be updated by the weighted value and the second LLR sequence, so as to improve the accuracy of the obtained Q _ji [k], and increase the Q _ji [k ] Effectiveness.

Optionally, in some possible implementation manners, updating the information Q _ji [k] transmitted by the j-th variable node to the i-th check node by the preset weight value and the second LLR sequence may include:

If the sign of Q _ji [k] obtained by the k-th iterative decoding is different from the sign of Q _ji [k-1] obtained by the k- _1th iterative decoding, then Q _ji [k]=ω*Q _ji [ k]+(1-ω)*Q _ji [k-1], ω is a weighted value.

In the embodiment of the present application, it is provided that the Q _ji [k] of this iterative decoding is updated through the result of the previous iterative decoding during iterative decoding, which can be the decoding between multiple iterative decodings. The results are combined to improve the accuracy of decoding.

Optionally, in some possible implementation manners, before perturbing one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences, the method may further include:

LDPC decoding of the first LLR sequence fails.

In the embodiment of the present application, after the LDPC decoding of the first LLR sequence fails, the first LLR sequence is disturbed, and then the decoding is performed based on the second LLR sequence obtained after the disturbing processing. Therefore, even after the first LLR sequence fails to be decoded for the first time, one or more sets of second LLR sequences can be used for decoding to obtain the first decoded data that is successfully verified, which can improve the successful verification. The accuracy of the decoded data.

A second aspect of the present application provides a decoding device, which has the function of implementing the method for data decoding in the first aspect. This function can be realized by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

A third aspect of the embodiments of the present application provides a decoding device, which may include:

A processor, a memory, and an input-output interface, the processor, the memory are connected to the input-output interface; the memory is used to store program code; the processor executes the first aspect or the first aspect of the application when calling the program code in the memory On the one hand, the steps of the method provided by any embodiment.

A fourth aspect of the embodiments of the present application provides a terminal, which may include:

A fifth aspect of the embodiments of the present application provides a base station, which may include:

The sixth aspect of the embodiments of the present application provides a decoding device, which can be applied to equipment such as a terminal or a base station. The decoding device is coupled with a memory, and is used to read and execute instructions stored in the memory, so that The decoding device implements the steps of the method provided in the first aspect or any one of the first aspect of the application. In one possible design, the decoding device is a chip or a system on a chip.

A seventh aspect of the present application provides a chip system including a processor, which is used to support a base station or a terminal to implement the functions involved in the above aspects, for example, for processing data and/or information involved in the above methods. In a possible design, the chip system further includes a memory, and the memory is used to store necessary program instructions and data for the base station or terminal. The chip system may be composed of chips, or may include chips and other discrete devices.

Among them, the processor mentioned in any of the above can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more for controlling the above The first aspect of the data search method is an integrated circuit for program execution.

The eighth aspect of the embodiments of the present application provides a storage medium. It should be noted that the technical solution of the present invention is essentially or a part that contributes to the existing technology, or all or part of the technical solution can be produced by software. In the form of manifestation, the computer software product is stored in a storage medium for storing computer software instructions used by the above-mentioned equipment, which includes a decoding device for executing any optional implementation of the above-mentioned first aspect, such as a base station Or the program designed by the terminal.

The storage medium includes: U disk, mobile hard disk, read-only memory (English abbreviation ROM, English full name: Read-Only Memory), random access memory (English abbreviation: RAM, English full name: Random Access Memory), magnetic disk or CD Various media that can store program codes.

The ninth aspect of the embodiments of the present application provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the method described in any optional implementation manner of the first aspect of the present application.

A tenth aspect of the embodiments of the present application provides a communication system, which may include a terminal and a base station;

The terminal may be the terminal provided in the fourth aspect of the embodiments of the present application;

The base station may be the base station provided in the fifth aspect of the embodiments of the present application.

In the embodiment of the present application, one or more first LLRs in the first LLR sequence are disturbed to obtain one or more sets of second LLR sequences, and then the one or more sets of second LLR sequences are translated Code to obtain the first decoded data. Therefore, by perturbing one or more LLRs in the first LLR sequence, a new LLR sequence, that is, the second LLR sequence, can be obtained, and then the new LLR sequence is used for decoding, which improves the decoding success. The accuracy of the code data. And for the obtained one or more sets of new LLR sequences, parallel decoding can be realized, and the complexity and time delay of LDPC decoding can be reduced, and the decoding efficiency can be improved.

Description of the drawings

FIG. 1a is an application scenario of the data decoding method provided by an embodiment of this application;

FIG. 1b is another application scenario of the data decoding method provided by the embodiment of this application;

2 is a schematic diagram of an embodiment of a data decoding method provided by an embodiment of this application;

3 is a schematic diagram of another embodiment of a data decoding method provided by an embodiment of this application;

4 is a schematic diagram of a check matrix and a check equation of an LDPC code provided by an embodiment of the application;

FIG. 5 is a Tanner graph corresponding to a check matrix H provided by an embodiment of the application;

FIG. 6a is a schematic diagram of a base map matrix provided by an embodiment of this application;

FIG. 6b is a schematic diagram of another base map matrix provided by an embodiment of the application;

FIG. 7 is a schematic diagram of an offset matrix provided by an embodiment of the application;

FIG. 8 is a schematic diagram of a permutation matrix provided by an embodiment of this application;

FIG. 9 is a schematic diagram of the application range of two base image matrices provided by an embodiment of this application;

FIG. 10a is a schematic diagram of updating variable nodes according to an embodiment of the application;

FIG. 10b is a schematic diagram of updating a check node according to an embodiment of the application;

FIG. 11 is a schematic diagram of alternately updating variable nodes and check nodes according to an embodiment of the application;

FIG. 12 is a schematic diagram of a simulation result provided by an embodiment of this application;

FIG. 13 is a schematic diagram of another simulation result provided by an embodiment of the application;

FIG. 14 is a schematic structural diagram of a decoding device provided by an embodiment of this application;

15 is a schematic diagram of another structure of a decoding device provided by an embodiment of this application;

FIG. 16 is a schematic structural diagram of a base station provided by an embodiment of this application;

FIG. 17 is a schematic diagram of another structure of a terminal provided by an embodiment of the application.

Detailed ways

The data decoding method provided in this application can be applied to various communication systems or communication networks, for example, 5G systems, Long Term Evolution (LTE) systems, Global System for Mobile Communication (GSM) or Code Division Multiple Access (CDMA) network, Wideband Code Division Multiple Access (WCDMA) network, etc., can also be Worldwide Interoperability for Microwave Access (WiMAX) or wireless Other communication networks or communication systems that require data decoding, such as Wireless Fidelity (WiFI).

Exemplarily, the specific application scenario of the embodiment of the present application may be as shown in Fig. 1a or Fig. 1b. Among them, the LDPC code can be applied to the communication coding between the base station and the terminal. Specifically, the application scenario may include one or more base stations and one or more terminals. As shown in Figure 1a, a base station can access multiple terminals (for example, terminal 1 and terminal 2 in Figure 1a), that is, a base station can communicate with multiple terminals, and the base station can send encoded Data, the base station can also receive encoded data sent by the terminal. As shown in Figure 1b, a terminal can also communicate with multiple base stations (base station 1, base station 2, and base station 3 in Figure 1b). It can be that the terminal receives encoded data sent by multiple base stations, and the terminal can communicate to multiple base stations. Each base station sends the encoded data.

Therefore, the data decoding method provided by the embodiments of the present application can also be executed by various decoding devices. The decoding device can include a base station, a terminal, etc., or the decoding device can be included in a base station, a terminal, etc. Wait for the device. The base station may be various forms of macro base stations, micro base stations (also called small stations), relay stations, access points, and so on. In different communication systems, the name of the base station may also be different. For example, the base station may be a base transceiver station (BTS) in a GSM or CDMA network, an NB (NodeB) in WCDMA, or an LTE system. The long-term evolution node (Evolutional NodeB, eNB, or eNodeB) in the network may also be the base station equipment in the 5G network or the communication device in the future evolved Public Land Mobile Network (PLMN) network, for example, the 5G base station ( Next generation NodeB, gNB). The terminal may be a variety of handheld devices including communication functions, wearable devices, computing devices, or other processing devices connected to a wireless modem, and so on. For example, it can be a mobile station (Mobile Station, MS), subscriber unit (subscriber unit), cellular phone (cellular phone), smart phone (smart phone), wireless data card, personal digital assistant (Personal Digital Assistant, PDA for short) Computer, tablet computer, wireless modem (modem), handheld device (handset), laptop computer (laptop computer), machine type communication (Machine Type Communication, MTC) terminal, etc.

It should be understood that the data decoding method provided in the embodiments of this application can be executed by the above-mentioned various independent decoding devices, or the decoding devices in the base station or terminal equipment, etc. The following is based on the decoding devices provided in the embodiments of this application The specific process of the data decoding method will be described in detail.

The specific process of the data decoding method provided in this application may be as shown in Fig. 2 and may include:

201. Acquire a first log-likelihood ratio LLR sequence corresponding to the transmission data.

Generally, the decoding device can receive a signal sent by another network device. For example, when the decoding device that receives the signal is a base station, another network device that sends a signal can be a terminal. When the decoding device that receives a signal is a terminal, the other signal-sending device can be a terminal or a base station, etc. .

The network device that sends the signal performs LDPC encoding on the data to be transmitted to obtain the transmission data, and sends its corresponding signal after modulation and mapping. The transmission data can consist of information bits and check data. For example, if the transmission data is an n-bit sequence Data, the transmission data may include k bits of information bits and (nk) bits of check data, k<n.

After receiving the signal, the decoding device receiving the signal obtains the first LLR sequence corresponding to the transmission data after demodulation.

For example, the received signal may be demodulated, synchronized, etc., to obtain the first LLR sequence. Each LLR in the first LLR sequence corresponds to each bit in the transmission data one-to-one. Each LLR can be expressed as

p(1) represents the probability that the corresponding bit is judged as 1, and p(0) represents the probability that the corresponding bit is judged as 0.

202. Perform perturbation processing on one or more first LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences.

After the first LLR sequence corresponding to the transmission data is determined, perturbation processing is performed on one or more first LLRs in the first LLR sequence.

Optionally, in some possible implementation manners, performing perturbation processing on one or more first LLRs in the first LLR sequence may be adding one or more perturbation values to the one or more first LLRs. , That is, add at least one perturbation value to at least one first LLR to obtain one or more sets of second LLR sequences. It should be understood that in the embodiments of the present application, multiple groups are two or more than two, and multiple groups are two or more than two groups.

Optionally, in some possible implementation manners, perturbation processing is performed on one or more first LLRs in the first LLR sequence, or the one or more first LLRs are respectively multiplied by one or more perturbations Value to get one or more sets of second LLR sequences.

Of course, in addition to the above adding or multiplying one or more disturbance values, other methods can also be used, for example, subtracting one or more disturbance values, dividing by one or more disturbance values, etc. to LLR And the perturbation value is the algebraic operation performed by the parameter, which can be specifically adjusted according to actual application scenarios, for example, it can be one or more of addition, subtraction, multiplication, or division, etc. The present application deals with the perturbation processing of the first LLR sequence The method is not limited.

Among them, the disturbance value can be a preset value, or a value obtained by learning based on historical data, and so on.

For example, the disturbance processing may be to add the same disturbance value to each of the one or more first LLRs, including adding the same one or more disturbance values to each first LLR to obtain a set of Or multiple sets of second LLR sequences. For example, you can add a perturbation value to each first LLR for the first time to obtain a set of second LLR sequences, and then continue to add an AND to each first LLR for the second time. The first different disturbance values obtain two sets of second LLR sequences, and so on; it is also possible to add different disturbance values to each first LLR to obtain one or more sets of second LLR sequences.

And, optionally, in a possible implementation manner, after the first LDPC decoding of the first LLR sequence fails, add one or more first LLRs in the first LLR sequence One or more disturbance values are used to obtain one or more sets of second LLR sequences, and then the transmission data is subjected to a second LDPC decoding based on the one or more sets of second LLR sequences.

203. Decode one or more sets of second LLR sequences to obtain first decoded data.

After one or more sets of second LLR sequences are obtained, the one or more sets of second LLR sequences are decoded to obtain corresponding first decoded data.

Specifically, the decoding method for decoding the second LLR sequence may include multiple, for example, it may be based on the minimum sum (Min-Sum, MS) decoding of one or more sets of the second LLR sequence, and layered translation. Codes, Maximum Likelihood (ML) decoding, etc., can be specifically adjusted according to actual application scenarios and are not limited here.

Moreover, when decoding one or more sets of second LLR sequences, all second LLR sequences in the one or more sets of second LLR sequences may be decoded in parallel, or the set of second LLR sequences may be decoded in parallel. Or all the second LLR sequences in the multiple sets of second LLR sequences are serially decoded, which can be specifically adjusted according to actual application scenarios, which is not limited here.

In addition, when performing LDPC decoding, it is also necessary to determine the decoding result to determine the decoded data successfully decoded. Specifically, the verification may be performed through LDPC self-checking, or may be performed through cyclic redundancy check (cyclic redundancy check, CRC), etc. The specific may be adjusted according to actual application scenarios, which is not limited here.

In the embodiment of the present application, one or more LLRs in the first LLR sequence are disturbed to obtain one or more sets of second LLR sequences, and then according to the one or more sets of second LLR sequences, The LLR sequence is decoded to obtain the first decoded data. Therefore, by adding disturbance values to one or more LLRs in the first LLR sequence, a new LLR sequence can be obtained, and then the new LLR sequence is used for decoding, and the next step is to select the variable node that does not satisfy the check equation The embodiment of the application can directly decode the second LLR sequence obtained after the disturbance processing. Compared with selecting variable nodes, the embodiment of the application can reduce the complexity. And after one or more sets of second LLR sequences are obtained, the decoding can be performed directly based on the one or more sets of second LLR sequences, which can realize parallel decoding, and can improve the efficiency of decoding compared with serial decoding. Reduce decoding delay. In addition, multiple sets of second LLR sequences can be decoded, and multiple sets of decoded data can be subsequently obtained, which can improve the accuracy of successfully decoded decoded data.

The foregoing describes the flow of the data decoding method provided by this application. Among them, there are many ways to decode the second LLR sequence in the embodiment of this application, which can be ML decoding or LDPC iterative decoding, etc., examples In terms of nature, the following uses LDPC iterative decoding as an example to describe the data decoding method provided in this application in more detail. Please refer to FIG. 3, which is a schematic diagram of another flow of a data decoding method provided by an embodiment of the present application, which may include:

301. Acquire a first LLR sequence corresponding to transmission data.

Generally, the decoding device can receive a signal sent by another network device. The network device that sends the signal may be the aforementioned base station, terminal, etc. For example, the base station may send a signal to the terminal or the terminal may send a signal to the base station.

The signal sending device can obtain the transmission data after encoding the data to be transmitted, and send the corresponding signal after modulation and mapping.

After receiving the signal, the decoding device obtains the first LLR sequence corresponding to the transmission data after demodulation.

The transmission data can be composed of information bits and check data. The information bits are information to be transmitted, and the check data is data obtained by calculating the information bits to be transmitted through a preset encoding method. For example, if the transmission data is data of an n-bit sequence, the transmission data may include k bits of information bits and (n-k) bits of check data, k<n. The specific encoding method used by the network device that sends the signal to encode the information bits may be LDPC encoding, CRC encoding, turbo encoding, and so on. Correspondingly, the decoding method of the transmission data by the decoding device corresponds to the encoding method. For example, the decoding method may be a decoding method for LDPC encoding, a decoding method for CRC encoding, or a decoding method for turbo encoding, etc. The embodiments of the present application only illustrate LDPC decoding. The decoding method used can be adjusted according to actual application scenarios, which is not limited in this application. Generally, the transmission data can be represented by a matrix, and therefore, the corresponding first LLR sequence can also be represented by a matrix.

Exemplarily, an LDPC code can be understood as a (n, k) linear block code, and its check matrix is a sparse matrix, the code length is n, the information sequence length is k, and can be uniquely determined by its check matrix H, It can also be uniquely determined by the Tanner graph corresponding to the check matrix H. Exemplarily, the check matrix H of the LDPC code and the corresponding check equation are shown in FIG. 4. The representation of the Tanner graph corresponding to the check matrix H is shown in FIG. 5. Among them, each circular node is represented as a variable node, representing a column in the H matrix of the check matrix, and each square node is a check node, representing a row in the H matrix, each of which connects the check node and the variable node in Figure 5 The line represents that there is a non-zero element at the intersection of the row and column corresponding to the two nodes.

Generally, LDPC codes can be used for encoding in communication systems. For example, in 5G communication systems, LDPC codes can be used to encode data to obtain transmission data. The LDPC code can usually be represented by a parity check matrix H, and the parity check matrix H can usually be obtained from a base graph and an offset value. A base image can usually include m*n matrix elements, which can be represented in the form of a matrix with m rows and n columns. The matrix elements have a value of 0 or 1, and an element with a value of 0 can also be called a zero element. A zero element can mean that the element can be replaced by a z*z all-zero matrix, and an element with a value of 1 can also be called a non-zero element. A non-zero element can also mean that the element can be replaced by a z*z circulant permutation matrix. Therefore, each matrix element can be replaced with an all-zero matrix or a cyclic permutation matrix.

Exemplarily, as shown in FIG. 6a and FIG. 6b, they are respectively different base image matrices. As shown in Fig. 6a, the base image matrix has 46 rows and 68 columns, and as shown in Fig. 6b, the base image matrix has 42 rows and 52 columns. In the base image matrix shown in Figure 6a and Figure 6b, the row number is marked in the leftmost column, and the column number is marked in the top row. Each row and column only shows non-zero elements, which are represented by "1", and the blank parts are zero elements. . Among them, the 0th column and the 1st column are two built-in punctured columns, which do not participate in bit selection during the rate matching process, that is, they do not enter the circular buffer.

Exemplarily, FIG. 7 is an example of an offset value matrix based on the aforementioned FIG. 6a. If the value of the element in the i-th row and the j-th column of the base image matrix is 1, its offset value is P _i,j , P _{i, j} is an integer greater than or equal to 0, which means that the element in the i-th row and j-th column of the base image matrix with a value of 1 can be replaced by the z*z circulant matrix corresponding to _Pi,j . The circulant matrix can be replaced by z The identity matrix of *z is obtained by cyclically shifting P _{i,j to} the right. It can be seen that each element with a value of 0 in the base image matrix of Figure 6a is replaced with a z*z all-zero matrix, and each element with a value of 1 is passed through the corresponding P _i,j with a z*z identity matrix The check matrix H of the LDPC code can be obtained by cyclic shifting to the right one time. Among them, z is a positive integer, z may also be called an expansion factor, and the value of z may be specifically determined according to the size of the code block supported by the communication system and the size of the information data. The size of the parity check matrix H is (m*z)*(n*z).

For example, if z=4, the permutation matrix corresponding to each element value of the base image matrix can be shown in Fig. 8, where, from left to right in Fig. 8 are z*z matrices with an offset value of 1; The z*z matrix with the offset value of 0, that is, the identity matrix; the z*z matrix with the offset value of 1, that is, the matrix offset by 1 to the right; the z*z matrix with the offset value of 2, that is offset to the right A matrix of 2; a z*z matrix with an offset of 3, that is, a matrix with an offset of 3 to the right. Exemplarily, when the element value in the base image matrix is greater than the preset expansion factor, it is necessary to perform a modulo operation on the element value, specifically: Pi _,j =mod(V _i,j ,Z _C ), where , Vi _,j is the corresponding element value in the base image matrix, Z _C is the actual expansion factor, P _i,j is the actual offset value, mod(x,y) is the modulo operation, and returns the remainder of x divided by y Then, calculate the actual cyclic displacement value P _i,j according to the formula, and then expand the cyclic displacement to obtain the offset z*z matrix.

Generally, the LDPC code in 5G can be implemented in a quasi-cyclic structure. For example, based on the two base picture matrices provided in the aforementioned Figure 6a and Figure 6b, two LDPC encoding methods can be supported. The specific application can be shown in Fig. 9, wherein the base picture matrix shown in Fig. 6a is called BG1, and the base picture matrix shown in Fig. 6b is called BG2. The base picture matrix used can be determined according to the encoded data. Specifically, different base picture matrices can be selected for encoding according to the length and code rate of different transmission blocks. For example, as shown in Figure 9, when the size of the transport block to be transmitted is less than or equal to 308, or the size of the transport block to be transmitted is less than or equal to 3840 and the encoding rate is less than or equal to 2/3, or the encoding rate is less than 1/4, That is, BG2 is used for encoding; if the size of the transmission block to be transmitted is greater than 308 and the coding rate is greater than 2/3, or the size of the transmission block to be transmitted is greater than 3840 and the encoding rate is greater than 1/4, then BG1 is used for encoding. After encoding, check data can be obtained. For example, if the transmission data is data of an n-bit sequence, the transmission data may include k bits of information bits, that is, k bits of data to be transmitted, and (n-k) bits of check data, k<n.

302. Perform LDPC decoding on the first LLR sequence. If the decoding is successful, perform step 305, and if the decoding fails, perform step 303.

After the transmission data is obtained, the first LDPC decoding can be performed on the first LLR sequence. Specific decoding methods can include minimum sum MS decoding, hierarchical decoding, etc. to obtain a set of decoded data. The decoded data can be verified. If the verification result is that the decoding is successful, step 305 can be executed, that is, other steps can be executed. If the verification result is that the decoding fails, step 303 may be executed, that is, the LDPC decoding is continued.

The specific check method for the group of decoded data may be LDPC self-check, CRC check, etc., which can be adjusted according to actual application scenarios.

Exemplarily, the LDPC self-check may be to determine whether the decoded data meets the check relationship of the LDPC code. For example, the preset check matrix of the LDPC code is H, and c is a sequence of LDPC code words containing information bits and check bits, that is, decoded data. The check relation H*c ^T =0, that is, the result of multiplying the decoded data and the check matrix is 0, then the check result can be determined to be a successful decoding, if the result of multiplying the decoded data and the check matrix is not If it is 0, it can be determined that the verification result is a decoding failure. In addition, if the transmission data has also undergone CRC processing, c may also include CRC check bits.

Exemplarily, the CRC check may be to determine whether the decoded data meets the CRC check relationship, and the check relationship may be H _CRC *c _CRC ^T =0, where H _CRC is the preset CRC check matrix, c _CRC That is, it contains a sequence of information bits and CRC check bits. If the decoded data satisfies the check relationship, it can be determined that the decoded result is successful, and if the decoded data does not satisfy the check relationship, it can be determined that the decoded result has failed.

303. Perform perturbation processing on one or more first LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences.

After the first LLR sequence is obtained, one or more perturbations can be added to one or more first LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences; or, for the first LLR sequence One or more first LLRs in is multiplied by one or more disturbance values to obtain one or more sets of second LLR sequences.

Optionally, in some possible implementations, the disturbance value may be a preset set of values, or a set of values generated randomly, and the added disturbance value may be a preset position in the first LLR sequence, or It is a randomly determined location. In addition, each group of second LLR sequences can be one-to-one corresponding to a group of LDPC iterative decoding. It can be understood that when there are multiple sets of second LLR sequences, LDPC iterative decoding needs to be performed on each set of second LLR sequences. Exemplarily, when performing perturbation processing on the first LLR sequence, different perturbation values can be added to the same position in the first LLR sequence, or the same perturbation can be added to different positions in the first LLR sequence. value. Of course, it is also possible to add different disturbance values to different positions of the first LLR sequence. For example, after obtaining the first LLR sequence, let LLR _i = LLR _i + n _i , where n _i is the disturbance value, and i is the position corresponding to the disturbance value. You can add a n _i to the position of the same _i , Obtain a set of second LLR sequences, or add multiple n _{i to the} same i position to obtain multiple sets of second LLR sequences, or add multiple n _{i to} different i positions to obtain multiple sets of Two LLR sequence.

For example, after the first LLR sequence is obtained, one or more disturbance values are used to form m groups of disturbance value groups. Each group of disturbance values may include the same or different disturbance values, and each group of disturbance values in the m groups of disturbance values may correspond to LLRs at the same or different positions. Then, the first LLR sequence is disturbed by the m groups of disturbance value groups to obtain m groups of second LLR sequences. And each group of second LLR sequences in the m groups of second LLR sequences is different. For example, the first set of second LLR sequences may be obtained by adding the first set of disturbance value sets to the first LLR sequence, and the second set of second LLR sequences may be obtained after adding the second set of disturbance value sets to the first LLR sequence Obtained, the position of the LLR corresponding to each perturbation value in the first perturbation value group and each perturbation value in the second perturbation value group may be the same or different, the first perturbation value group and the second perturbation value group The group may include equal or unequal disturbance values. The first group of disturbance values and the second group of disturbance values are not completely equal, and can be adjusted according to actual application scenarios, which is not limited in this application.

304. Perform LDPC decoding on one or more sets of second LLR sequences to obtain first decoded data.

After one or more sets of second LLR sequences are obtained, LDPC iterative decoding may be performed on the one or more sets of second LLR sequences to obtain successfully decoded first decoded data. When performing LDPC iterative decoding, the maximum number of iterations may be a preset number of iterations.

Optionally, when there are multiple sets of second LLR sequences, the decoding method for the multiple sets of second LLR sequences can be parallel decoding or serial decoding, which can be adjusted according to actual application scenarios. The application is not limited. For example, in order to improve decoding efficiency, parallel decoding may be used for the multiple sets of second LLR sequences.

Optionally, in a possible implementation manner, LDPC iterative decoding may be performed respectively based on each group of second LLR sequences in the one or more groups of second LLR sequences, and each group of second LLR sequences corresponds to a group of LDPC Iterative decoding. When the LDPC iterative decoding corresponding to any set of second LLR sequences obtains a successfully decoded set of decoded data, stop decoding the one or more sets of second LLR sequences, and decode the set The data serves as the first decoded data. For example, if there are m groups of second LLR sequences, when LDPC iterative decoding is performed based on the m-th group of second LLR sequences, when the m-th group of second LLR sequences corresponding to the LDPC iterative decoding first obtains a correct decoded data , That is, stop all LDPC iterative decoding based on the second LLR sequence, and use the correct decoded data as the first decoded data.

Optionally, in a possible implementation manner, LDPC iterative decoding may be performed on the transmission data based on each group of the second LLR sequence in the one or more groups of second LLR sequences to obtain one or more groups Successfully decoded decoded data. If only a group of successfully decoded decoded data is obtained, it can be directly determined that the group of decoded data is the first decoded data. If multiple sets of successfully decoded decoded data are obtained, one set of decoded data can be selected from the multiple sets of decoded data as the first decoded data according to a preset rule.

Optionally, in a possible implementation manner, the preset rule may be a set of decoded data whose Euclidean metric between the multiple sets of decoded data and the first LLR sequence is not greater than a threshold. As the first decoded data. Of course, a group of decoded data may be randomly determined as the first decoded data from the plurality of sets of decoded data, which can be specifically adjusted according to actual application scenarios, which is not limited in this application. In addition, the threshold may be preset or calculated according to actual application scenarios. For example, the decoded data with the smallest Euclidean metric value may be selected from multiple sets of decoded data as the first decoded data.

Exemplarily, the Euclidean metric may also be referred to as Euclidean distance below. The specific calculation method of the Euclidean distance may include: the second LLR sequence LLR=[LLR ₀ ,LLR ₁ ,LLR ₂ ,...,LLR _n-1 ] obtained after the disturbance processing, the LDPC decoding result of the second LLR sequence It is u=[u ₀ ,u ₁ ,...,u _N-1 ]. First, make a hard decision on the LLR sequence, and get d=[d ₀ ,d ₁ ,...,d _N-1 ], where the specific hard decision method can be:

or,

The specific hard decision method can be consistent with the mapping relationship during LDPC encoding. Then compare the values of sequence d and sequence c. If they are not equal, add the absolute value of the LLR at the corresponding position, and the final Euclidean distance is

Optionally, in a possible implementation manner, when performing iterative decoding from the first time to the Nth time on any group of the second LLR sequence in one or more groups of second LLR sequences, In the k-th LDPC iterative decoding: update the information R _ij [k] transmitted from the i-th check node to the j-th variable node, and update the j-th variable node to the i-th check through the second LLR sequence The node information Q _ji [k], 1≤k≤N, N is less than or equal to the preset number of iterations, and the decoded data of any set of second LLR sequence includes the R _ij [k] and Q _ji [k] .

Optionally, in a possible implementation manner, when performing LDPC iterative decoding on the second LLR sequence based on each of the second LLR sequences in one or more sets of second LLR sequences, in the kth iteration: The information R _ij [k] transmitted by the i-th check node to the j-th variable node can be updated by at least one preset correction value, and the j-th variable node can be updated and passed to the i-th checksum by the second LLR sequence. The node information Q _ji [k] is a set of decoded data, k is less than the preset number of iterations, and k is a positive integer. Optionally, the group of decoded data may be used as the first decoded data, or after multiple sets of decoded data are obtained, one of the sets of decoded data may be selected as the first decoded data, which may be specifically based on actual application scenarios. Make adjustments.

Exemplarily, taking any set of second LLR sequences as an example, the specific LDPC iterative decoding method may be: before the iteration, each parameter is initialized, the second LLR sequence to be decoded is determined, and the jth sequence of the input sequence is defined. The LLR information of each element λ _j =LLR_in _j , and,

It is a positive logic mapping (0→-1,1→+1). The information R _ij [0] transmitted by the i-th check node to the j-th variable node is initialized to 0, where j∈V(i). i=0,1,...,m-1, V(i) represents the set of variable nodes adjacent to the i-th check node. The information Q _ji [0] transmitted by the j-th variable node to the i-th check node is initialized to λ _j , where i∈C(j), j=0,1,...,n-1, C(j ) Represents the set of check nodes adjacent to the j-th variable node. Then perform LDPC iterative decoding, alternately update check nodes and variable nodes.

Optionally, in the k-th iterative decoding, k can be any iteration, and k is not greater than a preset number of iterations. If Q _ji [k-1]=min _j'∈V(i) (|Q _j'i [k-1]|), it can be understood as if Q _ji [k-1] is the k- _1th iteration The minimum value of Q _ji obtained in, then R _ij [k]=α ₁ *∏ _j'∈V(i)\j sgn(Q _j'i [k-1])*min _j'∈V(i) (|Q _j'i [k-1]|); if Q _ji [k-1] is not the minimum value of Q _ji obtained in the k- _1th iteration, then R _ij [k]=α ₂ ∏ _{j '∈V(i)\j} sgn(Q _j'i [k-1])*min _j'∈V(i) (|Q _j'i [k-1]|). Among them, sgn is a symbol operation, min is a minimum value operation, and V(i)\j represents the set of variable nodes connected to the i-th check node except the j-th variable node. α ₁ and α ₂ are preset correction values, which can also be called correction factors, and α ₁ and α ₂ are normalized correction factors. It can be understood that, in the embodiment of the present application, when Q _ji is the minimum value, the update of the check node is corrected, that is, the minimum value uses the correction factor α ₁ , and the remaining values use the correction factor α ₂ , usually α ₁ and α ₂ are positive numbers less than 1. Therefore, in the embodiments of the present application, a correction factor can be used to improve the decoding performance, compensate for calculation errors, and improve the accuracy of decoding.

In the k-th iteration, the information passed from the j-th variable node to the i-th check node: Q _ji [k]=λ _j +Σ _i'∈C(j)\i R _i'j [k], C(j) is the set of check nodes connected to the j-th variable node, and C(j)\i represents the set of check nodes connected to the j-th variable node except the i-th check node.

Optionally, if the sign of Q _ji [k] in the kth iteration is different from the sign of Q _ji [k-1] in the previous iteration, then let Q _ji [k]=0.

Exemplarily, in the kth iteration, the process of updating the variable node may be as shown in FIG. 10a, and the process of updating the check node may be as shown in FIG. 10b. Among them, the variable node can be updated according to the LLR after adding the disturbance value, that is, λ _{j in} Figure 10a.

Optionally, one variable node or check node may be updated at the same time, or multiple variable nodes or check nodes may be updated at the same time, which can be adjusted according to actual application scenarios, which is not limited here.

After alternately updating the check node and the variable node, it is also necessary to calculate the posterior probability information of the variable node:

Then, the hard decision decoding is completed according to the posterior probability information. For example, the hard decision can be:

or,

After obtaining the decoded data of the k-th iterative decoding of the second LLR sequence according to the hard decision decoding, the decoded data can also be checked, which can be LDPC self-check or CRC check, etc. It can also check all the decoded data obtained after multiple iterations to determine the successfully decoded data. For example, taking LDPC self-checking as an example, when the decoded data is obtained

After that, calculate

If

The verification result is a successful decoding, if

The verification result is that the decoding failed.

Optionally, in a possible implementation manner, when performing LDPC iterative decoding on one or more sets of second LLR sequences, in the kth iteration, the i-th check node is updated and passed to the j-th variable Node information R _ij [k], and update the information Q _ji [k] transmitted from the j-th variable node to the i-th check node through the preset weight value and the second LLR sequence to obtain a set of decoded data, k can be any iteration, and k is not greater than the preset number of iterations.

For example, in the embodiment of this application, R _ij [k] and Q _ji [k] can also be updated alternately, and the information R _ij [k] transmitted by the i-th check node to the j-th variable node can be updated with the aforementioned implementation. In the example, the method of updating R _ij [k] with at least one correction value is similar. Of course, R _ij [k] can also be directly updated without using the correction value. When the information Q _ji [k] transmitted by the j-th variable node to the i-th check node is updated through the preset weight value and the second LLR sequence, the specific decoding process can be, for example, in the k-th iteration, Update Q _ji [k] through the second LLR sequence, Q _ji [k]=λ _j +Σ _i'∈C(j)\i R _i'j [k]. If Q _ji [k] the symbols of the previous iteration different Q _ji [k-1] of the symbol, so _{that: Q ji [k] = ω} * Q ji [k] + (1-ω) * Q ji [ k-1], when Q _ji [k] the symbols of the previous iteration same Q _ji [k-1] of the symbol, the Q _ji [k] remains constant current calculation result. Among them, ω is a preset weight value, which can usually be a positive number greater than 0 and less than 1, and can be determined based on learning a large amount of decoded data, or can be determined as an empirical value. For example, ω can usually be 0.75. In the embodiment of the present application, the information transmitted by the variable node to the check node can be updated by the weighted value. The weighted value can be calculated or a preset value, so that the symbol of Q _ji [k] is different from the previous one. iteration Q _ji [k-1] is not the same symbol, the weighting value may be used to update the value Q _ji [k], improve Q _ji [k] obtained accuracy, and increase the Q _ji [k] of validity .

Optionally, in the embodiment of the present application, in addition to the foregoing LDPC iterative decoding, the decoding method for the second LLR sequence may be LDPC decoding for one or more groups of second LLR sequences. MS decoding, hierarchical decoding algorithms, etc., can be adjusted according to actual needs and are not limited here.

For example, based on the aforementioned LDPC decoding method for the second LLR sequence, the check node and the variable node can be updated alternately. When the check node and the variable node are alternately updated, optionally, the check node and the variable node can be updated in a layered decoding manner. For example, the way to update variable nodes and check nodes can be from top to bottom, divide the data matrix into multiple layers by rows, and then update the layers sequentially. After the row update of each layer is completed, the column corresponding to that layer is updated, and after the row and column of each layer are updated, the next layer is updated. For example, as shown in Figure 11, when updating variable nodes and check nodes, the update can be done hierarchically, according to the rows of the matrix, one row can be divided into one layer, and then the rows of each layer can be updated separately, and Update the column corresponding to each row. As shown in Figure 11, the rows and columns of the first to fifth layers are updated respectively. In the embodiment of the present application, each layer can be updated by layered decoding, the data to be decoded is divided into multiple layers, and then updated layer by layer. Therefore, after the rows and columns of the previous layer are updated, the next layer is updated. Since the rows of the next layer are updated based on the information of other rows that have been updated, the iteration convergence speed is relatively fast. Compared with updating the columns after all the rows are updated, and the rows cannot obtain the relevant information obtained by the update in advance, the iteration convergence speed is slow. In the embodiment of the present application, the rows and columns are alternately updated to make each layer The updates can be correlated to improve the convergence speed.

305. Other steps.

After the first LDPC decoding is successful, the decoded data obtained from the first decoding can be directly used as the decoding result of the transmitted data.

Optionally, after the successfully decoded first decoded data is obtained, subsequent steps such as information interpretation or instruction execution may also be performed on the first decoded data, which may be specifically adjusted according to actual application scenarios.

Therefore, in the embodiment of the present application, after the first LDPC decoding fails, the LDPC decoding may be continued based on one or more sets of second LLR sequences obtained after perturbing the first LLR sequence. When there are multiple sets of second LLR sequences, parallel decoding can be realized and the efficiency of decoding can be improved. In addition, the embodiment of the present application directly performs decoding based on the second LLR sequence obtained after the perturbation process. In addition to reducing the decoding complexity, it can also improve the accuracy of the obtained decoded data and improve the decoding performance.

Exemplarily, in the saturated minimum sum (Saturated Min-Sum, SMS) decoding mode, after the first decoding fails, the received channel LLRs are sorted, the j positions with the smallest amplitude are selected, and then the The LLRs at the j positions are respectively saturated to the integer maximum and negative maximum to obtain 2 ^j sequences, and then re-input the 2 ^j sequences to the decoder for decoding respectively, output the legal codewords, and then select the LLR sequence with the original channel The codeword with the smallest Euclidean distance, but only selects the VN based on the channel LLR, and the obtained decoding result has poor accuracy and poor decoding performance. Compared with the SMS decoding, the embodiment of this application selects a part of the VN from the VN that does not satisfy the check equation for decoding. The embodiment of this application can directly decode based on the second LLR sequence obtained after the perturbation process without performing the VN. Selection can reduce decoding complexity and improve decoding efficiency.

Exemplarily, the performance of LDPC decoding can be measured by the Block Error Rate (BLER). Exemplarily, the following is a more vivid description with the simulation result of BLER. Please refer to Figure 12, in the Additive White Gaussian Noise (AWGN) environment, the length of the information block is 120 bits, the coding rate is 1/5, and the same LLR sequence (list) 16, each BLER of a decoding method. It can be seen from Figure 12 that under the same conditions and the same signal-to-noise ratio (SNR or S/N), the decoding method with the highest bit error rate is layered normalized min-sum, LNMS) 15 iterative decoding, followed by LNMS 850 iterative decoding, then SMS decoding, followed by enhanced BP (augmented belief propagation, ABP), the disturbance processing provided in the embodiment of the application (can The decoding method (referred to as perturbation) has the lowest block error rate, which is significantly lower than other methods of BLER. In addition, the BLER of the scene where the length of the information block is 360 bits is shown in Fig. 13. Similar to the result in Fig. 12, the decoding method of disturbance processing provided in the embodiment of this application has the lowest block error rate, which is significantly lower than BLER in other ways. Therefore, the BLER of the data decoding method provided by the embodiment of the present application is significantly higher than the BLER of other decoding methods, which improves the reliability and decoding efficiency of LDPC decoding.

The foregoing provides a detailed description of the data decoding method provided in the embodiments of the present application, and the following describes the device provided in the present application.

For a schematic structural diagram of the decoding device provided in this application, refer to FIG. 14, and may include: a processing unit 1401 and an acquiring unit 1402.

The obtaining unit 1402 may be used to obtain the first log-likelihood ratio LLR sequence corresponding to the transmission data;

The processing unit 1401 may also be used to perform perturbation processing on one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences;

The processing unit 1401 may also be used to decode one or more sets of second LLR sequences to obtain first decoded data.

Exemplarily, the processing unit may be used to perform steps 201-203 in FIG. 2 or any one of steps 301-305 in FIG. 3, and the obtaining unit 1402 may be used to perform steps 201-203 in FIG. 2 or FIG. 3. Steps to obtain transmission data.

Optionally, in some possible implementation manners, the processing unit 1401 may be specifically configured to:

Perform LDPC iterative decoding on one group of second LLR sequences;

If a group of decoded data of the second LLR sequence is successfully checked, then the decoded data of the second LLR sequence is used as the first decoded data.

Perform LDPC iterative decoding on each group of second LLR sequences in one or more groups of second LLR sequences to obtain one or more groups of decoded data with successful verification;

According to a preset rule, a group of decoded data is determined as the first decoded data from one or more sets of successfully verified decoded data.

A group of decoded data whose Euclidean metric between the first LLR sequence and the first LLR sequence is less than or equal to a threshold is determined from one or more sets of decoded data successfully verified as the first decoded data.

Perform N iterative decoding on a set of second LLR sequences, and update the information R _ij [k] transmitted by the i-th check node to the j-th variable node in the k-th LDPC iterative decoding among them, and pass The second LLR sequence updates the information Q _ji [k] transmitted from the j-th variable node to the i-th check node, 1≤k≤N, and N is less than or equal to the preset number of iterations;

Among them, the decoded data of the k-th iterative decoding of a group of second LLR sequences includes R _ij [k] and Q _ji [k].

Update the information R _ij [k] transmitted from the i-th check node to the j-th variable node through at least one preset correction value.

Optionally, in some possible implementations,

The processing unit 1401 is further configured to perform LDPC decoding on the first LLR sequence before perturbing one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences.

15 is a schematic structural diagram of a decoding device provided by an embodiment of the present application. The decoding device 1500 may have relatively large differences due to differences in configuration or performance, and may include one or more central processing units (CPU). ) 1522 (or other types of processors) and a storage medium 1530. The storage medium 1530 is used to store one or more application programs 1542 or data 1544. The storage medium 1530 may be short-term storage or persistent storage. The program stored in the storage medium 1530 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the decoding device. Further, the central processing unit 1522 may be configured to communicate with the storage medium 1530, and execute a series of instruction operations in the storage medium 1530 on the decoding device 1500.

The central processing unit 1522 can execute any of the aforementioned embodiments corresponding to FIGS. 2 to 11 according to instruction operations.

The decoding device 1500 may also include one or more power supplies 1526, one or more wired or wireless network interfaces 1550, one or more input and output interfaces 1558, and/or one or more operating systems 1541, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

The steps that can be executed by the decoding device in FIGS. 2 to 11 in the foregoing embodiment may be based on the structure of the decoding device shown in FIG. 15.

The decoding device provided in this application may include a base station, a terminal, and so on.

Exemplarily, when the decoding device is a base station, or the decoding device is included in a base station, the structure of the base station may be as shown in FIG. 16.

16 is a schematic diagram of the structure of a base station provided by an embodiment of the present application. The base station 1600 may have relatively large differences due to different configurations or performance, and may include one or more central processing units (CPU) 1622 (or Other types of processors) and a storage medium 1630. The storage medium 1630 is used to store one or more application programs 1642 or data 1644. The storage medium 1630 may be short-term storage or persistent storage. The program stored in the storage medium 1630 may include one or more modules (not shown in the figure), and each module may include a series of command operations on the base station. Further, the central processing unit 1622 may be configured to communicate with the storage medium 1630, and execute a series of instruction operations in the storage medium 1630 on the base station 1600.

The central processing unit 1622 can execute any of the aforementioned embodiments corresponding to FIGS. 2 to 11 according to instruction operations.

The base station 1600 may also include one or more power supplies 1626, one or more wired or wireless network interfaces 1650, one or more input and output interfaces 1658, and/or one or more operating systems 1641, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

The steps that can be executed by the decoding device in FIGS. 2 to 11 in the foregoing embodiment may be based on the base station structure shown in FIG. 16.

The decoding device provided in this application can be various terminals, or, it can also be understood that the decoding device can be included in the terminal, for example, it can be a mobile phone, a tablet computer, a notebook computer, a TV, a smart wearable device, or other devices with display Screen electronic equipment and so on. In the above embodiments, there is no restriction on the specific form of the terminal. Among them, the system that the terminal can carry can include

Or other operating systems, etc., this embodiment of the present application does not impose any limitation on this.

The terminal can be applied to various communication systems. Specifically, the communication system is, for example, CDMA, TDMA, FDMA, OFDMA, SC-FDMA, and other systems. The term "system" can be replaced with "network". The CDMA system can implement wireless technologies such as UTRA and CDMA2000. UTRA can include WCDMA technology and other CDMA variants. CDMA2000 can cover the interim standard (IS) 2000 (IS-2000), IS-95 and IS-856 standards. The TDMA system can implement wireless technologies such as the global system for mobile communication (GSM). OFDMA system can realize such as evolved universal wireless terrestrial access (evolved UTRA, E-UTRA), ultra mobile broadband (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, Flash OFDMA And other wireless technologies. UTRA and E-UTRA are UMTS and UMTS evolved versions. 3GPP is a new version of UMTS using E-UTRA in long term evolution (LTE) and various versions based on LTE evolution. And the fifth generation (5Generation, "5G") communication system, and the New Radio ("NR") are next-generation communication systems under study. In addition, the communication system may also be suitable for future-oriented communication technologies, and all of them may be applied to the technical solutions provided in the embodiments of the present application.

Exemplary to carry

Take the terminal 100 of the operating system as an example. As shown in FIG. 17, the terminal 100 can be logically divided into a hardware layer 21, an operating system 161, and an application layer 31. The hardware layer 21 includes hardware resources such as an application processor 101, a microcontroller unit 103, a modem 107, a Wi-Fi module 111, a sensor 114, a positioning module 150, and a memory. The application layer 31 includes one or more applications, such as an application 163. The application 163 may be any type of application such as a social application, an e-commerce application, or a browser. The operating system 161, as a software middleware between the hardware layer 21 and the application layer 31, is a computer program that manages and controls hardware and software resources.

In one embodiment, the operating system 161 includes a kernel 23, a hardware abstraction layer (HAL) 25, a library and runtime (libraries and runtime) 27, and a framework 29. Among them, the kernel 23 is used to provide underlying system components and services, such as: power management, memory management, thread management, hardware drivers, etc.; hardware drivers include Wi-Fi drivers, sensor drivers, positioning module drivers, etc. The hardware abstraction layer 25 encapsulates the kernel driver, provides an interface to the framework 29, and shields low-level implementation details. The hardware abstraction layer 25 runs in the user space, and the kernel driver runs in the kernel space.

The library and runtime 27 is also called the runtime library, which provides the required library files and execution environment for the executable program at runtime. The library and runtime 27 include the Android Runtime (ART) 271 and the library 273. ART 271 is a virtual machine or virtual machine instance that can convert the bytecode of an application program into machine code. The library 273 is a program library that provides support for the executable program at runtime, and includes a browser engine (such as webkit), a script execution engine (such as a JavaScript engine), a graphics processing engine, and the like.

The framework 29 is used to provide various basic common components and services for the applications in the application layer 31, such as window management, location management, and so on. The frame 29 may include a phone manager 291, a resource manager 293, a location manager 295, and so on.

The functions of the various components of the operating system 161 described above can all be implemented by the application processor 101 executing programs stored in the memory.

Those skilled in the art can understand that the terminal 100 may include fewer or more components than those shown in FIG. 17, and the terminal shown in FIG. 17 only includes components that are more relevant to the multiple implementations disclosed in the embodiments of the present application. .

The terminal usually supports the installation of multiple applications (Application, APP), such as word processing applications, phone applications, email applications, instant messaging applications, photo management applications, web browsing applications, and digital music player applications , And/or digital video player applications.

The present application provides a chip system including a processor for supporting the decoding device to implement the functions involved in the above aspects, for example, sending or processing the data and/or information involved in the above methods. In a possible design, the chip system further includes a memory, and the memory is used to store necessary program instructions and data. The chip system may be composed of chips, or may include chips and other discrete devices.

In another possible design, when the decoding device is a chip in a terminal or a base station, the chip includes a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, Input/output interface, pin or circuit, etc. The processing unit can execute the computer-executable instructions stored in the storage unit, so that the chip in the terminal or the base station, etc. executes the steps of the method executed by the network in any one of the above-mentioned embodiments of FIGS. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip in the terminal or base station, such as read-only Memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), etc.

An embodiment of the present application also provides a chip, including: a processing module and a communication interface, and the processing module can execute the method flow related to the decoding device in any of the foregoing method embodiments. Further, the chip may also include a storage module (for example, a memory), the storage module is used to store instructions, and the processing module is used to execute the instructions stored in the storage module, and perform processing on the instructions stored in the storage module. The execution of the instruction causes the processing module to execute the method flow related to the decoding device in any of the foregoing method embodiments.

The embodiment of the present application also provides a communication system. The communication system may include a terminal and a base station. The terminal may be a terminal as shown in FIG. 17, and the terminal may be used to perform any of the foregoing embodiments of FIGS. 2-11. One step. The base station may be the base station shown in FIG. 16, and the base station may be used in any step in the foregoing embodiments of FIGS. 2-11.

The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the method flow related to the decoding device in any of the foregoing method embodiments is implemented. Correspondingly, the computer may be the aforementioned decoding device.

The embodiments of the present application also provide a computer program or a computer program product including a computer program. When the computer program is executed on a computer, the computer will enable the computer to implement the decoding method in any of the above-mentioned method embodiments. Device-related method flow. Correspondingly, the computer may be the aforementioned decoding device.

In each of the above-mentioned embodiments in FIGS. 2-11, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website site, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or data center integrated with one or more available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

It should be understood that the processor mentioned in this application may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application specific integrated circuits (Application Specific Integrated Circuits). Integrated Circuit, ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.

It should also be understood that the number of processors in the present application may be one or multiple, and may be specifically adjusted according to actual application scenarios. This is only an exemplary description and is not limited. The number of memories in the embodiments of the present application may be one or multiple, and may be specifically adjusted according to actual application scenarios. This is only an exemplary description and is not limited.

It should also be noted that when the decoding device includes a processor (or processing module) and a memory, the processor in the present application may be integrated with the memory, or the processor and the memory may be connected through an interface. It is adjusted according to actual application scenarios and is not limited.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which can be a personal computer, a server, or other network devices, etc.) execute all or part of the steps of the methods described in the various embodiments in Figures 2-11 of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

It should be understood that the storage medium or memory mentioned in this application may include volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. The volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache. By way of exemplary but not restrictive description, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced SDRAM, ESDRAM), Synchronous Link Dynamic Random Access Memory (Synchlink DRAM, SLDRAM) ) And Direct Rambus RAM (DR RAM).

It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

A method for data decoding, characterized by comprising:

Acquiring the first log-likelihood ratio LLR sequence corresponding to the transmission data;

Performing perturbation processing on one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences;

The one or more sets of second LLR sequences are decoded to obtain first decoded data.
The method of claim 1, wherein the decoding the one or more sets of second LLR sequences to obtain the first decoded data comprises:

Perform LDPC iterative decoding on one group of second LLR sequences;

If the verification of the decoded data of the second LLR sequence is successful, then the decoded data of the second LLR sequence is used as the first decoded data.
The method of claim 1, wherein the decoding the one or more sets of second LLR sequences to obtain the first decoded data comprises:

LDPC iterative decoding is performed on each group of second LLR sequences in the one or more groups of second LLR sequences to obtain one or more groups of decoded data with successful verification;

A set of decoded data is determined as the first decoded data from the one or more sets of decoded data successfully verified according to a preset rule.
The method according to claim 3, wherein said determining a set of decoded data from the one or more sets of successfully verified decoded data as the first decoded data according to a preset rule, include:

A group of decoded data whose Euclidean metric between the first LLR sequence and the first LLR sequence is less than or equal to a threshold is determined from the one or more sets of decoded data successfully verified as the first decoded data.
The method according to claim 2, wherein said performing LDPC iterative decoding on one group of second LLR sequences comprises:

Perform N iterations of decoding on the set of second LLR sequences, and update the information R ij [k] transmitted from the i-th check node to the j-th variable node in the k-th LDPC iterative decoding among them, And update the information Q ji [k] transmitted from the j-th variable node to the i-th check node through the second LLR sequence, 1≤k≤N, and the N is less than or equal to the preset number of iterations;

Wherein, the decoded data of the k-th iterative decoding of the set of second LLR sequences includes the R ij [k] and the Q ji [k].
The method according to claim 5, wherein the updating the information R ij [k] transmitted from the i-th check node to the j-th variable node comprises:

Update the information R ij [k] transmitted from the i-th check node to the j-th variable node through at least one preset correction value.
The method according to claim 5 or 6, wherein the updating the information Q ji [k] transmitted from the j-th variable node to the i-th check node through the second LLR sequence comprises:

The information Q ji [k] transmitted from the j-th variable node to the i-th check node is updated by the preset weight value and the second LLR sequence.
The method according to claim 7, wherein the information Q ji [k] transmitted from the j-th variable node to the i-th check node is updated by the preset weight value and the second LLR sequence, include:

If the sign of Q ji [k] obtained by the k-th iterative decoding is different from the sign of Q ji [k-1] obtained by the k- 1th iterative decoding, then Q ji [k]=ω*Q ji [ k]+(1-ω)*Q ji [k-1], the ω is the weighted value.
The method according to any one of claims 1-8, wherein the perturbation process is performed on one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences Before, the method also includes:

LDPC decoding of the first LLR sequence fails.
A decoding device, characterized by comprising: an acquisition unit and a processing unit;

The acquiring unit is configured to acquire the first log-likelihood ratio LLR sequence corresponding to the transmission data;

The processing unit is configured to perform perturbation processing on one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences;

The processing unit is also used to decode the one or more sets of second LLR sequences to obtain first decoded data.
The decoding device according to claim 10, wherein the processing unit is specifically configured to:

Perform LDPC iterative decoding on one group of second LLR sequences;

If the verification of the decoded data of the second LLR sequence is successful, then the decoded data of the second LLR sequence is used as the first decoded data.
The decoding device according to claim 10, wherein the processing unit is specifically configured to:

LDPC iterative decoding is performed on each group of second LLR sequences in the one or more groups of second LLR sequences to obtain one or more groups of decoded data with successful verification;

A set of decoded data is determined as the first decoded data from the one or more sets of decoded data successfully verified according to a preset rule.
The decoding device according to claim 12, wherein the processing unit is specifically configured to:

A group of decoded data whose Euclidean metric between the first LLR sequence and the first LLR sequence is less than or equal to a threshold is determined from the one or more sets of decoded data successfully verified as the first decoded data.
The decoding device according to claim 11, wherein the processing unit is specifically configured to:

Perform N iterations of decoding on the set of second LLR sequences, and update the information R ij [k] transmitted from the i-th check node to the j-th variable node in the k-th LDPC iterative decoding among them, And update the information Q ji [k] transmitted from the j-th variable node to the i-th check node through the second LLR sequence, 1≤k≤N, and the N is less than or equal to the preset number of iterations;

Wherein, the decoded data of the k-th iterative decoding of the set of second LLR sequences includes the R ij [k] and the Q ji [k].
The decoding device according to claim 14, wherein the processing unit is specifically configured to:

Update the information R ij [k] transmitted from the i-th check node to the j-th variable node through at least one preset correction value.
The decoding device according to claim 14 or 15, wherein the processing unit is specifically configured to:

The information Q ji [k] transmitted from the j-th variable node to the i-th check node is updated by the preset weight value and the second LLR sequence.
The decoding device according to claim 16, wherein the processing unit is specifically configured to:

If the sign of Q ji [k] obtained by the k-th iterative decoding is different from the sign of Q ji [k-1] obtained by the k- 1th iterative decoding, then Q ji [k]=ω*Q ji [ k]+(1-ω)*Q ji [k-1], the ω is the weighted value.
The decoding device according to any one of claims 10-17, wherein:

The processing unit is further configured to perform LDPC decoding on the first LLR sequence before perturbing one or more LLRs in the first LLR sequence to obtain one or more sets of second LLR sequences failure.
A base station, characterized by comprising the decoding device according to any one of claims 10 to 18.
A terminal, characterized by comprising the decoding device according to any one of claims 10 to 18.
A computer-readable storage medium, comprising instructions, which when run on a computer, causes the computer to execute the method according to any one of claims 1-9.
A decoding device, comprising a processor and a memory, wherein the processor is coupled with the memory, and is used to read and execute the instructions stored in the memory, so as to implement any one of claims 1-9 step.
The device of claim 22, wherein the decoding device is a chip or a system on a chip.
A computer program product containing instructions, characterized in that, when the instructions run on a computer, the computer is caused to execute the method according to any one of claims 1-9.
A communication system, characterized by comprising the base station according to claim 19 and the terminal according to claim 20.