WO2020220225A1

WO2020220225A1 - Resource acquisition method, related apparatus, and computer storage medium

Info

Publication number: WO2020220225A1
Application number: PCT/CN2019/085059
Authority: WO
Inventors: 查克拉博蒂·齐元吉; 谢时岳; 张建明
Original assignee: 华为技术有限公司
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2020-11-05
Also published as: CN113767368A

Abstract

Embodiments of the present invention disclose a resource acquisition method, a related apparatus, and a computer storage medium. The method comprises: receiving at least one resource request, and storing the at least one resource request in a logical stack, each resource request being sent by a processor core, the resource request corresponding to the processor core on a one-to-one basis, and the resource request being used to request a logical resource for the corresponding processor core; and allocating a target logical resource to a target resource request, wherein only one logical resource is allowed to be allocated to one resource request within an operating clock cycle, and the target resource request is a resource request located in the logical stack and having the highest priority level. Embodiments of the present invention resolve the issue in which existing multi-threaded parallel allocations of logical resources to resource requests cause difficulty in the allocation of a logical resource to a certain resource request, affecting a service and performance corresponding to the resource request.

Description

Resource acquisition method, related device and computer storage medium

Technical field

The present invention relates to the field of Internet technology, in particular to a resource acquisition method, related devices and computer storage media.

Background technique

With the improvement of technological processes and the improvement of Internet business requirements, the design of system on chip (SOC) has become more complicated, and the number of CPUs integrated on the same chip has also increased. Due to reasons such as cost and power consumption, the central processing unit (CPU) supports a limited number of resources to be called, and multiple CPUs support the calling of the same resource. The resource may be a data resource provided by a preset resource module, such as a key resource generated by a key generator, an algorithm resource provided by an algorithm engine module, and so on. Taking into account the information security of the CPU, hardware locks are used to isolate different CPUs. For each CPU, when an application needs to use resources, it needs to query idle resources through the CPU and configure commands to preempt the hardware lock, which is used to lock the idle resources. In order to release the hardware lock after using the free resources, the next re-grab lock is performed.

For each CPU, it will go through the process of command parsing-execution-response-result return. The working clock cycle of each CPU is generally hundreds of microseconds or even milliseconds. In a scenario where multiple CPUs run in parallel through multiple threads, each CPU will run separately through its own thread to preempt the idle resource and the hardware lock of the idle resource for the CPU. In practical applications, due to CPU hardware limitations and other reasons, the preemption speed of a certain CPU may be slower than the preemption speed of another CPU, making it difficult for the CPU to grab resources, thereby affecting the normal business communication and business performance of the CPU.

Summary of the invention

The embodiment of the invention discloses a resource acquisition method, a related device and a computer storage medium, which can solve the problems that data resources in the prior art are difficult to occupy and affect normal business communication and business performance.

In the first aspect, an embodiment of the present invention discloses a method for obtaining a resource. The method includes: a logic stack can receive and store at least one resource request, wherein each resource request is sent by a processor core, and the resource request There is a one-to-one correspondence with the processor core, and the resource request is used to request logic resources for the corresponding processor core. When the target resource request is popped from the logic stack, the resource allocation logic circuit can allocate the target logic resource to the target resource request, and only one resource request can be allocated logic resources in a working clock cycle, where the target resource request refers to The resource request with the highest priority in the logic stack.

By implementing the embodiments of the present invention, the logic stack can be used to store at least one resource request. The logic stack can only process one resource request within a working clock cycle, ensuring that every resource request stored in the logic stack can be processed, thereby It can ensure that the resource request of each processor core can finally grab the resource. In turn, it can solve the problem that individual CPUs cannot always grab resources when multi-threading is used to allocate resources for multiple CPUs in the traditional technology, which affects the normal business communication and business performance of the individual CPUs.

With reference to the first aspect, in some possible embodiments, after receiving the target resource request, the resource allocation logic circuit may query whether there are idle resources for the target processor core, and the target processor core is sent to the target resource request Processor cores. When the resource allocation logic circuit finds that there is an idle resource, it can allocate the idle resource as a target logic resource to the target processor core. The idle resources refer to unused or unoccupied resources.

By implementing this step, the resource allocation logic circuit can select idle resources as the target logic resources to allocate to the target processor core for use, avoiding allocating some occupied logic resources currently being used to the target processor core, resulting in the target processor core Unavailable, which improves the rationality and reliability of resource allocation.

With reference to the first aspect, in some possible embodiments, after the resource allocation logic circuit allocates the target processor core, it can also automatically preempt the target protection lock corresponding to the target logic resource according to the target resource request, so that the target processor core can be based on this The target protection lock accesses the target logical resource. Further, the resource allocation logic circuit may also report the lock grab result to the target processor core through an interrupt response, and the lock grab result is used to indicate that the target protection lock is successfully seized. It is convenient for the target processor core to obtain the target protection lock after receiving the lock grab result, and then access and use the target logical resource based on the target protection lock.

By implementing this step, the resource allocation logic circuit can allocate the target logic resource to the target processor core according to the target resource request, while also successfully seizing the target protection lock of the target logic resource, and the CPU is querying the target logic resource in the traditional technology. Compared with the need to issue another lock grab command later, it can greatly reduce the process steps of resource acquisition and improve the convenience and efficiency of resource acquisition. In addition, after any processor core (CPU) in this application sends the resource request of the processor core, it can automatically release the control right or occupancy right of the processor core, and then the resource allocation logic circuit will follow the processor core’s The resource request queries idle resources and automatically seizes the protection lock corresponding to the idle resources after the idle resources are found, which can reduce the CPU occupation and increase the CPU utilization rate.

With reference to the first aspect, in some possible embodiments, each resource request carries an identifier, and the identifier is used to indicate the processor core to which the corresponding resource request belongs. After receiving any resource request, the logic stack can determine the identifier carried in the resource request. Then, according to the identifier, it is determined whether to store the resource request in the logic stack.

By implementing this step, the logic stack can determine whether to store the resource request of the processor core in the logic stack according to the identifier of the processor core, so as to ensure that at least one resource request of each processor core is stored in the logic stack, thereby ensuring Subsequent resources will be allocated for at least one resource request of each processor core, which can prevent multiple resource requests from certain processor cores from entering the logic stack, causing resource requests from other processor cores to fail to stack after the logic stack is full. The resource request of each processing core provides a fair opportunity for stacking, avoiding some processor cores in the traditional technology that the CPU is difficult to seize resources, thereby affecting the normal business communication and business performance of the CPU.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logic stack supports storage of n resource requests, the total number of processor cores is m, and n=m, then the logic stack only allows m processor cores A resource request for each processor core is stored in the logic stack.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logic stack supports the storage of m resource requests, and the total number of processor cores is m, the logic stack only allows one of multiple resource requests with the same identifier A resource request is stored in the logic stack.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n>m, then the logical stack allows at least the first processor core Two resource requests are stored in the logic stack, and the first processor core is any one of the m processor cores.

With reference to the first aspect, in some possible embodiments, the logic stack is a first-in first-out unit FIFO logic stack.

With reference to the first aspect, in some possible embodiments, the resource allocation logic circuit is deployed independently of the processor core.

With reference to the first aspect, in some possible embodiments, the processor core is deployed in the communication device, that is, the communication device further includes a processor core, and the number of the processor core is not limited.

With reference to the first aspect, in some possible embodiments, the logic stack receives a cancel command for the first resource request, and the first resource request is any one of at least one resource request. Further, the logic stack may perform queue-insertion and de-stack processing for the first resource request according to the cancel command, so as to delete the first resource request stored in the logic stack.

By implementing this step, the logic stack supports the provision of a queue-insertion and pop-up mechanism to cancel the first resource request that you want to cancel, which improves the flexibility of resource acquisition.

With reference to the first aspect, in some possible embodiments, after the first resource request is deleted, the resource allocation logic circuit may report the cancellation result to the processor core corresponding to the first resource request through an interrupt response, where the cancellation result is used To indicate that the logic stack has completed the cancellation of the first resource request.

By implementing this step, the cancellation result is sent to the processor core to which the first resource request belongs in an interruption manner, so as to notify the completion of the cancellation of the first resource request, and improve the flexibility of resource acquisition.

In a second aspect, an embodiment of the present invention provides a communication device, including a logic stack and a resource allocation logic circuit, where:

The logic stack is configured to receive at least one resource request and store the at least one resource request in the logic stack, wherein each resource request is sent by a processor core, and the resource request and the processing There is a one-to-one correspondence between the processor cores, and the resource request is used to request logical resources for the corresponding processor core;

The resource allocation logic circuit is used to allocate a target logic resource for a target resource request, and allocate logic resources for only one resource request within a working clock cycle, wherein the target resource request refers to the logic stack and has The highest priority resource request.

With reference to the second aspect, in some possible embodiments, the resource allocation logic circuit is specifically configured to query whether there are free resources for the target processor core after receiving the target resource request; In the case of resources, the idle resource is allocated to the target processor core as the target logical resource, and the target processor core refers to the processor core that sends the target resource request.

With reference to the second aspect, in some possible embodiments, after the resource allocation logic circuit allocates the idle resource as the target logic resource to the target processor core, the resource allocation logic circuit is further configured to The target resource request automatically preempts the target protection lock corresponding to the target logic resource, wherein the target processor core accesses the target logic resource based on the target protection lock; and reports the lock grab result to the target processing through an interrupt response Device core, wherein the lock preemption result is used to indicate that the target protection lock has been successfully preempted.

With reference to the second aspect, in some possible embodiments, each resource request carries an identifier, and the identifier is used to indicate the processor core to which the corresponding resource request belongs, and the logic stack is also used to After the resource request, determine the identifier carried in the resource request; according to the identifier carried in the resource request, determine whether to store the resource request in the logic stack.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n=m, then the logical stack only allows One resource request of each of the m processor cores is stored in the logic stack.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of m resource requests, and the total number of processor cores is m, then the logical stack is only allowed to have the same identification One of the multiple resource requests is stored in the logic stack.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n is greater than m, then the logical stack allows the first At least two resource requests of a processor core are stored in the logic stack, and the first processor core is any one of the m processor cores.

With reference to the second aspect, in some possible embodiments, the logic stack is a first-in first-out unit FIFO logic stack.

With reference to the second aspect, in some possible embodiments, the resource allocation logic circuit is independent of the processor core.

With reference to the second aspect, in some possible embodiments, the apparatus further includes: a plurality of the processor cores.

With reference to the second aspect, in some possible embodiments, the logic stack is further configured to receive a cancel command for a first resource request, where the first resource request is any one of the at least one resource request; The cancel command deletes the first resource request stored in the logic stack.

With reference to the second aspect, in some possible embodiments, after the logic stack deletes the first resource request, the resource allocation logic circuit is configured to report the cancellation result to the first resource request station through an interrupt response. The corresponding processor core, wherein the cancellation result is used to indicate that the logic stack has completed the cancellation of the first resource request.

Regarding content not shown or explained in the embodiment of the present invention, reference may be made to the relevant introduction in the method embodiment described in the first aspect, which is not repeated here.

In the third aspect, an embodiment of the present invention provides a communication system including m processor cores, a logic stack, and a resource allocation logic circuit. Optionally, it may also include protection locks and resources. Among them, the processor core can be deployed in the host device, and the logic stack, resource allocation logic circuit, protection lock, and resources can be deployed in the slave device. Correspondingly, the communication system may include m master devices and slave devices, and the slave devices can be correspondingly used to execute the method described in the first aspect above through various components deployed in their own devices. Exemplarily, take the communication system including m master devices and slave devices as an example, where,

The host device is used to send a resource request to the slave device;

The slave device is configured to receive at least one resource request, and store the at least one resource request in the logical stack of the slave device, each resource request is sent by a processor core, and the resource There is a one-to-one correspondence between the request and the processor core, and the resource request is used to request logical resources for the corresponding processor core;

The slave device is also used to allocate target logic resources to target resource requests, and allocate logic resources to only one resource request within a working clock cycle, where the target resource request refers to the logic stack and The resource request with the highest priority.

With reference to the third aspect, in some possible embodiments, the slave device is specifically configured to, after receiving the target resource request, query whether there is an idle resource for the target processor core; when the idle resource is queried, The idle resource is allocated to the target processor core as the target logical resource, and the target processor core is the processor core that sends the target resource request.

With reference to the third aspect, in some possible embodiments, after the slave device allocates idle resources as the target logic resource to the target processor core, the slave device is further configured to automatically preempt the target logic according to the target resource request. The target protection lock corresponding to the resource, where the target processor core accesses the target logical resource based on the target protection lock; the lock grab result is reported to the target processor core through an interrupt response, where the lock grab result is used to indicate that the target protection lock has been successfully seized.

With reference to the third aspect, in some possible embodiments, each resource request carries an identifier, which is used to indicate the processor core to which the corresponding resource request belongs, and the slave device is also used for receiving a resource request Then, the identifier carried in the resource request is determined; according to the identifier carried in the resource request, it is determined whether to store the resource request in the logic stack.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of n resource requests, the total number of processor cores is m and n=m, then the logical stack only allows m processor cores A resource request for each processor core is stored in the logic stack.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logic stack supports the storage of m resource requests, and the total number of processor cores is m, then the logic stack only allows one of the multiple resource requests with the same identifier A resource request is stored in the logic stack.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of n resource requests, the total number of processor cores is m, and n>m, and the logical stack allows at least two of the first processor cores Each resource request is stored in the logic stack, and the first processor core is any one of the m processor cores.

With reference to the third aspect, in some possible embodiments, the logic stack is a first-in first-out unit FIFO logic stack.

With reference to the third aspect, in some possible embodiments, the slave device is further configured to receive a cancellation command for a first resource request, where the first resource request is any one of at least one resource request; according to the cancellation Command to delete the first resource request stored in the logic stack.

With reference to the third aspect, in some possible embodiments, after deleting the first resource request, the slave device is further configured to report the cancellation result to the host device corresponding to the first resource request through an interrupt response, wherein the cancellation The result is used to indicate that the logic stack has completed the cancellation of the first resource request.

In a fourth aspect, a communication device is provided. The communication device includes a processor deployed with a logic stack and a resource allocation logic circuit. In actual operation, the processor is used to execute the method described in the first aspect. Optionally, the communication device may further include any one or a combination of the following: logic resources, protection locks, and at least one processor core.

In a fifth aspect, a computer-readable storage medium is provided, and the computer-readable storage medium is used to execute instructions of the method described in the first aspect.

In a sixth aspect, a chip product is provided to implement the foregoing first aspect or the method in any possible implementation manner of the first aspect.

On the basis of the implementation manners provided in the above aspects, the present invention can be further combined to provide more implementation manners.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art.

Fig. 1 is a schematic diagram of a scenario in which a CPU preempts data resources provided by the prior art.

Fig. 2 is a schematic diagram of another scenario where a CPU preempts data resources provided by the prior art.

Fig. 3 is a schematic structural diagram of a communication system provided by an embodiment of the present invention.

Fig. 4 is a schematic diagram of a logical stack storage provided by an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of another communication system provided by an embodiment of the present invention.

Fig. 6 is a schematic flowchart of a resource acquisition method provided by an embodiment of the present invention.

Fig. 7 is a schematic diagram of a logic stack provided by an embodiment of the present invention.

FIG. 8 is a schematic flowchart of another resource acquisition method provided by an embodiment of the present invention.

Fig. 9 is a schematic diagram of a change of a logic stack provided by an embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a communication device provided by an embodiment of the present invention.

Fig. 11 is a schematic structural diagram of a communication device provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings of the present invention.

Figure 1 shows a schematic diagram of a scenario where a CPU preempts data resources. The schematic diagram shown in Figure 1 includes 3 lock grab requests, N resources, and N hardware locks. Among them, each hardware lock correspondingly protects a resource, which is used to encrypt and protect the resource. Each lock grab request is generated by a CPU when it needs to use resources, and different lock grab requests correspond to different CPUs. The figure shows the lock grab requests generated by each of the three CPUs, specifically CPU1request (lock grab request), CPU2request and CPU3request; N resources are resource 1 to resource N, and N hardware locks are Lock1 to LockN .

When the application on the device needs to use resources, a query request can be generated, and the CPU calls the loop query program to query the available idle data resources (hereinafter referred to as idle resources). For example, the CPU queries each resource by calling the loop query level. The status information, the status information includes occupied or idle. When the status information is occupied, it indicates that the resource is being occupied, such as being used by other applications. When the status information is idle, it means that the resource is not currently occupied and is idle, and the application can use the idle resource at this time. When the CPU finds that the status information is an idle resource, it indicates that the resource is an idle resource currently available to the application.

Correspondingly, after inquiring about free resources, the CPU can issue a lock grab command. The lock grab command is used to grab the hardware lock corresponding to the idle resource, so as to unlock the idle resource by using the hardware lock to obtain the idle resource. When the application program cannot query the available idle resources through the CPU, it can run the sleep waiting program and wait to continue to find the available idle resources.

However, in practice, it has been found that in the case of sufficient resources, the application can query the available idle resources through the CPU every time. In the case of resource shortage, all resources may be fully occupied, and the CPU cannot query available idle resources. However, when there are no free resources available, the application will still go through the process of query request resolution -> query request execution -> query request response -> result return. In practical applications, there is a certain delay in the transmission of lock grab requests on the chip bus. Therefore, the query cycle of an idle resource usually reaches the order of hundreds of microseconds or even milliseconds. In addition, considering the asynchronous multi-threaded scheduling scenario, at least one sleep waiting function needs to be inserted between every two query requests. In this scenario, the time consumed to complete an idle resource query is usually on the order of milliseconds or even tens of milliseconds. . In this time interval of tens of milliseconds, the query speed of the CPU may be slower than that of another CPU, which makes it difficult for the CPU to query and preempt available idle resources, thereby affecting normal business communications and business services quality.

Figure 2 shows a schematic diagram of a process in which a CPU preempts data resources. The horizontal axis represents time, and the figure shows the specific implementation process of three CPUs along the time axis for their respective CPUs to seize data resources. As shown in Figure 2, the time sequence for each of the three CPUs to issue query requests for idle resources is: CPU2>CPU1>CPU3. As shown in the figure, for a device that provides limited idle resources, the query request sent by the CPU 2 is processed first to query whether there are available idle resources in the device. After the query is found, the CPU 2 can preempt the hardware lock corresponding to the idle resource, so that the CPU can unlock the idle resource through the hardware lock to use the idle resource. Optionally, the CPU2 may also report a query result, which is used to indicate that the CPU2 has inquired about available idle resources, or used to indicate that the CPU2 has not inquired about available idle resources. Optionally, after the CPU 2 finishes using the idle resource, the idle resource may be released for use by other CPUs.

As shown in the figure, in the process of CPU2 inquiring about free resources, CPU1 also has a demand for use of free resources, and it sends a query request to query the available free resources in the device. As shown in the figure, the time when CPU1 sends the query request is later than the time when CPU2 sends the query request. When CPU1 queries idle resources through a query request, because the idle resources have been queried by CPU2, CPU1 can return the query result at this time. The query result is used to indicate that the idle resources have been preempted by CPU2 and there are currently no available idle resources to notify CPU1 waits to query again or ends the process. Optionally, the CPU1 can run the sleep waiting program, and after waiting for a preset time, continue to request the query through the query and preempt available idle resources. In the same way, while CPU1 is waiting, CPU2 has used and released idle resources. At this time, CPU3 sends a query request to meet its own demand for idle resources. Correspondingly, CPU3 queries and preempts free resources through query requests. After CPU1 runs the sleep waiting program, it can continue to query whether there are idle resources in the device through its own query request. Since the idle resource has been preempted by the CPU 3 at this time, the CPU 1 can report the corresponding query result, which is used to indicate that the idle resource has been preempted by the CPU 3, and there is currently no idle resource available.

It can be seen from the figure that in a scenario with a large number of CPUs, it is difficult for the CPU to seize idle resources, and it is easy for the CPU to fail to grab the idle resources, which affects the normal business communication of the CPU and affects business performance.

To solve the above-mentioned problems, this application proposes a resource acquisition method, and related devices and systems to which the method is applicable. Refer to FIG. 3, which is a schematic structural diagram of a communication system according to an embodiment of the present invention. The communication system 300 shown in FIG. 3 includes m processor cores 302, a logic stack 304, and a resource allocation logic circuit 306. Optionally, the communication system may further include a protection lock 308 and a resource 310. The number of the protection locks 308 and the resources 310 is not limited, and there may be one or more. The figure shows multiple protection locks 308 and multiple resources 310 as examples. m is a positive integer. among them,

The processor core 302 is configured to send a resource request when it is detected that the resource needs to be used, so as to obtain the idle resource required by the processor core. The idle resources refer to resources that are not used by other processor cores. The resources include but are not limited to computing resources, storage resources, and network resources. For example, the resource may be a key derivation module deployed in a communication system, and the key derivation The module is used to provide a communication key to ensure the safe transmission of data. In an optional situation, the resource is a hardware logic resource, and the processor core performs a corresponding logic operation or completes a corresponding function through the hardware logic resource.

The logic stack 304 is used to cache the resource request sent by the processor core 302 (that is, the query request mentioned above in this application), and the resource request is used to request the acquisition of idle resources for the processor core 302 to use. The number of storage resource requests supported in the logic stack 304 is not limited and depends on the storage capacity of the logic stack 304. The logic stack 304 supports storing one or more resource requests sent by the same processor core 302. Specifically, when the storage capacity of the logic stack 304 supports the storage of n resource requests, and n=m, the logic stack 304 is only allowed to store one resource request for each of the m processor cores 302. When n is greater than m, the logic stack 304 is allowed to store at least two resource requests of the first processor core, which is any one of the m processor cores; in other words, in the logic stack 304 When the number n of storage resource requests supported by the stack 304 is greater than the total number m of processor cores, the logical stack 304 supports storing at least two idle resources of the same processor core 302.

Optionally, each resource request carries an identifier, and the identifier is used to indicate the processor core that sends the resource request. The identifier may include, but is not limited to, the name of the processor core, the identity ID, and other information. Correspondingly, after the logic stack 304 receives the resource request sent by the processor core 302, it can automatically identify the identifier carried in the resource request to record the identifier of the processor core corresponding to the resource request. Further, the logic stack 304 can determine whether to store the resource request in the logic stack 304 according to the identifier carried in the resource request. For details, please refer to the foregoing description of storage according to the storage capacity of the logic stack 304. The number n of storage resource requests supported in the logic stack 304 can also be referred to as the depth (or length) of the logic stack 304, which is not limited.

Considering the rationality of resource request processing, the depth n of the logic stack 304 and the total number m of processor cores are usually equal. At this time, only one of the multiple resource requests with the same identifier is allowed to be stored in the logic stack 304. . Specifically, when multiple resource requests are sent by the same processor core, each resource request carries the identifier (cpu_id) of the same processor core. Correspondingly, after the logic stack 304 receives the resource request sent by the same processor core for the first time, it can automatically identify and record the identifier (cpu_id) carried in the resource request, and store the resource request in the logic stack. If the logic stack 304 subsequently receives the resource request sent by the same processor core again, it can be directly discarded, and an exception notification message is sent to the same processor core. The exception notification message is used to notify the logic stack 304 that the resource request cannot currently be processed .

The storage order of resource requests in the logic stack 304 is not limited. Exemplarily, the storage order of resource requests in the logic stack 304 is related to the order in which the logic stack 304 receives each resource request, and the specific implementation of the logic stack 304 storing resource requests is not limited. For example, the logic stack 304 may store according to the receiving time of each resource request. Illustratively, the resource request received earliest may be stored in the logic stack 304 first, and the resource request received last may be stored in the logic stack 304 last. Alternatively, the logic stack 304 may be stored according to the priority of each resource request. For example, a resource request with a higher priority is stored in the logic stack 304 first, and a resource request with a lower priority is stored secondly. Alternatively, the logic stack 304 can be stored according to the service level of each resource request. For example, the resource request with a higher service level is stored in the logic stack 304 first, and then the resource request with a lower service level is stored. This application does not limit it. .

In practical applications, the logic stack 304 may specifically include, but is not limited to, the first in first out unit (FIFO) logic stack, the last in first out unit (LIFO) logic stack, and the low latency logic Stack and user-defined logic stack, etc. This application will take the logic stack as the FIFO logic stack as an example to explain the relevant content. The first-in-first-out FIFO design can ensure that the first-in-first-out resource request in the logic stack 304 is preferentially popped out, thereby realizing resource request polling And fairness of processing.

In order to ensure the logic of resource request processing, the communication system (specifically, the logic stack 304 or the resource allocation logic circuit 306) supports the processing of a single resource request in the same working clock cycle. Specifically, in the same working clock cycle, the logic stack 304 only supports the pushing or popping of one resource request, and the resource allocation logic circuit 306 supports allocating logic resources for one resource request. Among them, the working clock period refers to the period of time consumed for processing a single resource request. Please refer to FIG. 4 showing a schematic diagram of the storage of a logic stack 304. The logic stack 304 shown in FIG. 4 stores resource requests of four CPUs, which may be specifically one resource request of each of CPU1 to CPU4 in the figure. Wherein, in the same working clock cycle, the logic stack 304 only allows one CPU's resource request to be pushed into or out of the stack, so as to realize the in-stack storage or out of the stack processing of the resource request.

The resource allocation logic circuit 306 is used to process the resource request in the logic stack 304 and allocate available idle resources for the resource request. Optionally, the resource allocation logic circuit 306 is also used to query whether there are available idle resources among the k resources 310. Specifically, when the resource allocation logic circuit 306 detects that the target resource request is popped from the logic stack 304, the resource allocation logic circuit 306 can receive the target resource request popped from the logic stack 304, and can further query whether there is currently available If the idle resource exists, the queried idle resource can be used as the target logical resource to be allocated to the target processor core that sends the target resource request.

In practical applications, the resource allocation logic circuit 306 can be implemented by, for example, an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex program logic device. (complex programmable logical device, CPLD), field-programmable gate array (field-programmable gate array, FPGA), generic array logic (generic array logic, GAL) or a combination of hardware resource implementation. In actual product deployment, the resource allocation logic circuit 306 is hardware logic independent of the m processor cores, that is, the resource allocation logic circuit 306 can be deployed independently of the m processor cores.

Optionally, the resource request sent by the processor core may also carry attribute information of the processor core. The attribute information refers to the information used to describe the attributes of the processor core, for example, it may include but not limited to the identifier of the processor core, the type of service supported by the processor core, the quality of service (QOS) index, the service level or Other attribute information, etc. Among them, the service quality indicators include but are not limited to delay, throughput, loss rate, priority, or other indicators used to affect service communication quality. The service level includes but is not limited to the QOS level and the class of service (COS) level, which can also be referred to as the QOS service level and COS service level for short. Among them, the QOS service level is mainly divided according to bandwidth or transmission time. For example, the larger the bandwidth required for processor core business communication, the higher the QOS service level of the processor core; conversely, the processor core business communication requires The smaller the bandwidth, the lower the QOS service level of the processor core. The COS service level usually refers to the transmission priority of traffic. For example, the COS service level of the processor core here may be the priority of data transmission required when the processor core supports business communication.

Correspondingly, after the resource allocation logic circuit 306 receives the resource request sent by the processor core, it can allocate the matching idle resources to the processor core according to the attribute information in the resource request. For example, when the attribute information is a service type supported by the processor core, after receiving the resource request, the resource allocation logic circuit 306 can query whether there are idle resources corresponding to the communication service supporting the processing of the service type among the k resources 310, For use by the processor core. When the attribute information is other attribute information of the processor core, similarly, after the resource allocation logic circuit 306 receives the resource request, it can query whether there are idle resources meeting the requirements of the other attribute information among the k resources 310 for the processor Nuclear use.

The protection lock 308 is used to protect the resource 310, specifically, it is used to lock the resource 310, for example, to lock the communication portal that accesses the resource. The number of the protection locks 308 is not limited. The same protection lock can be used to lock and protect one or more resources 310, and each resource 310 can be protected by one protection lock 308. In the figure, k resources 310 are used to lock and protect k protection locks 308 as an example. The resource 310 and the protection lock 308 are in a one-to-one correspondence, that is, one resource is locked to one protection lock.

In practical applications, the protection lock 308 may be a software lock or a hardware lock. Among them, the software lock is realized by software or program code. The hardware lock can be implemented by hardware logic circuits, dedicated hardware integrated circuits, or hardened hardware cores.

The resource 310 is a resource used by the m processor cores provided by the communication system 300, and the resource may be a hardware logic resource or a data resource, which is not limited. The number of the resources is also not limited, and it can be one or more. In the figure, k resources are taken as an example, and each resource needs a protection lock for security protection. In actual applications, when the resource allocation logic circuit 306 receives the resource request sent by the processor core, it can query from the k resources whether there are idle resources that are not used or preempted. If an idle resource is queried, the resource allocation logic circuit 306 can automatically issue a lock grab command to grab the protection lock corresponding to the idle resource. It is convenient to subsequently use the protection lock to unlock the idle resources, so that the processor core corresponding to the resource request can use the unlocked idle resources. In other words, the processor core can access and use idle resources based on the protection lock.

Optionally, after the resource allocation logic circuit 306 preempts the protection lock, it may also send the preemption result to the processor core through an interrupt response to notify that the protection lock has been successfully preempted. Optionally, after the resource allocation logic circuit 306 has processed the resource request sent by the processor core, the resource allocation logic circuit 306 may also send a resource response to the processor core. The resource response is used to notify whether the current free resource is successfully seized. (Or the protection lock corresponding to free resources). Specifically, when the resource allocation logic circuit 306 finds that there is an idle resource corresponding to the resource request, the resource allocation logic circuit 306 may return the first resource response to the processor core in an interrupt mode, and the first resource response is used In order to notify that the idle resource has been successfully seized, it can optionally also be used to notify that the protection lock corresponding to the idle resource has been successfully seized. When the resource allocation logic circuit 306 does not inquire about the existence of idle resources required by the resource request, the resource allocation logic circuit 306 can end the process; or the second resource response can still be returned to the processor core in an interrupt mode. The second resource response is used to notify that the idle resource has not been successfully preempted at present and wait for the next preemption.

In practical applications, any one or more of the m processor cores 302 may be deployed separately or in the same device. Illustratively, taking the independent deployment of m processor cores as an example, the m processor cores may be correspondingly deployed in m host devices, and each host device has a processor core deployed. Taking the common deployment of at least two of the m processor cores as an example, the at least two processor cores may be deployed in the same host device. The host device includes but is not limited to processor CPU, controller, mobile phone, tablet computer (table personal computer), personal digital assistant (personal digital assistant, PDA), mobile internet device (mobile internet device, MID), wearable device (wearable device), in-vehicle equipment, and other devices that support network communication.

The logic stack 304 and the resource allocation logic circuit 306 may be deployed in the same device, specifically in the same device as the processor core, or in another device different from the processor core. Illustratively, taking the logic stack 304 and the resource allocation logic circuit 306 deployed to slave devices other than m processor cores as an example, the logic stack 304 and the resource allocation logic circuit 306 can both be deployed to the slave device Among them, the slave device includes but is not limited to mobile phones, tablet computers (table personal computers), personal digital assistants (personal digital assistants, PDAs), mobile internet devices (MIDs), and wearable devices (wearable devices) , In-vehicle equipment and other equipment supporting network communication.

The protection lock 308 and the resource 310 can be deployed in the same device, which can be different from the device deployed by the logic stack 304 and the resource allocation logic circuit 306, or can be deployed to be the same as the logic stack 304 and the resource allocation logic circuit 306. In the equipment, the present invention is not limited. Exemplarily, the protection lock 308 and the resource 310 can be deployed in the above slave device. For details, please refer to FIG. 5 which shows another communication system of the present invention. The communication system as shown in FIG. 5 includes m host devices 502 and slave devices 504. Each host device 502 has a processor core 302 deployed, and the slave device 404 has a logic stack 304 and a resource allocation logic circuit 306. , K protection locks 308 and k resources 310. Regarding the hardware or components deployed in the device, refer to the relevant description in the embodiment of FIG. 3 for details, which will not be repeated here.

Based on the foregoing embodiments, specific embodiments related to resource acquisition of the present invention are described below. Refer to FIG. 6, which is a schematic flowchart of a resource acquisition method provided by an embodiment of the present invention. The method shown in FIG. 6 may include the following implementation steps:

Step S602: The processor core 302 sends a resource request to the logic stack 304, where the resource request is used to request logic resources for the processor core 302. Accordingly, the logic stack 304 receives the resource request.

In this application, any one of the m processor cores 302 may send a resource request when there is a resource usage requirement. For example, when an application program needs to use logic resources, it can send a resource request through the processor core CPU where the application program is running. After the resource request is sent, the control or occupation right of the processor core CPU can be automatically released , In order to reduce CPU usage by applications and increase CPU usage.

Step S604: The logic stack 304 receives at least one resource request, and stores the at least one resource request in the logic stack 304. Among them, each resource request is sent by one processor core, and there is a one-to-one correspondence between the resource request and the processor core.

The logic stack 304 can receive a resource request sent by any one of the m processor cores. Similarly, when multiple processor cores among the m processor cores send resource requests, the logic stack 304 may receive at least one resource request, and the at least one resource request is for at least one processor among the m processor cores. Each resource request is sent by one processor core, and the same processor core can send one or more resource requests. Further, the logic stack 304 may store at least one resource request received in the logic stack 304. Regarding the specific implementation manner of storing the resource request in the logic stack 304, the present invention does not limit it.

Exemplarily, after the logic stack 304 receives the resource request sent by any processor core 302, the resource request of any processor core 302 can be stored in the logic stack 304 according to a preset storage rule. The preset storage rule is customized by the system and used to determine the storage location and storage sequence of resource requests in the logic stack 304. For example, the preset storage rule may be the time sequence of resource request reception, or resource request transmission The order of priority and so on.

For example, FIG. 7 shows a specific storage schematic diagram of a logic stack 304. As shown in Figure 7, taking 4 processor cores (CPUs) sending a resource request as an example, the four CPUs are CPU1 to CPU4. The order in which the four CPUs send resource requests is: CPU1, CPU3, CPU4, and CPU2. Correspondingly, the logic stack 304 can store the resource requests of the four CPUs in the logic stack 304 according to the sequence of the receiving time of the resource request. Exemplarily, the logic stack 304 first receives the resource request of CPU1, and first writes the resource request of CPU1 to the logic stack 304 for storage; then, receives the resource request of CPU3, and writes the resource request of CPU3 to Stored in the logic stack 304, and so on, the logic stack 304 finally receives the resource request of the CPU2, and finally writes the resource request of the CPU2 to the logic stack 304 for storage.

Optionally, any resource request carries an identifier, and the identifier is used to indicate the processor core to which the any resource request belongs, that is, the processor core that sends the any resource request. After the logic stack 304 receives any resource request, it can obtain the identifier carried in the resource request by parsing the resource request. Then, according to the identifier carried in the resource request, it is determined whether to store the resource request in the logic stack 304. Specifically, when the storage capacity of the logic stack 304 supports the storage of m resource requests, after the logic stack 304 identifies the identifier carried in the resource request, only one resource request with the identifier is allowed to be stored in the logic stack 304. If a resource request with the identifier is already stored in the logic stack 304, the received resource request can be directly discarded at this time, and an exception message is sent to the processor core to which the resource request belongs to notify the logic stack 304 that it cannot currently store or process The resource request. If no resource request with the identifier is stored in the logic stack 304, the received resource request may be stored in the logic stack 304.

When the storage capacity of the logic stack 304 supports the storage of n resource requests, and n is greater than m, the logic stack 304 can determine whether to store the received resource request according to its own storage capacity. For example, there is currently a remaining storage capacity in the logic stack 304 that is sufficient to support By storing the received resource request, the received resource request can be stored in the logic stack 304. In this case, the logic stack 304 supports storing at least two resource requests of a certain processor core (for example, the first processor core), and the first processor core is any one of the m processor cores. .

Step S606: After the target resource request is popped from the logic stack 304, the resource allocation logic circuit 306 allocates the target logic resource for the target resource request. Wherein, logic resources are allocated to only one resource request in one working clock cycle, and the target resource request refers to the resource request with the highest priority in the logic stack 304.

In this application, after the logic stack 304 stores any received resource request into the logic stack 304, the resource request in the logic stack 304 can be processed according to a preset mechanism. The preset mechanism can be self-defined by the system, such as a FIFO mechanism. The logic stack 304 supports the in-stack storage and out-stack processing of a resource request in each working clock cycle. In this application, the target resource request in the logic stack 304 is taken as an example to describe the related content. The target resource request may be the resource request with the highest priority in the logic stack 304. Specifically, when the target resource request is popped from the logic stack 304, the resource allocation logic circuit 306 may allocate the target logic resource to the target resource request for use by the target processor core that sends the target resource request.

In a specific implementation, the logic stack 304 may perform popping processing on the target resource request according to a preset rule, so as to send the target resource request to the resource allocation logic circuit 306 for processing. Correspondingly, after the resource allocation logic circuit 306 receives the target resource request, it can respond to the target resource request to query whether there are free resources for the target processor core. The specific resource allocation logic circuit 306 can query whether there are k resources 310 There are idle resources, and the idle resources refer to resources that are not used or preempted. If there is an idle resource, the resource allocation logic circuit 306 may use the idle resource as a target logic resource and allocate it to the target processor core.

Optionally, the resources involved in this application may refer to resources that meet the requirements of different communication services. After the resource allocation logic circuit 306 receives the target resource request, it needs to allocate corresponding target logic resources to the target processor core according to the actual business requirements of the target processor core. Exemplarily, the target resource request carries attribute information of the target processor core, and the attribute information is information used to describe the attributes of the target processor core, which may include, but is not limited to, quality of service QOS indicators, QOS service levels, COS Information such as service level, identification, and business type. After receiving the target resource request, the resource allocation logic circuit 306 can respond to the target resource request and query whether there is an idle resource that matches the attribute information of the target processor core. If it exists, the resource allocation logic circuit 306 may use the idle resource as a target logic resource and allocate it to the target processor core for use. If it does not exist, the resource allocation logic circuit 306 can end the process; or, send a notification message to the target processor core, the notification message is used to notify the resource allocation logic circuit 306 that the target processor core cannot currently allocate the target logic resource, and there is no available Free resources.

For example, take the attribute information of the target processor core as a network delay of 100 ms as an example. After the resource allocation logic circuit 306 receives the resource request sent by the target processor core, the resource request of the target processor core carries a network delay of 100 ms. The resource allocation logic circuit 306 can respond to the resource request and query whether there is an idle resource within 100ms of the network delay that supports the processing of the communication service. If it exists, the idle resource is allocated to the target processor core for use, that is, the idle resource As the resource allocation logic circuit 306, the target logic resource allocated to the target processor core is used.

Optionally, the resource allocation logic circuit 306 may send a resource response to the target processor core after responding to the target resource request, and the resource response may be used to notify whether the target logic resource has been successfully preempted or allocated for the target processor core.

Step S608: The resource allocation logic circuit 306 automatically preempts the target protection lock corresponding to the target logic resource according to the target resource request, wherein the target processor core accesses the target logic resource based on the target protection lock, and the target processor core refers to sending the target resource The requested processor core.

Step S610: The resource allocation logic circuit 306 reports the lock grab result to the target processor core through an interrupt response, where the lock grab result is used to indicate that the target protection lock is successfully seized.

In order to improve the processing efficiency of resource acquisition, the resource allocation logic circuit 306 can also automatically preempt the target protection lock corresponding to the target logic resource after assigning the target logic resource to the target processor core, so that the target processor core can access based on the target protection lock The target logic resource, and then use the target logic resource. Further, the resource allocation logic circuit 306 may report the lock grab result to the target processor core through an interrupt response, and the lock grab result is used to indicate that the target protection lock is successfully seized.

Step S612: The target processor core receives the lock grab result, and obtains the target protection lock according to the lock grab result, so as to access and use the target logical resource based on the target protection lock.

The target processor core receives the lock grab result reported by the resource allocation logic circuit 306, and can further read the target protection lock indicated by the lock grab result from a preset register based on the lock grab result, and then access the target based on the target protection lock Logical resource to use the target logical resource. In other words, after the target processor core receives the lock preemption result, it can directly use the target protection lock to access and use the target logical resources. It is no longer necessary to configure the preemption protection lock through the target processor core (such as CPU) as in the traditional technology. Command to preempt the protection lock. Compared with traditional technology, it can greatly simplify the process of resource acquisition, save time, reduce CPU usage, and improve CPU utilization.

Optionally, when the target processor core uses the target logical resource, the target processor core may update the status of the target logical resource. For example, update the status of the target logical resource to occupied, indicating that the target logical resource is currently Is being used, in an occupied state. After the target processor core has used the target logical resource, the target logical resource can be released, and then the state of the target processor is updated to idle, which means that the target logical resource is not used and is in an idle state.

Considering the application scenarios of resource request withdrawal, such as misoperation, or temporarily not requesting idle resources for the host device, etc., this application proposes another resource acquisition method process. The resource acquisition method described in FIG. 8 may include the following implementation steps:

Step S802: The processor core 302 sends a cancel command for the first resource request to the logic stack 304, where the first resource request is any resource request in at least one resource request. Correspondingly, the logic stack 304 receives the cancel command for the first resource request.

In this application, after any one of the m processor cores sends a corresponding resource request, if any one of the processor cores does not want to apply for logic resources for any one of the processor cores, then any one of the processor cores will be processed The processor core may send a revocation command to the logic stack 304, and the revocation command is used to request the revocation of the resource request of any processor core, that is, the processing of the logic stack 304 on the resource request of any processor core is withdrawn. This application uses the first resource request as an example to describe the relevant content. Specifically, after sending the first resource request, the processor core 302 to which the first resource request belongs wants to temporarily cancel the processing of the first resource request due to special reasons. In order to realize the temporary cancellation of the first resource request, the present invention is logically The stack 304 has a newly added queue-insertion and de-stack mechanism, which can only be initiated by the cancel command for the first resource request. For example, when the processor core 302 to which the first resource request belongs wants to cancel the first resource request, it can send a cancel command for the first resource request to the logic stack 304. Correspondingly, the logic stack 304 can receive the cancel command, and the first resource request can be any one of the at least one resource request sent by the m processor cores. The resource request corresponding to the cancel command can be deleted according to the cancel command, and the storage order of the resource request in the logical stack can be ignored, and the queue can be removed from the stack.

Step S804: According to the cancel command, the logic stack 304 performs queue insertion and ejection processing on the first resource request stored in the logic stack 304 to delete the first resource request.

Step S806: After deleting the first resource request, the resource allocation logic circuit 306 may report the cancellation result to the processor core 302 corresponding to the first resource request through an interrupt response. The cancellation result is used to indicate that the logic stack 304 has completed the cancellation of the first resource request.

After the logic stack 304 receives the cancel command, it can respond to the cancel command to insert and pop the first resource request stored in the logic stack 304 to delete the first resource request from the logic stack 304, so that the first resource request is no longer A resource request for logical resource allocation processing. Optionally, after deleting the first resource request, the resource allocation logic circuit 306 can report the cancellation result to the processor core to which the first resource request belongs through an interrupt response, where the cancellation result is used to indicate that the logic stack 304 has successfully completed the Cancellation of the first resource request.

For example, referring to the example described in FIG. 7, suppose that after the CPU3 sends the resource request of the CPU3, it wants to temporarily withdraw the resource request of the CPU3. Then, the CPU3 can send the cancel command of the CPU3 to the logic stack 304, and the cancel command is used to request to cancel the resource request of the CPU3, and the logic stack 304 is not processing the resource request of the CPU3. Correspondingly, after the logic stack 304 receives the cancel command of the CPU3, it needs to update the respective resource requests of the four CPUs stored in the logic stack 304, so that the resource request of CPU3 can be inserted and removed from the stack, and the resources of the CPU3 are deleted and withdrawn. For details of the request, refer to FIG. 9 showing a schematic diagram of the logic stack 304 being inserted from the queue.

By implementing the embodiments of the present invention, it is possible to solve the problem that a certain CPU that exists in the process of multi-CPU preempting resources through multi-threading in the traditional technology is difficult to preempt resources, thereby affecting the normal business communication and business performance of the CPU. The present invention adopts a logic stack to process the resource requests of each CPU in the stack one by one to ensure the fairness and rationality of the CPU's preemption of resources, and avoid the problems that some CPUs are difficult to preempt resources in the traditional technology.

With reference to the relevant explanations in the embodiments described in Figs. 1-9, the relevant devices and systems involved in the present invention are described below. Refer to FIG. 10, which is a schematic structural diagram of a communication device 1000 according to an embodiment of the present invention. The communication device 1000 shown in FIG. 10 includes a logic stack 1004 and a resource allocation logic circuit 1006. Optionally, the communication device may further include a processor core 1002, the number of the processor core 1002 is not limited, and there may be one or more. among them:

The logic stack 1004 is configured to receive at least one resource request and store the at least one resource request in the logic stack 1004, wherein each resource request is sent by a processor core 1002, and the resource request and There is a one-to-one correspondence between the processor cores, and the resource request is used to request logical resources for the corresponding processor cores;

The resource allocation logic circuit 1006 is configured to allocate a target logic resource to a target resource request, and allocate logic resources to only one resource request within a working clock cycle, wherein the target resource request refers to being located in the logic stack 1004 And has the highest priority resource request.

In some possible embodiments, the resource allocation logic circuit 1006 is specifically configured to query whether there are idle resources for the target processor core after receiving the target resource request; when the idle resources are inquired, the The idle resource is allocated to a target processor core as the target logical resource, and the target processor core refers to a processor core that sends the target resource request.

In some possible embodiments, after the resource allocation logic circuit 1006 allocates the idle resource as the target logic resource to the target processor core, the resource allocation logic circuit 1006 is further configured to Request to automatically preempt the target protection lock corresponding to the target logic resource, wherein the target processor core accesses the target logic resource based on the target protection lock; and report the lock grab result to the target processor core through an interrupt response, The lock preemption result is used to indicate that the target protection lock has been successfully preempted.

In some possible embodiments, each resource request carries an identifier, and the identifier is used to indicate the processor core to which the corresponding resource request belongs, and the logic stack 1004 is also used to, after receiving a resource request, Determine the identifier carried in the resource request; determine whether to store the resource request in the logic stack according to the identifier carried in the resource request.

In some possible embodiments, the storage capacity of the logical stack 1004 supports storage of n resource requests, and the total number of processor cores is m, and n=m, then the logical stack 1004 only allows the m One resource request of each processor core in the two processor cores is stored in the logic stack 1004.

In some possible embodiments, the storage capacity of the logic stack 1004 supports storage of m resource requests, and the total number of the processor cores is m, then the logic stack 1004 only allows multiple resources with the same identifier A resource request in the request is stored in the logic stack.

In some possible embodiments, the storage capacity of the logical stack 1004 supports storage of n resource requests, and the total number of processor cores is m and n is greater than m, then the logical stack 1004 allows the first processor At least two resource requests of the cores are stored in the logic stack, and the first processor core is any one of the m processor cores.

In some possible embodiments, the logic stack 1004 is a first-in first-out unit FIFO logic stack.

In some possible embodiments, the resource allocation logic circuit 1006 is independent of the processor core 1002.

In some possible embodiments, the processor core 1002 is deployed in the communication device 1000.

In some possible embodiments, the logic stack 1004 is further configured to receive a cancel command for a first resource request, where the first resource request is any one of the at least one resource request; according to the cancel command, Deleting the first resource request stored in the logic stack.

In some possible embodiments, after deleting the first resource request, the resource allocation logic circuit 1006 is further configured to report the cancellation result to the processor core corresponding to the first resource request through an interrupt response, where The cancellation result is used to indicate that the logic stack has completed the cancellation of the first resource request.

In practical applications, each component involved in the communication device in the embodiment of the present invention can be implemented by hardware, for example, it can be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (programmable logic device, PLD), the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof Implementation is not limited in the present invention.

It should be noted that FIG. 10 is only a possible implementation of the embodiment of the present application. In actual applications, the communication device may also include more or fewer components, which is not limited here. Regarding the content not shown or described in the embodiment of the present invention, reference may be made to the relevant description in the foregoing method embodiment, which is not repeated here.

By implementing the embodiments of the present invention, it is possible to solve the problem that a certain CPU in the traditional technology is difficult to seize resources, thereby affecting the normal business communication and business performance of the CPU.

Refer to FIG. 11, which is a schematic structural diagram of a communication device according to an embodiment of the present invention. The communication device 110 shown in FIG. 11 includes one or more processors 1101, a communication interface 1102, and a memory 1103. Among them, a logic stack and a resource allocation logic circuit are deployed in the processor 1101. Optionally, any one or more of the m processor cores (not shown) may be deployed in the processor 1101, and the processor core may also be deployed outside the processor 1101 in actual applications , Is not limited. Among them, the processor 1101, the communication interface 1102, and the memory 1103 may be connected via a bus, or communication may be achieved by other means such as wireless transmission. The embodiment of the present invention takes the connection via the bus 1104 as an example, where the memory 1103 is used to store instructions, and the processor 1101 is used to execute instructions stored in the memory 1103. The memory 1103 stores program codes, and the processor 1101 can call the program codes stored in the memory 1103 to implement the implementation steps in the method embodiments shown in FIGS. 1 to 9 and/or other content described in the text. I won’t go into details here.

Optionally, the processor 1101 may be composed of one or more general-purpose processors, such as a controller and a central processing unit (CPU). The processor 1101 is configured to run related program codes by calling the deployed related hardware to implement the related descriptions in the embodiments shown in FIG. 1 to FIG. 9, which will not be repeated here.

It should be understood that the communication interface 1102 may be a wired interface (for example, an Ethernet interface) or a wireless interface (for example, a wireless fidelity (WiFi) interface), which is used to communicate with other modules or devices. For example, the communication interface 1102 in the embodiment of the present application may be specifically used to receive a resource request sent by a processor core.

The memory 1103 may include volatile memory (Volatile Memory), such as random access memory (Random Access Memory, RAM); the memory may also include non-volatile memory (Non-Volatile Memory), such as read-only memory (Read-Only Memory). Memory, ROM, Flash Memory, Hard Disk Drive (HDD), or Solid-State Drive (SSD); the memory 1103 may also include a combination of the foregoing types of memories. The memory may be used to store a group of program codes, so that the processor can call the program codes stored in the memory to implement relevant steps involved in the embodiments of the present invention.

It should be noted that FIG. 11 is only a possible implementation of the embodiment of the present application. In actual applications, the communication device may also include more or fewer components, which is not limited here. Regarding the content not shown or described in the embodiment of the present invention, reference may be made to the relevant description in the foregoing method embodiment, which is not repeated here.

The embodiment of the present invention also provides a communication system, which includes m processor cores, a logic stack, and a resource allocation logic circuit. Optionally, it may also include protection locks and resources. Wherein, when the processor core is deployed in the host device, and the logic stack, resource allocation logic circuit, protection lock, and resources are deployed in the slave device, the communication system may specifically include m host devices and slave devices. Regarding the relevant description of the communication system, please refer to the relevant description in the embodiment of FIG. 1 for details, which will not be repeated here.

The embodiment of the present invention also provides a computer-readable storage medium that stores instructions in the computer-readable storage medium, and when it runs on a communication device, the method flow shown in the embodiment of FIG. 6 or FIG. 8 can be realized .

The embodiment of the present invention also provides a computer program product. When the computer program product runs on a communication device, the method flow shown in the embodiment of FIG. 6 or FIG. 8 is realized.

The steps of the method or algorithm described in combination with the disclosure of the embodiments of the present invention may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions. Software instructions can be composed of corresponding software modules, which can be stored in random access memory (English: Random Access Memory, RAM), flash memory, read-only memory (English: Read Only Memory, ROM), erasable and programmable Read-only memory (English: Erasable Programmable ROM, EPROM), electrically erasable programmable read-only memory (English: EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM, or well-known in the art Any other form of storage medium. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in the ASIC. In addition, the ASIC may be located in the communication device. Of course, the processor and the storage medium may also exist as separate components in the communication device.

A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing relevant hardware through a computer program. The program can be stored in a computer readable storage medium. When executed, it may include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM, RAM, magnetic disks or optical disks and other media that can store program codes.

Claims

A resource acquisition method, characterized in that the method includes:

Receiving at least one resource request, and storing the at least one resource request in the logic stack, each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core, The resource request is used to request logic resources for the corresponding processor core;

A target logical resource is allocated to a target resource request, and logical resources are allocated to only one resource request within a working clock cycle, where the target resource request refers to a resource request with the highest priority located in the logical stack.
The method according to claim 1, wherein the allocating logical resources for the target resource request comprises:

After receiving the target resource request, query whether there are free resources for the target processor core;

When an idle resource is inquired, the idle resource is allocated to the target processor core as the target logical resource, and the target processor core refers to the processor core that sends the target resource request.
The method according to claim 2, wherein after allocating the idle resource as the target logical resource to the target processor core, the method further comprises:

Automatically preempting the target protection lock corresponding to the target logic resource according to the target resource request, wherein the target processor core accesses the target logic resource based on the target protection lock;

The lock grab result is reported to the target processor core through an interrupt response, where the lock grab result is used to indicate that the target protection lock has been successfully seized.
The method according to any one of claims 1-3, wherein each resource request carries an identifier, and the identifier is used to indicate the processor core to which the corresponding resource request belongs, and the method further comprises :

After receiving a resource request, determine the identifier carried in the resource request;

According to the identifier carried in the resource request, it is determined whether to store the resource request in the logic stack.
The method according to any one of claims 1 to 4, wherein the storage capacity of the logical stack supports storage of n resource requests, the total number of processor cores is m and n=m, then The logic stack allows only one resource request of each of the m processor cores to be stored in the logic stack.
The method according to claim 4, wherein the storage capacity of the logical stack supports the storage of m resource requests, and the total number of the processor cores is m, then the logical stack only allows those with the same identifier One of the multiple resource requests is stored in the logic stack.
The method according to any one of claims 1 to 4, wherein the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n>m, then The logic stack allows at least two resource requests of the first processor core to be stored in the logic stack, and the first processor core is any one of the m processor cores.
The method according to any one of claims 1-7, wherein the logic stack is a first-in first-out unit FIFO logic stack.
The method according to any one of claims 1-8, wherein the method further comprises:

Receiving a cancellation command for a first resource request, where the first resource request is any one of the at least one resource request;

According to the cancel command, the first resource request stored in the logic stack is deleted.
The method according to claim 9, characterized in that, after deleting the first resource request, the method further comprises:

The cancellation result is reported to the processor core corresponding to the first resource request through an interrupt response, where the cancellation result is used to indicate that the logic stack has completed the cancellation of the first resource request.
A communication device, which is characterized by comprising a logic stack and a resource allocation logic circuit, wherein:

The logic stack is configured to receive at least one resource request and store the at least one resource request in the logic stack, wherein each resource request is sent by a processor core, and the resource request and the processing There is a one-to-one correspondence between the processor cores, and the resource request is used to request logical resources for the corresponding processor core;

The resource allocation logic circuit is used to allocate a target logic resource for a target resource request, and allocate logic resources for only one resource request within a working clock cycle, wherein the target resource request refers to the logic stack and has The highest priority resource request.
The device according to claim 11, wherein the resource allocation logic circuit is specifically configured to:

After receiving the target resource request, query whether there are free resources for the target processor core;

When an idle resource is found, the idle resource is allocated to a target processor core as the target logical resource, and the target processor core refers to the processor core that sends the target resource request.
The apparatus according to claim 12, wherein after the resource allocation logic circuit allocates the idle resource as the target logic resource to the target processor core, the resource allocation logic circuit is further configured to:

Automatically seize the target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock;

The lock grab result is reported to the target processor core through an interrupt response, where the lock grab result is used to indicate that the target protection lock has been successfully seized.
The device according to any one of claims 11-13, wherein each resource request carries an identifier, and the identifier is used to indicate the processor core to which the corresponding resource request belongs, and the logical stack also Used for:

After receiving a resource request, determine the identifier carried in the resource request;

According to the identifier carried in the resource request, it is determined whether to store the resource request in the logic stack.
The device according to any one of claims 11-14, wherein the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n=m, then The logic stack allows only one resource request of each of the m processor cores to be stored in the logic stack.
The device according to any one of claims 11-14, wherein the storage capacity of the logical stack supports storage of m resource requests, and the total number of processor cores is m, then the logical stack Only one resource request among multiple resource requests with the same identifier is allowed to be stored in the logic stack.
The device according to any one of claims 11-14, wherein the storage capacity of the logical stack supports storage of n resource requests, and the total number of processor cores is m and n is greater than m, then The logic stack allows at least two resource requests of the first processor core to be stored in the logic stack, and the first processor core is any one of the m processor cores.
The device according to any one of claims 11-17, wherein the logic stack is a first-in first-out unit FIFO logic stack.
The device according to any one of claims 11-18, wherein the resource allocation logic circuit is independent of the processor core.
The device according to any one of claims 11-19, wherein the device further comprises: a plurality of the processor cores.
The device according to any one of claims 11-20, wherein the logical stack is further used for:

Receiving a cancellation command for a first resource request, where the first resource request is any one of the at least one resource request;

According to the cancel command, the first resource request stored in the logic stack is deleted.
The device according to claim 21, wherein after the logic stack deletes the first resource request, the resource allocation logic circuit is configured to:

The cancellation result is reported to the processor core corresponding to the first resource request through an interrupt response, where the cancellation result is used to indicate that the logic stack has completed the cancellation of the first resource request.