WO2020215872A1

WO2020215872A1 - Array substrate and display device

Info

Publication number: WO2020215872A1
Application number: PCT/CN2020/076248
Authority: WO
Inventors: 冯雪欢; 吴思翔
Original assignee: 京东方科技集团股份有限公司; 合肥京东方卓印科技有限公司
Priority date: 2019-04-24
Filing date: 2020-02-21
Publication date: 2020-10-29
Also published as: CN110061035A

Abstract

Provided are an array substrate and a display device. The array substrate comprises: a base, a drive circuit and N rows of light-emitting units, wherein the drive circuit is arranged on the base, and the N rows of light-emitting units are arranged on one side, away from the base, of the drive circuit. The drive circuit comprises: N rows of drive circuit units and a plurality of first scanning signal lines (Gn-1, Gn, Gn+1); the projection of the first scanning signal line (Gn) on the base is located in a first area; the first area is an area between the projection of the first row of light-emitting units (Pn) in any two adjacent rows of light-emitting units among the N rows of light-emitting units on the base and the projection of the second row of light-emitting units (Pn+1) on the base; and a gate electrode of a second transistor (T2) of the first row of drive circuit units and a gate electrode of a first transistor (T1) of the second row of drive circuit units are connected to the first scanning signal line (Gn).

Description

Array substrate and display device

Cross references to related applications

This application claims the priority of the Chinese patent application No. 201910333288.7 filed on April 24, 2019, and the content of the above-mentioned Chinese patent application is quoted here in full as a part of this application.

Technical field

The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.

Background technique

With the development and progress of technology, OLED display devices have been widely used in various electronic products, and electronic products have increasingly higher requirements for display quality and screen ratio of display devices. In a display device, a pixel unit is usually driven to emit light through a driving circuit to display a picture. The driving circuit includes a large number of signal lines, such as source lines and gate lines.

It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

Summary of the invention

The purpose of the present disclosure is to provide an array substrate and a display device.

According to an aspect of the present disclosure, there is provided an array substrate, the array substrate including:

Substrate

A plurality of light-emitting units arranged on the substrate, including a first light-emitting unit arranged on the nth row and a second light-emitting unit arranged on the n+1th row;

A plurality of driving circuit units are arranged on the substrate, including a first driving circuit unit arranged in the nth row and connected to the first light-emitting unit, and a first driving circuit unit arranged in the n+1th row and connected to the second light-emitting unit A second driving circuit unit of the unit, each of the plurality of driving circuit units includes a first transistor and a second transistor;

The first scan signal line, the projection of the first scan line on the substrate is located at the projection of the first light-emitting unit on the substrate and the projection of the second light-emitting unit on the substrate In between, the gate of the second transistor of the first driving circuit and the gate of the first transistor of the second driving circuit are connected to the first scan signal line;

Wherein, the first driving circuit unit precedes the second driving circuit unit during scanning, and n is a positive integer and n≥2. According to an embodiment of the present disclosure, the driving circuit further includes:

The second scanning signal line, whose projection on the substrate is located on the first side of the projection of the light-emitting unit on the substrate in the starting row, is connected to the first of the driving circuit unit in the scanning starting row The gate of the transistor;

The third scan signal line, whose projection on the substrate is located on the second side of the projection of the light-emitting unit on the substrate in the end row, is connected to the second transistor of the drive circuit unit in the scan end row The gate, wherein the first side is the side of the light-emitting unit projected on the substrate close to the scanning start line, and the second side is the side of the light-emitting unit projected on the substrate close to the scanning end line side.

According to an embodiment of the present disclosure, the driving circuit unit includes:

The driving transistor includes a gate, a source and a drain, the source of which is connected to the first power signal, and the pixel electrode of the light-emitting unit is connected to the drain of the driving transistor;

The first transistor has a source connected to a data signal, and a drain connected to the gate of the driving transistor, for being turned on in response to the scan signal to transmit the data signal to the gate of the driving transistor;

The source of the second transistor is connected to the drain of the driving transistor, and the drain is connected to the first node, for being turned on in response to a reset control signal to transmit the signal of the first node to the drain of the driving transistor. pole;

For the energy storage unit, the first terminal is connected to the gate of the driving transistor, and the second terminal is connected to the drain of the driving transistor.

According to an embodiment of the present disclosure, the array substrate further includes:

The reference voltage sub-circuit is connected to the first node for providing a reference voltage;

The compensation detection sub-circuit is connected to the first node and is used to detect the signal of the drain of the driving transistor.

According to an embodiment of the present disclosure, the reference voltage sub-circuit includes:

Reference voltage terminal, used to output reference voltage;

For the first switch unit, a first terminal is connected to the reference voltage terminal, and a second terminal is connected to the first node;

The compensation detection sub-circuit includes:

Detection unit

The second switch unit has a first end connected to the detection unit, and a second end connected to the first node. The detection unit is used to detect a signal from the drain of the driving transistor.

According to an embodiment of the present disclosure, the driving circuit includes:

A first conductive layer, the first scan signal line is provided on the first conductive layer;

The second conductive layer is provided with a data signal line, a first power line, a second power line, and a detection signal line. The source of the first transistor is connected to the data signal line. The source of the driving transistor is connected to the first power line, and the drain of the second transistor is connected to the detection signal line.

According to an embodiment of the present disclosure, an insulating layer is provided between the first conductive layer and the second conductive layer.

According to an embodiment of the present disclosure, the first scan signal line is arranged along a first direction, the data signal line is arranged along a second direction, and the first direction and the second direction intersect.

According to an embodiment of the present disclosure, the projection of the first power line on the substrate is located on one side of the N rows of the light-emitting units on the substrate along the second direction;

The driving circuit also includes a first source connection line, and the projection of one end of the first source connection line on the substrate coincides with the projection of the first power signal line on the substrate. The via is connected to the first power signal line, and the source of the driving transistor is connected to the first source connection line.

According to an embodiment of the present disclosure, the projection of the data signal line on the substrate is located on one side of the corresponding row of the light emitting unit on the substrate along the second direction;

The driving circuit further includes a second source connection line, and the projection of one end of the second source connection line on the substrate coincides with the projection of the data signal line on the substrate and passes through a conductive via Connected to the data signal line, and the source of the first transistor is connected to the second source connection line.

According to an embodiment of the present disclosure, the projection of the detection signal line on the substrate is located on one side of the projection of the corresponding row of the light-emitting units on the substrate;

The driving circuit further includes a drain connection line, and the projection of one end of the drain connection line on the substrate coincides with the projection of the detection signal line on the substrate. The detection signal line is connected, and the drain of the second transistor is connected to the drain connection line.

According to an embodiment of the present disclosure, the light emitting unit includes:

The pixel electrode is connected to the drain of the driving transistor;

A common electrode, connected to the second power line;

The light-emitting layer is located between the pixel electrode and the common electrode.

According to another aspect of the present disclosure, there is provided a display device including the above-mentioned array substrate.

According to another aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:

Forming a plurality of light-emitting units on a base substrate, the plurality of light-emitting units arranged in the first light-emitting unit in the nth row and the second light-emitting unit in the n+1th row;

A plurality of driving circuit units are formed on the substrate, the plurality of driving circuit units including a first driving circuit unit arranged in the nth row and connected to the first light emitting unit and a parallel arrangement arranged in the n+1th row A second driving circuit unit connected to the second light-emitting unit, each of the plurality of driving circuit units including a first transistor and a second transistor;

A first scan signal line is formed on the substrate, and the projection of the first scan line on the substrate is located between the projection of the first light-emitting unit on the substrate and the projection of the second light-emitting unit on the substrate. Between the projections on the substrate, the gate of the second transistor of the first driving circuit and the gate of the first transistor of the second driving circuit are connected to the first scanning signal line;

Wherein, the first driving circuit unit precedes the second driving circuit unit during scanning, and n is a positive integer and n≥2.

According to an embodiment of the present disclosure, the method further includes:

A second scanning signal line is formed on the substrate, and its projection on the substrate is located on the first side of the projection of the light-emitting unit on the substrate in the starting row, and is connected to all the scanning starting rows. The gate of the first transistor of the driving circuit unit;

A third scan signal line is formed on the substrate, and its projection on the substrate is located on the second side of the projection of the light-emitting unit on the substrate in the end row, and is connected to the drive of the scan end row The gate of the second transistor of the circuit unit, wherein the first side is the side of the light-emitting unit projected on the substrate close to the scanning start line, and the second side is the light-emitting unit on the substrate The projection is closer to the side of the scanning end line.

According to an embodiment of the present disclosure, forming the driving circuit unit includes:

Forming a driving transistor and an energy storage unit on the substrate; and

Forming an energy storage unit on the substrate,

Wherein, the transistor includes a gate, a source, and a drain, the source of which is connected to the first power signal, and the pixel electrode of at least one of the plurality of light-emitting units is connected to the drain of the driving transistor,

The source of the first transistor is connected to a data signal, and the drain is connected to the gate of the driving transistor, for being turned on in response to the scanning signal to transmit the data signal to the gate of the driving transistor,

The source of the second transistor is connected to the drain of the driving transistor, and the drain is connected to the first node, for being turned on in response to a reset control signal to transmit the signal of the first node to the drain of the driving transistor. pole,

The first end of the energy storage unit is connected to the gate of the driving transistor, and the second end is connected to the drain of the driving transistor.

Forming a reference voltage sub-circuit on the substrate, connected to the first node for providing a reference voltage;

A compensation detection sub-circuit is formed on the substrate, connected to the first node, and used for detecting the signal of the drain of the driving transistor.

Forming a first conductive layer, and the first scan signal line is provided on the first conductive layer;

A second conductive layer is formed. The second conductive layer is provided with a data signal line, a first power line, a second power line, and a detection signal line, the source of the first transistor is connected to the data signal line, and The source of the driving transistor is connected to the first power line, and the drain of the second transistor is connected to the detection signal line.

According to an embodiment of the present disclosure, the method further includes: forming an insulating layer between the first conductive layer and the second conductive layer.

According to an embodiment of the present disclosure, the first scan signal line is formed to be arranged along a first direction, and the data signal line is formed to be arranged along a second direction, and the first direction and the second direction intersect.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure.

This section provides an overview of various implementations or examples of the technology described in this disclosure, and is not a comprehensive disclosure of the full scope or all features of the disclosed technology.

Description of the drawings

The drawings herein are incorporated into the specification and constitute a part of the specification, show embodiments in accordance with the disclosure, and together with the specification are used to explain the principle of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of an array substrate provided by an exemplary embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a pixel circuit provided by an exemplary embodiment of the present disclosure.

FIG. 3 is a timing diagram of a pixel circuit display mode provided by an exemplary embodiment of the present disclosure.

FIG. 4 is a timing diagram of a pixel circuit compensation mode provided by an exemplary embodiment of the present disclosure.

FIG. 5 is a schematic circuit diagram of a shift register provided by an exemplary embodiment of the present disclosure.

FIG. 6 is a circuit timing diagram of a shift register provided by an exemplary embodiment of the present disclosure.

FIG. 7 is a schematic diagram of the cascade of a shift register provided by an exemplary embodiment of the present disclosure.

FIG. 8 is a schematic flowchart of a method for manufacturing an array substrate provided by an exemplary embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present invention will be comprehensive and complete, and fully convey the concept of the example embodiments To those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used in this specification only for convenience, for example, according to the drawings. The direction of the example described. It can be understood that if the device of the icon is turned over and turned upside down, the component described as "upper" will become the "lower" component. When a structure is “on” another structure, it may mean that a certain structure is integrally formed on another structure, or that a certain structure is “directly” arranged on another structure, or that a certain structure is “indirectly” arranged on another structure through another structure. On other structures.

The terms "a", "a", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "including" and "have" are used to indicate open-ended The inclusive means and means that in addition to the listed elements/components/etc., there may be other elements/components/etc.; the terms "first", "second", etc. are only used as marks, not Limit the number of its objects.

In this example embodiment, an array substrate is first provided, the array substrate includes: a substrate, a driving circuit, and N rows of light-emitting units; the driving circuit is arranged on the substrate; the N rows of light-emitting units are arranged far from the driving circuit One side of the substrate;

Wherein, as shown in FIG. 1, the driving circuit includes N rows of driving circuit units and a plurality of first scanning signal lines, and each row of the driving circuit units in the N rows of driving circuit units drives a row of the light-emitting units to emit light, The driving circuit unit includes a first transistor T1 and a second transistor T2; a projection of the first scan signal line Gn on the substrate is located in a first area, and the first area is N rows of the light emitting The area between the projection of the first row of light emitting unit Pn on the substrate and the projection of the second row of light emitting unit Pn+1 on the substrate in any two adjacent rows of the light emitting unit, so The gates of the second transistors of the first row drive circuit and the gates of the first transistors of the second row drive circuit are connected to a first scan signal line, and the first row drive circuit unit first In the second row of driving circuit units, N≥2, and N is an integer. In other words, the first light emitting unit and the corresponding first driving unit located in the nth row (n is a positive integer greater than or equal to 2) are arranged between the second light emitting unit and the corresponding second driving unit located in the n+1th row There is a first scanning signal line, and the second transistor of the first driving unit is connected to the first scanning signal line, and the first transistor of the second driving unit is connected to the first scanning signal line.

The array substrate provided by the present disclosure reduces the number of scan signal lines by sharing the reset signal of one row of drive circuit units in two adjacent rows of drive circuit units and the scan signal of another row of circuit units in a plurality of rows of drive circuit units. The wiring space is saved, the number of pixel units in a unit area is increased, and the display quality is improved; and the two transistors share the gate line, which is beneficial to reduce the area of the gate driving circuit, thereby reducing the frame of the display device.

Further, the driving circuit further includes a second scan signal line and a third scan signal line; the projection of the second scan signal line on the substrate is located in the first projection of the light emitting unit on the substrate in N rows One side (ie, the first side of the light-emitting unit in the starting row) is connected to the gate of the first transistor of the driving circuit unit in the scanning starting row; the projection of the third scanning signal line on the substrate is located at N The second side of the row of the light-emitting unit projected on the substrate (that is, the second side of the end row of the light-emitting unit) is connected to the gate of the second transistor of the driving circuit unit of the scanning end row, wherein the first One side is the side of the N rows of light emitting units projected on the substrate close to the scanning start line, and the second side is the side of the N rows of light emitting units projected on the substrate close to the scanning end line. The second scan signal line, the third scan signal line, and the first scan signal line may be arranged in parallel, the first scan signal line is located between two adjacent rows of light-emitting units, and the second scan signal line is connected to the first row drive circuit unit The third scan signal is connected to the gate of the second transistor of the driver circuit unit in the last row.

For example, an array substrate only includes two rows of light-emitting units as shown in FIG. 1, and the scanning sequence is from top to bottom, then Gn is the first scanning signal line, Gn-1 is the second scanning signal line, and Gn+1 is the third Scan the signal line.

As shown in FIG. 2, the driving circuit unit according to the embodiment of the present disclosure includes: a driving transistor T3, a first transistor T1, a second transistor T2, and an energy storage unit Cst; the driving transistor T3 includes a gate, a source, and a drain. The source of the light-emitting unit OLED is connected to the drain of the driving transistor T3; the gate of the first transistor T1 is connected to the first scan signal in the nth row, the source is connected to the data signal, and the drain The pole is connected to the gate of the driving transistor T3, and is used to turn on in response to the scan signal to transmit the data signal to the gate of the driving transistor T3; the gate of the second transistor T2 is connected to the n+1 th The first scan signal is line, the source is connected to the drain of the driving transistor T3, and the drain is connected to the first node, for turning on in response to the reset control signal to transmit the signal of the first node to the driving transistor T3 The drain of the energy storage unit Cst is connected to the gate of the driving transistor T3, and the second terminal is connected to the drain of the driving transistor T3. Wherein, the first scan signal of the nth row is the scan signal of the driving circuit unit of the current row, and the first scan signal of the second n+1 row is the scan signal of the driving circuit unit of the next row.

Further, the array substrate may further include: a reference voltage sub-circuit 100 and a compensation detection sub-circuit 200, the reference voltage sub-circuit 100 is connected to the first node for providing a reference voltage; the compensation detection sub-circuit 200 is connected to the The first node is used to detect the signal of the drain S of the driving transistor T3.

Wherein, the reference voltage sub-circuit may include: a reference voltage terminal Vref and a first switch unit K1, the reference voltage terminal Vref is used to output a reference voltage; the first terminal of the first switch unit K1 is connected to the reference voltage terminal Vref, Two ends are connected to the first node; the compensation detection sub-circuit 200 may include: a detection unit and a second switch unit K2, the first end of the second switch unit K2 is connected to the detection unit, and the second end is connected to For the first node, the detection unit is used to detect the signal of the drain S of the driving transistor T3.

The reference voltage sub-circuit 100 and the compensation detection sub-circuit 200 may be arranged on or outside the array substrate, which is not specifically limited in the embodiment of the present disclosure. For example, the first switch unit K1 and the second switch unit K2 may be transistors and are provided on the array substrate, and the reference voltage terminal Vref and the compensation detection sub-circuit are provided outside the array substrate.

The driving circuit unit provided by the embodiment of the present disclosure may have two working modes: a display mode and a compensation mode. In the display mode, the first switch unit K1 is turned on, and the second switch unit K2 is turned off. With reference to the timing diagram shown in FIG. 3, the data writing phase and the light emitting phase may be included. For example, the transistors are all N-type transistors:

Data writing stage t1: the scan signal and the reset signal are both high level, the first transistor T1 and the second transistor T2 are turned on, and the data voltage and the reference voltage are written into the energy storage unit Cst.

Light-emitting stage t3: the scan signal and the reset signal are both low, the first transistor T1 and the second transistor T2 are turned off, the signal in the energy storage unit controls the driving transistor T3 to turn on, and the light-emitting element emits light. Among them, a holding phase t2 can be set between t1 and t3.

In the compensation mode, referring to the timing diagram shown in Figure 4, the following stages can be included:

Reset stage t1: the first switch unit K1 is turned on, the second switch unit K2 is turned off, the scan signal and the reset signal of the drive circuit unit in the previous row are both high, the first transistor T1 and the second transistor T2 are turned on to drive The gate and drain of the transistor T3 are written with a correction level (low level), and the driving transistor T3 is turned off.

Writing stage t2: the first switch unit K1 is turned on, the second switch unit K2 is turned off, the scan signal and the reset signal of the drive circuit unit of this row are both high, the first transistor T1 and the second transistor T2 are turned on, The data voltage and the reference voltage are written into the energy storage cell Cst.

Charging stage t3: the scan signal and the reset signal of the drive circuit unit in this row are both low level, the first transistor T1 and the second transistor T2 are turned off, and the gate of the drive transistor T3 is charged.

Detection stage t4: the first switching unit K1 is turned off, the second switching unit K2 is turned on, and the second transistor T2 is turned on, and the signal of the drain of the driving transistor is detected by the detection and compensation module 200;

Resuming writing stage t5: the first switch unit K1 is turned on, the second switch unit K2 is turned off, the scan signal and reset signal of the drive circuit unit of this row are both high, and the first transistor T1 and the second transistor T2 are turned on , The data voltage and the reference voltage are written into the energy storage cell Cst again.

FIG. 5 is a gate driving circuit provided by an embodiment of the present disclosure. Combined with the timing shown in FIG. 6, as an example, the specific working process for the 11th row in the display stage of a frame of picture is as follows:

The first stage: CRN-4 is high level, in the figure CRN+8, CLKA, CLKE, CLKD, CLKF are all low level, VDD_A and VDD_B always keep one high or one of them works. Initially, M18 is turned on to make QB_B high, M14 and M15 are turned on to make Q low, and Q11 and Q12 are set to low; CRN-4 is high to make M8 and M33 turn on, Q11 , Q12 point writes high voltage and keeps it high, the gate level of M19 and M44 is set high, M19 and M44 are turned on to pull down QB_A and QB_B points. The output terminals CLKD and CLKE are low so that the output CR and OUT are both low.

The second stage: CLKD_1, CLKE_1 are high level, STU, CLKA, OE, TRST are all low level, VDD_A and VDD_B always maintain a high level or one of them works. At this time, point Q11 remains high because of the presence of C2 and C3, M23 and M26 are turned on, and CLKD_1 and CLKE_1 are high so that CR11 and OUT1<11> output high levels.

The third stage: CLKE_2 is high, STU, CLKA, OE, TRST are all low, VDD_A and VDD_B always keep one high or one of them works. At this time, point Q12 remains high because of the existence of C4 and C5, M48 is turned on, CLKE_2 is high, and point Q performs the second bootstrapping to further increase the level, and OUT1<11> outputs high level.

The fourth stage: CLKD_1, CLKE_1, STU, CLKA are all low, VDD_A and VDD_B always keep one high or one of them works. At this time, point Q11 is still high because C2 and C3 are still high. At this time, CLKD_1 and CLKE_1 become low, making CR<11> and OUT1<11> output low.

The fifth stage: CLKE_2, STU, CLKA are all low, VDD_A and VDD_B always keep one high or one of them works. At this time, point Q12 is still high because C4 and C5, and CLKE_2 becomes low at this time, making OUT1<11> output low.

The sixth stage: CRN+8 (CR19) is high, VDD_A and VDD_B always keep one high or one of them works. At this time, CR19 is high to make M12, M13, M37, M38 turn on, Q11, Q12 points are pulled low, reset is completed.

Shift in turn to complete the display of all lines in the display phase, and then enter the blanking phase. In this process, for the SENSE on line 12, the OE signal has the same waveform pulse width as CR<7>, so when CR7 is output, H11 and H13 will be charged. After the OE signal is low, H11 and H13 will be charged. The high level will remain until the blanking stage.

M7 has been in the off state during this process. Isolate the effect of detecting the pre-stored voltage point H on the display. The Q point presents a tower-shaped waveform, and a large drive tube M26 is shared with the rising and falling edges of the output CR and OUT. M48 greatly reduces the area of the layout.

The display process of the 11th line above is then passed in order until the last line is displayed, and the display phase of one frame ends.

FIG. 7 is a schematic diagram of a cascade connection of a shift register provided by an exemplary embodiment of the present disclosure. The working principle of the gate driving circuit and the driving circuit unit provided in the embodiment of the present disclosure when detecting the drain of the driving transistor is as follows:

The first stage: During the display of the first frame, when the 7th line is output, the OE signal is high, making H11 and H13 write high-level signals (here because the overlap between CLK makes H13 high, if the detection Only one H11 is needed if the four rows of the unit are shared)

The second stage: CLKA is high to make M4, M7, and M32 in the 11th, 12th, 13th, and 14th rows turn on, and point Q is written to a high level.

The third stage: CLKA is turned off, CLKE_1 and CLKE_2 are turned on, so that Q11, Q12 will perform a second bootstrap raising level because of the presence of C2 and C3, then G1 and G2 in the 11th row are high, and the 11th row is written Correction level DATA, VREF.

The fourth stage: then CLKE_2, CLKE_3 is turned on to make the output OUT112 high.

The fifth stage: CLKE_2, CLKE_3 become low level, and the output terminal OUT112 becomes low level.

The sixth stage: OE TRST turns on to reset the H and Q points of all rows to low level, thus completing the display and compensation detection. .

It should be noted that all the capacitors in the figure can be TFT parasitic capacitors or external capacitors.

Using the method of sharing G2 in the Nth row and G1 in the N+1th row can reduce the GOA frame, while using G2<N> and G1<N+1> to share in the pixel can reduce the load of the original two lines to The load generated by a line. At the same time, the load of one gate line is saved, and the number of defects caused by two gate lines is reduced.

For example, taking the sub-pixel R as an example, the data signal Data is connected to the source of the first transistor T1, the drain of the first transistor T1 is connected to point G and also connected to the gate of the driving transistor T3, and the source of the driving transistor T3 Connect to VDD, connect the drain to point S, the second conductive layer metal connected from point G as one pole of the capacitor, and the ACTIVE layer connected from point S as the other pole of the capacitor. The source of the second transistor T2 is connected to point S, and the drain is connected to the detection line. The gate line of the second transistor T2 in the Nth row is also the gate line of the first transistor T1 in the N+1th row. In this way, T2 in the Nth row and T1 in the N+1th row share the gate line, which reduces the defects caused by the crossing of the gate lines, and at the same time saves the space of a gate line, which is effective for high PPI pixel design.

It should be noted that in the above-mentioned specific embodiments, all the transistors are N-type transistors; however, those skilled in the art can easily obtain a pixel drive circuit in which all transistors are P-type transistors based on the pixel drive circuit provided in the present disclosure. In an exemplary embodiment of the present disclosure, all the transistors may be P-type transistors. The use of all P-type thin film transistors has the following advantages: for example, strong noise suppression; for example, due to low-level conduction, low level is easy to achieve in charge management; for example, P-type thin film transistors have simple manufacturing process and relatively low price; for example, P-type thin film transistors have better stability and so on. Of course, the pixel drive circuit provided in the present disclosure can also be changed to a CMOS (Complementary Metal Oxide Semiconductor) circuit, etc., and is not limited to the pixel drive circuit provided in this embodiment, and will not be repeated here.

The driving circuit may include a first conductive layer and a second conductive layer. The first scan signal line and the second scan signal line are provided on the first conductive layer; the second conductive layer is provided with data signal lines Data, A power supply line VDD, a second power supply line VSS and a detection signal line SE, the first end of the first transistor T1 is connected to the data signal line Data, and the source of the driving transistor T3 is connected to the first power line VDD , The drain is connected to the pixel electrode; the drain of the second transistor T2 is connected to the detection signal line. An insulating layer may be provided between the first conductive layer and the second conductive layer.

As shown in FIG. 2, the first scan signal line is arranged along the first direction, and the data signal line Data is arranged along the second direction. The first direction and the second direction intersect, such as being arranged vertically. Of course, in practical applications, the first The first direction and the second direction may also be arranged in parallel or crossing, and the embodiment of the present disclosure is not limited thereto.

Further, the driving circuit may further include a first source connection line, a second source connection line, and a drain connection line, and the projection of the first power signal line VDD on the substrate is located in the N rows of the light-emitting units Projecting one side along the second direction on the substrate; the projection of one end of the first source connection line on the substrate and the projection of the first power signal line VDD on the substrate They overlap and are connected to the first power signal line VDD through a conductive via, and the source of the driving transistor is connected to the first source connection line. An insulating layer is provided between the first source connection line and the first power signal line VDD and the source of the driving transistor T3, and the first source connection line and the source of the driving transistor T3 are connected through a conductive via.

The projection of the data signal line Data on the substrate is located on one side of the corresponding column of the light-emitting unit projected on the substrate along the second direction; one end of the second source connection line is on the substrate The projection on the substrate coincides with the projection of the data signal line Data on the substrate, and is connected to the data signal line through a conductive via. The source of the first transistor T1 is connected to the second Source connection line. An insulating layer is provided between the second source connection line and the data signal line Data and the source of the first transistor T1, and the second source connection line and the source of the first transistor T1 are connected through a conductive via.

The projection of the detection signal line SE on the substrate is located on one side of the projection of the light-emitting unit on the substrate; the projection of one end of the drain connection line on the substrate and the detection The projection of the signal line SE on the substrate overlaps, and is connected to the detection signal line through a conductive via, and the drain of the second transistor T2 is connected to the drain connection line. An insulating layer is provided between the drain connection line and the detection signal line SE and the drain of the second transistor diagram, and the drain connection line and the drain of the second transistor T2 are connected through a conductive via.

For example, for the Nth row of pixel units, the N-1th first gate line Gn-1 is laterally arranged on one side of the light-emitting unit, and the Nth first gate line Gn is laterally arranged on the other side of the light-emitting unit. , The data signal line Data, the first power supply line VDD and the detection signal line SE are arranged perpendicular to the first scanning signal line Gn, that is, the data signal line Data, the first power supply line VDD and the detection signal line SE are arranged longitudinally, the first power supply The line VDD is located on one side of the pixel unit, and the data signal line Data is located on the other side of the pixel unit. The first transistor T1 is arranged on the side of the pixel unit close to the data signal line Data, the source is connected to the data signal line, and the gate is connected to the first data signal line Gn-1; the driving transistor T3 is arranged on the pixel unit close to the first power line On the side of VDD, the gate is connected to the drain of the first transistor T1, the source is connected to the first power line VDD, and the drain is connected to the pixel electrode; the second transistor T2 is provided at the pixel unit near the first gate line Gn On one side, the gate is connected to the first gate line Gn, the source is connected to the drain (pixel electrode) of the driving transistor T3, and the drain is connected to the detection signal line SE.

It should be noted that in the above example, the positional relationship is the positional relationship of the projection of the pixel unit, the first conductive layer, the second conductive layer, etc., which are located in different levels in practical applications, and devices of different levels The connection to the connecting line can be achieved through conductive vias.

Further, the driving circuit may further include an active layer. The first conductive layer may be provided on the side of the active layer away from the substrate. The active layer may include, for example, polysilicon, and may include, for example, a channel region and a source region. And drain area. The channel region may not be doped with impurities, and therefore has semiconductor characteristics. The source region and the drain region are on the respective sides of the channel region, and are doped with impurities, and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.

The gate electrode in the first conductive layer may have a single-layer or multi-stack structure, for example, in consideration of adhesion of adjacent layers, planarization of the surface of the stack target layer, formability, etc., a single-layer or multi-stack structure Including aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), titanium (Nd), iridium (Ir), chromium (Cr) , Keng (Li), Calcium (Ca), Molybdenum (Mo), Titanium (Ti), Tungsten (W) and at least one of copper (Cu). In order to insulate the corresponding active layer from the corresponding gate electrode, the insulating layer includes an inorganic material (for example, silicon oxide, silicon nitride, and/or silicon oxynitride) between the active layer and the gate electrode.

The light-emitting unit includes a pixel electrode, a common electrode, and a light-emitting layer. The pixel electrode is connected to the drain of the driving transistor; the common electrode is connected to the second power line; the light-emitting layer is located between the pixel electrode and the common electrode. . The pixel layer is divided into multiple rows of light emitting units by the pixel defining layer, and each row of light emitting units includes a plurality of light emitting units, that is, the light emitting units are arranged in an array.

This example embodiment also provides a display device including the above-mentioned array substrate. Wherein, the display device may include, for example, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.

The display device provided by the present disclosure includes an array substrate, and the array substrate shares a scanning signal line through the reset signal of one row of drive circuit units in two adjacent rows of drive circuit units in a plurality of rows of drive circuit units and the scanning signal of another row of circuit units, The number of scanning signal lines is reduced, the wiring space is saved, the number of pixel units per unit area is increased, and the display quality is improved; and the two transistors share the gate line, which is beneficial to reduce the area of the gate drive circuit, thereby reducing Display the frame of the device.

Referring to FIG. 8, according to another embodiment of the present disclosure, there is provided a method of manufacturing an array substrate, including:

S101, forming a plurality of light-emitting units on a base substrate, the light-emitting units being arranged in the first light-emitting unit in the nth row and the second light-emitting unit in the n+1th row;

S102, forming a plurality of driving circuit units on the substrate, the plurality of driving circuit units including a first driving circuit unit arranged in the nth row and connected to the first light emitting unit and a first driving circuit unit arranged in the n+1th row. A second driving circuit unit connected in parallel to the second light-emitting unit, each of the plurality of driving circuit units includes a first transistor and a second transistor;

S103. A first scan signal line is formed on the substrate, and the projection of the first scan line on the substrate is located between the projection of the first light-emitting unit on the substrate and the second light-emitting unit. Between the projection of the unit on the substrate, the gate of the second transistor of the first driving circuit and the gate of the first transistor of the second driving circuit are connected to the first scanning signal line;

It should be understood that the marks S101, S102, and S103 of the method steps described in the embodiments of the present disclosure should not be construed as limiting the division or order of the specific method steps. For example, in some embodiments, steps S101, S102, and S103 can be performed simultaneously, time-sharing, or in reverse order. In some embodiments, several operations in steps S101, S102, and S103 can be combined into one step, or performed partially overlapping, or one or more of them can be split into several sub-steps. These sub-steps It can also be executed simultaneously, time-sharing, or in reverse order.

In an embodiment of the present disclosure, the method of manufacturing an array substrate further includes:

In an embodiment of the present disclosure, forming the driving circuit unit includes:

Forming a driving transistor and an energy storage unit on the substrate; and

Forming an energy storage unit on the substrate,

In an embodiment of the present disclosure, the method of manufacturing an array substrate further includes: forming an insulating layer between the first conductive layer and the second conductive layer.

In an embodiment of the present disclosure, the first scan signal line is formed to be arranged along a first direction, and the data signal line is formed to be arranged along a second direction, and the first direction and the second direction intersect.

Other aspects of the method for manufacturing an array substrate according to the present invention can be understood with reference to the embodiments described in detail for the array substrate in this application, and will not be repeated here.

It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of a module or unit described above can be further divided into multiple modules or units to be embodied.

Through the description of the foregoing embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or can be implemented by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , Including several instructions to make a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) execute the method according to the embodiment of the present disclosure.

Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The description and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

An array substrate, including:

Substrate

A plurality of light-emitting units arranged on the substrate, including a first light-emitting unit arranged in the nth row and a second light-emitting unit arranged in the n+1th row;

A plurality of driving circuit units are arranged on the substrate, including a first driving circuit unit arranged in the nth row and connected to the first light-emitting unit, and a first driving circuit unit arranged in the n+1th row and connected to the second light-emitting unit A second driving circuit unit of the unit, each of the plurality of driving circuit units includes a first transistor and a second transistor;

The first scan signal line, the projection of the first scan line on the substrate is located at the projection of the first light-emitting unit on the substrate and the projection of the second light-emitting unit on the substrate In between, the gate of the second transistor of the first drive circuit unit and the gate of the first transistor of the second drive circuit unit are connected to the first scan signal line;

Wherein, the first driving circuit unit precedes the second driving circuit unit during scanning, and n is a positive integer and n≥2.
The array substrate of claim 1, further comprising:

The second scanning signal line, whose projection on the substrate is located on the first side of the projection of the light-emitting unit on the substrate in the starting row, is connected to the first of the driving circuit unit in the scanning starting row The gate of the transistor;

The third scan signal line, whose projection on the substrate is located on the second side of the projection of the light-emitting unit on the substrate in the end row, is connected to the second transistor of the drive circuit unit in the scan end row The gate, wherein the first side is the side of the light-emitting unit projected on the substrate close to the scanning start line, and the second side is the side of the light-emitting unit projected on the substrate close to the scanning end line side.
8. The array substrate of claim 1, wherein the driving circuit unit comprises:

The driving transistor includes a gate, a source, and a drain, the source of which is connected to the first power signal, and the pixel electrode of at least one of the plurality of light-emitting units is connected to the drain of the driving transistor;

The first transistor has a source connected to a data signal, and a drain connected to the gate of the driving transistor, for being turned on in response to the scan signal to transmit the data signal to the gate of the driving transistor;

The source of the second transistor is connected to the drain of the driving transistor, and the drain is connected to the first node, for being turned on in response to a reset control signal to transmit the signal of the first node to the drain of the driving transistor. pole;

For the energy storage unit, the first terminal is connected to the gate of the driving transistor, and the second terminal is connected to the drain of the driving transistor.
5. The array substrate of claim 3, wherein the array substrate further comprises:

The reference voltage sub-circuit is connected to the first node for providing a reference voltage;

The compensation detection sub-circuit is connected to the first node and is used to detect the signal of the drain of the driving transistor.
5. The array substrate of claim 4, wherein the reference voltage sub-circuit comprises:

Reference voltage terminal, used to output reference voltage;

For the first switch unit, a first terminal is connected to the reference voltage terminal, and a second terminal is connected to the first node;

The compensation detection sub-circuit includes:

Detection unit

The second switch unit has a first end connected to the detection unit, and a second end connected to the first node. The detection unit is used to detect a signal from the drain of the driving transistor.
3. The array substrate of claim 3, further comprising a driving circuit, the driving circuit unit is included in the driving circuit, and the driving circuit further comprises:

A first conductive layer, the first scan signal line is provided on the first conductive layer;

The second conductive layer is provided with a data signal line, a first power line, a second power line, and a detection signal line. The source of the first transistor is connected to the data signal line. The source of the driving transistor is connected to the first power line, and the drain of the second transistor is connected to the detection signal line.
7. The array substrate of claim 6, wherein an insulating layer is provided between the first conductive layer and the second conductive layer.
8. The array substrate of claim 7, wherein the first scan signal line is arranged along a first direction, the data signal line is arranged along a second direction, and the first direction and the second direction intersect.
8. The array substrate of claim 8, wherein the projection of the first power signal line on the substrate is located on one side of the projection of the plurality of light-emitting units on the substrate along the second direction ；

The driving circuit also includes a first source connection line, and the projection of one end of the first source connection line on the substrate coincides with the projection of the first power signal line on the substrate. The via is connected to the first power signal line, and the source of the driving transistor is connected to the first source connection line.
8. The array substrate according to claim 8, wherein the projection of the data signal line on the substrate is in a column corresponding to the projection of the plurality of light-emitting units on the substrate along the second direction One side

The driving circuit further includes a second source connection line, and the projection of one end of the second source connection line on the substrate coincides with the projection of the data signal line on the substrate and passes through a conductive via Connected to the data signal line, and the source of the first transistor is connected to the second source connection line.
8. The array substrate according to claim 8, wherein the projection of the detection signal line on the substrate is located on one side of the projection of the plurality of light-emitting units on the substrate in a corresponding column;

The driving circuit further includes a drain connection line, and the projection of one end of the drain connection line on the substrate coincides with the projection of the detection signal line on the substrate. The detection signal line is connected, and the drain of the second transistor is connected to the drain connection line.
8. The array substrate of claim 6, wherein at least one of the plurality of light emitting units comprises:

The pixel electrode is connected to the drain of the driving transistor;

A common electrode, connected to the second power line;

The light-emitting layer is located between the pixel electrode and the common electrode.
A display device comprising the array substrate according to any one of claims 1-12.
A method of manufacturing an array substrate includes:

Forming a plurality of light-emitting units on a base substrate, the plurality of light-emitting units arranged in the first light-emitting unit in the nth row and the second light-emitting unit in the n+1th row;

A plurality of driving circuit units are formed on the substrate, the plurality of driving circuit units including a first driving circuit unit arranged in the nth row and connected to the first light emitting unit and a parallel arrangement arranged in the n+1th row A second driving circuit unit connected to the second light-emitting unit, each of the plurality of driving circuit units including a first transistor and a second transistor;

A first scan signal line is formed on the substrate, and the projection of the first scan line on the substrate is located between the projection of the first light-emitting unit on the substrate and the projection of the second light-emitting unit on the substrate. Between the projections on the substrate, the gate of the second transistor of the first driving circuit and the gate of the first transistor of the second driving circuit are connected to the first scanning signal line;

Wherein, the first driving circuit unit precedes the second driving circuit unit during scanning, and n is a positive integer and n≥2.
The method according to claim 14, further comprising:

A second scanning signal line is formed on the substrate, and its projection on the substrate is located on the first side of the projection of the light-emitting unit on the substrate in the starting row, and is connected to all the scanning starting rows. The gate of the first transistor of the driving circuit unit;

A third scan signal line is formed on the substrate, and its projection on the substrate is located on the second side of the projection of the light-emitting unit on the substrate in the end row, and is connected to the drive of the scan end row The gate of the second transistor of the circuit unit, wherein the first side is the side of the light-emitting unit projected on the substrate close to the scanning start line, and the second side is the light-emitting unit on the substrate The projection is closer to the side of the scanning end line.
The method of claim 14, wherein forming the driving circuit unit comprises:

Forming a driving transistor and an energy storage unit on the substrate; and

Forming an energy storage unit on the substrate,

Wherein, the transistor includes a gate, a source, and a drain, the source of which is connected to the first power signal, and the pixel electrode of at least one of the plurality of light-emitting units is connected to the drain of the driving transistor,

The source of the first transistor is connected to a data signal, and the drain is connected to the gate of the driving transistor, for being turned on in response to the scanning signal to transmit the data signal to the gate of the driving transistor,

The source of the second transistor is connected to the drain of the driving transistor, and the drain is connected to the first node, for being turned on in response to a reset control signal to transmit the signal of the first node to the drain of the driving transistor. pole,

The first end of the energy storage unit is connected to the gate of the driving transistor, and the second end is connected to the drain of the driving transistor.
The method of claim 16, further comprising:

Forming a reference voltage sub-circuit on the substrate, connected to the first node for providing a reference voltage;

A compensation detection sub-circuit is formed on the substrate, connected to the first node, and used for detecting the signal of the drain of the driving transistor.
The method of claim 16, further comprising:

Forming a first conductive layer, and the first scan signal line is provided on the first conductive layer;

A second conductive layer is formed. The second conductive layer is provided with a data signal line, a first power line, a second power line, and a detection signal line, the source of the first transistor is connected to the data signal line, and The source of the driving transistor is connected to the first power line, and the drain of the second transistor is connected to the detection signal line.
The method of claim 18, further comprising: forming an insulating layer between the first conductive layer and the second conductive layer.
The method of claim 19, wherein the first scan signal line is formed to be arranged along a first direction, and the data signal line is formed to be arranged along a second direction, and the first direction and the second direction intersect.