WO2020206822A1

WO2020206822A1 - Method for enhancing durability of three-dimensional nand flash memory

Info

Publication number: WO2020206822A1
Application number: PCT/CN2019/088441
Authority: WO
Inventors: 陈杰智; 曹芮; 杨文静
Original assignee: 山东大学
Priority date: 2019-04-12
Filing date: 2019-06-26
Publication date: 2020-10-15
Also published as: CN110112135A

Abstract

A method for enhancing durability of a three-dimensional NAND flash memory. The method is based on a NAND flash memory having a three-dimensional structure, and comprises: for a device having performed multiple erase and programming operations, if a BER reaches a threshold set by a user, keeping the device in a final erased state, and performing annealing on the device. If a memory unit is kept in a random write state or in a highest G state after the device has performed an erase/programming operation, the restoration operation does not occur. The present invention performs high-temperature annealing on a memory in an erased state and compared with ordinary methods, an error rate is significantly reduced after a process of this method is completed. The invention enhances the durability of three-dimensional NAND flash memories by using a simple method, and repairs, by means of high-temperature annealing, data damage of three-dimensional NAND flash memories caused during PE cycles.

Description

A method for improving the durability of three-dimensional NAND flash memory

Technical field

The invention relates to a method for improving the durability of a three-dimensional NAND flash memory, and belongs to the technical field of flash memory reliability.

Background technique

Flash memory is divided into two types, NAND flash memory and NOR flash memory. The present invention is aimed at NAND flash memory. NAND flash memory can achieve high storage density, and the speed of writing and erasing is also very fast.

NAND flash memory is divided into Floating Gate and Charge Trap structures according to different storage media. The Floating Gate structure stores charges in polysilicon, which can move freely in the storage layer. The Charge Trap structure stores charges in silicon nitride. In the storage layer, it is stored in a discrete trap, and the charge cannot move in the storage layer.

While the demand for NAND flash memory in the market is increasing, NAND flash memory is also developing in technology. NAND flash memory is divided into several architectures such as SLC, MLC, and TLC according to the number of bits stored in each memory cell, and is still developing. The reduction of device size and the reduction of bit cost have reduced the reliability of two-dimensional NAND flash memory. High-reliability NAND flash memory is essential for NAND flash memory applications.

"Moore's Law" means that the number of transistors on a chip doubles every 18 to 24 months. But with the development of the semiconductor industry, we have entered the "post-Moore era." For NAND flash memory, as the size of floating gate memory continues to shrink, the thickness of the polysilicon floating gate and the charge tunneling oxide layer continues to decrease, and the limitations of traditional floating gate memory will become more and more prominent. There are more and more problems with NAND flash memory, and the industry has begun to focus on the development of three-dimensional NAND flash memory. Three-dimensional NAND flash memory has different ideas for solving problems. In order to increase the capacity of NAND and reduce costs, more layers are stacked. In this way, the capacity, performance and reliability of three-dimensional NAND flash memory are guaranteed. The flash memory also has problems different from the planar structure.

Figure 1 shows the basic structure of a three-dimensional Charge Tarp NAND flash memory. From the inside to the outside, it is the core dielectric layer, the polysilicon channel, the tunnel oxide layer, the charge trap layer, and the blocking oxide layer. The left side in Figure 1 is a three-dimensional structure, which belongs to the Bit Cost Scalable (BICS) structure. The BICS process uses a gate-first process to alternately deposit an oxide layer and a polysilicon layer, and then form a channel hole in the stacked layer and fill it Oxide-nitride-oxide and polysilicon realization. The basic structure of each cell is a SONOS (control gate-blocking oxide layer-charge trapping layer-tunneling oxide layer-channel) structure. The right side of Figure 1 is a cross-sectional view of the BICS, including: control gate, blocking oxide layer, charge trapping layer, tunnel oxide layer and polysilicon ring channel layer. In the write state, charges are stored in the traps of the charge trapping layer.

Figure 2 shows the threshold voltage distribution diagram of TLC 3D NAND. NAND has three basic operations: erasing, writing and reading. Block is the basic unit of erasing, and page is the basic unit of writing and reading. Figure 2(a) shows the basic structure of NAND. TLC NAND flash memory is divided into three different page types, namely LSB, CSB and MSB. While TLC has brought a significant reduction in storage costs, there is also a reduction in the threshold voltage window, which brings more reliability problems. TLC NAND flash memory contains eight allocation levels (erase, A, B...) ....G), as shown in Figure 2(b).

Figure 3 shows the relationship between the BER of TLC 3D NAND and the number of programming/erase cycles. As the number of programming/erase cycles increases, negative charges in the oxide layer continue to accumulate, blocking part of the control gate voltage, increasing the threshold voltage, and BER will gradually increase. The specific relationship in the figure is: the blue curve is the change of the error rate (BER) after the number of programming/erase cycles is 1,200, 400...2000. It can be seen from the figure that as the number of cycles increases, the BER becomes non-zero. Linear rapid growth.

Device data retention characteristics and device durability are important parameters that affect the reliability of NAND flash memory. The data retention feature refers to the ability of the memory to store information so that it is not lost; the durability of the device is the ability of the device to store information after many erasing and programming operations.

High temperature annealing is to bake the chip particles at a high temperature for a period of time, and the device itself will produce a certain physical reaction. The reliability of devices is a topic worthy of research and attention. With the continuous increase in the number of programming/erase cycles during the use of NAND flash memory, the probability of errors will show a non-linear rapid increase.

CN103842974A discloses a "method for managing the endurance of non-volatile memory", which relates to an improved sense amplifier and related methods used for read operations in flash memory devices; 1. The sense amplifier includes a built-in voltage Offset. 2. A voltage offset is induced in the sense amplifier by using a capacitor; 3. The sense amplifier uses a timing with a slope for the reference signal to increase the current drawn from the selected cell compared to the reference cell. "Or "1"; 4. The sense amplifier is used without any voltage offset.

CN104464801A discloses a method for effectively improving the durability of a resistive random access memory. When the resistive random access memory is programmed, a series of small programming pulses with varying pulse widths and constant pulse height are loaded into the resistive random access memory. It can prevent hard breakdown due to excessive pulse width during programming, thereby improving the durability of RRAM.

The above method is not suitable for improving the durability of three-dimensional NAND flash memory. At present, the error correction capability of ECC is improved to improve the reliability of NAND flash memory, but the improvement of ECC level increases the complexity of actual operation.

Therefore, the present invention aims to provide a simple and effective method to improve the reliability of the three-dimensional NAND flash memory.

Summary of the invention

Aiming at the disadvantages of the existing technology for reducing the error rate of flash memory and improving device durability, the present invention provides a method that can effectively improve the durability of a three-dimensional NAND flash memory.

The method for improving the durability of the three-dimensional NAND flash memory of the present invention is:

Based on the three-dimensional architecture NAND flash memory, for devices that undergo multiple erasing and programming operations, when the BER (Bit Error Rate) reaches the threshold set by the user, the device is finally kept in the erased state (ie, the hole state), and then Anneal the device.

The detection of the BER is to detect a single NAND device in the NAND matrix, or to detect a block in a single device.

The annealing is maintained at a temperature of 150°C-250°C for 1-72 hours, and then cooled at normal temperature. The preferred annealing conditions are 180-220 degrees for 2 hours to 20 hours, and then cooled at room temperature. The best annealing condition is to keep at 200 degrees for 3 hours, and then cool down at normal temperature.

The annealing is achieved by the following ways: annealing the chip where the detected Block is located through the circuit below the chip, or taking the chip where the detected Block is located from the NAND matrix for annealing.

When the memory is finally kept in the erased state, if you want to save the previously stored information before erasing, copy the information to the adjacent NAND flash memory or adjacent Block first.

If the device undergoes an erase/program operation, if the last memory cell retention state is random write or the highest state G state, this repair phenomenon will not occur.

The method of the present invention is to perform high-temperature annealing on the memory in the erased state. After the process of this method, the error rate is greatly reduced compared with the ordinary method. A simple method is adopted to improve the durability of the three-dimensional NAND flash memory. .

Description of the drawings

Figure 1 is a schematic diagram of the structure of a three-dimensional NAND flash memory.

Figure 2 is a diagram of the threshold voltage distribution of TLC 3D NAND.

Figure 3 shows the relationship between the BER of TLC 3D NAND and the number of programming/erase cycles.

Figure 4 is a flowchart of the method of the present invention.

FIG. 5 is a schematic diagram of the operation of the three-dimensional NAND flash memory during high temperature annealing.

FIG. 6 is a diagram showing the results of high temperature annealing in the erased state that can repair the NAND flash memory that has been erased/programmed for many times.

FIG. 7 is a graph showing the effect of high temperature annealing on the NAND flash memory after multiple erasing/programming operations under the state of randomly writing data.

FIG. 8 is a graph showing the effect of high temperature annealing on the NAND flash memory after multiple erasing/programming operations under the highest data state (ie, G state).

detailed description

The method for improving the durability of the three-dimensional NAND flash memory of the present invention is based on the three-dimensional architecture NAND flash memory, taking TLC 3D NAND flash memory as an example for experiments; as shown in Figure 4, the specific method is:

First, let the device work normally, that is, perform abrasion operation on the device. The BER will gradually increase with the increase of cycling. Set the BER threshold A. The range of BER setting is customized by the user and set according to the user's needs. When the value of BER exceeds A, the particles are erased to put them in Erase state, and then high-temperature annealing is performed. After annealing, the chip is restored to normal working state, and then the wear operation is performed. It will be found that the high-temperature annealing will wear multiple times. The operating NAND flash memory has a repair function. Among them, the BER detection can be to detect a single NAND device in the NAND matrix, or to detect a certain Block in a single device. If you want to save the previously stored information before erasing, copy the information to the adjacent NAND chip or adjacent Block first.

If a single NAND device in the NAND matrix is tested, a high temperature annealing operation is performed on a single NAND device in the NAND matrix. This operation can be achieved in two ways: one is to perform high temperature on the tested chip through the circuit under the NAND matrix Annealing, one is to take the tested chip out of the NAND matrix and take it to the incubator for high temperature annealing. If a block in a single device is detected, then a high temperature annealing operation is performed on a block in a single device. This operation can also be achieved in two ways: one is to check the location of the detected block through the circuit under the chip The chip is annealed at a high temperature. First, the chip where the detected Block is located is taken out of the NAND matrix and brought to the incubator for high-temperature annealing.

Figure 6 shows the result that high temperature annealing in the erased state can repair the NAND flash memory that has been erased/programmed many times. First select three new blocks in the NAND flash memory particles, and perform multiple programming/erase cycles on these three blocks, which are 500 cycles, 1000 cycles, and 2000 cycles respectively. After that, the error rate curve is obtained, that is, the first Part of the Cycling-BER curve; the final state of the NAND flash memory cell after the cycle is the erased state (that is, the hole state); then the NAND flash memory particles are placed in the incubator at 200°C for 3 hours (the following conditions can also be used : 250 degrees for 1 hour, 220 degrees for 2 hours, 200 degrees for 3 hours, 190 degrees for 10 hours, 180 degrees for 20 hours, 170 degrees for 30 hours, 165 degrees for 40 hours, 160 degrees for 50 hours, 155 The temperature is maintained for 60 hours, and the temperature is maintained at 150 degrees for 72 hours), and then the chip is cooled at room temperature and then subjected to abrasion operation, that is, the three blocks are respectively subjected to 500, 1000, and 2000 programming/erase cycles. Get the Cycling-BER curve of the second part. It can be seen from the curve in Figure 6 that high temperature annealing has a repair effect on NAND flash memory that has undergone multiple wear operations, but the premise is that the final state of the NAND flash memory cell after the cycle is the erased state (that is, the hole state) before the high temperature annealing. .

Figure 7 shows the effect of high temperature annealing on the NAND flash memory after multiple erasing/programming operations under the state of randomly writing data. First select three new blocks in the NAND flash memory particles, and perform multiple programming/erase cycles on these three blocks, which are 500 cycles, 1000 cycles, and 2000 cycles respectively. After that, the error rate curve is obtained, that is, the first Part of the Cycling-BER curve; the final state of the NAND flash memory cell after the cycle is the random write state (that is, the state of charge exists); then the NAND flash memory particles are placed in the incubator at 200°C for 3 hours (it can also be The following conditions: 250 degrees for 1 hour, 220 degrees for 5 hours, 200 degrees for 3 hours, 190 degrees for 10 hours, 180 degrees for 20 hours, 170 degrees for 30 hours, 165 degrees for 40 hours, and 160 degrees for 50 hours , 155°C for 60 hours, 150°C for 72 hours), then put the chip at room temperature to cool down and then perform abrasion operation, that is, perform 500, 1000, and 2000 program/erase cycles for three blocks respectively Operate to get the Cycling-BER curve of the second part. It can be seen from the curve in FIG. 7 that the high-temperature annealing has no obvious effect on the final state of the NAND flash memory cell after the cycle is the random write state (that is, the state with the presence of charge).

Figure 8 shows the effect of high temperature annealing on the NAND flash memory that has undergone multiple erasing/programming operations under the highest data write state (ie, G state). First select three new blocks in the NAND flash memory particles, and perform multiple programming/erase cycles on these three blocks, which are 500 cycles, 1000 cycles, and 2000 cycles respectively. After that, the error rate curve is obtained, that is, the first Part of the Cycling-BER curve; after the cycle, the final state of the NAND flash memory cell is the state of writing the highest data (ie G state); then put the NAND flash memory particles in the incubator at 200°C for 3 hours (it can also be the following Conditions: 250 degrees for 1 hour, 220 degrees for 5 hours, 200 degrees for 3 hours, 190 degrees for 10 hours, 180 degrees for 20 hours, 170 degrees for 30 hours, 165 degrees for 40 hours, and 160 degrees for 50 hours. 155°C for 60 hours, 150°C for 72 hours), then put the chip at room temperature to cool down and then perform abrasion operations, that is, perform 500, 1000, and 2000 program/erase cycles for the three blocks respectively. , Get the Cycling-BER curve of the second part. It can be seen from the curve in FIG. 8 that high-temperature annealing has no effect on the chip in the final state of the NAND flash memory cell after the cycle is the random write state (that is, the state with charge exists), and the error rate will increase significantly.

Claims

A method for improving the durability of three-dimensional NAND flash memory, which is characterized by: based on three-dimensional architecture NAND flash memory, for devices that undergo multiple erasing and programming operations, when the BER reaches the threshold set by the user, the memory is finally maintained as Erase the state, and then anneal the device.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, wherein the detection of the BER is detection of a single NAND device in the NAND matrix, or detection of a block in a single device.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, wherein the annealing is maintained at a temperature of 150° C.-250° C. for 1-72 hours, and then cooled at normal temperature.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, wherein the annealing is maintained at 180-220 degrees for 2 hours-20 hours, and then cooled at room temperature.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, wherein the annealing condition is maintained at 200 degrees for 3 hours, and then cooled at normal temperature.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, wherein the annealing is achieved by the following ways: annealing the chip where the detected Block is located through the circuit below the chip, or the The chip where Block is located is taken out of the NAND matrix for annealing.
The method for improving the durability of a three-dimensional NAND flash memory according to claim 1, characterized in that: when the memory is finally kept in the erased state, if the previously stored information is to be saved before erasing, the information is first copied to the corresponding Adjacent NAND flash memory or adjacent Block.