WO2020206808A1 - Procédé permettant à un cycle de commande interne asservi de suivre dynamiquement un cycle de synchronisation de bus ethercat - Google Patents

Procédé permettant à un cycle de commande interne asservi de suivre dynamiquement un cycle de synchronisation de bus ethercat Download PDF

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Publication number
WO2020206808A1
WO2020206808A1 PCT/CN2019/087247 CN2019087247W WO2020206808A1 WO 2020206808 A1 WO2020206808 A1 WO 2020206808A1 CN 2019087247 W CN2019087247 W CN 2019087247W WO 2020206808 A1 WO2020206808 A1 WO 2020206808A1
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WIPO (PCT)
Prior art keywords
cycle
internal control
servo
bus synchronization
control cycle
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PCT/CN2019/087247
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English (en)
Chinese (zh)
Inventor
杨露
徐小军
钱巍
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南京埃斯顿自动化股份有限公司
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Publication of WO2020206808A1 publication Critical patent/WO2020206808A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Definitions

  • the invention relates to a method for dynamically adjusting errors in an EtherCat bus synchronization cycle, specifically, a method for an EtherCat bus type servo internal control cycle to dynamically follow the EtherCat bus synchronization cycle, which belongs to the field of servo motor control.
  • the synchronization signal of the bus is affected by the processing of the host computer and the size of the communication content.
  • the synchronization cycle of the EtherCat bus is often greater than the internal control cycle of the servo.
  • the method we usually adopt is to set the EtherCat bus synchronization cycle to be an integer n (n ⁇ 1) times the internal control cycle of the servo.
  • the verification platform of the present invention sets the EtherCat bus synchronization cycle to 2ms and the servo internal control cycle to 125us, that is, there are 16 servo internal control cycles in each EtherCat bus synchronization cycle, and each EtherCat bus synchronization cycle time period The 16 servo internal control cycles are generated according to the local clock.
  • the local clock and the bus clock are non-same-source clocks, there is an inherent deviation between the non-same-source clocks, so the servo internal control cycle signal generated by this local clock is in the last (first 16) There will definitely be errors between the periodic signals synchronized with the EtherCat bus.
  • the existing general architecture is that the bus synchronization signal generated by the EtherCat slave station is transmitted to the programmable logic device (FPGA/CPLD), and the programmable logic device (FPGA/CPLD) will generate the servo internal control cycle signal according to its own internal clock to the algorithm processor Unit, and will correct the generation time point of the last servo internal control cycle signal in the EtherCat bus synchronization cycle according to the bus synchronization signal to make it consistent with the arrival point of the EtherCat bus synchronization cycle signal, that is, in the last servo internal control cycle, centralized forced synchronization .
  • FPGA/CPLD programmable logic device
  • the locally generated servo internal control cycle is generally faster than the EtherCat bus synchronization cycle, it will appear as the last servo internal control cycle (the 16th servo internal control cycle) in an EtherCat bus synchronization cycle
  • the EtherCat bus synchronization cycle signal arrives ⁇ T later than the servo internal control cycle signal that should be generated. At this time, even if the time when the slave station should generate the last servo internal control cycle signal is reached, it will not be generated, but wait for the EtherCat bus synchronization When the cycle signal arrives, once it arrives, the last servo internal control cycle signal is immediately generated to keep the synchronization with the EtherCat bus synchronization cycle signal.
  • the technical problem to be solved by the present invention is to overcome the defects in the prior art and propose a method for the servo internal control cycle to dynamically follow the EtherCat bus synchronization cycle.
  • the basic idea is to disperse the error evenly to the next cycle, and then disperse it evenly to the next cycle according to the error of the next cycle, repeat iteratively, and keep following to achieve the bus synchronization cycle and the servo internal control cycle.
  • the technical problem to be solved by the present invention is to overcome the defects in the prior art and propose a method for the servo internal control cycle to dynamically follow the EtherCat bus synchronization cycle.
  • the basic idea is to disperse the error evenly to the next cycle, and then disperse it evenly to the next cycle according to the error of the next cycle, repeat iteratively, and keep following to achieve the bus synchronization cycle and the servo internal control cycle.
  • dynamic error elimination is to overcome the defects in the prior art and propose a method for the servo internal control cycle to dynamically follow the
  • the present invention is a method for the servo internal control cycle to dynamically follow the EtherCat bus synchronization cycle. The steps are:
  • the servo receives the EtherCat command and completes the distributed clock function, and generates a periodic EtherCat bus synchronization cycle signal, which is used to periodically synchronize the internal control cycle of the servo. In a multi-node (slave) system, it is used to synchronize the entire system to the EtherCat bus.
  • the bus synchronization cycle signal generated by the EtherCat slave station is transmitted to the programmable logic device (such as FPGA/CPLD).
  • the programmable logic device (FPGA/CPLD) generates the servo internal control cycle signal according to the local clock to the algorithm processor unit, usually servo
  • the frequency of the internal control cycle signal is an integer multiple of the frequency of the bus synchronization cycle signal, denoted as n (n ⁇ 1); that is, an EtherCat bus synchronization cycle contains n servo internal control cycles. Record the internal control cycle time of each servo as T, and the EtherCat bus synchronization cycle time as Tesync.
  • Tesync n ⁇ T.
  • the generated internal control cycle signal of the last servo arrives earlier than ⁇ T.
  • the internal control cycle signal of the servo is forced to be generated in advance to maintain synchronization with the EtherCat bus synchronization cycle signal; but in the next EtherCat bus synchronization cycle, each servo internal
  • the control cycle time is adjusted to T- ⁇ T/n; every subsequent EtherCat bus synchronization cycle will be processed the same.
  • the performance results are: dynamic elimination of errors, real-time adjustment, so that the internal control cycle signal of the servo is basically consistent with the bus synchronization signal. Once there is an error, it will be eliminated in the next bus cycle.
  • the last servo internal control cycle signal arrives late by ⁇ T. At this time, even if the time point when the internal servo internal control cycle signal should be generated internally, it will not be generated. Instead, it will wait for the arrival of the bus synchronization signal. Once it arrives, the last servo internal control signal will be generated immediately.
  • the performance results are: dynamic elimination of errors, real-time adjustment, so that the internal control cycle signal of the servo is basically consistent with the bus synchronization cycle signal. Once there is an error, it will be eliminated in the next bus synchronization cycle.
  • the method of the present invention evenly disperses the error to the next cycle, repeats iteratively, keeps following, and dynamically corrects to achieve the elimination of dynamic error between the EtherCat bus synchronization cycle and the servo internal control cycle.
  • the method of the present invention is applied in a servo drive, and when the servo internal control cycle generation counter and the control motor PWM generation counter are integrated into one counter, the servo internal control cycle and the PWM generation cycle are fully synchronized, which is more conducive to the stable control of the servo motor.
  • FIG. 1 is a schematic diagram of the servo structure and synchronization signal connection of an embodiment of the present invention.
  • Fig. 2 is a schematic diagram of a processing method for eliminating errors when the servo internal control cycle is generally slower than the EtherCat bus synchronization cycle in the prior art.
  • Fig. 3 is a schematic diagram of the error processing method of the present invention when the sum of n servo internal control cycles in an EtherCat bus synchronization cycle, n ⁇ T, is greater than the EtherCat bus synchronization cycle.
  • Fig. 4 is a schematic diagram of the error elimination processing method in the prior art when the servo internal control cycle is generally faster than the EtherCat bus synchronization cycle.
  • Figure 5 is a schematic diagram of the error processing method of the present invention when the sum of n servo internal control cycles in an EtherCat bus synchronization cycle, n ⁇ T, is less than the EtherCat bus synchronization cycle.
  • the method of the present invention is mainly implemented in a programmable logic device FPGA.
  • the servo receives the EtherCat command and completes the distributed clock function, and then generates a bus synchronization cycle signal to periodically synchronize the internal control cycle of the servo. (Slave) system, used to synchronize the entire system to the EtherCat bus.
  • EtherCat bus synchronization cycle Tesync 2ms
  • the cycle is generated by itself based on the local clock, and the servo internal control cycle signal generated by this local clock and the EtherCat bus synchronization cycle will definitely produce an error ⁇ T.
  • the existing general architecture is that the bus synchronization signal generated by the EtherCat slave station is transmitted to the programmable logic device (FPGA/CPLD), and the programmable logic device (FPGA/CPLD) will generate the servo internal control cycle signal according to its own internal clock to the algorithm processor Unit, and will modify the generation time point of the last servo internal control cycle signal in the EtherCat bus synchronization cycle according to the EtherCat bus synchronization cycle signal, so that the generation time point is consistent with the bus synchronization cycle signal generation point.
  • FPGA/CPLD programmable logic device
  • Figure 3 shows that when the internal control cycle of the servo generated by the local clock is slower than the synchronization cycle of the EtherCat bus, it appears that the bus synchronization cycle signal arrives earlier than the internal control cycle signal ⁇ T of the servo that should be generated.
  • the last servo internal control cycle in the bus synchronization cycle (the 16th servo internal control cycle) is forcibly generated in advance of the servo internal control cycle signal to maintain synchronization with the bus synchronization signal, but at the same time, this time point and the original should be noted
  • Fig. 5 When the servo internal control cycle generated by the local clock is generally faster than the EtherCat bus synchronization cycle, it appears that the bus synchronization cycle signal arrives later than the servo internal control cycle signal ⁇ T that should be generated.
  • the processing method of the present invention is: the first time, even if The time when the servo internal control signal should be generated internally has arrived, and it will not be generated. Instead, it will wait for the arrival of the EtherCat bus synchronization cycle signal. Once it arrives, the last (16th) servo internal control cycle signal will be generated immediately to maintain synchronization with the EtherCat bus.
  • the verification of the present invention is implemented in FPGA, and the specific method is two sets of counters, one is used to monitor the EtherCat bus synchronization cycle, and the other is used to generate the servo internal control cycle signal.
  • the generation of the internal control cycle signal of the servo adopts the decimal frequency division method. Only the cycle calculation module provides the cycle value that should generate the internal control cycle signal to accurately generate the synchronization signal.
  • the fractional frequency method itself is also a method to eliminate accumulated errors, and it is also very suitable for FPGA implementation.
  • the cycle calculation module only needs to calculate the error according to the monitored bus synchronization cycle and the generated internal control cycle, and compensate it to the cycle generated by each servo internal control cycle signal in the next bus synchronization cycle.
  • the present invention When the present invention is applied in a servo driver, when the servo internal control cycle generation counter and the control motor PWM generation counter are integrated into one counter, the servo internal control cycle and the PWM generation cycle are completely synchronized, which is more conducive to the smooth control of the servo motor.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Numerical Control (AREA)
  • Control Of Multiple Motors (AREA)

Abstract

L'invention concerne un procédé permettant à un cycle de commande interne asservi de suivre dynamiquement un cycle de synchronisation de bus EtherCAT. Le temps de cycle de commande interne asservi est enregistré selon la notation T et le temps de cycle de synchronisation de bus EtherCAT est enregistré selon la notation Tesync. Si n×T est supérieur à un cycle de bus EtherCAT, un signal de cycle de commande interne asservi est généré en force à l'avance pour maintenir une synchronisation avec un signal de cycle de synchronisation de bus ; sinon, si n×T est inférieur au cycle de synchronisation de bus EtherCAT, aucun signal de cycle de commande interne asservi n'est généré, même si le temps de production d'un signal de cycle de commande interne asservi est atteint, puisqu'il est nécessaire d'attendre l'arrivée du signal de cycle de synchronisation de bus ; une fois que le signal de cycle de synchronisation de bus arrive, le dernier signal de cycle de commande interne asservi est généré immédiatement pour maintenir une synchronisation avec le signal de cycle de synchronisation de bus. Ensuite, chaque cycle de synchronisation de bus EtherCAT est traité de manière similaire selon le principe décrit. Des erreurs dynamiques sont éliminées par réglage dynamique du signal de cycle de commande interne asservi et du signal de cycle de synchronisation de bus, afin que des erreurs entre des signaux de synchronisation, provoquées par l'écart inhérent entre des horloges non homologues, soient éliminées et que la synchronisation finale des stations esclaves de tous les étages soit maintenue.
PCT/CN2019/087247 2019-04-12 2019-05-16 Procédé permettant à un cycle de commande interne asservi de suivre dynamiquement un cycle de synchronisation de bus ethercat WO2020206808A1 (fr)

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CN201910292890.0 2019-04-12
CN201910292890.0A CN109947030A (zh) 2019-04-12 2019-04-12 伺服内部控制周期动态跟随EtherCat总线同步周期的方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114679249A (zh) * 2022-05-26 2022-06-28 深圳市杰美康机电有限公司 一种EtherCAT通讯同步方法及装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111381539B (zh) * 2020-03-18 2023-11-24 深圳市小步数控有限公司 一种总线实时同步控制装置
CN111552325B (zh) * 2020-04-28 2023-07-25 深圳易能电气技术股份有限公司 位置指令同步方法、装置和计算机可读存储介质
CN111953469B (zh) * 2020-07-21 2023-03-24 季华实验室 一种伺服驱动器与Ethercat DC时钟的同步方法、装置及电子设备
CN112115079B (zh) * 2020-08-19 2022-07-26 苏州伟创电气科技股份有限公司 总线周期同步的方法和系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005275575A (ja) * 2004-03-23 2005-10-06 Toyota Motor Corp データ収集方法及びデータ収集装置
CN104301188A (zh) * 2013-05-29 2015-01-21 株式会社安川电机 工业用设备、控制器、数据传输方法及数据发送方法
CN105024777A (zh) * 2015-07-29 2015-11-04 上海新时达电气股份有限公司 基于EtherCAT实时以太网的伺服驱动器同步方法
CN107465474A (zh) * 2016-06-03 2017-12-12 上海铼钠克数控科技股份有限公司 数控系统总线设备的时间同步系统及方法
CN109554851A (zh) * 2018-11-19 2019-04-02 杰克缝纫机股份有限公司 缝纫机双轴同步控制方法、装置、设备、系统和存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005275575A (ja) * 2004-03-23 2005-10-06 Toyota Motor Corp データ収集方法及びデータ収集装置
CN104301188A (zh) * 2013-05-29 2015-01-21 株式会社安川电机 工业用设备、控制器、数据传输方法及数据发送方法
CN105024777A (zh) * 2015-07-29 2015-11-04 上海新时达电气股份有限公司 基于EtherCAT实时以太网的伺服驱动器同步方法
CN107465474A (zh) * 2016-06-03 2017-12-12 上海铼钠克数控科技股份有限公司 数控系统总线设备的时间同步系统及方法
CN109554851A (zh) * 2018-11-19 2019-04-02 杰克缝纫机股份有限公司 缝纫机双轴同步控制方法、装置、设备、系统和存储介质

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114679249A (zh) * 2022-05-26 2022-06-28 深圳市杰美康机电有限公司 一种EtherCAT通讯同步方法及装置

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