WO2020194649A1 - Control device and control system - Google Patents

Abstract

This control device (20) is provided with: a first communication unit (21) which receives a control command; a computation unit (22) which, in accordance with the control command received by the first communication unit (21), generates a gate signal for controlling a switching element in an electric power conversion device (2); and a second communication unit (23) which transmits the gate signal to the electric power conversion device (2). The control command includes an instruction to operate or stop the electric power conversion device (2). In addition, the control device (20) is disposed adjacent to the electric power conversion device (2).

Description

Control device and control system

The present invention relates to a control device and a control system that control a power conversion device.

Some electric railway cars are equipped with a power conversion device that converts the power supplied from the substation through the overhead wire into the desired power and supplies the converted power to the load inside the car. By controlling the switching element of the power conversion device by the control device, the power conversion device converts the power supplied from the substation into the desired power. An example of this type of power conversion device is disclosed in Patent Document 1.

International Publication No. 2000/19590

The power conversion device disclosed in Patent Document 1 measures a voltage between input terminals of a main circuit and a current flowing through an electric motor, and outputs a sensor signal indicating a voltage measurement value and a current measurement value, and a sensor. It includes a control device that generates a gate signal according to a measured value of voltage and a measured value of current indicated by the signal and outputs the gate signal in parallel, and a main circuit having a switching element that is switched on and off by the gate signal. The control device performs PWM (Pulse Width Modulation) control that adjusts the duty ratio of the gate signal according to the measured value of voltage and the measured value of current indicated by the sensor signal.

If the control device and the main circuit are arranged apart from each other, the wiring connecting the control device and the main circuit becomes long, which causes a signal delay, and thus the responsiveness of PWM control deteriorates.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the responsiveness of control of a power conversion device by a control device.

In order to achieve the above object, the control device of the present invention includes a first communication unit, a calculation unit, and a second communication unit. The first communication unit receives a control command including an instruction to start or stop the power conversion device. The arithmetic unit generates a signal for controlling the power conversion device in response to a control command received by the first communication unit. The second communication unit transmits a signal to the power converter. The control device is arranged adjacent to the power conversion device.

According to the present invention, a control device that transmits a signal generated in response to a control command to the power conversion device is arranged adjacent to the power conversion device. As a result, the signal delay due to the wiring length does not occur, so that the responsiveness of the control of the power conversion device by the control device is improved.

Block diagram of the control system according to the first embodiment of the present invention The figure which shows the implementation example of the control system which concerns on Embodiment 1. Block diagram of the control system according to the second embodiment of the present invention The figure which shows the implementation example of the control system which concerns on Embodiment 2. Block diagram of the control system according to the third embodiment of the present invention The figure which shows the mounting example of the command device which concerns on Embodiment 3. The figure which shows the mounting example of the control device which concerns on Embodiment 3. The figure which shows the mounting example of the control device which concerns on Embodiment 3. Block diagram of the control system according to the fourth embodiment of the present invention The figure which shows the mounting example of the control apparatus which concerns on Embodiment 4. The figure which shows the mounting example of the control apparatus which concerns on Embodiment 4.

Hereinafter, the control device according to the embodiment of the present invention, specifically, the control device for controlling the electronic device by transmitting a signal to the electronic device and the control system having the control device will be described in detail with reference to the drawings. Explain to. In the figure, the same or equivalent parts are designated by the same reference numerals.

(Embodiment 1)
Some electric railway vehicles are equipped with a power conversion device that converts the power supplied from the substation through the overhead wire into three-phase AC power and supplies the three-phase AC power to the electric motor. Taking this power conversion device as an example, the control device and the control system that control the power conversion device will be described in the first embodiment.

FIG. 1 shows a control system according to the first embodiment. The control system 1 shown in FIG. 1 controls a switching element included in the power conversion device 2 that supplies electric power to the electric motor 3. The control system 1 will be described by taking as an example a case where the power conversion device 2 is composed of a VVVF (Variable Voltage Variable Frequency) inverter and the electric motor 3 is composed of a three-phase induction motor. The control system 1 acquires an operation command from a driver's cab (not shown) and acquires a sensor signal from the sensor 4. The sensor 4 measures the current of each phase output by the power conversion device 2. The sensor signal output by the sensor 4 indicates a measured value of the current of each phase.

The control system 1 generates a signal for controlling the power conversion device 2 and transmits the signal to the power conversion device 2. Specifically, the control system 1 generates a gate signal for controlling the switching element of each phase of the power conversion device 2 according to the operation command and the measured value of the current of each phase indicated by the sensor signal. , The gate signal is transmitted to the switching element included in the power conversion device 2. By repeating on / off of the switching element controlled by the gate signal, the power conversion device 2 converts the power supplied from a power source (not shown), for example, a substation into three-phase AC power, and converts the three-phase AC power into the electric motor 3. Supply to. By driving the electric motor 3 supplied with the three-phase AC electric power, the propulsive force of the railway vehicle can be obtained.

The control system 1 is a command device 10 that generates a control command including an instruction to start or stop the power conversion device 2, and a control that generates a gate signal that controls a switching element of the power conversion device 2 in response to the control command. The device 20 is provided.
The control system 1 further includes a high-speed serial line 5 that connects the command device 10 and the control device 20. The high-speed serial line 5 may be a transmission line conforming to the Ethernet (registered trademark) standard and may be a transmission line capable of serial communication.
Further, the control system 1 includes a first parallel line 6 that connects the control device 20 and the sensor 4. Further, the control system 1 includes a second parallel line 7 that connects the control device 20 and the power conversion device 2. The first parallel line 6 and the second parallel line 7 are composed of transmission lines that enable parallel transmission.

The command device 10 includes a command generation unit 11 that acquires an operation command from a driver's cab (not shown) and generates a control command in response to the operation command, and a command transmission unit 12 that sends the control command to the control device 20.

The command generation unit 11 generates a control command instructing the operation or stop of the power conversion device 2 in response to the operation command, and sends the control command to the command transmission unit 12. The operation command includes a power running command indicating the target acceleration of the railway vehicle, a brake command indicating the target deceleration of the railway vehicle, and the like.
The command transmission unit 12 is connected to the first communication unit 21 of the control device 20, which will be described later, via the high-speed serial line 5. Further, the command transmission unit 12 sends a control command to the first communication unit 21 of the control device 20.

The control device 20 has a first communication unit 21 that receives a control command, a calculation unit 22 that generates a gate signal in response to the control command and a sensor signal, and a second communication that transmits the gate signal to the power conversion device 2. A unit 23 and a measured value acquisition unit 24 that acquires a sensor signal from the sensor 4 are provided.

When the first communication unit 21 receives the control command from the command device 10 via the high-speed serial line 5, the first communication unit 21 sends the control command to the calculation unit 22.
The measured value acquisition unit 24 is connected to the sensor 4 via the first parallel line 6. Further, the measured value acquisition unit 24 acquires a sensor signal from the sensor 4 and sends the measured value of the current of each phase indicated by the sensor signal to the calculation unit 22.
The calculation unit 22 generates a gate signal for bringing the output of the power conversion device 2 closer to the target value according to the control command according to the control command and the measured value of the current of each phase.
The second communication unit 23 is connected to the power conversion device 2 via the second parallel line 7. Further, the second communication unit 23 sends a gate signal to the switching element of each phase of the power conversion device 2.

Further, the control device 20 is arranged adjacent to the power conversion device 2. Specifically, during transmission of the gate signal from the control device 20 to the power conversion device 2, the control device 20 is adjacent to the power conversion device 2 to such an extent that the influence of noise superimposed on the gate signal is sufficiently small. Be placed. The distance between the control device 20 and the power conversion device 2 is preferably 1 meter or less. More preferably, the housing of the control device 20 may be arranged in contact with the housing of the power conversion device 2. In this case, the switching element of the power conversion device 2 is housed in a shield housing made of a conductive member, and then the housing of the control device 20 is arranged in contact with the housing of the power conversion device 2. Is preferable. By accommodating the switching element in the shield housing, it is possible to suppress the superimposition of switching noise on the gate signal.
More preferably, the control device 20 may be arranged adjacent to the sensor 4. Specifically, the control device 20 is arranged adjacent to the sensor 4 so that the influence of noise superimposed on the sensor signal is sufficiently reduced during transmission of the sensor signal from the sensor 4 to the measured value acquisition unit 24. Is preferable.

An implementation example of the control system 1 will be described with reference to FIG. As shown in FIG. 2, the command generation unit 11 included in the command device 10 is realized by a CPU (Central Processing Unit) 31, a memory 32, and an input IF (Interface) 33, and the command transmission unit 12 , FPGA (Field Programmable Gate Array) 34, UDP (User Datagram Protocol) / IP (Internet Protocol) core 35, and PHY (Physical layer) chip It is realized by 36. The CPU 31, the memory 32, the input IF 33, and the FPGA 34 are connected to each other by the system bus 37. The system bus 37 is composed of a serial bus. The UDP / IP core 35 communicates with the MAC (Media Access Control) layer, the IP (Internet Protocol) layer, and the UDP layer. Further, the PHY chip 36 communicates with the physical layer.

Further, the first communication unit 21 included in the control device 20 is realized by the UDP / IP core 42 included in the FPGA 41 and the PHY chip 43, and the arithmetic unit 22 is a DSP (Digital Signal Processor) 44 and a memory. It is realized by 45 and the arithmetic circuit 46 included in the FPGA 41. Further, the second communication unit 23 is realized by the output IF 47 included in the FPGA 41. Further, the measured value acquisition unit 24 is realized by the input IF 48 included in the FPGA 41. The DSP 44, the memory 45, and the FPGA 41 are connected to each other by the system bus 49. The system bus 49 is composed of a serial bus. The UDP / IP core 42 communicates with the MAC layer, the IP layer, and the UDP layer. Further, the PHY chip 43 communicates with the physical layer.

The PHY chip 36 and the PHY chip 43 are connected by a high-speed serial line 5. Further, the input IF 48 and the sensor 4 are connected by the first parallel line 6. Further, the output IF 47 and the power conversion device 2 are connected by a second parallel line 7.

The operation of the control system 1 having the above configuration will be described.
When the operation command includes a power running command, the command generating unit 11 sends a control command instructing the operation of the power conversion device 2 to the command transmitting unit 12 so as to output a target value corresponding to the power running command. When the operation command includes a brake command, the command generation unit 11 sends a control command instructing the stop of the power conversion device 2 to the command transmission unit 12.

Specifically, the input IF 33 sends an operation command to the CPU 31 via the system bus 37 when an operation command is input from a driver's cab (not shown). A program for generating a control command is stored in the memory 32. The CPU 31 executes a program stored in the memory 32 and generates a control command from an operation command input via the input IF 33. The CPU 31 sends a control command to the UDP / IP core 35 included in the FPGA 34 via the system bus 37.

Next, the command transmission unit 12 performs serial transmission via the high-speed serial line 5 and sends a control command to the control device 20. Specifically, the UDP / IP core 35 generates an Ethernet packet including a control command and sends it to the PHY chip 36. The PHY chip 36 generates a communication signal from the Ethernet packet and sends the communication signal to the high-speed serial line 5.

When the first communication unit 21 receives the control command from the command device 10, it sends it to the calculation unit 22. Specifically, when the PHY chip 43 receives the communication signal via the high-speed serial line 5, it generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42. The UDP / IP core 42 extracts a control command from the Ethernet packet generated by the PHY chip 43, and sends the control command to the DSP 44 via the system bus 49.

Further, the measured value acquisition unit 24 acquires a sensor signal indicating the measured value of the current from the sensor 4 via the first parallel line 6, and sends the measured value of the current indicated by the sensor signal to the calculation unit 22. Specifically, the input IF48 performs parallel-serial conversion by an A-D (Analog-to-Digital) converter (not shown), in which the measured value of the current acquired from the sensor 4 via the first parallel line 6 is serialized. Data is generated and sent to the arithmetic circuit 46. The serial data converted by the AD converter (not shown) is serial-parallel converted by the arithmetic circuit 46. The arithmetic circuit 46 sends parallel data to the DSP 44 via the system bus 49.

The calculation unit 22 generates a gate signal according to the control command and the measured value of the current.
When the control command instructs the operation of the power conversion device 2 to output the target value corresponding to the power running command, the calculation unit 22 issues the magnetic flux current command Id * and the torque current command Iq * in response to the power running command. Generate. The calculation unit 22 holds in advance the correspondence between the target acceleration indicated by the power running command and the magnetic flux current command and the torque current command. Then, the calculation unit 22 brings the exciting current Id obtained by three-phase and two-phase conversion of the measured value of each phase current indicated by the sensor signal close to the magnetic flux current command Id *, and sets the measured value of each phase current indicated by the sensor signal. The voltage commands Vd * and Vq * are calculated so that the torque current Iq obtained by the three-phase two-phase conversion approaches the torque current command Iq *. Further, the calculation unit 22 performs rotational coordinate conversion and two-phase three-phase conversion of the voltage commands Vd * and Vq * to calculate the respective voltage commands of the U phase, the V phase, and the W phase. Then, the arithmetic unit 22 generates a gate signal for the switching element of each phase based on the comparison between the voltage commands of the U phase, the V phase, and the W phase and the triangular wave carrier signal, and sends the gate signal to the second communication unit 23.

As another example, when the control command instructs the power conversion device 2 to stop, the calculation unit 22 performs the U-phase, the V-phase, and the V-phase so that the respective voltage commands of the U-phase, the V-phase, and the W-phase gradually decrease. , W phase voltage commands are calculated. Then, the arithmetic unit 22 generates a gate signal for the switching element of each phase based on the comparison between the voltage commands of the U phase, the V phase, and the W phase and the triangular wave carrier signal, and sends the gate signal to the second communication unit 23.

Specifically, the DSP 44 calculates each of the U-phase, V-phase, and W-phase voltage commands from the control commands according to the program for calculating the voltage commands stored in the memory 45, and via the system bus 49. And send it to the arithmetic circuit 46. The arithmetic circuit 46 generates a gate signal for the switching element of each phase based on the comparison between the U-phase, V-phase, and W-phase voltage commands and the triangular wave carrier signal, and sends the gate signal to the output IF 47.

The second communication unit 23 sends a gate signal to the switching element of each phase of the power conversion device 2. The second communication unit 23 transmits the gate signal to the power conversion device 2 by parallel communication. Specifically, the output IF 47 sends a gate signal of parallel data to the power conversion device 2 via the second parallel line 7.

The switching element of each phase of the power conversion device 2 is turned on or off according to the gate signal sent from the control device 20. As an example, when the switching element of each phase of the power conversion device 2 repeats on / off according to the gate signal, the power conversion device 2 converts the power supplied from a power source (not shown) into three-phase AC power, and three-phase. AC power is supplied to the electric motor 3.

As described above, the control device 20 according to the first embodiment is arranged adjacent to the power conversion device 2. As a result, the second parallel line 7 is shortened, and signal delay due to the wiring length does not occur, so that the responsiveness of the control of the power conversion device 2 by the control device 20 is improved. Further, it is possible to reduce the influence of noise superimposed on the gate signal during transmission of the gate signal. As a result, it is not always necessary to provide the control device 20 with an isolator for reducing the influence of noise superimposed on the gate signal, and by not providing the isolator, the responsiveness of the control of the power conversion device 2 by the control device 20 is improved. It is also possible.

Further, when the control device 20 is arranged adjacent to the sensor 4, the wiring between the control device 20 and the sensor 4 is shortened, and the signal delay due to the wiring length does not occur. Therefore, the power conversion device 2 by the control device 20 The responsiveness of the control is improved. Further, by shortening the wiring between the control device 20 and the sensor 4, it is possible to reduce the influence of noise superimposed on the sensor signal output by the sensor 4.

Further, since the command device 10 and the control device 20 are connected by the high-speed serial line 5, the number of wirings is reduced and the man-hours for wiring work are reduced as compared with the case where the command device 10 and the control device 20 are connected by a parallel line. It becomes possible. When the high-speed serial line 5 is composed of, for example, a transmission line conforming to the standard of IEEE802.3u, transmission over a long distance, for example, 100 m is possible via the high-speed serial line 5. Therefore, since the command device 10 can be arranged at a position far away from the control device 20, the degree of freedom of the arrangement position of the command device 10 is increased with respect to the position of the control device 20.

Further, since the command transmission unit 12 is realized by the UDP / IP core 35 and the PHY chip 36 included in the FPGA 34, the processing speed of the command transmission unit 12 is higher than that in the case where the processing of the UDP / IP core 35 is performed by the CPU 31. It will be possible to make it faster. Similarly, since the first communication unit 21 is realized by the UDP / IP core 42 included in the FPGA 41 and the PHY chip 43, the first communication unit 21 is more than the case where the processing of the UDP / IP core 42 is performed by the DSP 44. The processing speed of 21 can be increased.

(Embodiment 2)
In order to increase the reliability of communication via the high-speed serial line 5, the control system 1 may include a plurality of high-speed serial lines 5. A configuration in which the control system 1 includes a plurality of high-speed serial lines 5 for connecting the command device 10 and the control device 20 will be described in the second embodiment. As shown in FIG. 3, the control system 1 includes two high-speed serial lines 5a and 5b that connect the command device 10 and the control device 20. When an abnormality occurs in the communication via the high-speed serial line 5a, the command device 10 and the control device 20 communicate with each other via the high-speed serial line 5b.

An implementation example of the control system 1 having the above configuration will be described with reference to FIG. The configuration of the command transmitting unit 12 and the first communication unit 21 different from those of the first embodiment will be described. As shown in FIG. 4, the command transmission unit 12 is realized by the UDP / IP cores 35a and 35b included in the FPGA 34, the PHY chips 36a and 36b, and the switching unit 38. The UDP / IP cores 35a and 35b are connected to the PHY chips 36a and 36b, respectively. The UDP / IP cores 35a and 35b communicate with the MAC layer, the IP layer, and the UDP layer. Further, the PHY chips 36a and 36b communicate with each other in the physical layer.

Further, the first communication unit 21 is realized by the UDP / IP cores 42a and 42b included in the FPGA 41, the PHY chips 43a and 43b, and the switching unit 50. The UDP / IP cores 42a and 42b are connected to the PHY chips 43a and 43b, respectively. The UDP / IP cores 42a and 42b communicate with the MAC layer, the IP layer, and the UDP layer. Further, the PHY chips 43a and 43b communicate with each other in the physical layer.

The operation of the control system 1 having the above configuration will be described.
The operation of the command generation unit 11 is the same as that of the first embodiment. However, the CPU 31 constituting the command generation unit 11 sends the generated control command to the switching unit 38 included in the FPGA 34 via the system bus 37. When the switching unit 38 acquires the control command from the CPU 31, the switching unit 38 sends it to the UDP / IP core 35a. The UDP / IP core 35a generates an Ethernet packet from the control command and sends it to the PHY chip 36a. The PHY chip 36a generates a communication signal from the Ethernet packet and sends the communication signal to the high-speed serial line 5a.

When the PHY chip 43a receives the communication signal via the high-speed serial line 5a, the PHY chip 43a generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42a. The UDP / IP core 42a extracts a control command from the Ethernet packet generated by the PHY chip 43a and sends it to the switching unit 50. The switching unit 50 sends a control command to the DSP 44 via the system bus 49. The operation of the DSP44, the input IF48, and the output IF47 is the same as that of the first embodiment. The gate signal generated in the same manner as in the first embodiment is sent to the switching element of the power conversion device 2, and the switching element is turned on or off.

In parallel with the process of controlling the switching element of the power conversion device 2 described above, the control system 1 determines whether or not an abnormality has occurred in the high-speed serial line 5a used for communication. When the control system 1 determines that an abnormality has occurred in the high-speed serial line 5a, it stops communication via the high-speed serial line 5a and starts communication via the high-speed serial line 5b. As an example, the control device 20 determines whether or not an abnormality has occurred in the high-speed serial line 5a based on the error detection of the data sent from the command device 10, and the command device 10 determines the interval of communication from the control device 20. A configuration for determining whether or not an abnormality has occurred in the high-speed serial line 5a will be described.

The first communication unit 21 performs error detection on the data transmitted from the command transmission unit 12. Specifically, the UDP / IP core 42a extracts predetermined data used for calculating the control command, the checksum value, and the checksum value from the Ethernet packet, and sends the data to the switching unit 50. The UDP / IP core 35a of the command device 10 generates a checksum value from predetermined data included in the Ethernet packet when generating an Ethernet packet from a control command, and generates an Ethernet packet including the checksum value. And. The predetermined data includes, for example, an IP header, a UDP header, and the like.

The switching unit 50 calculates a checksum value from predetermined data and compares it with the checksum value included in the Ethernet packet. When the switching unit 50 determines that the calculated checksum value and the checksum value included in the Ethernet packet match, the switching unit 50 sends a control command acquired from the UDP / IP core 42a to the DSP 44 via the system bus 49. send. When the switching unit 50 determines that the calculated checksum value and the checksum value included in the Ethernet packet do not match, the switching unit 50 discards the control command acquired from the UDP / IP core 42a and discards the control command acquired from the UDP / IP core 42b. Wait until a control command is received.

Further, when the switching unit 50 determines that the calculated checksum value and the checksum value included in the Ethernet packet match, the switching unit 50 notifies the UDP / IP core 42a of the determination result. The UDP / IP core 42a notified of the discrimination result generates an Ethernet packet for notifying the discrimination result and sends it to the PHY chip 43a. The PHY chip 43a generates a communication signal from an Ethernet packet for notifying the determination result, and sends the communication signal to the high-speed serial line 5a.
When the PHY chip 36a receives the communication signal via the high-speed serial line 5a, the PHY chip 36a generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 35a. The UDP / IP core 35a extracts the discrimination result from the Ethernet packet generated by the PHY chip 36a and sends it to the switching unit 38. When the switching unit 38 receives the determination result, the switching unit 38 continues to send the control command acquired from the CPU 31 to the UDP / IP core 35a.

On the other hand, when the switching unit 50 determines that the calculated checksum value and the checksum value included in the Ethernet packet do not match, the switching unit 50 does not notify the UDP / IP core 42a of the determination result. Therefore, the UDP / IP core 42a does not generate the Ethernet packet for notifying the determination result as described above, and the communication signal is not transmitted from the PHY chip 43a to the high-speed serial line 5a.
The switching unit 38 determines whether or not the period during which the determination result is not received is equal to or longer than the predetermined period. When the switching unit 38 determines that the period during which the determination result is not received exceeds the predetermined period, the switching unit 38 stops sending the control command acquired from the CPU 31 to the UDP / IP core 35a. Then, the switching unit 38 sends the control command acquired from the CPU 31 to the UDP / IP core 35b. The UDP / IP core 35b generates an Ethernet packet from the control command and sends it to the PHY chip 36b. The PHY chip 36b generates a communication signal from the Ethernet packet and sends the communication signal to the high-speed serial line 5b.

When the PHY chip 43b receives the communication signal via the high-speed serial line 5b, the PHY chip 43b generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42b. The UDP / IP core 42b extracts a control command from the Ethernet packet generated by the PHY chip 43b and sends it to the switching unit 50. As described above, the switching unit 50 calculates the checksum value from the predetermined data and compares it with the checksum value included in the Ethernet packet. When the switching unit 50 determines that the calculated checksum value and the checksum value included in the Ethernet packet match, the switching unit 50 sends a control command acquired from the UDP / IP core 42b to the DSP 44 via the system bus 49. send. Subsequent processing is the same as in the above example.

As described above, the control system 1 according to the second embodiment transmits a control command via the other of the high-speed serial lines 5a and 5b when an abnormality occurs in one of the high-speed serial lines 5a and 5b. This improves the reliability of the control system 1. That is, even if a transmission abnormality occurs in one of the high-speed serial lines 5a and 5b, the transmission of the control command is not interrupted, so that the responsiveness of the control of the power conversion device 2 by the control device 20 is improved.

(Embodiment 3)
The number of control devices 20 to which the command device 10 sends a control command is not limited to one, and may be plural. As shown in FIG. 5, the control system 1 according to the third embodiment includes one command device 10 and two control devices 20a and 20b. The control device 20a is a power conversion device 2a according to a control command acquired from the command device 10 and a measured value of the current of each phase acquired from the sensor 4a that measures the current of each phase output by the power conversion device 2a. Control the switching element. The control device 20b is a power conversion device 2b according to a control command acquired from the command device 10 and a measured value of the current of each phase acquired from the sensor 4b that measures the current of each phase output by the power conversion device 2b. Control the switching element.

The control system 1 includes a high-speed serial line 5a that connects the command device 10 and the control device 20a, and a high-speed serial line 5b that connects the command device 10 and the control device 20b. Further, the control system 1 includes a first parallel line 6a that connects the control device 20a and the sensor 4a, a second parallel line 7a that connects the second communication unit 23a and the power conversion device 2a, and the control device 20b and the sensor 4b. A first parallel line 6b for connecting the above and a second parallel line 7b for connecting the second communication unit 23b and the power conversion device 2b are provided.

The configuration and operation of the command device 10 are the same as those in the first embodiment, except that the command transmission unit 12 sends a control command to each of the control devices 20a and 20b.
The configuration and operation of the control devices 20a and 20b are the same as those of the control device 20 according to the first embodiment. Specifically, the control device 20a includes a first communication unit 21a, a calculation unit 22a, a second communication unit 23a, and a measured value acquisition unit 24a. Further, the control device 20a according to the second embodiment includes a first communication unit 21b, a calculation unit 22b, a second communication unit 23b, and a measured value acquisition unit 24b.

The control device 20a is arranged adjacent to the power conversion device 2a. Specifically, the control device 20a is adjacent to the power conversion device 2a to such an extent that the influence of noise superimposed on the gate signal during transmission of the gate signal from the control device 20a to the power conversion device 2a is sufficiently small. Be placed. The distance between the control device 20a and the power conversion device 2a is preferably 1 meter or less. More preferably, the housing of the control device 20a may be arranged in contact with the housing of the power conversion device 2a. In this case, the switching element of the power conversion device 2a is housed in a shield housing made of a conductive member, and then the housing of the control device 20a is arranged in contact with the housing of the power conversion device 2a. Is preferable. By accommodating the switching element in the shield housing, it is possible to suppress the superimposition of switching noise on the gate signal.
More preferably, the control device 20a may be arranged adjacent to the sensor 4a. Specifically, the control device 20a is arranged adjacent to the sensor 4a so that the influence of noise superimposed on the sensor signal is sufficiently reduced during transmission of the sensor signal from the sensor 4a to the measured value acquisition unit 24a. Is preferable.

Similarly, the control device 20b is arranged adjacent to the power conversion device 2b. Specifically, the control device 20b is adjacent to the power conversion device 2b to such an extent that the influence of noise superimposed on the gate signal during transmission of the gate signal from the control device 20b to the power conversion device 2b is sufficiently small. Be placed. The distance between the control device 20b and the power conversion device 2b is preferably 1 meter or less. More preferably, the housing of the control device 20b may come into contact with the housing of the power conversion device 2b. In this case, the switching element of the power conversion device 2b is housed in a shield housing made of a conductive member, and then the housing of the control device 20b is arranged in contact with the housing of the power conversion device 2b. Is preferable. By accommodating the switching element in the shield housing, it is possible to suppress the superimposition of switching noise on the gate signal.
More preferably, the control device 20b may be arranged adjacent to the sensor 4b. Specifically, the control device 20b is arranged adjacent to the sensor 4b so that the influence of noise superimposed on the sensor signal is sufficiently reduced during transmission of the sensor signal from the sensor 4b to the measured value acquisition unit 24b. Is preferable.

An implementation example of the control system 1 having the above configuration will be described with reference to FIGS. 6 to 8. The points different from the first embodiment will be mainly described.
As shown in FIG. 6, the command transmission unit 12 is realized by the UDP / IP cores 35a and 35b included in the FPGA 34 and the PHY chips 36a and 36b. The UDP / IP cores 35a and 35b are connected to the PHY chips 36a and 36b, respectively. The PHY chips 36a and 36b are connected to the PHY chips 43 of the first communication units 21a and 21b via high-speed serial lines 5a and 5b, respectively.

As shown in FIG. 7, similarly to the control device 20 according to the first embodiment, the first communication unit 21a is realized by the UDP / IP core 42 included in the FPGA 41 and the PHY chip 43, and the calculation unit 22a , The DSP 44, the memory 45, and the arithmetic circuit 46 included in the FPGA 41. Further, the second communication unit 23a is realized by the output IF47 included in the FPGA 41. Further, the measured value acquisition unit 24a is realized by the input IF48 included in the FPGA 41. The DSP 44, the memory 45, and the FPGA 41 are connected to each other by the system bus 49. The system bus 49 is composed of a serial bus. The PHY chip 43 constituting the first communication unit 21a is connected to the PHY chip 36a constituting the command transmitting unit 12 of the command device 10 via the high-speed serial line 5a.

As shown in FIG. 8, similarly to the control device 20 according to the first embodiment, the first communication unit 21b is realized by the UDP / IP core 42 included in the FPGA 41 and the PHY chip 43, and the calculation unit 22b , The DSP 44, the memory 45, and the arithmetic circuit 46 included in the FPGA 41. Further, the second communication unit 23b is realized by the output IF47 included in the FPGA 41. Further, the measured value acquisition unit 24b is realized by the input IF48 included in the FPGA 41. The DSP 44, the memory 45, and the FPGA 41 are connected to each other by the system bus 49. The system bus 49 is composed of a serial bus. The PHY chip 43 constituting the first communication unit 21b is connected to the PHY chip 36b constituting the command transmission unit 12 of the command device 10 via the high-speed serial line 5b.

The operation of the control system 1 having the above configuration will be described.
The operation of the command generation unit 11 is the same as that of the first embodiment. However, the CPU 31 constituting the command generation unit 11 sends the generated control command to each of the UDP / IP cores 35a and 35b included in the FPGA 34 via the system bus 37.
The command transmission unit 12 sends a control command to the first communication units 21a and 21b of the control devices 20a and 20b via the high-speed serial lines 5a and 5b, respectively.

Specifically, the UDP / IP core 35a generates an Ethernet packet from the control command and sends it to the PHY chip 36a. The PHY chip 36a generates a communication signal from the Ethernet packet and sends the communication signal to the high-speed serial line 5a.
The UDP / IP core 35b also generates an Ethernet packet from the control command and sends it to the PHY chip 36b. The PHY chip 36b generates a communication signal from the Ethernet packet and sends the communication signal to the high-speed serial line 5b.

When the first communication unit 21a of the control device 20a receives the control command from the command device 10 via the high-speed serial line 5a, the first communication unit 21a sends the control command to the calculation unit 22a as in the first embodiment. Specifically, when the PHY chip 43 receives the communication signal via the high-speed serial line 5a, the PHY chip 43 generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42. The UDP / IP core 42 extracts a control command from the Ethernet packet generated by the PHY chip 43, and sends the control command to the DSP 44 via the system bus 49.
The operations of the measured value acquisition unit 24a, the calculation unit 22a, and the second communication unit 23a of the control device 20a are the same as those in the first embodiment. The gate signal generated in the same manner as in the first embodiment is sent to the switching element of the power conversion device 2a, and the switching element is turned on or off.

When the first communication unit 21 of the control device 20b receives the control command from the command device 10 via the high-speed serial line 5b, the first communication unit 21 sends the control command to the calculation unit 22b as in the first embodiment. Specifically, when the PHY chip 43 receives a communication signal via the high-speed serial line 5b, it generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42. The UDP / IP core 42 extracts a control command from the Ethernet packet generated by the PHY chip 43, and sends the control command to the DSP 44 via the system bus 49.
The operations of the measured value acquisition unit 24b, the calculation unit 22b, and the second communication unit 23b of the control device 20b are the same as those in the first embodiment. The gate signal generated in the same manner as in the first embodiment is sent to the switching element of the power conversion device 2b, and the switching element is turned on or off.

As described above, the control devices 20a and 20b according to the third embodiment are arranged adjacent to the power conversion devices 2a and 2b, respectively. As a result, the second parallel lines 7a and 7b are shortened, and signal delay due to the wiring length does not occur, so that the responsiveness of control of the power conversion devices 2a and 2b by the control devices 20a and 20b is improved. Further, it is possible to reduce the influence of noise superimposed on the gate signal during transmission of the gate signal.

Further, when the control devices 20a and 20b are arranged adjacent to the sensors 4a and 4b, respectively, the wiring connecting the control devices 20a and 20b and the sensors 4a and 4b becomes shorter, and the signal delay due to the wiring length becomes shorter. Since it does not occur, the responsiveness of the control of the power conversion devices 2a and 2b by the control devices 20a and 20b is improved. Further, by shortening the wiring connecting the control devices 20a and 20b and the sensors 4a and 4b, it is possible to reduce the influence of noise superimposed on the sensor signals output by the sensors 4a and 4b.

Further, since the command device 10 and the control devices 20a and 20b are connected by high-speed serial lines 5a and 5b, the wiring is more than when the command device 10 and the control devices 20a and 20b are connected by a parallel line. The number of wiring work is reduced, and the man-hours for wiring work can be reduced. When the high-speed serial lines 5a and 5b are composed of, for example, transmission lines compliant with the IEEE802.3u standard, a long distance, for example, 100 m, is provided via the high-speed serial lines 5a and 5b without causing signal delay. Can be transmitted. Therefore, since the command device 10 can be arranged at a position far away from the control devices 20a and 20b, the degree of freedom of the arrangement position of the command device 10 is increased with respect to the positions of the control devices 20a and 20b.

Further, since the command transmission unit 12 is realized by the UDP / IP cores 35a and 35b and the PHY chips 36a and 36b included in the FPGA 34, the command is issued as compared with the case where each processing of the UDP / IP cores 35a and 35b is performed by the CPU 31. The processing speed of the transmission unit 12 can be increased. Similarly, since the first communication unit 21 of each of the control devices 20a and 20b is realized by the UDP / IP core 42 included in the FPGA 41 and the PHY chip 43, the processing of the UDP / IP core 42 is performed by the DSP 44. It is possible to increase the processing speed of the first communication unit 21 more than in the case.

(Embodiment 4)
In the control system 1 according to the third embodiment, the control devices 20a and 20b may notify each other of the presence or absence of failure of the power conversion devices 2a and 2b. In addition to the configuration of the control device 20a according to the third embodiment, the control device 20a according to the fourth embodiment shown in FIG. 9 further includes a failure determination unit 25a for determining the presence or absence of a failure of the power conversion device 2a. Further, the control device 20b further includes a failure determination unit 25b for determining the presence or absence of a failure of the power conversion device 2b, in addition to the configuration of the control device 20b according to the third embodiment. The control system 1 further includes a high-speed serial line 8 for connecting the control devices 20a and 20b, in addition to the configuration of the control system 1 according to the third embodiment. Preferably, the high-speed serial line 8 may be a transmission line conforming to the Ethernet standard and may be a transmission line capable of serial communication.

The configuration and operation of the command device 10 are the same as those in the third embodiment.
The configurations of the control devices 20a and 20b will be described focusing on the differences from the third embodiment. When the first communication unit 21a receives the control command from the command device 10 via the high-speed serial line 5a, the first communication unit 21a sends the control command to the calculation unit 22a. Further, the first communication unit 21a transmits the determination result of the failure determination unit 25a, which will be described later, to the first communication unit 21b of the control device 20b. Further, the first communication unit 21a receives the determination result of the failure determination unit 25b of the control device 20b from the first communication unit 21b.

The calculation unit 22a generates a gate signal according to the control command, the measured value of the current, and the determination result of the failure determination units 25a and 25b.
Specifically, as long as neither of the power conversion devices 2a and 2b has failed, the calculation unit 22a generates a gate signal as in the first and third embodiments. When the determination result of the failure determination unit 25a indicates that the power conversion device 2a has a failure, the calculation unit 22a generates a gate signal for stopping the power conversion device 2a. Further, the determination result of the failure determination unit 25a indicates that the failure of the power conversion device 2a has not occurred, and the determination result of the failure determination unit 25b indicates that the failure of the power conversion device 2b has occurred. If so, the arithmetic unit 22a generates a gate signal that increases the output of the power conversion device 2a.

The failure determination unit 25a acquires the measured value of the current of each phase output by the power conversion device 2a from the measured value acquisition unit 24a, and the power conversion device 2a fails according to the measured value of the current of each phase. Determine if or not. Specifically, the failure determination unit 25a determines whether or not the amplitude of the measured value of the current of each phase is equal to or greater than the threshold value. When the amplitude of the measured value of the current of each phase is equal to or larger than the threshold value, it can be considered that the power conversion device 2a has failed. The threshold value is set to a value larger than a value that the amplitude of the current of each phase output by the power conversion device 2a can take.

When the first communication unit 21b receives the control command from the command device 10 via the high-speed serial line 5b, the first communication unit 21b sends the control command to the calculation unit 22b. Further, the first communication unit 21b transmits the determination result of the failure determination unit 25b, which will be described later, to the first communication unit 21a of the control device 20a. Further, the first communication unit 21b receives the determination result of the failure determination unit 25a of the control device 20a from the first communication unit 21a.

The calculation unit 22b generates a gate signal according to the control command, the measured value of the current, and the determination result of the failure determination units 25a and 25b.
Specifically, as long as none of the power conversion devices 2a and 2b has failed, the arithmetic units 22a and 22b generate gate signals, respectively, as in the first and third embodiments. When the determination result of the failure determination unit 25b indicates that the power conversion device 2b has a failure, the calculation unit 22b generates a gate signal for stopping the power conversion device 2b. Further, the determination result of the failure determination unit 25b indicates that the failure of the power conversion device 2b has not occurred, and the determination result of the failure determination unit 25a indicates that the failure of the power conversion device 2a has occurred. If so, the arithmetic unit 22b generates a gate signal that increases the output of the power conversion device 2b.

The failure determination unit 25b acquires the measured value of the current of each phase output by the power conversion device 2b from the measured value acquisition unit 24b, and a failure occurs in the power conversion device 2b according to the measured value of the current of each phase. Determine if or not. Specifically, the failure determination unit 25b determines whether or not the amplitude of the measured value of the current of each phase is equal to or greater than the threshold value. When the amplitude of the measured value of the current of each phase is equal to or larger than the threshold value, it can be considered that the power conversion device 2b has failed. The threshold value is set to a value larger than a value that the amplitude of the current of each phase output by the power conversion device 2b can take.

An implementation example of the control system 1 having the above configuration will be described with reference to FIGS. 10 and 11. The mounting example of the command device 10 is the same as that of the third embodiment. An implementation example of the control devices 20a and 20b different from the third embodiment will be described.
As shown in FIG. 10, the first communication unit 21a of the control device 20a is realized by the UDP / IP cores 42a and 42c included in the FPGA 41 and the PHY chips 43a and 43c. The UDP / IP cores 42a and 42c are connected to the PHY chips 43a and 43c, respectively. Further, the failure determination unit 25a is realized by the failure determination circuit 51 included in the FPGA 41.

As shown in FIG. 11, the first communication unit 21b of the control device 20b is realized by the UDP / IP cores 42b and 42c included in the FPGA 41 and the PHY chips 43b and 43c. The UDP / IP cores 42b and 42c are connected to the PHY chips 43b and 43c, respectively. Further, the failure determination unit 25b is realized by the failure determination circuit 51 included in the FPGA 41.

The operation of the control system 1 having the above configuration will be described. The operation of the command device 10 is the same as that of the third embodiment. Further, since the operations of the control devices 20a and 20b are the same, the operation of the control device 20a will be described in detail.
When the first communication unit 21a receives the control command from the command device 10, the first communication unit 21a sends the control command to the calculation unit 22a as in the first embodiment.
Further, when the first communication unit 21a acquires the determination result from the failure determination unit 25a, the first communication unit 21a performs serial transmission via the high-speed serial line 8 and sends the determination result to the first communication unit 21b. Specifically, the UDP / IP core 42c generates an Ethernet packet including the determination result and sends it to the PHY chip 43c. The PHY chip 43c generates a communication signal from the Ethernet packet including the discrimination result, and sends the communication signal to the high-speed serial line 8.

Further, the first communication unit 21a receives the determination result of the failure determination unit 25b from the first communication unit 21b. Specifically, when the PHY chip 43c receives the communication signal via the high-speed serial line 8, it generates an Ethernet packet from the communication signal and sends it to the UDP / IP core 42c. The UDP / IP core 42c extracts the discrimination result from the Ethernet packet generated by the PHY chip 43c, and sends the discrimination result to the DSP 44 via the system bus 49.

The operation of the measured value acquisition unit 24a is the same as that of the first and third embodiments. However, the measured value acquisition unit 24a sends the measured value of the current of each phase output by the power conversion device 2a indicated by the sensor signal to the calculation unit 22a and the failure determination unit 25a.

The failure determination unit 25a determines whether or not the amplitude of the measured value of the current of each phase is equal to or greater than the threshold value. If the amplitude of the measured current value is equal to or greater than the threshold value, it can be considered that the power conversion device 2a has failed. Then, the failure determination unit 25a transmits the determination result to the calculation unit 22a and the first communication unit 21a.

Specifically, the failure determination circuit 51 acquires the measured value of the current of each phase output by the power conversion device 2a from the input IF48. Then, the failure determination circuit 51 determines whether or not the amplitude of the measured value of the current of each phase is equal to or greater than the threshold value, and sends the determination result to the DSP 44 via the system bus 49. Further, the failure determination circuit 51 sends the determination result to the UDP / IP core 42c.

The discrimination result acquired from the failure discrimination unit 25a indicates that the power conversion device 2a has not failed, and the discrimination result acquired by the first communication unit 21a from the first communication unit 21b is the power conversion device 2b. The calculation unit 22a generates a gate signal as in the first and third embodiments while indicating that the device has not failed.

Further, when the determination result acquired from the failure determination unit 25a indicates that the power conversion device 2a has a failure, the calculation unit 22a generates a gate signal for stopping the power conversion device 2a. Specifically, when the discrimination result acquired from the fault discrimination circuit 51 indicates that the power conversion device 2a has a fault, the DSP 44 gradually receives voltage commands for the U phase, the V phase, and the W phase. The voltage commands for each of the U phase, V phase, and W phase are calculated so as to decrease. Then, the DSP 44 sends the calculated voltage command to the arithmetic circuit 46 via the system bus 49. The arithmetic circuit 46 generates a gate signal and sends it to the output IF 47, as in the first embodiment.

Further, the discrimination result acquired from the failure discrimination unit 25a indicates that the failure of the power conversion device 2a has not occurred, and the discrimination result acquired by the first communication unit 21a from the first communication unit 21b is the power conversion. When indicating that the device 2b is out of order, the arithmetic unit 22a generates a gate signal that increases the output of the power conversion device 2a. Specifically, when the control command instructs the operation of the power conversion device 2 so as to output the target value according to the power running command, the DSP 44 sets the magnetic flux current command Id * and the torque current command Iq according to the operation command. * And generate. Then, the discrimination result acquired from the failure discrimination circuit 51 indicates that the failure of the power conversion device 2a has not occurred, and the discrimination result obtained from the UDP / IP core 42c causes the failure of the power conversion device 2b. When indicating that, the DSP 44 adjusts the magnetic flux current command Id * and the torque current command Iq * so as to increase the output power of the power conversion device 2a. Then, the DSP44 calculates the voltage commands Vd * and Vq * so as to approach the magnetic flux current command Id * in which the exciting current Id is adjusted and the torque current command Iq * in which the torque current Iq is adjusted. The DSP 44 sends the calculated voltage commands Vd * and Vq * to the arithmetic circuit 46 via the system bus 49. The arithmetic circuit 46 generates a gate signal and sends it to the output IF 47, as in the first embodiment.

As described above, according to the control system 1 according to the fourth embodiment, the first communication unit 21a of the control device 20a and the first communication unit 21b of the control device 20b transmit and receive the discrimination result to each other. Therefore, when one of the power conversion devices 2a and 2b fails, the output of the other of the power conversion devices 2a and 2b can be increased. As a result, it is possible to suppress a decrease in the propulsive force of the railway vehicle on which the power conversion devices 2a and 2b are mounted.

Further, since the control devices 20a and 20b are connected by the high-speed serial line 8, the wiring is reduced as compared with the case where the control devices 20a and 20b are connected by the parallel line, and the man-hours of the wiring work can be reduced. When the high-speed serial line 8 is composed of, for example, a transmission line conforming to the standard of IEEE802.3u, long-distance transmission, for example, 100 m is possible via the high-speed serial line 8. Therefore, since the control device 20b can be arranged at a position far away from the control device 20a, the degree of freedom of the arrangement position of the control device 20b is increased with respect to the position of the control device 20a.

The present invention is not limited to the example of the above-described embodiment. Among the above-described embodiments, a plurality of embodiments can be arbitrarily combined. As an example, the high-speed serial lines 5a and 5b included in the control system 1 according to the third embodiment may be duplicated, respectively.

The circuit configuration of the control system 1 is not limited to the above example. As an example, the processing of the CPU 31 may be realized by the DSP. Further, as another example, the calculation circuit 46 may generate the voltage commands for each of the U phase, V phase, and W phase performed by the DSP 44.

The power supply that supplies power to the power converters 2, 2a and 2b is arbitrary. As an example, the power source includes a generator that generates electricity by being driven by an internal combustion engine, a power storage device mounted on a railway vehicle, and the like.

The power conversion devices 2, 2a and 2b are not limited to VVVF converters, and are optional as long as they are power conversion devices having a switching element. As an example, the power conversion devices 2, 2a, 2b may be composed of a static inverter, a converter, or the like. The load supplied by the power converters 2, 2a, 2b is not limited to the electric motors 3, 3a, 3b, and is arbitrary as long as it is a device operated by electric power. As an example, the power conversion devices 2, 2a, 2b may supply electric power to in-vehicle devices such as air conditioners and lighting devices.

Further, the power conversion devices 2a and 2b may supply power to loads independent of each other, the power conversion device 2a supplies power to the power conversion device 2b, and the power conversion device 2b is supplied from the power conversion device 2a. The electric power may be converted into, for example, three-phase AC electric power and supplied to the electric motor 3b. As an example, the power conversion device 2a may be configured by a converter, and the power conversion device 2b may be configured by an inverter. In this case, in the control system 1 according to the fourth embodiment, the control device 20a may stop the power conversion device 2a when the power conversion device 2b fails. Similarly, when the power conversion device 2a fails, the control device 20b may stop the power conversion device 2b. Specifically, when the determination result of the failure determination unit 25b acquired by the first communication unit 21a indicates that the power conversion device 2b has a failure, the calculation unit 22a stops the power conversion device 2a. A gate signal may be generated. Similarly, when the determination result of the failure determination unit 25a acquired by the first communication unit 21b indicates that the power conversion device 2a has a failure, the calculation unit 22b causes the gate signal to stop the power conversion device 2b. Should be generated.

The control devices 20a and 20b may be connected by a parallel line.
The sensors 4, 4a, 4b are not limited to the currents of the respective phases output by the power conversion devices 2, 2a, 2b, but are the direct currents output by the power conversion devices 2, 2a, 2b, and the power conversion devices 2, 2a, 2b. The voltage between the output terminals, the voltage of each phase, and the like may be measured.

The method for discriminating the failure discriminating units 25a and 25b is not limited to the above example, and is arbitrary as long as it can detect that a failure has occurred in the power conversion devices 2a and 2b. As an example, the failure determination unit 25a may determine whether or not the amplitude of the measured value of the voltage of each phase output by the power conversion device 2a is equal to or greater than the threshold voltage. In this case, when the amplitude of the measured value of the voltage of each phase is equal to or larger than the threshold voltage, it can be considered that the power conversion device 2a has failed.

The control target of the control devices 20, 20a, 20b is not limited to the power conversion devices 2, 2a, 2b, and is arbitrary as long as it is an electronic device mounted on a railway vehicle. As an example, the control devices 20, 20a, 20b may control the propulsion control device, the power supply device, and the like.

In the above-described embodiment, the command device 10 is provided with one CPU 31, but a plurality of CPUs 31 may cooperate to execute the above-mentioned functions. Similarly, a plurality of DSPs 44 may cooperate to perform the above-mentioned functions. Further, the command device 10 may include a plurality of memories 32, and the control devices 20, 20a, and 20b may each include a plurality of memories 45. In addition, the above hardware configuration is an example, and can be changed and modified arbitrarily.

The control system 1 can be realized by using a normal computer system without relying on a dedicated system. For example, a computer program for executing the above operation can be a computer-readable recording medium (flexible disk, CD-ROM (Compact Disc Read-Only Memory), DVD-ROM (Digital Versatile Disc Read-Only Memory), etc. ), The computer program may be installed in the computer to configure the control system 1 for executing the above-mentioned processing. Further, the control system 1 may be configured by storing the computer program in a storage device of the server device on the communication network and downloading it by a normal computer system.

Further, when the function of the control system 1 is realized by sharing the OS (Operating System) and the application program, or by coordinating the OS and the application program, only the application program part is stored in the recording medium or the storage device. You may.

It is also possible to superimpose a computer program on a carrier wave and distribute it via a communication network. For example, the computer program may be posted on a bulletin board system (BBS: Bulletin Board System) on the communication network, and the computer program may be distributed via the communication network. Then, the above-mentioned processing may be executed by starting this computer program and executing it in the same manner as other application programs under the control of the OS.

The present invention enables various embodiments and modifications without departing from the broad spirit and scope of the present invention. Moreover, the above-described embodiment is for explaining the present invention, and does not limit the scope of the present invention. That is, the scope of the present invention is indicated by the scope of claims, not by the embodiment. Then, various modifications made within the scope of the claims and the equivalent meaning of the invention are considered to be within the scope of the present invention.

1 Control system, 2,2a, 2b power converter, 3,3a, 3b electric motor, 4,4a, 4b sensor, 5,5a, 5b, 8 high-speed serial line, 6,6a, 6b first parallel line, 7, 7a, 7b 2nd parallel line, 10 command device, 11 command generator, 12 command transmitter, 20, 20a, 20b control device, 21,21a, 21b first communication unit, 22, 22a, 22b calculation unit, 23, 23a, 23b 2nd communication unit, 24, 24a, 24b measurement value acquisition unit, 25a, 25b failure determination unit, 31 CPU, 32,45 memory, 33,48 input IF, 34,41 FPGA, 35,35a, 35b, 42, 42a, 42b, 42c UDP / IP core, 36, 36a, 36b, 43, 43a, 43b, 43c PHY chip, 37, 49 system bus, 38, 50 switching unit, 44 DSP, 46 arithmetic circuit, 47 output IF , 51 Failure determination circuit.

Claims (11)

1. The first communication unit that receives a control command including an instruction to start or stop the power converter, and
   A calculation unit that generates a signal for controlling the power conversion device in response to the control command received by the first communication unit.
   A second communication unit that transmits the signal to the power converter, and
   With
   Arranged adjacent to the power converter,
   Control device.
2. Further, a measurement value acquisition unit for acquiring a measurement value of the current from a sensor for measuring the current output from the output terminal of the power conversion device is provided.
   The calculation unit generates the signal according to the control command received by the first communication unit and the measured value of the current acquired by the measured value acquisition unit.
   The control device according to claim 1.
3. The measured value acquisition unit and the sensor are connected via a first parallel line.
   The control device according to claim 2.
4. A high-speed serial line is connected to the first communication unit.
   The first communication unit receives the control command via the high-speed serial line.
   The control device according to any one of claims 1 to 3.
5. A plurality of the high-speed serial lines are connected to the first communication unit.
   The first communication unit receives the control command using any one of the plurality of high-speed serial lines, and receives the control command.
   Further provided with a discriminating unit for determining whether or not the high-speed serial line used for receiving the control command has a failure.
   When the discriminating unit determines that the high-speed serial line used for receiving the control command has failed, the first communication unit uses the other high-speed serial line among the plurality of high-speed serial lines. Use to receive control commands,
   The control device according to claim 4.
6. The second communication unit and the power conversion device are connected by a second parallel line.
   The second communication unit transmits the signal to the power conversion device via the second parallel line.
   The control device according to any one of claims 1 to 5.
7. The first communication unit communicates with the MAC (Media Access Control) layer, IP (Internet Protocol) layer, and UDP (User Datagram Protocol) layer of the Ethernet standard. It has an IP core and a PHY (Physical layer) chip that communicates with the physical layer.
   UDP / IP core is implemented in FPGA (Field Programmable Gate Array).
   The control device according to any one of claims 1 to 6.
8. The control device according to any one of claims 1 to 7.
   A command device that generates the control command and transmits the control command to the control device,
   Control system with.
9. A high-speed serial line connecting the control device and the command device is further provided.
   The control system according to claim 8.
10. With the plurality of the control devices
    A plurality of independent high-speed serial lines connecting the control device and the command device, each of which corresponds to the control device.
    The control system according to claim 8 or 9.
11. Each of the plurality of control devices further includes a failure determination unit for determining whether or not a failure has occurred in the power conversion device to which the control device transmits the signal.
    The first communication unit of the plurality of control devices transmits and receives the determination result of the failure determination unit to and from each other.
    The control system according to claim 10.

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