WO2020181999A1 - Panneau d'affichage électroluminescent et dispositif d'affichage électroluminescent - Google Patents

Panneau d'affichage électroluminescent et dispositif d'affichage électroluminescent Download PDF

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Publication number
WO2020181999A1
WO2020181999A1 PCT/CN2020/077209 CN2020077209W WO2020181999A1 WO 2020181999 A1 WO2020181999 A1 WO 2020181999A1 CN 2020077209 W CN2020077209 W CN 2020077209W WO 2020181999 A1 WO2020181999 A1 WO 2020181999A1
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Prior art keywords
voltage
pixel
capacitor
power
capacitance value
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PCT/CN2020/077209
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English (en)
Chinese (zh)
Inventor
承天一
黄炜赟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2020181999A1 publication Critical patent/WO2020181999A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an electroluminescence display panel and an electroluminescence display device.
  • an electroluminescent display device such as an organic light emitting diode (OLED) display device has the advantages of self-luminescence, short response time, high definition, etc., and it is more and more widely used.
  • OLED organic light emitting diode
  • the length of the power supply lines (such as the power supply line for supplying the ELVDD signal and the power supply line for supplying the ELVSS signal) arranged on the display panel is generally relatively long.
  • the voltage drop (IRDrop) generated by the longer power cord is more obvious. This voltage drop causes the ELVDD voltage and ELVSS voltage obtained by multiple pixel driving circuits in the display panel to be inconsistent.
  • different pixels provide different driving currents to their respective light-emitting devices, resulting in uneven light-emitting brightness of the entire display panel and uniformity over a long range. Poor sex.
  • an electroluminescent display panel including:
  • a first pixel the first pixel including a first capacitor
  • a second pixel the second pixel including a second capacitor
  • a second power trace the first end of the second power trace is connected to the voltage generator, and the second end of the second power trace is connected to the second pixel for connecting the voltage generator
  • the generated first voltage is supplied to the second pixel
  • the capacitance value of the first capacitor depends on the voltage difference between the first voltage and the voltage at the second end of the first power trace
  • the capacitance value of the second capacitor depends on the The voltage difference between the first voltage and the voltage at the second end of the second power trace.
  • the capacitance value of the first capacitor and the capacitance value of the second capacitor are different from each other to compensate for the difference between the voltage drop on the first power line and the voltage drop on the second power line.
  • the voltage generator is also used to generate a second voltage
  • the electroluminescence display panel further includes: a first power signal line, a first end of the first power signal line is connected to the voltage generator, and a second end of the first power signal line is connected to the first A pixel for supplying a second voltage generated by the voltage generator to the first pixel; and a second power signal line, the first end of the second power signal line is connected to the voltage generator, the The second end of the second power signal line is connected to the second pixel for supplying the second voltage generated by the voltage generator to the second pixel,
  • the capacitance value of the first capacitor also depends on the voltage difference between the second voltage and the voltage at the second end of the first power signal line
  • the capacitance value of the second capacitor also depends on The voltage difference between the second voltage and the voltage at the second end of the second power signal line.
  • the voltage difference between the voltage at the second end of the first power supply line and the voltage at the second end of the first power signal line is the first supply voltage difference
  • the second power supply The voltage difference between the voltage at the second end of the trace and the voltage at the second end of the second power signal line is the second supply voltage difference
  • the first supply voltage difference is greater than the second supply voltage difference, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.
  • the length of the first power trace is different from the length of the second power trace.
  • the length of the first power trace is smaller than the length of the second power trace, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.
  • the length of the first power signal line is different from the length of the second power signal line.
  • the length of the first power signal line is smaller than the length of the second power signal line, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.
  • the first pixel further includes a driving transistor, one capacitor plate of the first capacitor is connected to the first power supply line, and the other capacitor plate of the first capacitor is connected to the driving transistor. Grid; and/or,
  • the second pixel further includes a driving transistor, one capacitor plate of the second capacitor is connected to the second power supply line, and the other capacitor plate of the second capacitor is connected to the driving transistor of the second pixel. Grid.
  • the first voltage is higher than the second voltage.
  • the electroluminescence display panel includes at least two of the voltage generators, and the first power trace is used to electrically connect one of the at least two voltage generators to the For the first pixel, the second power trace is used to electrically connect the other voltage generator of the at least two voltage generators to the second pixel.
  • an electroluminescent display panel including:
  • a first pixel the first pixel including a first capacitor
  • a second pixel the second pixel including a second capacitor
  • a third pixel, the third pixel includes a third capacitor
  • a first voltage generator for generating a first voltage
  • the second voltage generator is used to generate the first voltage
  • a first voltage generated by a voltage generator is supplied to the first pixel
  • a second power trace the first end of the second power trace is connected to the second voltage generator, and the second end of the second power trace is connected to the second pixel for connecting the first
  • the first voltage generated by the two voltage generators is supplied to the second pixel
  • a third power trace a first end of the third power trace is connected to the first voltage generator, and a second end of the third power trace is connected to the third pixel for connecting the first A first voltage generated by a voltage generator is supplied to the third pixel;
  • the first voltage generator and the second voltage generator are located at different positions of the display panel, and the capacitance value of the first capacitor depends on the connection between the first voltage and the first power supply line.
  • the voltage difference between the voltage at the second end, the capacitance value of the second capacitor depends on the voltage difference between the first voltage and the voltage at the second end of the second power trace, the The capacitance value of the third capacitor depends on the voltage difference between the first voltage and the voltage at the second end of the third power trace.
  • the capacitance value of the first capacitor and the capacitance value of the third capacitor are different from each other to compensate for the difference between the voltage drop on the first power line and the voltage drop on the third power line. different.
  • the first voltage generator and the second voltage generator are also used to generate a second voltage
  • the electroluminescent display panel further includes: a first power signal line, a first end of the first power signal line is connected to the first voltage generator, and a second end of the first power signal line is connected to the The first pixel is used to supply the second voltage generated by the first voltage generator to the first pixel; the second power signal line, the first end of the second power signal line is connected to the second voltage Generator, the second end of the second power signal line is connected to the second pixel, and is used to supply the second voltage generated by the second voltage generator to the second pixel; and a third power signal line , The first end of the third power signal line is connected to the first voltage generator, and the second end of the third power signal line is connected to the third pixel for generating the first voltage generator The second voltage of is supplied to the third pixel,
  • the capacitance value of the first capacitor also depends on the voltage difference between the second voltage and the voltage at the second end of the first power signal line
  • the capacitance value of the second capacitor also depends on The voltage difference between the second voltage and the voltage at the second end of the second power signal line
  • the capacitance value of the third capacitor also depends on the second voltage and the third power signal line The voltage difference between the voltages at the second end.
  • the capacitance value of the first capacitor, the capacitance value of the second capacitor, and the capacitance value of the third capacitor are different from each other; or,
  • the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the capacitance value of the first capacitor is smaller than the capacitance value of the third capacitor.
  • the electroluminescent display panel further includes:
  • a fourth pixel the fourth pixel includes a fourth capacitor, and the fourth pixel is electrically connected to the first voltage generator;
  • a fifth pixel the second pixel includes a fifth capacitor, and the fifth pixel is electrically connected to the second voltage generator,
  • the capacitance value of the first capacitor, the capacitance value of the second capacitor, the capacitance value of the third capacitor, the capacitance value of the fourth capacitor and the capacitance value of the fifth capacitor are different from each other; or ,
  • the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor
  • the capacitance value of the fourth capacitor is equal to the capacitance value of the fifth capacitor
  • the capacitance value of the first capacitor is smaller than that of the third capacitor
  • the capacitance value of the third capacitor is smaller than the capacitance value of the fourth capacitor.
  • an electroluminescent display device including the electroluminescent display panel described in any one of the above.
  • FIG. 1 is a schematic diagram of an electroluminescent display device according to an embodiment of the present disclosure, in which the power supply wiring structure of the first power supply line is schematically shown;
  • FIG. 2 is a schematic diagram schematically showing a power wiring structure of a second power cord of an electroluminescent display device according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram schematically showing a power wiring structure of a first power line of an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram schematically showing a power wiring structure of a second power line of an electroluminescent display panel according to an embodiment of the present disclosure
  • Fig. 5 schematically shows a distribution diagram of voltage differences applied to different pixels
  • FIG. 6 is a circuit diagram of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 7 is an enlarged view of a pixel driving circuit in the circuit diagram shown in FIG. 6;
  • Fig. 8 schematically shows charging curves of capacitors with different capacitance values
  • FIG. 9 schematically shows a graph of the relative change trend of the voltage of different pixels at the node N in the circuit diagram shown in FIG. 7;
  • FIG. 10 schematically shows a distribution diagram of capacitance values of capacitors in a pixel driving circuit of an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 11 is a circuit diagram of a pixel driving circuit of an electroluminescent display panel according to another embodiment of the present disclosure.
  • FIG. 12 shows a signal timing diagram of the pixel driving circuit of FIG. 11.
  • FIG. 13 schematically shows an example of an electroluminescence display device according to an embodiment of the present disclosure.
  • first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element may be named as the second element, and similarly, the second element may be named as the first element.
  • the term "and/or" as used herein includes any and all combinations of one or more of the related listed items.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. Unless otherwise specified, the source and drain of the thin film transistor used are symmetrical, so the source and drain can be interchanged. In the following embodiments, a P-type thin film transistor is taken as an example for description. However, the embodiments of the present disclosure are not limited to this. In other embodiments, the transistors used may also be N-type thin film transistors.
  • the electroluminescence display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a controller 140, and a voltage generator 150.
  • the electroluminescent display device 100 may be an OLED display device.
  • the display panel 110 may include a substrate 11 and a plurality of pixels 10.
  • the substrate 11 includes a display area AA and a non-display area NA, and the plurality of pixels 10 are arranged in an array in the display area AA.
  • a first voltage such as ELVDD (shown in FIG. 1) and a second voltage such as ELVSS (shown in FIG. 2) may be applied to the pixel 10.
  • the first voltage of ELVDD may be higher than the second voltage of, for example, ELVSS.
  • a first voltage such as ELVDD may be applied to the anode of an organic light emitting device (such as OLED), and a second voltage such as ELVSS may be applied to the cathode of the organic light emitting device so that the organic light emitting device can emit light.
  • the first voltage and the second voltage may be generated by the voltage generator 150.
  • pixel in this document includes but is not limited to sub-pixels, sub-pixels or similar structures, such as red sub-pixels, green sub-pixels, blue sub-pixels, and so on.
  • the display panel 110 may further include a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.
  • each of the gate lines GL1 to GLn is connected to a plurality of pixels 10 in the same row, and each of the data lines DL1 to DLm is connected to a plurality of pixels 10 in the same column.
  • the gate driver 120 sends out scan signals, and the scan signals are applied to the pixels 10 through a plurality of gate lines GL1 to GLn
  • the data driver 130 sends out data signals, and the data signals pass through a plurality of data lines DL1 to DL1 DLm is applied to the pixel 10.
  • the pixel 10 In response to the scan signal received through the gate lines GL1 to GLn, the pixel 10 emits light or does not emit light according to the voltage of the data signal received through the data lines DL1 to DLm, respectively.
  • the gate driver 120 may be disposed in the non-display area NA on one side of the substrate 11, and the data driver 130 may be disposed in the non-display area NA on the other side of the substrate 11.
  • the gate driver 120 is provided on the left side of the substrate 11 and the data driver 130 is provided on the upper side of the substrate 11.
  • the embodiment of the present disclosure is not limited to this arrangement. In other embodiments, the gate driver 120 and the data driver 130 may change their positions.
  • the gate driver 120 and the data driver 130 may be disposed on any suitable position on the substrate 11.
  • the display panel 110 may further include a first power line 12 (as shown in FIG. 1) and a second power line 14 (as shown in FIG. 2).
  • the first power line 12 may transmit a first voltage such as ELVDD to each pixel 10.
  • the second power line 14 can deliver the second voltage, such as ELVSS, to each pixel 10.
  • the first power supply line 12 may include a plurality of power supply lines for transmitting the first voltage from the voltage generator 150 to each pixel 10.
  • the first power line 12 may include a first power line 121, a second power line 122, a third power line 123, and a fourth power line 124, for transmitting the first voltage from the voltage generator 150 respectively To pixels PX1, PX2, PX3, PX4.
  • each power trace may include a first part extending in a first direction and a second part extending in a second direction.
  • the first direction may be parallel to the column direction of the array formed by the arrangement of pixels 10
  • the second direction may be parallel to the row direction of the array formed by the arrangement of the pixels 10.
  • the display panel 110 includes a voltage generator 150, and the voltage generator 150 is located in the non-display area NA at the lower right of the substrate 11.
  • the first end 121A of the first power line 121 is connected to the voltage generator 150, and the second end 121B of the first power line 121 is connected to the pixel PX1, and is used to supply the first voltage generated by the voltage generator 150 to the pixel PX1 .
  • the first end 122A of the second power line 122 is connected to the voltage generator 150, and the second end 122B of the second power line 122 is connected to the pixel PX2 for supplying the first voltage generated by the voltage generator 150 to the pixel PX2.
  • FIG. 1 shows 4 pixels PX1, PX2, PX3, PX4 located at different positions of the substrate 11.
  • the pixels PX1, PX2 are located on the lower side of the substrate 11, that is, the side close to the voltage generator 150
  • the pixels PX3 and PX4 are located on the upper side of the substrate 11, that is, on the side away from the voltage generator 150. It can be seen that the distances between the four pixels PX1, PX2, PX3, and PX4 from the voltage generator 150 are all different.
  • the first voltage ELVDD passes from the voltage generator 150 to the four pixels PX1, PX2, PX3, and PX4.
  • the lengths of the power traces are different.
  • the first power line 12 is made of a conductive material such as metal, and has a non-zero resistance value, which will cause a voltage drop, that is, IR Drop. That is to say, the voltage of each power trace at one end connecting each pixel is not equal to the first voltage supplied by it, and there is a voltage difference between the two. For example, there is a voltage difference between the voltage at the second terminal 121B of the first power trace 121 and the first voltage, and there is a voltage difference between the voltage at the second terminal 122B of the second power trace 122 and the first voltage.
  • the first voltage ELVDD is from the voltage generator 150 to the 4 pixels PX1, PX2, and PX2.
  • the voltage drops of PX3 and PX4 are different, resulting in different ELVDD voltages applied to the four pixels PX1, PX2, PX3, and PX4.
  • the length of the first power trace 121 through which the first voltage ELVDD passes from the voltage generator 150 to the pixel PX1 is less than the first power trace 121 through which the first voltage ELVDD passes from the voltage generator 150 to the pixel PX4.
  • the voltage drop of the first voltage ELVDD from the voltage generator 150 to the pixel PX1 is smaller than the voltage drop of the first voltage ELVDD from the voltage generator 150 to the pixel PX4, as a result, the ELVDD voltage applied to the pixel PX1 is high This is the ELVDD voltage applied to the pixel PX4.
  • the IR drop phenomenon causes the ELVDD voltages applied to multiple pixels located at different positions of the substrate to be inconsistent, so that the currents flowing through the OLEDs in each pixel are inconsistent, resulting in uneven light emission of the display panel.
  • the aspect ratio of mobile phone screens has increased from 16:9 to 18:9, 18.5:9, 19.5:9, and even 21:9 Or higher.
  • IRDrop phenomenon leads to the inconsistency of the ELVDD voltage applied to multiple pixels located at different positions on the substrate.
  • the ELVDD voltage applied to the pixels PX1 and PX2 is more
  • the ELVDD voltages for the pixels PX3 and PX4 will be significantly different, which causes the uneven light emission of the display panel to be more prominent.
  • the second power line 14 may include a plurality of power signal lines for transmitting the second voltage from the voltage generator 150 to each pixel 10.
  • the second power line 14 may include a first power signal line 141, a second power signal line 142, a third power signal line 143, and a fourth power signal line 144 for respectively transmitting the second voltage from the voltage generator 150 To pixels PX1, PX2, PX3, PX4.
  • each power signal line of the second power line 14 may include a first portion extending in a first direction and a second portion extending in a second direction.
  • the expression “power trace” is used to describe the structure of the first power line
  • the expression “power signal line” is used to describe the structure of the second power line. This does not mean that the first power line and the second power line There is a significant difference in the structure of the power cord, just for the purpose of facilitating description and avoiding confusion.
  • the first end 141A of the first power signal line 141 is connected to the voltage generator 150, and the second end 141B of the first power signal line 141 is connected to the pixel PX1 for supplying the second voltage generated by the voltage generator 150 to the pixel PX1 .
  • the first end 142A of the second power signal line 142 is connected to the voltage generator 150, and the second end 142B of the second power signal line 142 is connected to the pixel PX2 for supplying the second voltage generated by the voltage generator 150 to the pixel PX2.
  • FIG. 2 shows 4 pixels PX1, PX2, PX3, PX4 located at different positions of the substrate 11.
  • the pixels PX1, PX2 are located on the lower side of the substrate 11, that is, close to the voltage generator.
  • the pixels PX3 and PX4 are located on the upper side of the substrate 11, that is, the side away from the voltage generator 150.
  • the voltage of each power trace at the end connecting each pixel is not equal to the second voltage supplied by it, and there is a voltage difference between the two. For example, there is a voltage difference between the voltage at the second end 141B of the first power signal line 141 and the second voltage, and there is a voltage difference between the voltage at the second end 142B of the second power signal line 142 and the first voltage.
  • the distances between the four pixels PX1, PX2, PX3, and PX4 from the voltage generator 150 are all different.
  • the second voltage ELVSS passes from the voltage generator 150 to the four pixels PX1, PX2, PX3, and PX4.
  • the length of the power signal line is different. Therefore, the voltage drop of the second voltage ELVSS from the voltage generator 150 to the four pixels PX1, PX2, PX3, and PX4 is different, resulting in different ELVSS voltages applied to the four pixels PX1, PX2, PX3, and PX4.
  • the second voltage ELVSS may be a negative value.
  • the length of the power signal line through which the second voltage ELVSS passes from the voltage generator 150 to the pixel PX1 is less than the length of the power signal line through which the second voltage ELVSS passes from the voltage generator 150 to the pixel PX4,
  • the voltage drop of the second voltage ELVSS from the voltage generator 150 to the pixel PX1 is smaller than the voltage drop of the second voltage ELVSS from the voltage generator 150 to the pixel PX4, and as a result, the ELVSS voltage applied to the pixel PX1 is lower than the ELVSS voltage applied to the pixel PX4 .
  • the second voltage ELVSS generated by the voltage generator 150 may be -10V, and the voltage drop of the second voltage ELVSS from the voltage generator 150 to the pixel PX1 may be 2V, then the ELVSS voltage applied to the pixel PX1 is -8V,
  • the voltage drop of the voltage ELVSS from the voltage generator 150 to the pixel PX4 should be greater than 2V, for example 5V, then the ELVSS voltage applied to the pixel PX4 is -5V.
  • the ELVSS voltage (-8V) applied to the pixel PX1 is lower than the voltage applied to the pixel PX1.
  • the voltage difference between the first voltage ELVDD and the second voltage ELVSS applied to each pixel is also not consistent.
  • the voltage at the second end 121B of the first power trace 121 of the first power line 12 is the same as the voltage at the second end 141B of the first power signal line 141 of the second power line 14
  • the voltage difference between the voltages of is the first supply voltage difference, that is, the voltage difference between the first voltage ELVDD and the second voltage ELVSS applied to the pixel PX1.
  • the voltage difference between the voltage at the second end of the fourth power trace 124 of the first power line 12 and the voltage at the second end of the fourth power signal line 144 of the second power line 14 is the second supply voltage difference , That is, the voltage difference between the first voltage ELVDD and the second voltage ELVSS applied to the pixel PX4.
  • the first supply voltage difference is different from the second supply voltage difference.
  • the first supply voltage difference (the voltage difference between the first voltage ELVDD and the second voltage ELVSS applied to the pixel PX1) is higher than the second supply voltage difference (application The voltage difference between the first voltage ELVDD and the second voltage ELVSS supplied to the pixel PX4).
  • the display panel 110 may include two voltage generators 150A and 150B.
  • the two voltage generators 150A and 150B may be respectively located at the lower end of the display panel 100 near the side edges.
  • Each of the two voltage generators 150A and 150B is The first voltage ELVDD and the second voltage ELVSS may be supplied.
  • the side where the voltage generator 150A is located is called the first side of the display panel (that is, the left side in the figure), and the side where the voltage generator 150B is located is called the second side of the display panel (that is, in the figure). In the right).
  • the voltage generator 150A may be referred to as the first voltage generator
  • the voltage generator 150B may be referred to as the second voltage generator.
  • FIG. 3 shows five pixels PX1, PX2, PX3, PX4, and PX5 located at different positions of the substrate 11.
  • the pixel PX1 is located at the lower end of the substrate 11 and close to the first side, that is, close to the voltage generation.
  • the pixel PX2 is located at the lower end of the substrate 11 and close to the second side, that is, close to the voltage generator 150B, the pixel PX3 is located at the lower end of the substrate 11 and between the first side and the second side, and the pixel PX4 is located on the substrate.
  • the pixel PX5 is located at the upper end of the substrate 11 and close to the first side, and the pixel PX5 is located at the upper end of the substrate 11 and close to the second side.
  • the first power supply line 12 may include a plurality of power supply lines for transmitting the first voltage from the voltage generator 150 to each pixel 10.
  • the first power supply line 12 may include a first power supply line 121, a second power supply line 122, a third power supply line 123, a fourth power supply line 124, and a fifth power supply line 125 for applying the first voltage
  • the voltage generator 150 is respectively sent to the pixels PX1, PX2, PX3, PX4, and PX5.
  • each power trace may include a first part extending in a first direction and a second part extending in a second direction.
  • the first voltage ELVDD can be applied to the pixels PX1 and PX3 from the voltage generator 150A through the first power trace 121 and the third power trace 123 on the first side, respectively, and the first voltage ELVDD can be applied from the voltage generator 150B through the first power trace 121 and the third power trace 123.
  • the second power trace 122 on both sides is applied to the pixel PX2, the first voltage ELVDD can be applied from the voltage generator 150A to the pixel PX4 through the fourth power trace 124 on the first side, and the first voltage ELVDD can be from the voltage generator 150B is applied to the pixel PX5 through the fifth power trace 125 on the second side.
  • the length of the power traces passing through the first voltage ELVDD from the voltage generator 150A/150B to the five pixels PX1, PX2, PX3, PX4, and PX5 is at least partially different.
  • the first voltage ELVDD is from the voltage generator 150A to the pixel.
  • the length of the first power trace 121 through which PX1 passes or the length of the second power trace 122 through which the first voltage ELVDD passes from the voltage generator 150B to the pixel PX2 is less than the length of the first voltage ELVDD through the first voltage ELVDD from the voltage generator 150A to the pixel PX3.
  • the length of 122 is smaller than the length of the fourth power trace 124 through which the first voltage ELVDD passes from the voltage generator 150A to the pixel PX4 or the length of the fifth power trace 125 through which the first voltage ELVDD passes from the voltage generator 150B to the pixel PX5. Therefore, the voltage drop of the first voltage ELVDD from the voltage generators 150A and 150B to the pixel is not the same, which causes the ELVDD voltage applied to the pixel to be different.
  • the ELVDD voltage applied to the pixel PX1 or PX2 is higher than the ELVDD voltage applied to the pixel PX3, and the ELVDD voltage applied to the pixel PX1 or PX2 is higher than the ELVDD applied to the pixel PX4 or PX5. Voltage.
  • the IR drop phenomenon causes the ELVDD voltages applied to multiple pixels located at different positions of the substrate to be inconsistent, so that the currents flowing through the OLEDs in each pixel are inconsistent, resulting in uneven light emission of the display panel.
  • the IR drop phenomenon causes the ELVDD voltages applied to the multiple pixels located at different positions on the substrate to be inconsistent, which will be more obvious, resulting in the uneven light emission of the display panel.
  • the second power line 14 may include a plurality of power signal lines for transmitting the second voltage from the voltage generators 150A and 150B to the respective pixels 10.
  • the second power line 14 may include a first power signal line 141, a second power signal line 142, a third power signal line 143, a fourth power signal line 144, and a fifth power signal line 145 for applying the second voltage
  • the voltage generators 150A and 150B are respectively sent to the pixels PX1, PX2, PX3, PX4, and PX5.
  • each power signal line may include a first portion extending in a first direction and a second portion extending in a second direction.
  • FIG. 4 shows five pixels PX1, PX2, PX3, PX4, and PX5 located at different positions of the substrate 11.
  • the voltage drops of the second voltage ELVSS from the voltage generators 150A, 150B to the respective pixels PX1, PX2, PX3, PX4, and PX5 are different, resulting in different ELVSS voltages applied to the pixels.
  • the ELVSS voltage applied to the pixel PX1 or PX2 is lower than the ELVSS voltage applied to the pixel PX3, and the ELVSS voltage applied to the pixel PX1 or PX2 is lower than the ELVSS voltage applied to the pixel PX4 or PX5. Voltage.
  • the voltage difference between the first voltage ELVDD and the second voltage ELVSS applied to each pixel is also inconsistent.
  • the voltage difference between the ELVDD voltage applied to the pixel PX1 or PX2 and the ELVSS voltage is higher than the voltage difference between the ELVDD voltage applied to the pixel PX3 and the ELVSS voltage, and the ELVDD voltage applied to the pixel PX1 or PX2
  • the voltage difference of the ELVSS voltage is higher than the voltage difference between the ELVDD voltage applied to the pixel PX4 or PX5 and the ELVSS voltage.
  • FIG. 5 schematically shows the distribution of the voltage difference applied to the pixels PX1, PX2, PX3, PX4, and PX5.
  • FIG. 6 schematically shows a circuit diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 7 is an enlarged view of a pixel driving circuit in the circuit diagram shown in FIG. 6.
  • the display panel 100 may include n gate lines GL1 to GLn and m data lines DL1 to DLm, which surround and form n ⁇ m pixels, and each pixel has a pixel driving circuit.
  • the pixel driving circuit of may be one of n ⁇ m pixel driving circuits, which is connected to the i-th gate line GLi and the j-th data line DLj, where 1 ⁇ i ⁇ n and 1 ⁇ j ⁇ m.
  • the pixel driving circuit 200 may include a driving transistor T1, a switching transistor T2, and a capacitor Cst to drive an organic light emitting device (such as an OLED).
  • the driving transistor T1 is connected between the ELVDD power supply line and the organic light emitting device.
  • the switching transistor T2 is connected between the data line DLj and the gate of the driving transistor T1, and is turned on/off in response to a scan signal sent to the gate line GLi.
  • the capacitor Cst is connected between the ELVDD power supply line and the gate of the driving transistor T1.
  • the operation of the pixel driving circuit includes the following processes. First, when a scan signal having a low level is transmitted to the gate line GLi, the switching transistor T2 is turned on. In this state, the data voltage Vdata applied to the data line DLj is applied to the node N through the switching transistor T2, that is, applied to the gate of the driving transistor T1, and at the same time, the capacitor Cst is charged, and the data voltage Vdata is stored in the capacitor Cst. Then, the driving transistor T1 operates with a predetermined voltage stored in the capacitor Cst as a static current source, and supplies current to the organic light emitting device.
  • the driving transistor T1 works in the saturation region, and the current flowing in the organic light-emitting device can be calculated by the following formula.
  • I d is the driving current provided by the driving transistor T1 to the organic light-emitting device
  • Vgs is the voltage applied between the gate and source of the driving transistor T1
  • Vth is the threshold voltage of the driving transistor T1
  • ELVDD is the power line application
  • Vdata is the data voltage
  • K is a constant related to the driving transistor T1.
  • the IR Drop phenomenon causes the ELVDD voltage and the ELVSS voltage applied to each pixel by the power line to be inconsistent.
  • the ELVDD voltage applied to the pixel PX1 is not consistent with the ELVDD voltage applied to the pixel PX4, resulting in the current flowing in the organic light-emitting device (such as OLED) of the pixel PX1 and the pixel PX4
  • the current flowing in the organic light emitting device is not consistent, so that the light-emitting brightness of the pixel PX1 and the pixel PX4 are not consistent.
  • the ELVDD voltage applied to the pixel PX1 is higher than the ELVDD voltage applied to the pixel PX4, causing the current flowing in the organic light emitting device of the pixel PX1 to be greater than the current flowing in the organic light emitting device of the pixel PX4, so that the pixel PX1 is brighter than the pixel PX4 .
  • the capacitance value of the capacitor Cst in the pixel driving circuit can be designed to compensate for the inconsistency of brightness.
  • the capacitance value C1 of the capacitor Cst in the pixel PX1 can be designed to be smaller than the capacitance value C4 of the capacitor Cst in the pixel PX4.
  • FIG. 8 schematically shows the charging curves of the capacitor Cst (shown as CstA in Fig. 8) in the pixel PX1 and the capacitor Cst (shown as CstB in Fig. 8) in the pixel PX4.
  • the capacitance value C1 of the capacitor Cst in the pixel PX1 is designed to be smaller than the capacitance value C4 of the capacitor Cst in the pixel PX4. Therefore, the charging rate of the capacitor Cst in the pixel PX1 is greater than that of the capacitor Cst in the pixel PX4. The charging rate.
  • the data voltage Vdata is applied to the node N through the switching transistor T2, the capacitor Cst is charged, and the data voltage Vdata is stored in the capacitor Cst.
  • the voltage stored at the end of the capacitor Cst near the node N after the charging is completed will be very close to the data voltage Vdata, but not completely equal to the data voltage Vdata.
  • the voltage V1 at the node N in the pixel PX1 is higher than the voltage V4 at the node N in the pixel PX4.
  • the voltage of the gate of the driving transistor T1 will also be different.
  • the gate voltage V1 of the driving transistor T1 in the pixel PX1 is higher than the gate voltage V4 of the driving transistor T1 in the pixel PX4.
  • the ELVDD voltage applied to the pixel PX1 is higher than the ELVDD voltage applied to the pixel PX4, that is, the source voltage ELVDD of the driving transistor T1 in the pixel PX1 is higher than the source voltage ELVDD of the driving transistor T1 in the pixel PX4.
  • the voltage between the gate and source of the driving transistor T1 in the pixel PX1 and the voltage between the gate and the source of the driving transistor T1 in the pixel PX4 tend to be the same, thereby making The current flowing in the organic light emitting device of the pixel PX1 tends to be the same as the current flowing in the organic light emitting device of the pixel PX4, thereby realizing compensation for IR Drop.
  • FIG. 9 is schematic The relative change trend of the voltage at the node N in the pixel PX1 and the voltage at the node N in the pixel PX4 is shown. That is to say, even when the driving transistor T1 leaks, the relative tendency that the voltage at the node N in the pixel PX1 is higher than the voltage at the node N in the pixel PX4 will not change, so that the IR drop can still be achieved. make up.
  • the pixel PX1 and PX4 and the compensation of the voltage drop on the ELVDD power line are taken as an example to illustrate the design principle of the capacitance value of the capacitor Cst in the pixel driving circuit.
  • this design principle can also be applied to the design of the capacitance value of the capacitor Cst in the pixel drive circuit of other pixels (such as pixels PX2, PX3, PX5, etc.) to compensate for the voltage drop on the ELVSS power line.
  • the capacitance value of the capacitor in the pixel PX1 is different from the capacitance value of the capacitor in the pixel PX4 to compensate for the difference between the voltage drop on the first power line 121 and the voltage drop on the fourth power line 124.
  • the inconsistency of the voltage drop generated on the power supply line leads to the inconsistency of the power supply voltage (for example, ELVDD voltage, ELVSS voltage) applied to each pixel.
  • the capacitor in the pixel drive circuit of each pixel can be made The capacitance values of Cst are inconsistent to achieve compensation for IR Drop.
  • the compensation for IR Drop can be realized without changing the power supply line including the ELVDD power line and the ELVSS power line.
  • the wiring design and formation process have the advantages of low cost and high process feasibility.
  • the compensation of IR Drop has the advantages of finely controllable compensation amount and the position of the pixel to be compensated can be selected according to actual conditions.
  • the voltage drop on the ELVDD power supply line and the ELVSS power supply line causes the voltage difference between the ELVDD voltage and the ELVSS voltage applied to different pixels (eg, pixels PX1, PX2, PX3, PX4, and PX5) to be inconsistent.
  • the inventor found through experimental research that the capacitance value of the capacitor in the pixel driving circuit can be proportional to the voltage difference, for example, the capacitance value of the capacitor in the pixel driving circuit can be inversely proportional to the voltage difference.
  • FIG. 10 schematically shows the capacitance value distribution of capacitors in a pixel driving circuit of a display panel according to an embodiment of the present disclosure.
  • the voltage difference in the pixels PX1 and PX2 is relatively large. Therefore, the capacitance values C1 and C2 of the capacitors Cst in the pixels PX1 and PX2 can be designed to be small, and the pixels PX3, PX4, PX5 The voltage difference is small, so the capacitance values C3, C4, and C5 of the capacitors Cst in the pixels PX3, PX4, and PX5 can be designed to be larger.
  • the capacitance values C1, C2, C3, C4, and C5 may not be consistent with each other, for example, C1 ⁇ C2 ⁇ C3 ⁇ C4 ⁇ C5.
  • the capacitance values C1, C2, C3, C4, and C5 can be designed so that some of them are inconsistent.
  • the lengths of the power supply lines and the power supply signal lines of the power supply lines from the voltage generator 150A to the pixel PX1 may be equal to the voltage generation.
  • C1 can be equal to C2
  • the lengths of the power traces and power signal lines from the power supply line from the voltage generator 150A to the pixel PX4 may be equal to the voltage
  • the voltage drop on the power supply line is related to the length of the power supply line and the power supply signal line from the voltage generator to the power supply line of the pixel. In order to compensate for the voltage drop, it can be The length of the power trace and the power signal line of the pixel power supply line design the capacitance value of the capacitor.
  • the capacitance value of the capacitor in the pixel (for example, the pixels PX3, PX4, and PX5) can be designed to be larger.
  • the embodiments of the present disclosure are not limited to the design of the capacitance value of the capacitor according to the length of the power trace and the power signal line.
  • the voltage drop on the power line is in addition to the power supply of the power line from the voltage generator to the pixel.
  • the capacitance value of the capacitor can also be designed according to the cross-sectional area of the power trace and the power signal line. . That is, based on the voltage drop on the first power line (eg ELVDD power line) and/or the second power line (eg ELVSS power line), the capacitance value of the capacitor of each pixel is designed to compensate for the voltage drop.
  • FIG. 11 is a circuit diagram of a pixel driving circuit of a display panel according to another embodiment of the present disclosure.
  • the pixel driving circuit has a 7T1C structure, that is, includes transistors T1, T2, T3, T4, T5, T6, T7 and a capacitor Cst, wherein the transistor T3 is a driving transistor.
  • ELVDD represents the ELVDD voltage applied by the power line
  • EM represents the emission control signal from the emission control line
  • Data represents the data signal from the data line
  • Gate represents the scan signal from the gate line
  • Reset represents the reset signal, which can be generated by the previous gate Polar line application
  • Vinit represents the initialization voltage
  • ELVSS represents the ELVSS voltage applied by the power line.
  • the gate of the transistor T3 is connected to the first capacitor plate Cstl of the capacitor Cst.
  • the gate of the transistor T3 and the first capacitor plate Cstl of the capacitor Cst are electrically connected to the node N1.
  • the source of the transistor T3 is connected to the ELVDD power supply line through the transistor T5.
  • the drain of the transistor T3 is electrically connected to an organic light emitting device (such as an OLED) through the transistor T6.
  • the drain of the transistor T3 and the transistor T6 are electrically connected to the node N2.
  • the transistor T3 receives the data signal Data according to the switching operation of the transistor T4, and supplies the driving current I d to the organic light emitting device.
  • the gate of the transistor T4 is connected to the gate line, the source is connected to the data line, and the drain is connected to the source of the transistor T3 and connected to the ELVDD power line through the transistor T5.
  • the source of the transistor T3, the drain of the transistor T4, and the drain of the transistor T5 are electrically connected to the node N3.
  • the gate of the transistor T2 is connected to the gate line, the source is connected to the drain of the transistor T3 and to the organic light emitting device through the transistor T6, and the drain is connected to the first capacitor plate Cstl of the capacitor Cst, the drain of the transistor T1, and the transistor The gate of T3.
  • the drain of the transistor T2, the first capacitor plate Cstl of the capacitor Cst, the drain of the transistor T1, and the gate of the transistor T3 are electrically connected to the node N1.
  • the transistor T2 is turned on according to the scan signal Gate from the gate line to electrically connect the gate and drain of the transistor T3, thereby placing the transistor T3 in a diode connection state.
  • the gate of the transistor T1 receives the reset signal Reset, the source receives the initialization voltage Vinit, and the drain is connected to the node N1.
  • the transistor T1 is turned on according to the reset signal Reset to transmit the initialization voltage Vinit to the gate of the transistor T3.
  • the gate of the transistor T5 receives the emission control signal EM, the source is connected to the ELVDD power line, and the drain is connected to the node N3.
  • the gate of the transistor T6 receives the emission control signal EM, the source is connected to the node N2, and the drain is connected to the source of the transistor T7 and the organic light emitting device.
  • the drain of the transistor T6, the source of the transistor T7, and the organic light emitting device are electrically connected to the node N4.
  • the transistor T5 and the transistor T6 are simultaneously turned on according to the emission control signal EM.
  • the gate of the transistor T7 is connected to the gate line to receive the scan signal Gate, the source is connected to the node N4, and the drain receives the initialization voltage Vinit.
  • the capacitor Cst also includes a second capacitor plate Cst2 connected to the ELVDD power line, and the first electrode (e.g., anode) of the organic light emitting device is connected to the node N4, and the second electrode (e.g., cathode) is connected to the ELVSS power line. Therefore, the organic light emitting device of the pixel can emit light based on the driving current I d from the transistor T3.
  • the first electrode e.g., anode
  • the second electrode e.g., cathode
  • FIG. 12 shows a signal timing diagram of the pixel driving circuit of FIG. 11. Next, in conjunction with FIGS. 11 and 12, the operation process of the pixel driving circuit of FIG. 11 will be described.
  • a reset signal Reset having a low level is supplied to the transistor T1.
  • the transistor T1 is turned on based on the low level of the reset signal Reset, and the initialization voltage Vinit is transmitted to the gate (i.e., node N1) of the transistor T3 through the transistor T1. Therefore, the transistor T3 is initialized due to the initialization voltage Vinit. Therefore, the first time period t1 may also be referred to as the "initialization phase".
  • the scan signal Gate having a low level is supplied through the gate line.
  • the transistors T4 and T2 are turned on based on the low level of the scan signal Gate. Therefore, through the turned-on transistor T2, the gate of the transistor T3 is connected to the drain, is placed in a diode-connected state and is biased in the forward direction.
  • the data signal Data supplied via the data line is supplied to the source of the transistor T3 through the turned-on transistor T4. Therefore, the gate voltage of the transistor T3 (ie the voltage at the node N1) is equal to the data signal Data minus the threshold of the transistor T1
  • the theoretically obtained compensation voltage is Vdata+Vth (for example, Vth is a negative value).
  • the second time period t2 may also be referred to as the "data programming phase".
  • the emission control signal EM from the emission control line changes from a high level to a low level.
  • the transistors T5 and T6 are turned on based on the low level of the emission control signal EM.
  • the drive current I d is generated based on the difference between the voltage of the gate of the transistor T1 (ie, the voltage at the node N1) and the power supply voltage ELVDD. It is supplied to the organic light emitting device through the turned-on transistor T6. Therefore, the third time period t3 may also be referred to as the "light-emitting phase".
  • the gate voltage of the transistor T3 is maintained at Vdata+Vth
  • the source voltage of the transistor T3 is ELVDD
  • the gate-source voltage V GS of the transistor T3 is ELVDD-( Vdata+Vth).
  • the driving current I d for driving the organic light-emitting device OLED to emit light is proportional to (ELVDD-Vdata) 2 . Therefore, the driving current I d has nothing to do with the threshold voltage Vth of the driving transistor T3, so that the unevenness of the light emission caused by the difference in the threshold voltage Vth of the driving transistor can be eliminated.
  • the IR Drop phenomenon causes the ELVDD voltage and the ELVSS voltage applied to each pixel by the power line to be inconsistent.
  • the voltage at node N1 remains at Vdata+Vth, but referring to the capacitor charging curve in Figure 8, after the capacitor Cst is charged at this stage, the voltage at node N1 will be very close to Vdata+Vth , But not exactly equal to the data voltage Vdata+Vth.
  • the voltage V1 at the node N in the pixel PX1 is higher than the voltage V4 at the node N in the pixel PX4.
  • the voltage of the gate of the driving transistor T3 will also be different.
  • the gate voltage V1 of the driving transistor T3 in the pixel PX1 is higher than the gate voltage V4 of the driving transistor T3 in the pixel PX4.
  • the ELVDD voltage applied to the pixel PX1 is higher than the ELVDD voltage applied to the pixel PX4, that is, the source voltage ELVDD of the driving transistor T3 in the pixel PX1 is higher than the source voltage ELVDD of the driving transistor T3 in the pixel PX4.
  • the voltage between the gate and source of the driving transistor T3 in the pixel PX1 and the voltage between the gate and the source of the driving transistor T3 in the pixel PX4 tend to be the same, so that The current flowing in the organic light emitting device of the pixel PX1 tends to be consistent with the current flowing in the organic light emitting device of the pixel PX4, so as to achieve compensation for IR Drop.
  • the voltage drop on the power line is related to the length of the power trace and the power signal line from the voltage generator to the power line of the pixel. In order to compensate for the voltage drop, it can be The length of the power supply trace and the power supply signal line to the pixel design the capacitance value of the capacitor.
  • the capacitance value of the capacitor in the pixel (for example, the pixels PX3, PX4, and PX5) can be designed to be larger.
  • the embodiments of the present disclosure are not limited to the design of the capacitance value of the capacitor according to the length of the power trace and the power signal line. In addition to the length of the trace, it may also be related to the cross-sectional area of the power trace. Therefore, in other embodiments, the capacitance value of the capacitor can also be designed according to the cross-sectional area of the power trace and the power signal line. That is, based on the voltage drop on the first power line (eg ELVDD power line) and/or the second power line (eg ELVSS power line), the capacitance value of the capacitor of each pixel is designed to compensate for the voltage drop.
  • the first power line eg ELVDD power line
  • ELVSS power line the capacitance value of the capacitor of each pixel is designed to compensate for the voltage drop.
  • the electroluminescent display device may include, but is not limited to: electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • FIG. 13 an example in which the display device is a full-screen smart phone is schematically shown.
  • the aspect ratio of the screen of the full-screen smart phone 1300 may be 18:9, 18.5:9, or 19.5:9, or even 21:9 or higher.
  • the display device has the same beneficial effects as the display panel provided in the foregoing embodiments. That is, the display device according to the embodiment of the present disclosure can compensate for the voltage drop on the power line, thereby achieving the uniformity of light emission of the display device and improving the uniformity of the long range.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention concerne un panneau d'affichage électroluminescent et un dispositif d'affichage électroluminescent. Le panneau d'affichage électroluminescent comprend : un premier pixel comprenant un premier condensateur ; un second pixel comprenant un second condensateur ; un générateur de tension destiné à générer une première tension ; un premier câblage d'alimentation électrique, dont une première extrémité est connectée au générateur de tension, et une seconde extrémité est connectée au premier pixel, afin de fournir la première tension générée par le générateur de tension au premier pixel ; un second câblage d'alimentation électrique, dont une première extrémité est connectée au générateur de tension, et une seconde extrémité est connectée au second pixel, afin de fournir la première tension générée par le générateur de tension au second pixel. La valeur de capacité du premier condensateur dépend d'une différence de tension entre la première tension et la tension au niveau de la seconde extrémité du premier câblage d'alimentation électrique, et la valeur de capacité du second condensateur dépend de la différence de tension entre la première tension et la tension au niveau de la seconde extrémité du second câblage d'alimentation électrique. La valeur de capacité du premier condensateur diffère de celle du second condensateur, de manière à compenser la différence entre une chute de tension sur le premier câblage d'alimentation électrique et une chute de tension sur le second câblage d'alimentation électrique.
PCT/CN2020/077209 2019-03-14 2020-02-28 Panneau d'affichage électroluminescent et dispositif d'affichage électroluminescent WO2020181999A1 (fr)

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CN112991951B (zh) * 2021-02-26 2023-02-28 合肥维信诺科技有限公司 显示面板和显示装置
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