WO2020181473A1

WO2020181473A1 - CIRCUIT STRUCTURE, SYSTEM ON CHIP (SoC), AND DATA PROCESSING METHOD

Info

Publication number: WO2020181473A1
Application number: PCT/CN2019/077722
Authority: WO
Inventors: 陈学义; 刘瑛
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2019-03-11
Filing date: 2019-03-11
Publication date: 2020-09-17
Also published as: CN111247516A

Abstract

Provided are a circuit structure, a system on chip (SoC), and a data processing method. The circuit structure comprises one or more memories, and multiple channel controllers obtaining multiple pieces of data to be checked from the one or more memories, wherein each channel controller corresponds to one check algorithm; and the multiple channel controllers perform processing on said multiple data by means of the respective corresponding check algorithm, and writes the processed data into the one or more memories. The data is processed by the multiple channel controllers by means of the respective corresponding check algorithm, so that less CPU computing resources are consumed, and the resource utilization rate is improved; furthermore, respective data is processed by means of each channel controller, so that the speed of data processing is increased, and data throughput is improved.

Description

A circuit structure, system-level chip SoC, and data processing method

Copyright statement

The content disclosed in this patent document contains copyrighted material. The copyright belongs to the copyright owner. The copyright owner does not object to anyone copying the patent document or the patent disclosure in the official records and archives of the Patent and Trademark Office.

Technical field

This application relates to the field of communications, and more specifically, to a circuit structure, a system-on-chip SoC, and a method for processing data.

Background technique

In data transmission, taking into account the instability of the communication line, the interference of the external environment, instrument failure, etc., the data received by the receiving end often has certain errors. If these wrong signals are used normally, the user experience is very bad. , And sometimes even great losses. Therefore, it is necessary to introduce a verification system.

There are many common check methods in system-on-chip (system-on-chip, SoC) systems, such as cyclic redundancy check (CRC) and checksum (Checksum).

In the SoC system, considering the computing power of the central processing unit (CPU), generally only one type of calculation module is provided, for example, one type of CRC calculation module or a Checksum calculation module is provided. In addition, the verification of large amounts of data, such as CRC calculation and Checksum calculation of large amounts of data, consumes valuable CPU computing power.

Summary of the invention

This application provides a circuit structure, a system-on-chip SoC, and a method for processing data, which can avoid consuming too much CPU computing resources and improve resource utilization and data throughput.

In a first aspect, a circuit structure is provided, including: one or more memories, a plurality of channel controllers, a plurality of data to be verified are obtained from the one or more memories, and each channel controller corresponds to a kind of verification Algorithm; the multiple channel controllers process the multiple data to be verified through their respective corresponding verification algorithms, and write the processed data into the one or more memories.

In a second aspect, a method for processing data is provided, including: receiving a plurality of data to be verified on multiple channels, each channel corresponding to a verification algorithm; The verification algorithm processes the multiple data to be verified.

In a third aspect, a system-on-chip SoC is provided, including: a plurality of channel controllers, each channel controller corresponding to a check algorithm; the plurality of channel controllers use their respective check algorithms to perform verification on multiple The data to be verified is processed.

In a fourth aspect, a channel controller is provided. The channel controller is applied to the circuit structure of the above-mentioned first aspect, or the channel controller is applied to the system-on-chip SoC of the above-mentioned third aspect.

In a fifth aspect, a device is provided, and the device is configured to execute the method in the second aspect.

In a sixth aspect, a device is provided, the device includes a memory and a processor, the memory is configured to store instructions, the processor is configured to execute instructions stored in the memory, and execute the instructions stored in the memory The processor is caused to execute the method of the second aspect.

In a seventh aspect, a chip is provided. The chip includes a processing module and a communication interface, the processing module is configured to control the communication interface to communicate with the outside, and the processing module is also configured to implement the method of the second aspect.

In an eighth aspect, a computer-readable storage medium is provided, on which instructions for executing the method in the second aspect are stored.

In a ninth aspect, a computer program product containing instructions is provided, including instructions for executing the method in the second aspect.

In the solution provided by this application, multiple channel controllers respectively correspond to a verification algorithm, and multiple channel controllers process data through their corresponding verification algorithms, so that not only the resource utilization rate can be improved, but also the data throughput rate can be improved. .

Description of the drawings

FIG. 1 is a schematic diagram of a circuit structure provided by an embodiment of the application.

Fig. 2 is a schematic diagram of a channel controller suitable for an embodiment of the present application.

Fig. 3 is a schematic diagram of data processing by a channel controller applicable to an embodiment of the present application.

FIG. 4 is a schematic block diagram of a method for processing data provided by an embodiment of the application.

FIG. 5 is a schematic block diagram of an optimization device for processing data provided by an embodiment of the application.

FIG. 6 is a schematic structural diagram of an optimization device for processing data provided by an embodiment of the application.

detailed description

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of this application. The terms used in the description of the application herein are only for the purpose of describing specific embodiments, and are not intended to limit the application.

To facilitate understanding, first introduce the related technologies and concepts involved in the embodiments of the present application.

1. Cyclic redundancy check (CRC): It is the most commonly used error checking code in the field of data communication, and its feature is that the length of the information field and the check field can be arbitrarily selected. Cyclic Redundancy Check (CRC) is a data transmission error detection function, which performs polynomial calculation on data and attaches the obtained result to the back of the frame. The receiving device also executes similar algorithms to ensure the correctness and integrity of data transmission Sex.

The basic principle of CRC can be: after the K-bit information code and then splicing the R-bit check code, the entire code length is N bits, so this kind of code is also called (N, K) code. For a given (N, K) code, it can be proved that there is a polynomial G(x) with the highest power of N-K=R. According to G(x), the check code of K-bit information can be generated, and G(x) is called the generator polynomial of this CRC code. The specific generation process of the check code is: assuming that the information to be sent is represented by a polynomial C(X), shift C(x) to the left by R bits (which can be expressed as C(x)*2R), so that the right side of C(x) The R bit will be vacated, which is the location of the check code. The remainder obtained by dividing C(x)*2R by the generator polynomial G(x) is the check code.

It should be understood that the above only briefly introduces a possible basic principle of CRC for ease of understanding, and does not limit the protection scope of this application. The specific calculation method and verification method of CRC may be the same as the prior art. For brevity, a detailed description of the specific process is omitted here.

2. Checksum: In the field of data processing and data communication, the sum of a set of data items used for verification purposes. These data items can be numbers or other character strings that are treated as numbers in the calculation of the check sum.

Checksum may include transmission control protocol (transmission control protocol, TCP) checksum (TCP Checksum), user datagram protocol (user datagram protocol, UDP) checksum (UDP Checksum). Both TCPChecksum and TCPChecksum can be used to verify the data in the message.

It should be understood that the specific calculation method and verification method of Checksum may be the same as the prior art. For brevity, a detailed description of the specific process is omitted here.

It should be understood that the foregoing only exemplarily introduces two methods for verifying data, CRC and Checksum, and this application is not limited thereto. Any method that can verify data can use the technical solution of this application.

The calculation of CRC and Checksum is widely used in data transmission and security verification. At present, in the design of system-on-chip (SoC), it does not support multiple parallel calculations of different CRCs and Checksums, that is, generally only one CRC calculation module or one Checksum calculation is provided Module. In this way, not only the utilization of hardware resources is low, but the calculation of CRC and Checksum of large amounts of data consumes precious CPU computing power in SoC.

This application proposes a circuit structure that does not need to consume so much CPU computing resources, which not only improves resource utilization, but also improves data throughput.

FIG. 1 is a circuit structure 10 provided by an embodiment of the present application. The circuit structure 10 can be a chip, such as an SoC, or a device with a housing.

The circuit structure 10 may include multiple channel controllers. As shown in FIG. 1, the circuit structure 10 may include a first channel controller 11, a second channel controller 12, a third channel controller 13, and a fourth channel controller 14. The fifth channel controller 15, the sixth channel controller 16, the seventh channel controller 17, and the eighth channel controller 18. The above channel controllers can be implemented in the form of circuits, for example.

It should be understood that FIG. 1 only lists eight channel controllers for ease of understanding, and the present application is not limited thereto. The circuit structure 10 may include a greater number or a smaller number of channel controllers.

It should also be understood that the channel controller is only a naming and does not limit the protection scope of this application, and this application does not exclude the possibility of adopting other naming in the future.

The circuit structure 10 may include one or more memories, and the one or more memories can be used to store data to be verified, and can also be used to write processed data. As shown in Figure 1, the circuit structure 10 may include a memory 21, a first channel controller 11, a second channel controller 12, a third channel controller 13, a fourth channel controller 14, a fifth channel controller 15, and a The six-channel controller 16, the seventh-channel controller 17, and the eighth-channel controller 18 read the data to be processed from the memory 21 serially or in parallel, and different channel controllers correspond to different address ranges in the memory 21. The memory and each channel controller can be integrated on a circuit, or can be realized by separate circuits, which is not limited. In other embodiments, the circuit structure 10 may also include multiple memories, for example, one channel controller corresponds to one memory, two channel controllers correspond to one memory, or three channel controllers correspond to one memory... etc. This is not limited.

Exemplarily, the memory for storing the data to be verified and the memory for writing the processed data may be the same chip. For example, the channel controller may correspond to a memory that is used by the channel controller to obtain the data to be verified and used by the channel controller to write the processed data into the memory. For example, taking Figure 1 as an example, the first channel controller 11, the second channel controller 12, the third channel controller 13, the fourth channel controller 14, the fifth channel controller 15, the sixth channel controller 16, The seventh channel controller 17 and the eighth channel controller 18 read the data to be processed from the memory 21, and write the processed data into the memory 21 serially or in parallel

Exemplarily, the memory for storing the data to be verified and the memory for writing the processed data may be different slices. For example, the circuit structure 10 may include two memories, one of which is used by the channel controller to obtain the data to be verified, and the other memory is used by the channel controller to write the processed data into the memory; for example, the circuit structure may also Including multiple memories, etc., this is not limited.

Exemplarily, the type of the one or more memories may be the same or different.

Exemplarily, the memory may be a double-rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR), or a static random-access memory (static random-access memory, SRAM), etc. The application examples are not limited.

The memory included in the circuit structure 10 has been exemplified above, and this application does not strictly limit the memory.

The channel controller included in the circuit structure 10 will be described in detail below.

Each channel controller corresponds to a verification algorithm, and the multiple channel controllers process multiple data through their corresponding verification algorithms.

For example, each channel controller obtains data from the memory, processes the obtained data through a corresponding check algorithm, and writes the processed data into the memory.

Based on the above technical solution, the channel controller processes the data through their corresponding check algorithm, which does not need to consume so much CPU computing resources, improves resource utilization, and processes their own data through each channel controller to speed up processing The speed of data increases the data throughput rate.

As shown in Figure 2, each channel controller can correspond to a channel, for example, it is marked as channel 0, channel 1, channel 2, channel 3, channel 4, channel 5, channel 6, and channel 7. The data can be processed on its corresponding channel. Exemplarily, each channel may correspond to one or more memories.

Assume that the first channel controller 11 corresponds to channel 0, that is, the first channel controller 11 processes data on channel 0, such as calculating 0, calculating i, and calculating 15. Assume that the second channel controller 12 corresponds to channel 1, that is, the second channel controller 12 processes data on channel 1, such as calculating 0, calculating i, and calculating 15. Assume that the third channel controller 13 corresponds to channel 2, that is, the third channel controller 13 processes data on channel 2, such as calculating 0, calculating i, and calculating 15. Assume that the fourth channel controller 14 corresponds to channel 3, that is, the fourth channel controller 14 processes data on channel 3, such as calculating 0, calculating i, and calculating 15. Assume that the fifth channel controller 15 corresponds to channel 4, that is, the fifth channel controller 15 processes data on channel 4, such as calculating 0, calculating i, and calculating 15. Assume that the sixth channel controller 16 corresponds to channel 5, that is, the sixth channel controller 16 processes data on channel 5, such as calculating 0, calculating i, and calculating 15. It is assumed that the seventh channel controller 17 corresponds to channel 6, that is, the seventh channel controller 17 processes data on channel 6, such as calculating 0, calculating i, and calculating 15. Assume that the eighth channel controller 18 corresponds to channel 7, that is, the eighth channel controller 18 processes data on channel 7, such as calculating 0, calculating i, and calculating 15.

Among them, i = 1, 2, 3,..., 14, calculate 0, calculate i, calculate 15, which means that multiple data blocks can be calculated through the check algorithm corresponding to each channel controller, and each channel controller processes The data can be the same or different, for which there is no limitation.

As an example, each channel controller can process up to 16 different data blocks simultaneously. For example, calculate 0, calculate i, and calculate 15 shown in Figure 2.

The check algorithm, or the check calculation method, or the type used to check the data, is used to indicate the method of checking the data, for example, CRC, Checksum, etc. based on different generating polynomials.

As an example, the types of check algorithms include at least: CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, TCP Checksum, UDP Checksum, etc.

As an example, the type of the check algorithm corresponding to each channel controller may be the same or different.

In a possible implementation, the type of check algorithm corresponding to each channel controller can be different.

For example, the first channel controller 11 corresponds to the CRC polynomial 0x07, the second channel controller 12 corresponds to the CRC polynomial 0x31, and the third channel controller 13 corresponds to the CRC polynomial 0x5e.

Based on the above technical solution, by making the types of verification algorithms corresponding to the channel controllers different, the circuit structure can be used as a general circuit structure, supporting multiple different types of verification algorithms, and improving hardware utilization.

In another possible implementation manner, the types of verification algorithms corresponding to each channel controller may be partially the same.

For example, assuming that there is a large demand for a check algorithm of the type TCP Checksum, multiple channel controllers can be set to correspond to the CRC polynomial 0x07, such as the first channel controller 11, the second channel controller 12, and the third channel controller. The channel controller 13 corresponds to the CRC polynomial 0x07.

Based on the above technical solution, the types of verification algorithms corresponding to some channel controllers in multiple channel controllers can be made the same according to some factors such as the size of the demand, which can meet user needs as much as possible and improve user experience.

As an example, the type of check algorithm corresponding to each channel controller can be dynamically configured.

In other words, the type of check algorithm supported by each channel can be dynamically configured. For example, at the first moment, the first channel controller 11 corresponds to the CRC polynomial 0x07, and at the second moment, the first channel controller 11 corresponds to the CRC polynomial 0x31. For another example, when processing the first data block, the first channel controller 11 corresponds to the CRC polynomial 0x07, and when processing the second data block, the first channel controller 11 corresponds to the CRC polynomial 0x31.

Based on the above technical solution, the type of verification algorithm corresponding to the channel controller can be flexibly adjusted according to requirements, which can improve the utilization rate of the channel controller and save hardware resources.

As an example, each channel controller can process their corresponding data in parallel.

For example, the first channel controller 11, the second channel controller 12, the third channel controller 13, the fourth channel controller 14, the fifth channel controller 15, the sixth channel controller 16, the seventh channel controller 17 , The eighth channel controller 18 processes respective data in parallel, such as performing calculation 0, calculation i, and calculation 15 in parallel.

Based on the above technical solution, the parallel processing of data through each channel controller can improve the efficiency of data processing and increase the data throughput rate.

The following describes in detail how the channel controller processes data in conjunction with Figure 3.

The circuit structure 10 may also include multiple input modules and multiple output modules, and the multiple input modules correspond to multiple channel controllers one to one. Each channel controller reads the configured CRC or Checksum calculation configuration information through its corresponding input module, automatically completes the CRC or Checksum calculation, and outputs the calculation result through the corresponding output module. Each channel controller can have an independent input information descriptor.

As shown in Figure 3, the channel controller reads in data, that is, the channel controller reads the corresponding data input configuration information, and the channel controller can continuously read the input configuration information of up to 16 data blocks.

Each input configuration information can include configuration information related to the input data. For example, the input configuration information can include one or more of the following information: the starting address of the data to be calculated, the result output address, the initial value, the output XOR value, etc. . For another example, each input configuration information can consist of 4 pieces of 32-bit data.

Among them, the start address of the data to be calculated, that is, the first address of the data that needs to be CRC or Checksum operation (that is, the check algorithm corresponding to the channel controller). For example, the channel controller processes 16 data blocks, that is, the channel controller reads 16 input configuration information. For distinction, the starting address of the data to be calculated can be recorded as: the starting address of the data to be calculated 0, The starting address of the calculated data 1, the starting address of the data to be calculated 2,..., the starting address of the data to be calculated 15.

Among them, the result output address, that is, after the channel controller completes the data calculation, the channel controller outputs the first address of the calculation result. For example, the channel controller processes 16 data blocks, that is, the channel controller corresponds to 16 result output addresses. For distinction, the result output addresses can be recorded as: result output address 0, result output address 1, result output address 2, ……, the result output address is 15.

Among them, the initial value, for example, if it is a CRC operation, is the initial value of the CRC. For example, the channel controller processes 16 data blocks, that is, the channel controller corresponds to 16 initial values. Taking CRC calculation as an example, the initial values can be marked as: CRC initial value 0, CRC initial value 1, CRC Initial value 2,......, CRC initial value 15.

Among them, the output XOR value, for distinction, can also be recorded as: CRC output XOR value 0, CRC output XOR value 1, CRC output XOR value 2, ..., CRC output XOR value 15.

After the channel controller reads in the data, it processes the data. The channel controller can process data based on its corresponding check algorithm. It should be understood that the specific calculation method and verification method of the channel controller may be the same as the prior art. For brevity, a detailed description of the specific process is omitted here.

After the channel controller completes the corresponding operation (for example, CRC operation based on the generator polynomial or Checksum operation), it can output information related to the result, that is, it will write the result back to the output address specified in the input configuration information. For example, taking CRC as an example, any one or more of the following information can be output: output CRC value, CRC initial value in input information, calculated data length, CRC configuration information. For another example, each input configuration information can consist of 4 pieces of 32-bit data. For another example, the output information can consist of 4 pieces of 32bit data.

When the channel controller processes 16 data blocks, in order to distinguish, the results can be recorded as Calculate Output CRC 0, Calculate Output CRC 1, Calculate Output CRC 2,..., Calculate Output CRC 15; You can also separate the calculated lengths Recorded as CRC calculation length 0, CRC calculation length 1, CRC calculation length 2,..., CRC calculation length 15; CRC configuration information can also be recorded as CRC configuration information 0, CRC configuration information 1, CRC configuration information 2,... …, CRC configuration information 15.

It should be understood that FIG. 3 uses a channel controller as an example for description, and it should be understood that each channel controller can process data based on the foregoing manner.

It should also be understood that the above circuit structure may be loaded on one SoC, or the "circuit structure" in the above embodiment may be replaced with "SoC".

In the embodiment of the present application, multiple channel controllers process data through their corresponding verification algorithms, so that it does not need to consume so much CPU computing resources, which improves resource utilization, and each channel controller processes their own data, which speeds up The speed of data processing improves the data throughput rate.

The device embodiments of the present application are described above with reference to FIGS. 1 to 3, and the method embodiments corresponding to the above device embodiments will be described below with reference to FIG. 4. It should be understood that this method can be implemented by the circuit structure 10 described above. The description of the method embodiment and the description of the device embodiment correspond to each other. Therefore, for the content that is not described in detail, please refer to the previous device embodiment. For the sake of brevity, it will not be repeated here.

Fig. 4 is a schematic block diagram of a method 4 for processing data according to an embodiment of the present application. The method includes the following steps.

S410: Receive multiple data to be verified on multiple channels, and each channel corresponds to a verification algorithm;

S420: On multiple channels, process multiple data to be verified through respective corresponding verification algorithms.

In the embodiment of the present application, a circuit structure can be used, that is, multiple channels on the circuit structure process data through their corresponding check algorithms, so that there is no need to consume so much CPU computing resources, which improves the resources of the hardware circuit structure. Utilization rate, and each channel processes their own data, which speeds up data processing and improves data throughput.

Optionally, the type of the check algorithm corresponding to each channel can be dynamically configured.

In other words, the type of check algorithm corresponding to each channel can be dynamically configured. Therefore, the type of check algorithm corresponding to the channel can be flexibly adjusted according to the demand, which can improve the utilization rate of the channel and save hardware resources.

Optionally, the check algorithm corresponding to each channel is different.

Therefore, through the different types of verification algorithms corresponding to the channels, the circuit structure can be used as a general circuit structure, supporting multiple different types of verification algorithms, and improving hardware utilization.

Optionally, on multiple channels, processing multiple data to be verified through respective corresponding verification algorithms, including: processing multiple data to be verified in parallel through respective verification algorithms on multiple channels Test data.

In other words, each channel calculates its data independently and in parallel. Therefore, the efficiency of data processing can be improved, and the data throughput rate can be increased

Optionally, the first input configuration information is read on the first channel, the first input configuration information includes: the start address of the first data, the first result output address, the initial value, the output XOR value; through the first channel The corresponding verification algorithm calculates the first data to obtain the first result; output one or more of the following information to the first result output address: the first result, the initial value, the calculated data length, and the first input configuration information; Among them, the first channel is any one of the multiple channels.

Optionally, the type of the check algorithm includes at least: CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, TCPChecksum, UDPChecksum.

Optionally, each channel can process up to 16 data blocks simultaneously.

The method embodiment of the present application is described above with reference to FIG. 4, and the device embodiment of the present application is described below with reference to FIG. 5 and FIG. 6. It should be understood that the description of the device embodiment and the description of the method embodiment correspond to each other, and therefore, the parts that are not described in detail may refer to the previous method embodiment.

Fig. 5 is a schematic block diagram of a data processing apparatus provided by an embodiment of the present application. The device 500 includes the following units.

The transceiver unit 510 is configured to receive multiple data to be verified on multiple channels, and each channel corresponds to a verification algorithm;

The processing unit 520 is configured to process multiple data to be verified on multiple channels through respective verification algorithms.

Optionally, the check algorithm corresponding to each channel is different.

Optionally, the processing unit 520 is specifically configured to process multiple data to be verified in parallel through respective corresponding verification algorithms on multiple channels.

Optionally, the transceiver unit 510 is configured to: read the first input configuration information on the first channel, the first input configuration information including: the start address of the first data, the first result output address, the initial value, and the output XOR The processing unit 520 is configured to: calculate the first data through the check algorithm corresponding to the first channel to obtain the first result; the transceiver unit 510 is configured to: output one or more of the following information to the first result output address: The first result, the initial value, the calculated data length, and the first input configuration information; where the first channel is any one of the multiple channels.

Optionally, the type of the check algorithm includes at least: CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, TCP Checksum, UDP Checksum.

Optionally, each channel can process up to 16 data blocks simultaneously.

As shown in FIG. 6, an embodiment of the present application also provides a schematic structural diagram of an apparatus 600 for processing data. The apparatus 600 includes a processor 610 and a memory 620. The memory 620 is used to store instructions, and the processor 610 is used to execute the memory. The instructions stored in 620 and the execution of the instructions stored in the memory 620 enable the processor 610 to execute the data processing method in the above method embodiment.

The execution of the instructions stored in the memory 620 enables the processor 610 to execute the actions performed by the transceiver unit 510 and the processing unit 520 in the foregoing embodiment.

Optionally, as shown in FIG. 6, the apparatus 600 may further include a communication interface 630, which is used to exchange signals with external devices. For example, the processor 610 is configured to control the interface 630 to receive and/or send signals.

The embodiment of the present application also provides a computer storage medium on which a computer program is stored. When the computer program is executed by the computer, the computer executes the method in the method embodiment shown in FIG. 4.

The embodiment of the present application also provides a computer program product containing instructions, which when executed by a computer causes the computer to execute the method in the method embodiment shown in FIG. 4.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc. .

A person of ordinary skill in the art may be aware that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A circuit structure, characterized in that it comprises:

One or more memories;

Multiple channel controllers, acquiring multiple data to be verified from the one or more memories, and each channel controller corresponds to a verification algorithm;

The multiple channel controllers process the multiple to-be-verified data through respective corresponding verification algorithms, and write the processed data into the one or more memories.
The circuit structure according to claim 1, wherein:

The type of check algorithm corresponding to each channel controller can be dynamically configured.
The circuit structure according to claim 1 or 2, characterized in that:

The check algorithm corresponding to each channel controller is different.
The circuit structure according to any one of claims 1 to 3, wherein:

The multiple channel controllers process the respective data to be verified in parallel.
The circuit structure according to any one of claims 1 to 4, wherein:

The circuit structure includes multiple input modules and multiple output modules, and the multiple input modules correspond to the multiple channel controllers one-to-one,

The multiple channel controllers process multiple data to be verified through respective corresponding verification algorithms, including:

The first channel controller reads the first input configuration information in the first input module, where the first input configuration information includes: the start address of the first data, the first result output address, the initial value, and the output XOR value;

The first channel controller calculates the first data through a corresponding check algorithm to obtain the first result;

The first channel controller outputs one or more of the following information to the first result output address: the first result, the initial value, the calculated data length, and the first input configuration information;

Wherein, the first channel controller is any one of the plurality of channel controllers, and the first channel controller corresponds to the first input module.
The circuit structure according to any one of claims 1 to 5, wherein the type of the verification algorithm includes at least:

Cyclic Redundancy Check CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, Transmission Control Protocol Checksum TCPChecksum, User Datagram Protocol Checksum and UDP Checksum .
The circuit structure according to any one of claims 1 to 6, wherein:

Each channel controller can process up to 16 data blocks simultaneously.
A method for processing data, characterized in that it comprises:

Receive multiple data to be verified on multiple channels, and each channel corresponds to a verification algorithm;

On the multiple channels, the multiple to-be-verified data are processed through respective corresponding verification algorithms.
The method according to claim 8, wherein:

The type of check algorithm corresponding to each channel can be dynamically configured.
The method according to claim 8 or 9, characterized in that:

The check algorithm corresponding to each channel is different.
The method according to any one of claims 8 to 10, wherein:

The processing of the plurality of data to be verified on the plurality of channels through respective corresponding verification algorithms includes:

On the multiple channels, the multiple data to be verified are processed in parallel through respective corresponding verification algorithms.
The method according to any one of claims 8 to 11, wherein:

Read the first input configuration information on the first channel, where the first input configuration information includes: the start address of the first data, the first result output address, the initial value, and the output XOR value;

Calculating the first data by using the check algorithm corresponding to the first channel to obtain the first result;

Output one or more of the following information to the first result output address: the first result, the initial value, the calculated data length, and the first input configuration information;

Wherein, the first channel is any one of the multiple channels.
The method according to any one of claims 8 to 12, wherein the type of the verification algorithm at least includes:

Cyclic Redundancy Check CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, Transmission Control Protocol Checksum TCPChecksum, User Datagram Protocol Checksum and UDP Checksum .
The method according to any one of claims 8 to 13, wherein:

Each channel can process up to 16 data blocks at the same time.
A system-level chip SoC, which is characterized in that it includes:

Multiple channel controllers, each channel controller corresponds to a check algorithm;

The multiple channel controllers process multiple data to be verified through respective corresponding verification algorithms.
The SoC according to claim 15, wherein:

The type of check algorithm corresponding to each channel controller can be dynamically configured.
The SoC according to claim 15 or 16, characterized in that:

The check algorithm corresponding to each channel controller is different.
The SoC according to any one of claims 15 to 17, characterized in that:

The multiple channel controllers process the respective data to be verified in parallel.
The SoC according to any one of claims 15 to 18, characterized in that:

The SoC includes multiple input modules and multiple output modules, and the multiple input modules correspond to the multiple channel controllers one-to-one,

The multiple channel controllers process multiple data to be verified through respective corresponding verification algorithms, including:

The first channel controller reads the first input configuration information in the first input module, where the first input configuration information includes: the start address of the first data, the first result output address, the initial value, and the output XOR value;

The first channel controller calculates the first data through a corresponding check algorithm to obtain the first result;

The first channel controller outputs one or more of the following information to the first result output address: the first result, the initial value, the calculated data length, and the first input configuration information;

Wherein, the first channel controller is any one of the plurality of channel controllers, and the first channel controller corresponds to the first input module.
The SoC according to any one of claims 15 to 19, wherein the type of the verification algorithm at least includes:

Cyclic Redundancy Check CRC polynomial 0x07, CRC polynomial 0x31, CRC polynomial 0x5e, CRC polynomial 0x1021, CRC polynomial 0x8005, CRC polynomial 0x864CF8, CRC polynomial 0x04C11DB7, Transmission Control Protocol Checksum, TCP Checksum, User Datagram Protocol Checksum, and UDP Checksum.
The SoC according to any one of claims 15 to 20, wherein:

Each channel controller can process up to 16 data blocks simultaneously.
The SoC according to any one of claims 15 to 21, characterized in that:

The multiple channel controllers acquire the multiple data to be verified from one or more memories, and write the processed data into the one or more memories.
The SoC according to any one of claims 15 to 22, characterized by comprising the circuit structure according to any one of claims 1 to 7.
A channel controller, characterized in that the channel controller is applied to the circuit structure according to any one of claims 1 to 7, or the channel controller is applied to the circuit structure according to claims 15 to 22 In any of the system-on-chip SoCs.
A device for processing data, comprising: a memory and a processor, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory, and execute the instructions stored in the memory So that the processor is used to execute the method according to any one of claims 8 to 14.
A computer storage medium, characterized in that a computer program is stored thereon, and when the computer program is executed by a computer, the computer executes the method according to any one of claims 8 to 14.
A computer program product containing instructions, characterized in that when the instructions are executed by a computer, the computer executes the method according to any one of claims 8 to 14.