WO2020178437A1

WO2020178437A1 - Microprocessor event scheduler

Info

Publication number: WO2020178437A1
Application number: PCT/EP2020/056057
Authority: WO
Inventors: Damian Andrade Alfonseca; Tony Teixeira; Stéphane Guguen
Original assignee: Thales
Priority date: 2019-03-07
Filing date: 2020-03-06
Publication date: 2020-09-10
Also published as: FR3093579A1; FR3093579B1

Abstract

Method and system for temporal distribution of the events to be transmitted in an initial time window T_i=[t₀, t_max], characterised in that it includes at least the following steps: - identifying at least two events E₁, E_j to be executed by the first microprocessor (1), - identifying, for each event E₁, E_j, its frequency of execution F₁, F_j, according to frequencies that are multiples of two, and the duration T₁, T_j of execution of an event, - inserting a first event E₁ and calculating the time availability T_i remaining in the initial time window T, in order to determine the maximum size in time and the maximum permissible frequency of a future event E_j, - based on the time availability, the size of an event and its permissible frequency, calculating, for each future event Ej to be executed and for each of the n occurrences of said event in the initial time window, a time offset value dt such that t₀+dt₁(E_j), t₀+dt₂(E_j), t₀+dt₃(E_j),...t₀+dt_n(E_j) corresponding to the temporal position of the future event E_j relative to the start time t0 in the initial time window, - executing the event E_j and verifying whether the time of execution of the event E_j by the microprocessor, T_jmicro complies with the time of execution T_JFPGA expected in the FPGA.

Description

MICROPROCESSOR EVENT ORDER.

[0001] The invention relates to a scheduler of events or tasks or "scheduler" of an operating system or OS (Operating System).

[0002] Operating systems manage task priorities and interruptions. The busy time of the microprocessor is used to make context backups when an interrupt occurs. Therefore, the CPU occupancy time cannot be used at 100%, as allowances must be made for the operating system.

[0003] When a communication bus is shared by several devices, a margin for filling the bandwidth is taken in order to manage possible collisions between the tasks. The data processing capacity of a bus is therefore not fully exploited.

[0004] To increase the tool computation time of a microprocessor, ie, time available only for the computation, one solution is to use devices to operate more quickly in order to be able to hold real time with the operating system and user functions.

[0005] In terms of communications between several items of equipment, the prior art therefore tends to increase the number of connections or even to increase the bandwidth in order to ensure that all requests are processed by the bus.

[0006] The solutions known by the applicant therefore lead to the use of more efficient and more expensive components and to an increase in connections in the case of communication.

[0007] On a microprocessor, when many tasks must be executed simultaneously, an operating system must be implemented to manage access to the computing units, because the operations are carried out in series. If the real-time constraints are important, the computation speed must be increased in order to be able to execute all the necessary operations and to ensure the management of inputs and outputs at the microprocessor level. The management of inputs and outputs, the interruption of tasks with their context saving and other operations make it not possible to make optimum use of the computing capacities of the microprocessor. On a programmable component such as FPGA (Field Programming Gâte Array), it is possible to implement simultaneously several operations and thus optimize the calculations. The management of inputs / outputs can also be done without constraining calculations. Debugging the algorithms is difficult to achieve and the implementation of the algorithms requires significant resources which leads to an increase in the size and cost of an FPGA.

[0008] The idea of the present patent application is based in particular on pre-planning of events at the level of a microprocessor and communications in a deterministic manner, without resorting to management of the priorities of the interruptions. The events are executed in a specific order so as to never have two events running at the same time and without interrupting the execution of an event.

[0009] In the remainder of the description, the word "event" indifferently denotes tasks to be performed by a processor or an operating system, messages, or any other event or any other action executed by a microprocessor.

The invention relates to a method for temporally distributing the events to be transmitted in an initial time window Ti = [t ₀ , t _max ], said events being executed by a first microprocessor, the time distribution being carried out by a programmable device characterized in that it comprises at least the following steps:

- identify at least two events Ei, E _j , to be executed by the first microprocessor,

- identify for each event Ei, E _j , its execution frequency Fi, F _j , according to frequencies multiples of two, the duration Ti, T _j , of execution of an event,

- insert a first event Ei and calculate the time availability T _r remaining in the initial time window T, in order to determine the maximum size in time and the maximum admissible frequency of a future event E _j ,

- from the time availability, the size of an event and its admissible frequency, calculate for each future event E _j to be executed and for each of the n occurrences of said event in the initial time window, a time offset value dt such as to + dti (E _j ), to + dt ₂ (E _j ), to + dt ₃ (E _j ), ... to + dt _n (E _j ) corresponding to the temporal positioning of the future event E _j in relation to at the start time t ₀ in the initial time window, - execute the event E _j and check whether the execution time of the event E _j by the microprocessor, T _j micro conforms to the execution time 1 RQA expected in the FPGA.

The method can take into account the priority associated with the events to be executed in a time window to determine the times of execution of each of these events.

The invention also relates to a system for temporally distributing the events to be transmitted in an initial time window Ti = [t ₀ , t _max ] characterized in that it comprises at least the following elements:

- a device comprising a shared memory and an event scheduler,

- said scheduler is suitable for:

determine the execution times of at least two events in the initial time window T i = [to, t _ma x], taking into account the time availability T _r remaining in the initial time window T, after the insertion of d 'a first event, from the time availability, the size of a future event and its admissible frequency, to be calculated for each future event E ₂ to be executed a time offset value dt corresponding to the temporal positioning of the future event E ₂ in relation to the start time to in the initial time window and to check whether the execution time of the event E ₂ by the microprocessor, T2micro conforms to the execution time T ₂ FPGA,

- execute the event and check if the event execution time complies with the expected execution time,

- a first microprocessor configured to execute the events stored in a shared memory, on receipt of an interrupt command INT issued by said device and to transmit the execution time of an event to the scheduler.

[0013] The scheduler is, for example, configured to calculate the remaining time availability in each of the n windows generated by the positioning of the event executed n times in the initial time window.

The scheduler according to the invention can be used to distribute the tasks executed by at least a first equipment EQi and at least a second equipment EQ ₂ synchronized and which exchange data. Other characteristics and advantages of the invention will become apparent on reading the description of exemplary embodiments given by way of illustration and in no way limiting appended figures showing:

[0016] [Fig.1] a diagram of a parallel architecture for the implementation of the invention,

[0017] [Fig.2] a diagram illustrating the exchanges between the elements of Figure 1,

[0018] [Fig.3] illustrates the step of configuring tasks and communication messages,

[0019] [Fig.4] illustrates the planning step following the configuration step,

[0020] [Fig.5] illustrates a system implementing the method according to the invention.

The principle implemented in the method and the system according to the invention are based in particular on a management of the events processed by a microprocessor and of the communications in a deterministic manner, without having recourse to a management of the priorities of the interruptions, in normal operation . The tasks will be executed in a specific order, so that you never have two events running at the same time and without interrupting the execution of an event. The communication and the management of events or tasks are organized temporally so as to make all the equipment of the network interact in a synchronized manner and without any interruption.

[0022] FIG. 1 is a diagram showing a parallel bus architecture and the exchanges between a first microprocessor 1 and the FPGA 2.

The microprocessor 1 comprises a program 4 and a shared memory 3 with a memory of the FPGA. These elements are known to those skilled in the art and will not be detailed, the sharing of memories taking place according to a principle known to those skilled in the art. The microprocessor includes a timer which is activated when an interrupt execution of an event or a task is activated. When the execution of the task is finished, the timer stops and the microprocessor transmits the execution time of the task to the FPGA which will then stop its timer, before performing the execution time verification of a event. The sequence of these steps is illustrated in Figure 2. The programmable FPGA device 2 comprises a shared memory 5, a data and communication manager 6 and a scheduler 7 object of the invention. The data and communications manager exchanges information (data) with the shared memory of the microprocessor. The scheduler 7 manages the interrupts at the level of the microprocessor and will allow the execution of the events in a deterministic manner and one by one as was indicated previously. It is the scheduler which determines the instant of positioning of an event to be executed and which will calculate how to temporally position the various events to be executed in the time window. The data and communication manager is for example a communication bus shared by several devices.

FIG. 2 illustrates exchanges between the microprocessor and the FPGA.

The FPGA data and communication manager transmits a data write order from the FPGA to the shared memory 3 of the microprocessor 1, 21. At the same time, the scheduler 7 transmits an interrupt signal INT to the program 4 implemented on the microprocessor 1, 22. The microprocessor on reception of the interrupt signal reads the data which are in its shared memory 3, 23. The data read are transmitted to the program 4 which will select, 24, an application to be executed according to the content of the data and execute, 25, the selected application. Running the application generates data that will be written to shared memory 3 and then transmitted to shared memory 5 of the FPGA. The scheduler 7 knowing the execution time of an event and its temporal positioning in a time window will check the execution time, 27, then read the data, 28.

[0027] FIG. 3 illustrates the planning step carried out by the scheduler according to the invention, of the tasks and of the communication messages to be transmitted, in the example, three tasks and two messages. The tasks and messages to be sent are identified. By default, the tasks and the messages are stacked one behind the other at the level of a stack, not shown in the figure for reasons of simplification, according to the time availability remaining in a time window. For each message and for each task, the microprocessor identifies its execution frequency, according to frequencies that are multiples of two, the execution duration T _t of the task or the duration T _m of the message (time space taken up by the task or the message), and possibly the preceding messages and / or tasks. It is the slowest event which determines the repetition speed of the cycle, corresponding to a time window. At each interruption of the execution of an event, the _micro timer T of microprocessor 1 is activated, at the same time the TFPGA timer of the FPGA is activated. These two timers make it possible in particular to check the execution time of an event, at the level of the microprocessor and in the FPGA. At the end of the execution of the event, the microprocessor timer stops and transmits the measured time to the FPGA, which upon receipt of this information stops its timer.

After insertion of a new event (task or message), the scheduler recalculates the temporal availability of use of the resources of the microprocessor, in the time window. The scheduler will recalculate after each positioning of an event to be executed, taking into account the "execution time size" of the event, the time interval remaining in the time window and available so that the microprocessor can perform other events. In the case where an event is executed n times in the time window, the scheduler will calculate the interval remaining in the time window for each occurrence of the event. The scheduler will calculate the time interval remaining for the n time windows thus generated in the time window (T ₀ to T _max ), this is for example illustrated with the fourth event executed four times in the initial time window [To, T _max ] and therefore will lead to four time offset values to be used for the execution of events, which is illustrated in the figure by t ₀ + dti (E ₄ ), t ₀ + dt ₂ (E ₄ ), t ₀ + dt ₃ (E ₄ ), t ₀ + dt ₄ (E ₄ ). Generically for an event j, with a number of occurrences n in the time window, if the conditions of time availability are met, we will have n time instants of positioning of the event j, such as to + dt-i ( Ej), to + dt ₂ (Ej), to + dt ₃ (Ej), ... to + dt _n (Ej).

In the example of Figure 3, the messages and tasks are programmed according to an order of execution defined in advance by a user or a given application, the order of execution is guaranteed if the field "priority or previous ”, the previous task or message is filled in.

From the information given during the planning step, the scheduler will define the times of execution of the tasks and / or events. For this, the scheduler takes into account the minimum frequency value f _min of all the tasks and messages considered. This frequency (f _mî n) determines the cycle of repetition of events as well as the maximum time window (T ₀ to T _max ), T ₀ is the instant at which the processor begins to execute an event, T _max the upper limit. Then it determines a time offset value (t _x ) or offset for an event (task or message) which must be executed (To + t _x ). In figure 4, the time shifts or offsets lead to an execution order with: the first message transmitted at t ₀ = 0, the fifth event executed at t = t ₀ + 100ms, the second event executed at t = to + 125ms, the third event executed at t = to + 175ms, the fourth message is transmitted at t = to + 200ms. On each new cycle, the time offsets are repeated.

For the calculation of the remaining time window, after positioning the fourth event for example, the latter being executed n times in the time window, the scheduler 7 calculates the remaining interval for the time windows generated at each positioning of 'an occurrence of the fourth event, [t = (to + 200ms + size in ms of the event) + (t ₀ + n ^* 200ms)] where n corresponds to the number of times the fourth event appears in the time window.

[0032] The method according to the invention thus guarantees that all the planned events will be executed one by one, without ever crossing over time and taking into account their frequency of execution. The scheduler 7 generates the information used to generate interrupts in order to execute all the events, all the messages and the scheduled tasks sequentially.

[0033] At the end of the execution of an event, the event scheduler or "scheduler" checks whether the execution time corresponds to the expected. The measured time of execution of an event by the first microprocessor 1 is compared with the time measured by the FPGA, according to a principle known to those skilled in the art. This allows in particular to verify that the microprocessor did not stop during the execution of the event with an error or remained stuck in an infinite loop.

[0034] FIG. 5 illustrates an example of an implementation of the event scheduler according to the invention. In this configuration, the ancillary tasks are left to the FPGA. A communication protocol known to those skilled in the art allows the exchange of data between the first microprocessor 1 and the FPGA 2, as well as the verification of the correct execution of the desired computation task in the planned time slot. The computing power of the microprocessor is thus optimized.

[00351 Task settings:

- The FPGA contains an event scheduler according to the invention where the execution order of events or tasks has been obtained by implementing the method according to the invention described above,

- The FPGA writes (WR) on a DPRAM memory shared with the microprocessor the identifier (ID) of the task to be executed as well as the input parameters (DATA IN),

- The FPGA launches an INT interrupt to the first microprocessor 1 and starts an FPGA timer or Timer,

[0036] Execution of task or event

- The first microprocessor initializes a microprocessor Timer,

The first microprocessor 1 receives an interrupt from the FPGA and reads (RD) the DPRAM exchange memory,

The content of this reading (DATA IN) corresponds to the task to be performed as well as the input parameters,

The first microprocessor performs the corresponding task,

The first microprocessor initiates a write to shared memory DPRAM 3 and returns the microprocessor timer, the identifier of the task that has just been executed (ID) as well as the output parameters (DATA OUT),

[0037] Task verification

- The FPGA controls its Timer by comparing with the Timer of the first microprocessor, according to a method known to those skilled in the art,

- The FPGA can use the output parameters (DATA OUT),

- A new cycle can be started.

FIG. 4 is used to illustrate an example of implementation of the method according to the invention in the case where the scheduler according to the invention is used in a system comprising several devices, synchronized with each other and exchanging data or information. The scheduler will distribute the execution of the tasks on the different equipment. The events illustrated in FIG. 4 can be attributed to different equipment, distant from each other and interconnected. These events are clocked in multiples of two with respect to a frequency F ₀ . In the example, the event T ₂ is executed at the frequency T ₀ = 8Hz and all the other events are multiples of this frequency, i.e. 4 Hz, 2 Hz and 1 Hz. Since the events cannot be executed at the same time, this mechanism allows the execution of events in a perfectly deterministic manner. We know precisely the end and the start of an event at any moment whatever the frequency of execution, this under conditions that the event is a multiple of 2 compared to F ₀ , and the duration of the event .

In a system comprising several items of equipment, there may be several interactions between the items of equipment which need to be synchronized and executed at specific times. Let us take the example of two equipments EQ-i and EQ ₂ which need to exchange information. The first device EQ1 requires a certain amount of information coming from the second device EQ2 to perform its calculations, and vice versa. In figure 4, actions 1, 2 and 3 correspond to the first EQ-i device and actions 4 and 5 correspond to the second EQ _{2 device} . In the order of priorities, we see that the task T3 must be executed after the transmission of the message Mi. Therefore, the scheduler will ensure that in time, the execution of the tasks is as follows:

The transmission of the message Mi from the first equipment EQ-i to the second equipment EQ ₂ , then EQ-i can perform the tasks Ti and T ₂ ,

The second equipment EQ ₂ can send information to the first equipment EQ1 and finally the second equipment EQ ₂ will perform the task T3. The scheduler according to the invention therefore makes it possible to plan the events of several interconnected and interdependent equipment items.

The event scheduler according to the invention has the following advantages in particular: the management of the tasks of a microprocessor and of the communications in a deterministic manner, without having recourse to a management of the priorities of the interrupts. The tasks are executed in a precise order so as never to have two events running at the same time and without interrupting the execution of an event or a task,

- 100% use of the bandwidth is possible, in the absence of margin to provide for the management of possible collisions,

- the synchronous operation of several devices allows the use of the entire bandwidth, because there is no margin to be provided for the management of collisions, in normal operation of the system,

- the communication and the management of the tasks are organized temporally so as to make all the equipment of the network interact in a synchronized manner and without any interruption.

Claims

1. Method for temporally distributing the events to be transmitted in an initial time window Ti = [t ₀ , t _max ], said events being executed by a first microprocessor (1), the time distribution being carried out by a programmable device (2) characterized in that it comprises at least the following steps:

- identify for each event Ei, E _j , its execution frequency Fi, F _j , according to frequencies multiples of two and the duration Ti, T _j , of execution of an event,

- from the time availability, the size of an event and its admissible frequency, calculate for each future event E _j to be executed and for each of the n occurrences of said event in the initial time window, a time offset value dt such as t ₀ + dti (E _j ), t ₀ + dt ₂ (E _j ), t ₀ + dt ₃ (E _j ), ... t ₀ + dt _n (E _j ) corresponding to the temporal positioning of the future event E _j compared to the start time to in the initial time window,

- execute the event E _j and check whether the execution time of the event E _j by the microprocessor, T _jmicro conforms to the execution time T _jFPGA expected in the programmable device (2).

2. Method according to claim 1, characterized in that it takes into account the priority associated with the events to be executed in a time window to determine the times of execution of each of these events.

3. System for temporally distributing the events to be transmitted in an initial time window T i = [to,] characterized in that it comprises at least the following elements:

- a programmable device (2) comprising a shared memory (5) and an event scheduler (7),

- said scheduler (7) is adapted to

determine the execution times of at least two events in the initial time window T i = [t ₀ , t _max ], taking into account the time availability T _r remaining in the initial time window T, after the insertion of d '' a first event, based on the time availability, the size of a future event and of its admissible frequency, to calculate for each future event E ₂ to execute a time offset value dt corresponding to the temporal positioning of the future event E ₂ with respect to the start time t ₀ in the initial time window and to check whether the execution time of the event E ₂ by the microprocessor, T ₂ micro conforms to the execution time T ₂ FPGA,

- a first microprocessor (1) configured to execute the events stored in a shared memory (3), on receipt of an interrupt command INT sent by said device (2) and to transmit the execution time of an event to the scheduler (7).

4. System according to claim 3, characterized in that the scheduler is configured to calculate the remaining time availability in each of the n windows generated by the positioning of the event executed n times in the initial time window.

5. System according to one of claims 3 or 4 characterized in that the programmable device is of the FPGA type (Field Programmable Gâte Array).

6. System according to one of claims 3 to 5 characterized in that it comprises at least a first equipment EQ-i and at least a second equipment EQ ₂ synchronized and exchanging data.