WO2020172994A1

WO2020172994A1 - Display panel and detection method therefor

Info

Publication number: WO2020172994A1
Application number: PCT/CN2019/085632
Authority: WO
Inventors: 蒙艳红; 江志雄
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2019-02-27
Filing date: 2019-05-06
Publication date: 2020-09-03
Also published as: CN109709734A

Abstract

Provided is a display panel, comprising: an array substrate (10); a color resist layer (20) arranged above the substrate (10); a buffer layer (30) arranged above the color resist layer (20); a thin-film transistor (40) arranged above the buffer layer (30); a passivation layer (50) arranged above the thin-film transistor (40), wherein the passivation layer (50) is provided with an opening; a first transparent electrode layer (60) arranged above the passivation layer (50) and conformally covering the side wall and the bottom of the opening of the passivation layer (50), wherein the thin-film transistor (40) is electrically connected to the first transparent electrode layer (60) by means of the opening; a liquid crystal layer (70) arranged above the first transparent electrode layer (60); and a color filter substrate (80) arranged above the liquid crystal layer (70). The design of a large excavated hole on a color filter comprising a color resist is avoided, thereby improving the aperture ratio.

Description

Display panel and its detection method

Technical field

The present invention relates to a display panel, in particular to a display panel with a high aperture ratio.

Background technique

At present, the common bottom grid structure (Bottom gate) thin-film transistor and color filter The process of on array, TFT+COA) is shown in Figure 1. In the schematic diagram of the conventional display panel 1 shown in FIG. 1, on the display panel 1 of the glass substrate 10', in order to realize the overlap between the transparent electrode (ITO) 60' and the source drain (S/D), The color film (CF) 20' including color resistance (R/G/B) is digged to form an opening (shown by the arrow in Figure 1). The usual color film (CF) 20' has an opening (shown by the arrow in Figure 1). The size shown) is 30um*30um. Such a large opening greatly reduces the aperture ratio in the panel design.

technical problem

In order to solve the problems in the prior art, there is an urgent need for a display panel with a high aperture ratio. By using a new type of array on CF backplane manufacturing method, avoiding the problem of color resistance (R/G/ B) The color film (CF) adopts a large hole design to increase the aperture ratio.

Technical solutions

In order to achieve the above objective, the present invention provides a display panel, which includes: an array substrate; a color resist (RGB) layer disposed on the substrate; a buffer layer disposed on the color resist layer; a thin film Transistor (thin-film transistor, TFT), configured on the buffer layer; a passivation (PV) layer, configured on the thin film transistor and the passivation layer has an opening; a first transparent electrode layer, configured On the passivation layer, conformally cover the sidewalls and bottom of the opening of the passivation layer, wherein the thin film transistor and the first transparent electrode layer are electrically connected through the opening A liquid-crystal display (LCD) layer is disposed on the first transparent electrode layer; and a color filter (CF) substrate is disposed on the liquid crystal layer.

According to an embodiment of the present invention, in the display panel, the thin film transistor includes: a gate (G) is disposed on the array substrate; a gate insulating (gate insulating, IG) layer disposed on the gate and the array substrate; a semiconductor layer disposed on the gate insulating layer; and a source drain (source The drain (SD) layer includes a source (S) and a drain (Drain, D), and the source and the drain cover both ends of the semiconductor layer.

According to an embodiment of the present invention, the display panel further includes: a second transparent electrode layer disposed under the color filter substrate.

According to an embodiment of the present invention, the display panel further includes: a black matrix (BM) layer disposed between the color filter substrate and the second transparent electrode layer.

According to an embodiment of the present invention, in the display panel, the array substrate and the color filter substrate are each independently a glass substrate.

According to an embodiment of the present invention, in the display panel, the buffer layer includes at least one of silicon oxide and silicon nitride.

According to an embodiment of the present invention, the display panel further includes: an etch stop layer (ESL) disposed on the thin film transistor, and the opening further penetrates the etch stop layer.

According to an embodiment of the present invention, in the display panel, the size of the opening is 10um*10um to 8um*8um, preferably 8um*8um to 6um*6um, most preferably 6um*6um.

According to an embodiment of the present invention, in the display panel, the first transparent electrode layer and the second transparent electrode each independently include at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), Indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), tin oxide (TiO2), zinc oxide (ZnO), indium oxide (In2O3), and gallium oxide (Ga2O3).

According to an embodiment of the present invention, the display panel further includes: a photo spacer (PS) disposed between the array substrate and the color filter substrate.

According to an embodiment of the present invention, in the display panel, the semiconductor layer includes an amorphous silicon (a-Si).

Beneficial effect

Based on the above, the purpose of the present invention is to provide a display panel with a high aperture ratio. By using a new type of array on CF backplane manufacturing method, it avoids the problem of color resistance (R/G/B). ) The color film (CF) adopts a large hole design to increase the aperture ratio.

Description of the drawings

In order to explain the embodiments or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are merely inventions For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

Figure 1 is a schematic diagram of a conventional display panel.

FIG. 2 is a schematic diagram of a display panel according to an embodiment of the invention.

The best mode of the invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that the present invention can be implemented. The directional terms mentioned in the present invention, such as [vertical], [horizontal], [top], [bottom], [front], [back], [left], [right], [inside], [outside], [Side], etc., only refer to the direction of the attached drawings. Therefore, the directional terms used are used to describe and understand the present invention, rather than to limit the present invention. In the figure, units with similar structures are indicated by the same reference numerals.

The present invention provides a display panel with a high aperture ratio. The array on the color film CF) backplane manufacturing method avoids the use of large-cut holes on the color film (CF) including color resist (R/G/B), thereby increasing the aperture ratio.

FIG. 2 is a schematic diagram of a display panel according to an embodiment of the invention. Specifically, as shown in FIG. 2, the present invention provides a display panel 2, an array substrate 10; a color resist (RGB) layer 20 disposed on the array substrate 10; a buffer layer 30 disposed on the color On the resist layer 20; a thin-film transistor (TFT) 40 is disposed on the buffer layer 30; a passivation (PV) layer 50 is disposed on the thin-film transistor 40 and The passivation layer 50 has an opening (shown by the thick arrow in FIG. 2); a first transparent electrode layer 60 is disposed on the passivation layer 50 to conformally cover the passivation layer 50 The side walls and bottom of the opening (shown by the thick arrow in FIG. 2), wherein the thin film transistor 40 and the first transparent electrode layer 60 are electrically connected through the opening (shown by the thick arrow in FIG. 2) A liquid crystal (liquid-crystal display, LCD) layer 70 is configured on the first transparent electrode layer 60; and a color filter (CF) substrate 80 is configured on the liquid crystal layer 70.

Compared with the traditional COA process shown in FIG. 1, in the new process method shown in FIG. 2, since the production of the color resist (RGB) layer 20 is completed in the first step of the process, the transparent electrode layer (for example When the ITO) and the drain are overlapped, there is no need to pass through the color resist layer 20, but only by etching the passivation layer 50. Therefore, in the layout design of the panel, the design space for the opening of the excellent barrier layer can be saved, thereby greatly improving the opening ratio of the panel, which is of great significance for the development of high-resolution panels.

Compared with the 30um*30um color film (CF) opening of the traditional COA process in Figure 1, in the display panel 2 of Figure 2, a new type of color film on the array (array on CF) process, the opening can be reduced to 10um*10um to 8um*8um, preferably 8um*8um to 6um*6um, more preferably 6um*6um.

In one embodiment, as shown in FIG. 2, the thin film transistor 40 has a bottom gate (Bottom Gate) structure, and includes: a gate (G) G is disposed on the array substrate 10; An insulating (gate insulating, IG) layer IG is disposed on the gate G and the array substrate 10; a semiconductor layer 40a is disposed on the gate insulating layer IG; and a source drain (source The drain (SD) layer includes a source (S) S and a drain (D) D. The source S and the drain D cover both ends of the semiconductor layer 40a. In other embodiments, the thin film transistor may also have a top gate structure.

As shown in FIG. 2, according to an embodiment of the present invention, the display panel 1 further includes: a second transparent electrode layer 90 disposed under the color filter substrate 80; and a light shielding (black matrix, BM) layer BM is disposed 90 between the color filter substrate 80 and the second transparent electrode layer.

According to an embodiment of the present invention, in the display panel, the array substrate and the substrate 80 are each independently a glass substrate.

According to an embodiment of the present invention, in the display panel, the buffer layer 20 includes at least one of silicon oxide and silicon nitride. The buffer layer 30 can realize the transition between the color group 20 and the thin film transistor 40. The thickness of the buffer layer 20 is 2000Å to 3000Å, preferably 1000Å to 2000Å.

Referring to FIG. 2, the display panel 1 may further include: an etch stop layer (ESL) 100, which is disposed on the thin film transistor 40, and the opening (shown by the thick arrow in FIG. 2) is more through Through the etch stop layer 100.

2, according to an embodiment of the present invention, the display panel further includes: a photo spacer (PS) 110 disposed between the array substrate 10 and the color filter substrate 80.

It can be seen from the above that the present invention provides a display panel with a high aperture ratio, with a novel color film array (array On CF) backplane manufacturing method, avoiding the use of large digging design on color film (CF) including color resistance (R/G/B), thereby increasing the aperture ratio.

In summary, although the present invention has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various modifications without departing from the spirit and scope of the present invention. Such changes and modifications, therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims

A display panel, including;

An array of substrates;

A color resist (RGB) layer disposed on the substrate;

A buffer layer disposed on the color resist layer, wherein the buffer layer includes at least one of silicon oxide and silicon nitride;

A thin-film transistor (TFT) disposed on the buffer layer;

A passivation (passivation, The PV) layer is disposed on the thin film transistor and the passivation layer has an opening, wherein the size of the opening is 10um*10um to 6um*6um;

A first transparent electrode layer is disposed on the passivation layer to conformally cover the sidewall and bottom of the opening of the passivation layer, wherein the thin film transistor and the first transparent electrode layer Electrically connected by the opening;

An etch stop layer (ESL) is disposed on the thin film transistor, and the opening further penetrates the etch stop layer;

A liquid crystal (liquid-crystal display, LCD) layer, disposed on the first transparent electrode layer; and

Color film filter, CF) substrate, arranged on the liquid crystal layer.
The display panel according to claim 1, wherein the thin film transistor comprises:

A gate (gate, G) Disposing on the array substrate;

A gate insulating (IG) layer disposed on the gate and the array substrate;

A semiconductor layer disposed on the gate insulating layer; and

A source drain (SD) layer includes a source (S) and a drain (D), the source and the drain cover both ends of the semiconductor layer .
The display panel according to claim 1, further comprising:

A second transparent electrode layer is disposed under the color filter substrate.
The display panel according to claim 7, further comprising:

Black matrix, BM) layer, disposed between the color filter substrate and the second transparent electrode layer.
4. The display panel of claim 1, wherein the array substrate and the color filter substrate are each independently a glass substrate.
The display panel according to claim 1, further comprising:

An etch stop layer (ESL) is disposed on the thin film transistor, and the opening further penetrates the etch stop layer.
The display panel of claim 1, wherein the first transparent electrode layer comprises at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide ( IGZO), tin oxide (TiO 2 ), zinc oxide (ZnO), indium oxide (In 2 O 3 ), and gallium oxide (Ga 2 O 3 ).
2. The display panel of claim 1, further comprising: a photo spacer (PS) disposed between the array substrate and the color filter substrate.
A display panel, including;

An array of substrates;

A color resist (RGB) layer disposed on the substrate;

A buffer layer disposed on the color resist layer;

A thin-film transistor (TFT) disposed on the buffer layer;

A passivation (passivation, The PV) layer is disposed on the thin film transistor and the passivation layer has an opening;

A first transparent electrode layer is disposed on the passivation layer to conformally cover the sidewall and bottom of the opening of the passivation layer, wherein the thin film transistor and the first transparent electrode layer Electrically connected by the opening;

A liquid crystal (liquid-crystal display, LCD) layer, disposed on the first transparent electrode layer; and

Color film filter, CF) substrate, arranged on the liquid crystal layer.
9. The display panel of claim 9, wherein the thin film transistor comprises:

A gate (gate, G) Disposing on the array substrate;

A gate insulating (IG) layer disposed on the gate and the array substrate;

A semiconductor layer disposed on the gate insulating layer; and

A source drain (SD) layer includes a source (S) and a drain (D), the source and the drain cover both ends of the semiconductor layer .
9. The display panel of claim 9, further comprising:

A second transparent electrode layer is disposed under the color filter substrate.
The display panel according to claim 11, further comprising:

Black matrix, BM) layer, disposed between the color filter substrate and the second transparent electrode layer.
9. The display panel of claim 9, wherein the array substrate and the color filter substrate are each independently a glass substrate.
9. The display panel of claim 9, wherein the buffer layer includes at least one of silicon oxide and silicon nitride.
9. The display panel of claim 9, further comprising:

An etch stop layer (ESL) is disposed on the thin film transistor, and the opening further penetrates the etch stop layer.
9. The display panel of claim 9, wherein the opening size of the groove is 10um*10um to 6um*6um.
The display panel of claim 9, wherein the first transparent electrode layer comprises at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide ( IGZO), tin oxide (TiO 2 ), zinc oxide (ZnO), indium oxide (In 2 O 3 ), and gallium oxide (Ga 2 O 3 ).
9. The display panel of claim 9, further comprising: a photo spacer (PS) disposed between the array substrate and the color filter substrate.