WO2020168505A1 - Procédé et appareil de planification de tâches logicielles parmi de multiples processeurs - Google Patents

Procédé et appareil de planification de tâches logicielles parmi de multiples processeurs Download PDF

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Publication number
WO2020168505A1
WO2020168505A1 PCT/CN2019/075659 CN2019075659W WO2020168505A1 WO 2020168505 A1 WO2020168505 A1 WO 2020168505A1 CN 2019075659 W CN2019075659 W CN 2019075659W WO 2020168505 A1 WO2020168505 A1 WO 2020168505A1
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coroutine
group
processor
fusion
priority
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PCT/CN2019/075659
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English (en)
Chinese (zh)
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曹雷
王凯
鲁婷
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华为技术有限公司
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Priority to PCT/CN2019/075659 priority Critical patent/WO2020168505A1/fr
Priority to CN201980009713.5A priority patent/CN111837104B/zh
Publication of WO2020168505A1 publication Critical patent/WO2020168505A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

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  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a method and device for scheduling software tasks among multiple processors.
  • a communication system such as a processor in a 5G communication system, can run one or more threads at the same time.
  • OS operating system
  • traditional threads can satisfy the normal operation of traditional services.
  • SMP Symmetrical Multi-Processing
  • CR Coroutine
  • a group of strongly related coroutines can be divided into a coroutine group (Coroutine Group, CRG).
  • CRG Coroutine Group
  • a core is a processor, such as a central processing unit (CPU)
  • CPU central processing unit
  • the CPU resources are fully utilized, and each CPU runs a different CRG to meet the performance requirements of 5G communication;
  • multiple CRGs can be migrated to one CPU.
  • each circle represents a coroutine.
  • the SMP system includes four CPUs.
  • CRG0 runs on CPU2 and CRG1 runs on CPU3.
  • CRG0 and CRG1 have the same priority, and the coroutine A/ in CRG0 and CRG1
  • the priority of B is higher than that of coroutine C/D
  • the priority of coroutine C/D is higher than that of coroutine E/F.
  • the CRG1 in the CPU3 can be migrated to the CPU2, and the migration is also called switching.
  • an existing scheduling scheme can first schedule CRG0 and then schedule CRG1, but this will cause the high-priority coroutine A/B in CRG1 to be postponed to the lower priority coroutine in CRG0 Running after E/F does not meet business timing requirements and affects basic business functions.
  • scheduling can be performed based on a preset time sequence, but this scheme will cause the coroutines in CRG0 and CRG1 to run alternately between coroutine groups, which reduces the switching efficiency.
  • the embodiments of the present application provide a method and device for scheduling software tasks among multiple processors, which can improve the scheduling efficiency of software tasks and reduce system power consumption while meeting service timing requirements.
  • the first aspect of the embodiments of the present application provides a method for scheduling software tasks among multiple processors.
  • the method includes: acquiring a first coroutine group of a second processor among the multiple processors, and the first coroutine group
  • the program group is a group of coroutines migrated from the second processor to the first processor of the plurality of processors; the first coroutine group and the second coroutine group of the first processor are merged to obtain the fusion protocol Process group; wherein the fusion process group includes a plurality of processes including at least one first process in the first process group and at least one second process in the second process group, each The coroutines have a priority, and the multiple coroutines are sorted according to the priority of the multiple coroutines in the fusion coroutine group; when the fusion coroutine group is executed, the multiple coroutines are executed according to the sequence.
  • the fusion coroutine group is obtained by fusing the first coroutine group and the second coroutine group, and the fusion coroutine group is executed according to the priority order of multiple coroutines in the fusion coroutine group, so as to meet the business timing requirements ; And by merging multiple coroutine groups into a converged coroutine group for scheduling, the scheduling efficiency of software tasks can be improved and system power consumption can be reduced.
  • each coroutine group has a coroutine group priority; the above-mentioned fusion coroutine group, the above-mentioned first coroutine group, and the above-mentioned second coroutine group have the same first The priority of the coroutine group. Based on this solution, the first coroutine group and the second coroutine group with the same priority of the coroutine group can be merged to obtain a converged coroutine group.
  • the method further includes: determining, according to the priority of the first coroutine group, to support the integration of the first coroutine group and the second coroutine group; or, according to the first identifiers of the first coroutine group and the second coroutine group It is determined to support the integration of the first coroutine group and the second coroutine group. Based on this solution, it is possible to determine whether to support the fusion of the first coroutine group and the second coroutine group according to the priority of the coroutine group or the first identifier carried by the coroutine group.
  • the foregoing method further includes: acquiring a third coroutine group of the second processor, the third coroutine group being from the second processor
  • the processor migrates to the coroutine group of the first processor; the priority of the second coroutine group of the third coroutine group is different from the priority of the first coroutine group of the converged coroutine group, or the third coroutine group
  • the first identifier of the process group does not support fusion; the fusion process group and the third process group are executed according to the priority of the second process group and the priority of the first process group. Based on this solution, the third coroutine group and the converged coroutine group that do not support convergence can be scheduled according to the priority order of the coroutine group.
  • the multiple goroutines included in the fusion goroutine group share the same fusion stack space, task control block, and context information. Based on this solution, since multiple coroutines in the fusion coroutine group share the same fusion stack space, task control block, and context information, when the fusion coroutine group is executed in the order of priority of the multiple coroutines in the fusion coroutine group, yes Switching between different coroutines in a coroutine group is compared with switching between different coroutine groups in the prior art. In this embodiment, the switching time is shorter and the software task scheduling efficiency is higher.
  • the first coroutine group has a first stack space
  • the second coroutine group has a second stack space
  • the fusion coroutine group There is a fusion stack space
  • the fusion stack space is the same as the first stack space or the second stack space, or the fusion stack space is different from both the first stack space and the second stack space.
  • the stack space corresponding to the converged coroutine group can reuse the stack space corresponding to the first coroutine group or the second coroutine group, or a new stack space can be created for the converged coroutine group.
  • the foregoing method is executed by the first processor. Based on this solution, the first coroutine group and the second coroutine group can be merged through the first processor, and corresponding software tasks can be scheduled.
  • the foregoing method further includes: migrating the foregoing first goroutine group in the foregoing converged goroutine group At this time, the first coroutine group is migrated from the first processor to the third processor of the plurality of processors. Based on this solution, the first coroutine group and the second coroutine group can be managed separately at the granularity of the coroutine group.
  • the first coroutine group in the converged coroutine group can be The group re-migrates at the granularity of the coroutine group, without re-dividing multiple coroutine groups in the converged coroutine group, and can fully manage and utilize hardware resources.
  • the foregoing method further includes: migrating the foregoing first goroutine group in the foregoing converged goroutine group
  • the configuration information is used to instruct the first coroutine group to migrate from the first processor to the third processor among the plurality of processors; release the corresponding fusion coroutine group Fusion stack space.
  • a multi-core processing device includes multiple processors.
  • the multiple processors include a first processor and a second processor; the first processor is configured to : Obtain a first coroutine group of a second processor in the plurality of processors, where the first coroutine group is a coroutine group migrated from the second processor to the first processor of the plurality of processors; fusion The first coroutine group and the second coroutine group of the first processor to obtain a converged coroutine group; wherein, the converged coroutine group includes a plurality of coroutines, and the plurality of coroutines include those in the first coroutine group At least one first coroutine and at least one second coroutine in the second coroutine group, each coroutine has a priority, and the multiple coroutines are selected according to the priority of the multiple coroutines in the fusion coroutine group Sorting; when the above-mentioned fusion coroutine
  • each coroutine group has a coroutine group priority; the above-mentioned fusion coroutine group, the above-mentioned first coroutine group, and the above-mentioned second coroutine group have the same first The priority of the coroutine group.
  • the first processor is further configured to determine, according to the priority of the first coroutine group, to support the integration of the first coroutine group and the aforementioned The second coroutine group; or, according to the first identification of the first coroutine group and the second coroutine group, it is determined to support the integration of the first coroutine group and the second coroutine group.
  • the first processor is further configured to: obtain a third coroutine group of the second processor, and the third coroutine group To migrate from the second processor to the first processor coroutine group; the second coroutine group priority of the third coroutine group is different from the first coroutine group priority of the converged coroutine group, or,
  • the first identifier of the third goroutine group does not support fusion; the fusion goroutine group and the third goroutine group are executed according to the priority of the second goroutine group and the priority of the first goroutine group.
  • the multiple goroutines included in the fusion goroutine group share the same fusion stack space, task control block, and context information.
  • the first coroutine group has a first stack space
  • the second coroutine group has a second stack space
  • the fusion coroutine group There is a fusion stack space, which is the same as the first stack space or the second stack space, or the fusion stack space is different from the first stack space and the second stack space.
  • the first processor is the main processor, the first processor is also used to migrate the first processor in the converged coroutine group.
  • the first coroutine group in the fusion coroutine group is migrated from the first processor to the third processor of the plurality of processors.
  • the multiple processors further include a third processor, and if the first processor is a slave processor, the first processor, It is also used to: when migrating the first coroutine group in the converged coroutine group, receive configuration information sent by the main processor, where the configuration information is used to instruct the first coroutine group to migrate from the first processor to the multiple The third processor in each processor; releases the fusion stack space corresponding to the aforementioned fusion coroutine group.
  • a third aspect of the embodiments of the present application provides an apparatus for scheduling software tasks among multiple processors.
  • the apparatus includes: an obtaining unit configured to obtain a first coroutine group of a second processor among the multiple processors ,
  • the first coroutine group is a coroutine group that migrates from the second processor to the first processor of the plurality of processors;
  • the processing unit is configured to merge the first coroutine group and the first processor The second coroutine group to obtain the converged coroutine group; wherein the converged coroutine group includes multiple coroutines, and the multiple coroutines include at least one first coroutine in the first coroutine group and the second coroutine group At least one second goroutine of, each goroutine has a priority, and the multiple goroutines are sorted according to the priority of the multiple goroutines in the aforementioned fusion goroutine group; when the aforementioned fusion goroutine group is executed, according to This sorting executes the multiple coroutines described above.
  • each coroutine group has a coroutine group priority; the aforementioned fusion coroutine group, the aforementioned first coroutine group, and the aforementioned second coroutine group have the same first The priority of the coroutine group.
  • the foregoing processing unit is further configured to determine, according to the priority of the foregoing first coroutine group, to support the integration of the foregoing first coroutine group and the foregoing second coroutine group.
  • the acquisition unit is further configured to acquire a third coroutine group of the second processor, and the third coroutine group is from the aforementioned
  • the second processor migrates to the first processor coroutine group; the second coroutine group priority of the third coroutine group is different from the first coroutine group priority of the converged coroutine group, or the third coroutine group
  • the first identifier of the coroutine group does not support fusion; the processing unit is further configured to execute the fusion coroutine group and the third coroutine group according to the priority of the second coroutine group and the priority of the first coroutine group group.
  • the multiple goroutines included in the fusion goroutine group share the same fusion stack space, task control block, and context information.
  • the first coroutine group has a first stack space
  • the second coroutine group has a second stack space
  • the fusion coroutine group There is a fusion stack space
  • the fusion stack space is the same as the first stack space or the second stack space, or the fusion stack space is different from the first stack space and the second stack space.
  • the processing unit is also used for migrating the first protocol in the converged protocol group.
  • the first coroutine group in the fusion coroutine group is migrated from the first processor to the third processor of the plurality of processors.
  • the acquisition unit is also used for migrating the first protocol in the converged protocol group.
  • the configuration information sent by the main processor is received, and the configuration information is used to instruct the first coroutine group to migrate from the first processor to the third processor of the plurality of processors; the processing unit further Used to release the fusion stack space corresponding to the aforementioned fusion coroutine group.
  • a computer storage medium stores computer program code.
  • the processor executes the first aspect or the first aspect. The method for scheduling software tasks among multiple processors described in any of the possible implementation manners.
  • the fifth aspect of the embodiments of the present application provides a computer program product that stores computer software instructions executed by the above-mentioned processor, and the computer software instructions include a program for executing the solution described in the above-mentioned aspect.
  • the sixth aspect of the embodiments of the present application provides a device that exists in the form of a chip product.
  • the structure of the device includes a processor and a memory.
  • the memory is used to couple with the processor and store the necessary programs of the device. Instructions and data, the processor is used to execute program instructions stored in the memory, so that the device performs the function of the device for scheduling software tasks among multiple processors in the above method.
  • Figure 1 is a schematic diagram of a scheduling method provided in the prior art
  • FIG. 2 is a schematic structural diagram of an SMP system provided by an embodiment of this application.
  • FIG. 3 is a schematic flowchart of a method for scheduling software tasks among multiple processors according to an embodiment of the application
  • FIG. 4 is an application schematic diagram of a method for scheduling software tasks among multiple processors provided by an embodiment of the application
  • FIG. 5 is an application schematic diagram of another method for scheduling software tasks among multiple processors provided by an embodiment of the application.
  • FIG. 6 is a schematic flowchart of another method for scheduling software tasks among multiple processors according to an embodiment of the application.
  • FIG. 7 is a schematic flowchart of another method for scheduling software tasks among multiple processors according to an embodiment of the application.
  • FIG. 8 is an application schematic diagram of another method for scheduling software tasks among multiple processors provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of the composition of an apparatus for scheduling software tasks among multiple processors according to an embodiment of the application.
  • At least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • the lightweight scheduling of the coroutine may be used, and the scheduling of the coroutine is completely controlled by the user.
  • software tasks can be scheduled among multiple processors to improve operating efficiency and reduce system power. Consumption.
  • the software task may be a communication task, such as a 5G communication task.
  • the embodiment of the present application provides a method for scheduling software tasks among multiple processors, which can be applied to a Symmetrical Multi-Processing (SMP) system, but is not limited to such a system.
  • SMP Symmetrical Multi-Processing
  • the SMP is used in the following text
  • the system is introduced as an example.
  • the SMP system includes a plurality of processors, the plurality of processors are assembled on a computer, and the memory subsystem and bus structure are shared among the plurality of processors.
  • the computer can be a communication terminal, tablet computer, desktop, laptop, notebook computer, Ultra-mobile Personal Computer (UMPC), handheld computer, netbook, personal digital assistant (Personal Digital Assistant, PDA),
  • UMPC Ultra-mobile Personal Computer
  • PDA Personal Digital Assistant
  • the specific form of the computer is not particularly limited, and the computer is used as a communication terminal as an example for introduction.
  • the SMP system can be a chip, a chipset, or a circuit board, and can run necessary computer software programs and schedule software tasks among multiple processors. Each processor can be a core.
  • FIG. 2 is a schematic structural diagram of an SMP system provided by an embodiment of the application.
  • the SMP system 200 includes a hardware layer and a software layer.
  • the hardware layer includes multiple processors 201, a memory 202, a bus 203, etc.
  • the software layer includes an operating system 204.
  • the processor 201 is a core component of the SMP system 200, and is used to run the operating system 204 of the SMP system 200 and applications on the SMP system 200 (including system applications and third-party applications).
  • the multiple processors 201 in the SMP system 200 shown in FIG. 2 have no primary and secondary distinctions (except for startup and initialization). Each processor 201 dynamically schedules processes from the process ready queue for execution, and interrupt requests are also equal. The probability is dynamically allocated to a certain processor 201, which provides interrupt service.
  • the multiple processors 201 included in the SMP system 200 control the collaborative work between different processors through an operating system.
  • One processor 201 of the multiple processors 201 is the main processor, and the other processors are Slave processor, the master processor can manage other slave processors.
  • the main processor can migrate multiple coroutine groups to one processor according to a preset strategy.
  • the processor 201 may specifically be a central processing unit (CPU), which can implement or execute various exemplary logical blocks and processes described in conjunction with the content disclosed in the embodiments of the present application. It can include different modules and circuits.
  • CPU central processing unit
  • Each processor may also be a combination that implements computing functions, for example, including one or more microprocessor combinations, DSP and microprocessor combinations, etc., and may also be a specific processor, such as a microprocessor.
  • the embodiment of the present application only takes the processor including a CPU as an example for description, but in fact, each processor may also include a digital signal processor, a microprocessor, a microcontroller, or a neural network processor.
  • the SMP system 200 includes multiple CPUs, and each CPU includes one or more physical cores (Core).
  • Each Core can be a digital signal processor, a microprocessor, a microcontroller, or a neural network processor. .
  • the embodiment of the present application does not limit the number of CPUs included in the SMP system 200 and the number of physical cores included in each CPU. It is understandable that FIG. 2 is only an exemplary structural diagram, and the number of Cores included in each CPU may be the same or different, which is not limited in the embodiment of the present application.
  • the memory 202 can be used to store software programs and software modules, and the processor 201 executes various functional applications and data processing of the SMP system 200 by running the software programs and modules stored in the memory 202.
  • the memory 202 may include one or more computer-readable storage media.
  • the memory 202 includes a storage program area and a storage data area.
  • the storage program area can store an operating system, an application program required by at least one function, etc., for example, can store the scheduling between multiple processors provided in the embodiments of the present application.
  • the storage data area can store data created by the SMP system 200 and the like.
  • the memory 202 includes a stack space corresponding to each coroutine group, and each stack space is used to store local variables and local arrays generated when each coroutine group is scheduled.
  • the memory 202 may specifically include a volatile memory (volatile memory), for example, a random-access memory (RAM); the memory may also include a non-volatile memory (non-volatile memory) , Flash memory (flash memory), hard disk (HDD) or solid-state drive (SSD); the memory may also include a combination of the above-mentioned types of memory.
  • the bus 203 is a common communication trunk for transmitting information between various functional components of the computer.
  • the computer bus can be divided into a data bus, an address bus and a control bus, which are used to transmit data, data address, and control.
  • the signal and bus can also have the functions of the above multiple buses at the same time, which is not limited in this embodiment.
  • multiple processors 201 included in the SMP system 200 share a bus 203.
  • Operating System 204 is a computer program that manages and controls computer hardware and software resources. It is the most basic system software that runs directly on the "bare metal" and is used to support other software, such as various applications. run.
  • the operating system in the embodiments of the present application may be various operating systems, for example, Windows operating system, Linux operating system, iOS operating system, Android open source operating system, etc. It should be noted that multiple processors 201 included in the SMP system 200 in the embodiment of the present application run the same operating system. Alternatively, the solution may also support multiple operating systems, which is not limited in this embodiment.
  • FIG. 2 is only an exemplary illustration, and in practical applications, the SMP system 200 may include more or less components than those shown in FIG. 2.
  • the SMP system 200 may also include a user interface to support interaction and information exchange between the system and users, or the SMP system 200 may also include a communication interface to support communication between the terminal and other terminals, servers, and networks;
  • the structure shown in FIG. 2 does not constitute any limitation to the SMP system provided by the embodiment of the present application.
  • Coroutine It is a lightweight thread in user mode, and the scheduling of the coroutine is completely controlled by the user.
  • the coroutine has its own register context and stack. When the coroutine is scheduled to switch, save the register context and stack to other places. When switching back, restore the previously saved register context and stack. Directly operating on the stack basically has no kernel switching overhead, and you can access global variables without locking. , So the context switching is very fast.
  • a thread can include multiple coroutines.
  • Coroutine group a group of coroutines including multiple coroutines, and multiple coroutines in a coroutine group can satisfy preset rules.
  • the coroutines of a group of functions that are strongly related to the business can be divided into a coroutine group.
  • the embodiment of the present application does not limit the principle of dividing the coroutine group, and this is only an exemplary description. It is understandable that since the coroutine itself does not have an independent stack space and cannot be migrated in real time, by dividing multiple coroutines that meet the preset rules into a coroutine group, the coroutine group can be the same as a traditional task as a coroutine group.
  • the execution environment of the program has an independent stack space and supports real-time migration.
  • an embodiment of the present application provides a method for scheduling software tasks among multiple processors, which can meet business requirements. Timing requirements improve the scheduling efficiency of software tasks, reduce system power consumption, and fully manage and utilize hardware resources.
  • the method for scheduling software tasks among multiple processors provided in an embodiment of the present application may include steps S301-S303.
  • the first processor acquires the first coroutine group of the second processor.
  • the first coroutine group is the coroutine group of the first processor migrated from the second processor.
  • the first processor and the second processor may be processors in the SMP system 200 shown in FIG. 2.
  • obtaining the first coroutine group of the second processor by the first processor in step S301 may include: the first processor transfers the first coroutine group of the second processor The group is migrated from the second processor to the first processor, that is, the first processor configures the first coroutine group from the second processor to the first processor.
  • the main processor may modify the data structure binding relationship of the first coroutine group from binding with the second processor to binding with the main processor.
  • the first processor may be any processor in the SMP system 200 shown in FIG. 2. Processors other than the master processor in the SMP system 200 may be referred to as slave processors.
  • the goroutine group in one of the processors is the goroutine group run by the processor as a task.
  • the first goroutine group may include at least one The first coroutine, the multiple first coroutines in the first coroutine group are a group of coroutines satisfying preset rules.
  • the aforementioned first coroutine group has a first stack space, and the first stack space may be a stack space allocated for the first coroutine group during initialization, and the first stack space is used to store and schedule the first coroutine group. Local variables and local arrays, etc. generated by the coroutines in the program group.
  • the first processor may migrate one or more first coroutine groups in the second processor from the second processor to the first processor according to a preset strategy.
  • the embodiment of the present application is for the first coroutine
  • the number of groups is not limited.
  • the one or more first coroutine groups may be a coroutine group in a second processor, or a coroutine group in multiple second processors, that is, the main processor can process one or more second processors
  • the multiple first coroutine groups in the processor migrate to one or more other processors (first processors).
  • the first processor may migrate the first coroutine group of the second processor to the second processor.
  • One processor may migrate the first coroutine group of the second processor to the second processor.
  • the above-mentioned first processor migrating the first coroutine group of the second processor to the first processor may include: the first processor modifies the data structure relationship of the first coroutine group.
  • the first processor modifies the binding relationship of the first coroutine group. Before the binding relationship is modified, the first coroutine group is bound to the physical core of the second processor, and after the binding relationship is modified, the first coroutine The group is bound to the physical core of the first processor.
  • the SMP system 200 includes four processors, namely CPU0, CPU1, CPU2, and CPU3.
  • the four CPUs run the same operating system, and a circle represents a coroutine.
  • Any one of the four processors can be the main processor, and the first processor can migrate the first coroutine group (CRG0) running on CPU3 (second processor) to CPU2 (second processor) according to a preset strategy.
  • One processor It is understandable that only the second processor is used as one processor as an example.
  • the second processor may include multiple processors, that is, the first processor may combine each of the multiple second processors.
  • One or more first coroutine groups running on each processor are migrated to the first processor.
  • acquiring the first coroutine group of the second processor by the first processor in step S301 may include: the first processor receives the first coroutine group sent by the master processor. Configuration information, where the first configuration information is used to instruct the first coroutine group to migrate from the second processor to the first processor. That is, the main processor configures the first coroutine group from the second processor to the first processor. For example, the main processor can modify the data structure binding relationship of the first coroutine group from binding to the second processor. In order to bind with the first processor, the first processor receives the first configuration message, and then obtains the first coroutine group migrated to the first processor.
  • the main processor may be a processor in the SMP system 200 shown in FIG. 2.
  • the first processor merges the first coroutine group and the second coroutine group of the first processor to obtain a fused coroutine group.
  • the fusion coroutine group includes multiple coroutines, the multiple coroutines include at least one first coroutine in the first coroutine group and at least one second coroutine in the second coroutine group, and each coroutine has a priority, And multiple coroutines are sorted according to the priority of multiple coroutines in the fusion coroutine group.
  • the fusion of the first coroutine group and the second coroutine group of the first processor in step S302 to obtain the converged coroutine group refers to combining part or all of the first coroutine group and the second coroutine group
  • the coroutines are merged into a coroutine group (converged coroutine group) according to the priority order of the coroutines.
  • Multiple coroutines included in the fusion coroutine group share the same fusion stack space, task control block, and context information.
  • the fusion stack space is used to store the local variables and local arrays generated when the goroutines in the fusion goroutine group are run by the first processor.
  • the foregoing second coroutine group has a second stack space
  • the fusion coroutine group has a fusion stack space.
  • the fusion stack space can reuse the original stack space, and can also create a new stack space for the fusion coroutine group.
  • the merged stack space may be the same as the first stack space or the second stack space, or the merged stack space may also be different from both the first stack space and the second stack space. It is understandable that when the merged stack space is different from the first stack space and the second stack space, the merged stack space may be a stack space newly created by the first processor.
  • the above-mentioned first, second, and fused goroutine group have goroutine group priorities, and the first, second, and fused goroutine group may have the same first goroutine group, second goroutine group, and fused goroutine group.
  • the priority of a coroutine group may be any value between 1 and 255, and the priority of the coroutine group may be preset.
  • the priority of the coroutine group of CRG0 is 5 and the priority of the coroutine group of CRG2 is 5, the priority of the first coroutine group (CRG0) and the priority of the second coroutine group (CRG2) have The same priority of the first coroutine group, the priority of the first coroutine group is 5.
  • the method may further include: determining, according to preset conditions, to support the integration of the first coroutine group and the second coroutine group. Specifically, it can be determined to support the integration of the first coroutine group and the second coroutine group according to the priority of the first coroutine group; or, according to the first identification of the first coroutine group and the second coroutine group, it can be determined to support the integration of the first coroutine group.
  • the first identifier may be carried in the coroutine group. For example, the first identifier being 1 may indicate that the goroutine group supports fusion, and the first identifier being 0 may indicate that the goroutine group does not support fusion.
  • the specific form of the first identifier is not limited in the embodiment of this application.
  • step S302 if the first coroutine group and the second coroutine group have the same priority of the first coroutine group, it is determined that the first coroutine group and the second coroutine group support integration, and step S302 is executed;
  • the first identifiers of the first coroutine group and the second coroutine group are both 1, and it is determined that the first coroutine group and the second coroutine group support fusion, and step S302 is executed.
  • the CPU2 merges CRG0 and CRG2 according to the priority 5 of the first coroutine group.
  • the priority of the coroutine can be any value from 1 to 255, and the priority of the coroutine can be preset. The smaller the priority value, the higher the priority. If the priority of coroutine A is 3, the priority of coroutine B is 9, the priority of coroutine C is 15, the priority of coroutine D is 5, the priority of coroutine E is 10, and the priority of coroutine F is The priority is 17.
  • the priority order of the coroutines in the fusion coroutine group is: coroutine A- coroutine D- coroutine B- coroutine E- coroutine C- coroutine F.
  • S303 When the first processor executes the converged coroutine group, execute multiple coroutines according to the foregoing sequence.
  • the multiple coroutines included in the fusion coroutine group may be executed in the order of priority. For example, as shown in 5, it can be executed sequentially in the order of coroutine A-coroutine D-coroutine B-coroutine E-coroutine C-coroutine F.
  • multiple coroutines included in the fusion coroutine group share a fusion stack space, task control block, and context information. Therefore, when the fusion coroutine group is executed, it is equivalent to switching between different coroutines in a coroutine group, and there is no need to switch between different coroutine groups, which saves switching time and improves switching efficiency.
  • this embodiment performs scheduling by merging multiple coroutine groups into a converged coroutine group. Since the converged coroutine group corresponds to a converged stack space, it is executed in the priority order of multiple coroutines in the converged coroutine group. In the case of the multiple goroutines, switching between different goroutines in a goroutine group is performed. Compared with switching between different goroutine groups in the prior art, this embodiment can meet the business timing requirements while simultaneously, Improve the scheduling efficiency of software tasks and make full use of hardware resources.
  • the embodiment of the present application also provides a method for scheduling software tasks among multiple processors. As shown in FIG. 6, the method further includes steps S601-S602 after step S303. Step S301 is not shown in FIG. -S303.
  • the first processor acquires a third coroutine group of the second processor.
  • the third coroutine group is a coroutine group that migrates from the second processor to the first processor.
  • the priority of the second coroutine group of the third coroutine group is different from the priority of the first coroutine group of the fusion coroutine group, or the first identifier of the third coroutine group does not support fusion, for example, the third coroutine group
  • the first ID of the group is 0. That is, the third coroutine group is a coroutine group that does not support integration.
  • the priority of the first coroutine group of the fusion coroutine group is 5
  • the priority of the second coroutine group of the third coroutine group CRG1 is 8
  • the priority of the second coroutine group of the third coroutine group CRG1 is 8.
  • the process group priority 8 is different from the first coroutine group priority 5 of the fusion coroutine group.
  • obtaining the third coroutine group of the second processor by the first processor in step S601 may include: the first processor transfers the third coroutine group of the second processor The group migrates from the second processor to the first processor, that is, the first processor configures the third coroutine group from the second processor to the first processor, and the first processor can transfer the data of the third coroutine group The structural binding relationship is modified from binding with the second processor to binding with the first processor.
  • acquiring the third coroutine group of the second processor by the first processor in step S601 may include: the first processor receives the second processor sent by the master processor. Configuration information, where the second configuration information is used to instruct the third coroutine group to migrate from the second processor to the first processor. That is, the main processor configures the third coroutine group from the second processor to the first processor, and the main processor can modify the data structure binding relationship of the third coroutine group from binding with the second processor to The first processor is bound.
  • the first processor executes the fusion coroutine group and the third coroutine group according to the priority of the second coroutine group and the priority of the first coroutine group.
  • the first processor may execute the fusion coroutine group and the third coroutine group in the order of the priority of the second coroutine group and the priority of the first coroutine group from high to bottom.
  • scheduling may be performed according to the priority order of multiple coroutines in the converged coroutine group or the third coroutine group. For example, if the priority of coroutine A is 3, the priority of coroutine B is 9, the priority of coroutine C is 15, the priority of coroutine D is 5, the priority of coroutine E is 10, and the priority of coroutine E is 10. The priority of F is 17, the priority of coroutine X is 20, the priority of coroutine Y is 25, and the priority of coroutine Z is 30.
  • the fusion coroutine group can be scheduled first according to the priority of the coroutine group. Then schedule CRG1.
  • a fusion coroutine group is obtained by fusing multiple coroutine groups that meet preset conditions, and scheduling is performed based on the priority order of multiple coroutines in the fusion coroutine group, which will not meet the preset conditions.
  • the multiple coroutine groups of the conditions are scheduled according to the priority order of the coroutine groups, which can save handover time and improve handover efficiency.
  • the method for scheduling software tasks among multiple processors provided in the present application can satisfy business timing by taking multiple coroutine groups as a converged coroutine group and scheduling the converged coroutine group based on the priority of the coroutine Requirement; and when the priority scheduling fusion coroutine group is based on the coroutine, it is to switch between different coroutines in a coroutine group.
  • the switching time is shorter. The switching efficiency is higher, and the hardware resources can be fully managed and utilized.
  • the above method further includes steps S603-S604.
  • S603 When migrating the first coroutine group in the converged coroutine group, the main processor migrates the first coroutine group in the converged coroutine group from the first processor to the third processor.
  • the third processor may be the second processor, or may be any other processor different from the first processor, which is not limited in the embodiment of the present application.
  • the main processor determines to migrate the first coroutine group, for example, when the current business volume of the first processor is relatively large, in order to make full use of processor resources .
  • the main processor can migrate the first coroutine group from the first processor to the second processor, that is, the main processor configures the first coroutine group from the first processor to the second processor, for example, the main processor
  • the processor can unbind the first coroutine group with the physical core of the first processor, and bind the first coroutine group with the physical core of the second processor.
  • the first coroutine group and the second coroutine group are separately managed, but the above steps S302-S303 are only the first coroutine group And the second coroutine group is scheduled as a fusion coroutine group as a whole.
  • coroutine A, coroutine B, and coroutine C are still coroutines in CRG2
  • coroutine D, coroutine E, and coroutine F are still coroutines in CRG0.
  • CRG0 or CRG2 when CRG0 or When CRG2 is migrated to other processors, it can still be migrated according to the granularity of the coroutine group (CRG0 or CRG2), without the need for the business layer to re-divide multiple coroutines.
  • multiple coroutine groups that meet the preset conditions are scheduled as a coroutine group as a whole during scheduling, but when managing the multiple coroutine groups separately to manage each coroutine group, you can still The first coroutine group or the second coroutine group in the converged coroutine group is re-migrated at the granularity of the coroutine group, there is no need to re-divide multiple coroutine groups in the converged coroutine group, and the hardware resources can be fully managed and utilized.
  • the first processor releases the fusion stack space corresponding to the fusion coroutine group.
  • the fusion stack space corresponding to the fusion coroutine group is a stack space different from the first stack space and the second stack space, that is, the fusion stack space is a stack space newly created by the first processor.
  • the first processor may release the space of the fusion stack to save memory space. It is understandable that if the stack space corresponding to the fusion coroutine group reuses the original stack space, for example, the stack space corresponding to the fusion coroutine group is the first stack space or the second stack space, and the first coroutine group is migrated For other processors, there is no need to release the stack space corresponding to the fusion coroutine group, the stack space corresponding to the first coroutine group is still the first stack space, and the stack space corresponding to the second coroutine group is still the second stack space.
  • the method for scheduling software tasks among multiple processors provided in the present application can satisfy business timing by taking multiple coroutine groups as a converged coroutine group and scheduling the converged coroutine group based on the priority of the coroutine Requirement; and when the priority scheduling fusion coroutine group is based on the coroutine, it is to switch between different coroutines in a coroutine group.
  • the switching time is shorter. The switching efficiency is higher, and the hardware resources can be fully managed and utilized.
  • the embodiment of the present application may divide the computer into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 9 shows a possible structural schematic diagram of the apparatus 900 for scheduling software tasks among multiple processors involved in the foregoing embodiment.
  • the apparatus 900 may It is the first processor in the above embodiment or the software product run by the first processor or the combination of the processor and the software product, such as a processor 201 and an operating system 204 or an application program in FIG. 2 The combination between.
  • the apparatus 900 may include: an acquisition module 901 and a processing module 902.
  • the acquisition module 901 can be used to support the device 900 to perform S301 in FIG. 3 or S601 in FIG. 6; the processing module 902 can be used to support the device 900 to perform S302-S303 in FIG. 3, or S602 in FIG.
  • the foregoing device 900 may be any processor 201 or all or part of the operating system 204 in the SMP system 200 shown in FIG. 2, or a combination of the two.
  • This embodiment of the present application does not Qualify.
  • At least one unit in the device 900 can be implemented in a manner of software, hardware, or a combination of software and hardware. When any unit is implemented in software, it can be executed by the processor 201 in the previous embodiment corresponding to FIG. 2 and stored in the memory 202.
  • any unit is implemented in hardware, it can be located in any processor 201, specifically it can be an integrated circuit, circuit module, electronic component, processor, application specific integrated circuit (ASIC), or field programmable gate array (FPGA) And so on.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • an embodiment of the present application further provides an apparatus for scheduling software tasks among multiple processors.
  • the apparatus for scheduling software tasks among multiple processors includes : Processor 201.
  • the processor 201 is used to control and manage the actions of the device.
  • the processor 201 is used to support the device to execute S301-S303 in FIG. 3, or S601-S602 in FIG. 6, or S601-S601- in FIG. S604, and/or other processes used in the techniques described herein.
  • the device for scheduling software tasks among multiple processors can be any one of the processors in the SMP system 200 shown in FIG. 2, and the descriptions of all related content of the components involved in FIG.
  • the foregoing apparatus may further include a memory 202, and the memory 202 is configured to store computer program codes and data.
  • the structure of the apparatus for scheduling software tasks among multiple processors involved in the foregoing embodiment may further include a processor and an interface, and the processor and the interface communicate, and the processor is used to execute the embodiment of the present invention.
  • the processor may include at least one of a central processing unit (CPU), a digital signal processor (DSP), a microcontroller (MCU), or a microprocessor.
  • the embodiments of the present application also provide a device that exists in the form of at least one chip, such as a chipset.
  • the structure of the device includes the processor and the corresponding interface circuit mentioned in the previous embodiment.
  • the processor can pass through the interface circuit.
  • the device may also include a memory, which is used to couple with the processor to store the necessary program instructions and data of the device, and the processor is used to execute the program instructions stored in the memory to make the device execute The function of the scheduling device in the above method.
  • the memory may be a storage module in the chip, such as a register, a cache, etc., and the storage module may also be a storage module located outside the chip, such as a ROM or other storage modules that can store static information and instructions. Types of static storage devices, RAM, etc.
  • the steps of the method or algorithm described in conjunction with the disclosure of this application can be implemented in a hardware manner, or implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), and electrically erasable Programming read-only memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC may be located in the core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • the functions described in this application can be implemented by hardware, software, firmware or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

Abstract

Selon des modes de réalisation, la présente invention concerne un procédé et un appareil de planification de tâches logicielles parmi de multiples processeurs, ayant trait au domaine technique des communications, et résolvant des problèmes, lors de la planification d'un groupe de coroutines dans l'état de la technique, tels que l'impossibilité de satisfaire à des exigences temporelles de services et la faible efficacité de fonctionnement. Une solution spécifique consiste à : acquérir un premier groupe de coroutines d'un second processeur parmi les multiples processeurs, le premier groupe de coroutines étant un groupe de coroutines migrant du second processeur à un premier processeur parmi les multiples processeurs ; fusionner le premier groupe de coroutines avec un second groupe de coroutines du premier processeur, de façon à obtenir un groupe de coroutines fusionné, le groupe de coroutines fusionné comprenant de multiples coroutines, les multiples coroutines comprenant au moins une première coroutine du premier groupe de coroutines et au moins une seconde coroutine du second groupe de coroutines, chaque coroutine ayant un niveau de priorité, et les multiples coroutines étant séquencées dans le groupe de coroutines fusionné en fonction des niveaux de priorité des multiples coroutines ; lors de l'exécution du groupe de coroutines fusionné, exécuter les multiples coroutines selon la séquence.
PCT/CN2019/075659 2019-02-21 2019-02-21 Procédé et appareil de planification de tâches logicielles parmi de multiples processeurs WO2020168505A1 (fr)

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