WO2020162017A1 - Display data generation device and display device - Google Patents

Display data generation device and display device Download PDF

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Publication number
WO2020162017A1
WO2020162017A1 PCT/JP2019/047392 JP2019047392W WO2020162017A1 WO 2020162017 A1 WO2020162017 A1 WO 2020162017A1 JP 2019047392 W JP2019047392 W JP 2019047392W WO 2020162017 A1 WO2020162017 A1 WO 2020162017A1
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Prior art keywords
data
display data
display
dithering
probability
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PCT/JP2019/047392
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French (fr)
Japanese (ja)
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翔 仲光
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京セラ株式会社
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/66Transforming electric information into light information

Definitions

  • the present disclosure relates to a display data generation device and a display device that generate and supply display data including dithering data to each unit pixel unit of a display device driven by an active matrix method.
  • Patent Document 1 An example of the basic configuration of a conventional active matrix type liquid crystal display device (Liquid Crystal Display: LCD) is described in Patent Document 1, for example.
  • a display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method.
  • a first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more;
  • a data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data.
  • the ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided.
  • a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device.
  • a display device is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure.
  • 1 shows an example of an embodiment of a display data generation device of the present disclosure, and is a block circuit diagram of the display data generation device.
  • 1 shows an example of an embodiment of a display data generation device of the present disclosure, and is an arithmetic expression that determines a probability in a probability circuit.
  • 13 is a table illustrating another example of the display data generation device according to the present disclosure, and is a table illustrating that the dithering process is performed once every four frames.
  • It is a block circuit diagram of the stochastic circuit shown in FIG. 1A. It is a table explaining that the probability is variable by a plurality of lookup tables included in the probability circuit of FIG. 1A.
  • the number of bits m of the first dithering data is 2
  • the value ym in the decimal system is 0 to 3
  • the maximum value ymax in the decimal system is 3, four lookups included in the probability circuit of FIG. 3A. It is a table explaining operation of one of the tables.
  • FIG. 3 is a block circuit diagram of a basic configuration of an LCD having a configuration based on the liquid crystal display device of the present disclosure.
  • the display data generation device and the display device of the present disclosure may include well-known constituent members such as a circuit board, wiring conductors, control IC, and LSI, which are not shown.
  • FIG. 6 shows an example of the basic configuration of an active matrix type liquid crystal display device (Liquid Crystal Display: LCD) based on the liquid crystal display device of the present disclosure.
  • the TFT array side substrate 20 on which a large number of pixel electrode portions P11, P12, P13 to Pmn including the TFT 21 are formed is arranged in the first direction (for example, the row).
  • the first direction for example, the row.
  • the gate signal lines GL1, GL2, GL3 to GLm and gate signal lines GL1, GL2, GL3 to GLm in a second direction (eg, column direction) intersecting the first direction.
  • a common electrode for forming a lateral electric field (horizontal electric field) applied to the liquid crystal between the TFT 21, the pixel electrodes PE11, PE12, PE13 to PEmn and the pixel electrodes PE11, PE12, PE13 to PEmn.
  • the configuration includes a pixel electrode portion and a common voltage line 22 that supplies a common voltage (Vcom) to the common electrode.
  • Vcom common voltage
  • This IPS type LCD can enhance viewing angle characteristics such as contrast, gray inversion, and color shift compared to an LCD that drives a Twisted Nematic (TN) liquid crystal by a vertical electric field. As a result, a wide viewing angle can be obtained, which is suitable for large-sized LCDs.
  • TN Twisted Nematic
  • the dithering method is a method that allows an image to be displayed with an apparently larger number of colors than the actual number of colors (the number of gradations).
  • the dithering method is used, for example, when a single pixel portion is conspicuous more than necessary in a specific color tone, the periphery of the pixel portion is averaged as an intermediate color, and it is possible to suppress the conspicuousness more than necessary.
  • the dithering method eliminates the boundary between the image areas. As a result, a natural gradation appears between the image areas, and color unevenness is eliminated.
  • the display data generation device includes display data including dithering data in each unit pixel unit of a display device having a plurality of unit pixel units and driven by an active matrix method.
  • a display data generating device for generating and supplying a binary high-order bit data consisting of a plurality of bits (n bits/n is an integer of 2 or more) and 2 consisting of 1 bit or more (m bits/m is a natural number).
  • the first display data generation unit 1 that generates the first display data Din[n+m] having the binarized lower bit data and the binarized upper bit data as the second display data x are binarized.
  • the probability circuit 4 having a probability varying unit and the third display data Dout[n] generated by adding the second dithering data Y[1] to the second display data x[n] are displayed on the display device 6 And a second display data generating unit 5 for supplying In the configuration of FIG.
  • reference numeral 2 indicates a dithering portion
  • reference numeral 3a indicates a storage portion of the second display data x in the data separating portion 3
  • the second display data generation unit 5 is composed of an adder and the like.
  • the probability circuit 4 that determines the second dithering data Y[n] to “1” or “0” with a probability has a probability varying unit, it is high in performing dithering of various images. Image quality becomes easy and the degree of freedom is improved. That is, it becomes easy to improve the image quality of various images. Further, since the third display data as the driving display data used for image display in each unit pixel portion of the display device can be generated and directly supplied to the display device, the display data such as the display memory is temporarily stored. No need for large memory. As a result, the display data transferred to the display device can be transferred at a high speed, the power consumption can be reduced, and the display device can be manufactured at low cost.
  • the probability varying unit corresponds to a part including the selector 10, the lookup table (LUT) (0) 12, and the LUT (1) 13 to LUT (ymax) 14 shown in FIG. 3A.
  • the display data generation device of the present embodiment basically relates to dithering processing executed in a unit pixel unit. Therefore, it is not related to the dithering process performed by referring to the display data of the unit pixel portion around the certain unit pixel portion.
  • the display data of the peripheral unit pixel portion is intermittently and periodically added to the first display data Din[n+m]. By including it, it is possible to execute the dithering process with reference to the display data of the peripheral unit pixel portion.
  • the display data generation device of the present embodiment may be a driving element such as an IC or LSI in which the dithering processing program is stored in ROM (Read Only Memory), RAM (Random Access Memory), etc. It may be a drive circuit device in which a peripheral circuit and electronic elements are mounted on a substrate. Further, the driving element and the driving circuit device may be arranged inside the display device, but may be arranged as an external component outside the display device.
  • the binarized high-order bit data is about 2 to 12 bits. If it exceeds 12 bits, various circuits such as the drive circuit of the display device 6 tend to be complicated and the circuit scale tends to increase.
  • the binarized lower bit data is, for example, about 1 bit to 4 bits. When the number of bits exceeds 4 bits, the dithering unit 2 becomes complicated and the small-capacity memory size such as LUT in the probability circuit 4 tends to increase.
  • FIG. 1B is an arithmetic expression for determining the probability in the probability circuit 4.
  • the stochastic circuit 4 of the present embodiment operates as follows.
  • the probability circuit 4 sets the number of bits of the first dithering data y[m] to m (m is a natural number), the decimal value of the first dithering data y[m] to ym, and the first dithering.
  • ymax is the maximum value of the data y[m] in the decimal system
  • the second dithering data Y[1] is determined to be “1” with a probability of ⁇ ym/(ymax+1) ⁇ 100(%). ..
  • the probability can be made variable by variously setting the bit number m of the first dithering data y[m], the decimal value ym, and the decimal maximum value ymax. Further, the maximum probability is ⁇ ymax/(ymax+1) ⁇ 100(%), which is not 100(%). Therefore, a small memory of a lookup table (LUT) corresponding to 100(%) can be omitted. , It can be disabled at all times. As a result, the number of small-capacity memories such as a look-up table (LUT) used in the probability circuit 4 can be suppressed, and power consumption can be suppressed.
  • LUT lookup table
  • FIG. 2 shows another example of the display data generation device according to the present embodiment, and is a table for explaining that the dithering process is performed once every four frames.
  • the probability circuit 4 of the display data generating apparatus according to the present embodiment outputs the second dithering data Y[1] in ym frames of the selected (ymax+1) frames. It is better to decide "1". In this case, since the dithering process can be performed on the selected frame, the degree of freedom in improving the image quality of various images is improved.
  • the second dithering data Y[1] is determined to be "1".
  • the dithering data Y[1] of 2 is determined to be "1”.
  • the dithering data Y[1] of 2 is determined to be "1".
  • the dithering data Y[1] of 2 is determined to be "1".
  • FIG. 2 shows a case where the first display data Din[8+2] has binarized high-order bit data of 8 bits and binarized low-order bit data of 2 bits.
  • the binarized high-order bit data is data corresponding to the third display data Dout[n] for driving the display device.
  • the binarized lower-order bit data corresponds to the second dithering data Y[1], and is added to the second display data x[n] to be finally reduced.
  • the dithering process is executed in the third frame of the first to fourth frames. Further, the dithering process of adding “1” is executed in the fifth frame of the fifth to eighth frames.
  • (ymax+1) frames may be consecutive (ymax+1) frames.
  • all the frames can be the target of the dithering process, the image quality can be improved more effectively.
  • the display data generation device includes a random number generation circuit 11 in the probability circuit 4, and the random number generation circuit 11 is the second of the (ymax+1) frames. It is preferable to select the frame that determines the dithering data Y[1] of “1”. In this case, it is possible to effectively suppress the occurrence of unnatural gradation and color unevenness in the display image. Further, the random number generation circuit 11 can also select a frame in which the second dithering data Y[1] is determined to be “1” from among the (ymax+1) frames with variable probability.
  • any one of the output signals OUT1 and OUT2 to OUTymax+1 is input to one of the enable EN terminals of the LUT(0) and LUT(1) to LUT(ymax), and LUT(0) and LUT(1) to Any one of the LUTs (ymax) is activated (started) and operated.
  • the output signal OUT1 is input to the enable terminal EN of the LUT(0) and activates the LUT(0).
  • the output signal OUT2 is input to the enable terminal EN of the LUT(1) and activates the LUT(1).
  • the output signal OUTymax+1 is input to the enable terminal EN of the LUT(ymax) and activates the LUT(ymax).
  • a random selection signal is input from the random number generation circuit 11 to each of the input terminals IN of the LUT(0) and LUT(1) to LUT(ymax) together with any one of the output signals OUT1 and OUT2 to OUTymax+1 output from the selector 10. .. As shown in FIGS. 4A, 4B, and 4C, the random selection signal causes one of the LUT(0) and LUT(1) to LUT(ymax) to be activated and select one OUT data. ..
  • the OUT data of the LUT(0) is all “0” as shown in FIG. 4A, so the OUT data is always “0”. That is, the LUT(0) has a probability of ⁇ 0/(ymax+1) ⁇ 100(%) as shown in the column of LUT(0) in FIG. 3B, and the second dithering data Y[1] is “ 1”.
  • the LUT(1) When the LUT(1) is activated, as shown in FIG. 4B, only one OUT data of the LUT(1) is “1” and the rest is “0”, so the OUT data is ⁇ 1/( ymax+1) ⁇ 100(%) with a probability of “1”. That is, the LUT(1) has a probability of ⁇ 1/(ymax+1) ⁇ 100(%) as shown in the column of LUT(1) in FIG. 3B, and the second dithering data Y[1] is “ 1”.
  • the LUT(ymax) When the LUT(ymax) is activated, as shown in FIG. 4C, only one OUT data of the LUT(ymax) is “0” and the rest is “1”, so the OUT data is ⁇ ymax/( ymax+1) ⁇ 100(%) with a probability of “1”. That is, as shown in the LUT(ymax) column of FIG. 3B, the LUT(ymax) has the probability of ⁇ ymax/(ymax+1) ⁇ 100(%) and the second dithering data Y[1] is “ 1”.
  • any one of the activated LUT(0) and LUT(1) to LUT(ymax) sets the second dithering data Y[1] to “1” with its unique probability. decide. In other words, in order to change the probability, any one of LUT(0) and LUT(1) to LUT(ymax) may be activated.
  • 5A, 5B, 5C and 5D show that the bit number m of the first dithering data y[m] is 2, the decimal value ym is 0 to 3, and the decimal maximum value ymax is 3.
  • 3B is a table for explaining the operation of each of the four LUT(0) to LUT(3) included in the probability circuit of FIG. 3A.
  • the LUT(0) operates to determine the second dithering data Y[1] to be “1” with a probability of ⁇ 0/(3+1) ⁇ 100(%).
  • the LUT(1) operates to determine the second dithering data Y[1] to be “1” with a probability of ⁇ 1/(3+1) ⁇ 100(%).
  • the LUT(2) operates to determine the second dithering data Y[1] to be “1” with a probability of ⁇ 2/(3+1) ⁇ 100(%).
  • the LUT(3) operates to determine the second dithering data Y[1] to be “1” with a probability of ⁇ 3/(3+1) ⁇ 100(%).
  • the dithering data Y[1] of 2 can be determined to be "1". That is, the probability of determining the second dithering data Y[1] as “1” can be made variable to any of 0(%), 25(%), 50(%), and 75(%). it can.
  • the display device of the present embodiment is a display device including the display data generation device of the present embodiment, and selects whether to take in the third display data Dout[n] generated by the display data generation device. It is the structure provided with the selection part. With this configuration, it is possible to select whether or not to execute the dithering process, and the degree of freedom of image processing for various images is further improved.
  • the selection unit can be inserted and arranged in series in the transmission line between the third display data generation unit 5 and the display device 6, for example. It is possible to capture the third display data Dout[n] by setting the selection unit as a switch circuit and closing the switch circuit (ON state).
  • the third display data Dout[n] can be prevented from being taken in. Further, when the third display data Dout[n] is not captured, the display data that has not been subjected to the dithering process may be input to the display device 6. Further, the third display data Dout[n] can be always taken in by setting the switch circuit to the normally closed state (on state).
  • the display device of the present disclosure may be a display device having a plurality of unit pixel portions and driven by an active matrix method, and may be, for example, an LCD, an organic EL (Electro Luminescence) device, an inorganic EL device, a plasma display, an FED (Field). Emitting Display), SED (Surface-conduction Electron-emitter Display), GLV (Grating Light Valve) device, PDP (Plasma Display) device, DMD (Digital micro Mirror Device), piezoelectric ceramic display, micro LED display, etc. It may be.
  • display data generation device and the display device of the present disclosure are not limited to the above-mentioned embodiment, and may include appropriate design changes and improvements.
  • the present disclosure can have the following embodiments.
  • a display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method.
  • a first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more;
  • a data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data.
  • the ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided.
  • a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device.
  • the probability circuit is configured such that the number of bits of the first dithering data is m (m is a natural number), the decimal value of the first dithering data is ym, and the first dithering data is ym.
  • ymax is the maximum value of the dithering data of 1 in the decimal system
  • the second dithering data may be determined to be "1" with a probability of ⁇ ym/(ymax+1) ⁇ 100(%).
  • the probability circuit may determine the second dithering data to be “1” in ym frames of the selected (ymax+1) frames.
  • the probability circuit includes a random number generation unit, and the random number generation unit sets the second dithering data to “1” in the (ymax+1) frames.
  • the frame to be determined may be selected.
  • the (ymax+1) frames may be continuous (ymax+1) frames.
  • a display device is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure.
  • a display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method.
  • a first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more;
  • a data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data.
  • the ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided.
  • a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device. Therefore, the following effects are achieved. Since the probability circuit that determines the second dithering data to “1” or “0” with probability has the probability varying unit, it is easy to improve the image quality when performing dithering of various images. The degree of freedom increases as That is, it becomes easy to improve the image quality of various images.
  • the display data transferred to the display device can be transferred at a high speed, the power consumption can be reduced, and the display device can be manufactured at low cost.
  • the probability circuit is configured such that the number of bits of the first dithering data is m (m is a natural number), the decimal value of the first dithering data is ym, and When ymax is the maximum value of the dithering data of 1 in the decimal system, when the second dithering data is determined to be “1” with a probability of ⁇ ym/(ymax+1) ⁇ 100(%),
  • the probability can be made variable by variously setting the bit number m of the dithering data, the decimal value ym, and the decimal maximum value ymax. Further, the maximum probability is ⁇ ymax/(ymax+1) ⁇ 100(%), which is not 100(%). Therefore, the number of small-capacity memories such as a lookup table (LUT) used in the probability circuit is Can be suppressed.
  • LUT lookup table
  • the display data generation device is selected when the probability circuit determines the second dithering data to be “1” in ym frames of the selected (ymax+1) frames.
  • the dithering process can be performed on the selected frame. As a result, the degree of freedom in improving the image quality by the dithering process is improved.
  • the probability circuit includes a random number generation unit, and the random number generation unit sets the second dithering data to “1” in the (ymax+1) frames.
  • the (ymax+1) frames are continuous (ymax+1) frames, all the frames can be the target of the dithering process. As a result, more effective image quality can be achieved.
  • a display device is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure. With this configuration, it is possible to select whether or not to execute the dithering process, and the degree of freedom of image processing for various images is further improved.
  • the display data generation device and display device of the present disclosure can be applied to various electronic devices.
  • the electronic devices include car route guidance system (car navigation system), ship route guidance system, aircraft route guidance system, smartphone terminal, mobile phone, tablet terminal, personal digital assistant (PDA), video camera, digital still camera, electronic device.
  • ATM automatic teller machines
  • HMD head mounted image display devices

Abstract

This display data generation device is provided with: a first display data generation unit (1) which generates first display data Din[n+m] including binarized higher-order bit data (n-bit) and binarized lower-order bit data (m-bit); a data separation unit (3) which separates the binarized higher-order bit data and the binarized lower-order bit data as second display data x and first dithering data y (=y[m]), respectively; a probability circuit (4) whereby second dithering data Y[1] that is to be added to the second display data x (=x[n]) is determined to be "1" at a variable probability based on the bit count m and the value of the first dithering data y[m]; and a second display data generation unit (5) which feeds, to a display device (6), third display data Dout[n] generated by adding the second dithering data Y[1] to the second display data x[n].

Description

表示データ生成装置および表示装置Display data generation device and display device
 本開示は、アクティブマトリックス方式で駆動される表示装置の単位画素部のそれぞれにディザリングデータを含む表示データを生成し供給する表示データ生成装置および表示装置に関する。 The present disclosure relates to a display data generation device and a display device that generate and supply display data including dithering data to each unit pixel unit of a display device driven by an active matrix method.
 従来のアクティブマトリクス型の液晶表示装置(Liquid Crystal Display:LCD)の基本構成の1例が、例えば特許文献1に記載されている。 An example of the basic configuration of a conventional active matrix type liquid crystal display device (Liquid Crystal Display: LCD) is described in Patent Document 1, for example.
特開2004-78059号公報JP-A-2004-78059
 本開示の表示データ生成装置は、複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置の前記単位画素部のそれぞれに、ディザリングデータを含む表示データを生成し供給する表示データ生成装置であって、複数ビットから成る2値化上位ビットデータと、1ビット以上から成る2値化下位ビットデータと、を有する第1の表示データを、生成する第1の表示データ生成部と、前記2値化上位ビットデータを第2の表示データとし、前記2値化下位ビットデータを第1のディザリングデータとして分離するデータ分離部と、前記第2の表示データに加算する第2のディザリングデータを、前記第1のディザリングデータのビット数および値に基づく確率で「1」に決定し、それ以外の場合は「0」に決定するとともに、前記確率を可変とする確率可変部を有する確率回路と、前記第2の表示データに前記第2のディザリングデータを加算して生成した第3の表示データを、前記表示装置に供給する第2の表示データ生成部と、を備える構成である。 A display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method. A first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more; A data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data. The ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided. And a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device. Is.
 本開示の表示装置は、上記本開示の表示データ生成装置を備える表示装置であって、前記表示データ生成装置で生成した前記第3の表示データを取り込むか否かを選択する選択部を備えている構成である。 A display device according to the present disclosure is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure.
 本開示の目的、特色、および利点は、下記の詳細な説明と図面とからより明確になるであろう。
本開示の表示データ生成装置について実施の形態の1例を示すものであり、表示データ生成装置のブロック回路図である。 本開示の表示データ生成装置について実施の形態の1例を示すものであり、確率回路において確率を決定する演算式である。 本開示の表示データ生成装置について実施の形態の他例を示すものであり、4フレームに1回の割合でディザリング処理を行うことを説明する表である。 図1Aに示す確率回路のブロック回路図である。 図1Aの確率回路に含まれる複数のルックアップテーブルによって確率が可変とされることを説明する表である。 図3Aの確率回路に含まれる複数のルックアップテーブルのうちの1つの動作を説明する表である。 図3Aの確率回路に含まれる複数のルックアップテーブルのうちの1つの動作を説明する表である。 図3Aの確率回路に含まれる複数のルックアップテーブルのうちの1つの動作を説明する表である。 第1のディザリングデータのビット数mが2、10進法による値ymが0~3、10進法による最大値ymaxが3である場合に、図3Aの確率回路に含まれる4つのルックアップテーブルのうちの1つの動作を説明する表である。 第1のディザリングデータのビット数mが2、10進法による値ymが0~3、10進法による最大値ymaxが3である場合に、図3Aの確率回路に含まれる4つのルックアップテーブルのうちの1つの動作を説明する表である。 第1のディザリングデータのビット数mが2、10進法による値ymが0~3、10進法による最大値ymaxが3である場合に、図3Aの確率回路に含まれる4つのルックアップテーブルのうちの1つの動作を説明する表である。 第1のディザリングデータのビット数mが2、10進法による値ymが0~3、10進法による最大値ymaxが3である場合に、図3Aの確率回路に含まれる4つのルックアップテーブルのうちの1つの動作を説明する表である。 本開示の液晶表示装置が基礎とする構成のLCDの基本構成のブロック回路図である。
Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings.
1 shows an example of an embodiment of a display data generation device of the present disclosure, and is a block circuit diagram of the display data generation device. 1 shows an example of an embodiment of a display data generation device of the present disclosure, and is an arithmetic expression that determines a probability in a probability circuit. 13 is a table illustrating another example of the display data generation device according to the present disclosure, and is a table illustrating that the dithering process is performed once every four frames. It is a block circuit diagram of the stochastic circuit shown in FIG. 1A. It is a table explaining that the probability is variable by a plurality of lookup tables included in the probability circuit of FIG. 1A. It is a table explaining operation|movement of one of the some lookup tables contained in the probability circuit of FIG. 3A. It is a table explaining operation|movement of one of the some lookup tables contained in the probability circuit of FIG. 3A. It is a table explaining operation|movement of one of the some lookup tables contained in the probability circuit of FIG. 3A. When the number of bits m of the first dithering data is 2, the value ym in the decimal system is 0 to 3, and the maximum value ymax in the decimal system is 3, four lookups included in the probability circuit of FIG. 3A. It is a table explaining operation of one of the tables. When the number of bits m of the first dithering data is 2, the value ym in the decimal system is 0 to 3, and the maximum value ymax in the decimal system is 3, four lookups included in the probability circuit of FIG. 3A. It is a table explaining operation of one of the tables. When the number of bits m of the first dithering data is 2, the value ym in the decimal system is 0 to 3, and the maximum value ymax in the decimal system is 3, four lookups included in the probability circuit of FIG. 3A. It is a table explaining operation of one of the tables. When the number of bits m of the first dithering data is 2, the value ym in the decimal system is 0 to 3, and the maximum value ymax in the decimal system is 3, four lookups included in the probability circuit of FIG. 3A. It is a table explaining operation of one of tables. FIG. 3 is a block circuit diagram of a basic configuration of an LCD having a configuration based on the liquid crystal display device of the present disclosure.
 以下、本開示の表示データ生成装置および表示装置の実施の形態について、図面を参照しながら説明する。但し、以下で参照する各図は、本実施の形態の表示データ生成装置および表示装置の主要な構成部材等を示している。従って、本実施の形態の表示データ生成装置および表示装置は、図に示されていない回路基板、配線導体、制御IC,LSI等の周知の構成部材を備えていてもよい。 Hereinafter, embodiments of the display data generation device and the display device of the present disclosure will be described with reference to the drawings. However, the drawings referred to below show the main components of the display data generating device and the display device of this embodiment. Therefore, the display data generation device and the display device of the present embodiment may include well-known constituent members such as a circuit board, wiring conductors, control IC, and LSI, which are not shown.
 まず、図6を参照して、本開示の液晶表示装置が基礎とする構成の液晶表示装置について説明する。 First, a liquid crystal display device based on the liquid crystal display device of the present disclosure will be described with reference to FIG. 6.
 本開示の液晶表示装置が基礎とする構成のアクティブマトリクス型の液晶表示装置(Liquid Crystal Display:LCD)の基本構成の1例を図6に示す。例えばIPS(In-Plane Switching)方式のLCDの場合、TFT21を含む画素電極部P11,P12,P13~Pmnが多数形成されたTFTアレイ側基板20は、その上の第1の方向(例えば、行方向)に形成された複数本のゲート信号線GL1,GL2,GL3~GLmと、第1の方向と交差する第2の方向(例えば、列方向)にゲート信号線GL1,GL2,GL3~GLmと交差させて形成された複数本の画像信号線(ソース信号線)SL1,SL2,SL3~SLnと、ゲート信号線GL1,GL2,GL3~GLmと画像信号線SL1,SL2,SL3~SLnの交差部に形成された、TFT21、画素電極PE11,PE12,PE13~PEmn及びその画素電極PE11,PE12,PE13~PEmnとの間で液晶に印加する横電界(水平電界)を形成するための共通電極を含む画素電極部と、共通電極に共通電圧(Vcom)を供給する共通電圧線22と、を有する構成である。なお、図6において、23はゲート信号線GL1,GL2,GL3~GLmに順次ゲート信号を入力するゲート信号線駆動回路、24は画像信号線SL1,SL2,SL3~SLnに順次画像信号を入力する画像信号線駆動回路である。このIPS方式のLCDは、垂直電界によってツイステッドネマチック(Twisted Nematic:TN)液晶を駆動するLCDと比較して、コントラスト、グレー反転、色ずれ等の視野角特性を高めることができる。その結果、広視野角を得ることができるので、大型のLCDに好適に用いられている。 FIG. 6 shows an example of the basic configuration of an active matrix type liquid crystal display device (Liquid Crystal Display: LCD) based on the liquid crystal display device of the present disclosure. For example, in the case of an IPS (In-Plane Switching) type LCD, the TFT array side substrate 20 on which a large number of pixel electrode portions P11, P12, P13 to Pmn including the TFT 21 are formed is arranged in the first direction (for example, the row). Direction) and a plurality of gate signal lines GL1, GL2, GL3 to GLm, and gate signal lines GL1, GL2, GL3 to GLm in a second direction (eg, column direction) intersecting the first direction. Multiple image signal lines (source signal lines) SL1, SL2, SL3 to SLn formed by crossing, intersections of gate signal lines GL1, GL2, GL3 to GLm and image signal lines SL1, SL2, SL3 to SLn And a common electrode for forming a lateral electric field (horizontal electric field) applied to the liquid crystal between the TFT 21, the pixel electrodes PE11, PE12, PE13 to PEmn and the pixel electrodes PE11, PE12, PE13 to PEmn. The configuration includes a pixel electrode portion and a common voltage line 22 that supplies a common voltage (Vcom) to the common electrode. In FIG. 6, 23 is a gate signal line drive circuit for sequentially inputting gate signals to the gate signal lines GL1, GL2, GL3 to GLm, and 24 is sequentially inputting image signals to the image signal lines SL1, SL2, SL3 to SLn. This is an image signal line drive circuit. This IPS type LCD can enhance viewing angle characteristics such as contrast, gray inversion, and color shift compared to an LCD that drives a Twisted Nematic (TN) liquid crystal by a vertical electric field. As a result, a wide viewing angle can be obtained, which is suitable for large-sized LCDs.
 また、このようなLCDは高解像度化、多諧調化が進んでおり、それらに対応して画質を向上させるために、疑似的に階調数を増やすディザリング法が用いられている。ディザリング法は、実際の色数(階調数)よりも見かけ上多くの色数で画像を表示できるようにする方法である。ディザリング法を用いると、例えば、単一の画素部が特定の色調で必要以上に目立つ場合、その画素部の周辺を中間色として平均化し、必要以上に目立つことを抑えることができる。また、複数の画素部から成る或る画像領域と、その周辺の画像領域との間の色調差が大きいために、画像領域間に境界線が見えるような不自然なグラデーション、色ムラが生じている場合、ディザリング法を用いると、画像領域間の境界線が解消される。その結果、画像領域間が自然なグラデーションに見え、色ムラも解消される。 In addition, such LCDs are becoming higher resolution and more gradation, and in order to correspondingly improve the image quality, a dithering method that artificially increases the number of gradations is used. The dithering method is a method that allows an image to be displayed with an apparently larger number of colors than the actual number of colors (the number of gradations). When the dithering method is used, for example, when a single pixel portion is conspicuous more than necessary in a specific color tone, the periphery of the pixel portion is averaged as an intermediate color, and it is possible to suppress the conspicuousness more than necessary. Further, since there is a large difference in color tone between a certain image area composed of a plurality of pixel parts and the image area around it, unnatural gradation and color unevenness that makes a boundary line visible between the image areas occurs. If so, the dithering method eliminates the boundary between the image areas. As a result, a natural gradation appears between the image areas, and color unevenness is eliminated.
 本実施の形態の表示データ生成装置は、図1Aに示すように、複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置の単位画素部のそれぞれに、ディザリングデータを含む表示データを生成し供給する表示データ生成装置であって、複数ビット(nビット/nは2以上の整数)から成る2値化上位ビットデータと、1ビット以上(mビット/mは自然数)から成る2値化下位ビットデータと、を有する第1の表示データDin[n+m]を、生成する第1の表示データ生成部1と、2値化上位ビットデータを第2の表示データxとし、2値化下位ビットデータを第1のディザリングデータy(=y[m])として分離するデータ分離部3と、第2の表示データx(=x[n])に加算する第2のディザリングデータY[1]を、第1のディザリングデータy[m]のビット数mおよび値に基づく確率で「1」に決定し、それ以外の場合は「0」に決定するとともに、確率を可変とする確率可変部を有する確率回路4と、第2の表示データx[n]に第2のディザリングデータY[1]を加算して生成した第3の表示データDout[n]を、表示装置6に供給する第2の表示データ生成部5と、備える構成である。なお、図1Aの構成において、符号2はディザリング部を示し、符号3aはデータ分離部3における第2の表示データxの格納部を示し、符号3bは第1のディザリングデータy(=y[m])の格納部を示す。また、第2の表示データ生成部5は加算器等から成る。 As shown in FIG. 1A, the display data generation device according to the present embodiment includes display data including dithering data in each unit pixel unit of a display device having a plurality of unit pixel units and driven by an active matrix method. Is a display data generating device for generating and supplying a binary high-order bit data consisting of a plurality of bits (n bits/n is an integer of 2 or more) and 2 consisting of 1 bit or more (m bits/m is a natural number). The first display data generation unit 1 that generates the first display data Din[n+m] having the binarized lower bit data and the binarized upper bit data as the second display data x are binarized. A data separation unit 3 that separates the lower-order bit data as first dithering data y (=y[m]), and second dithering data Y that is added to the second display data x (=x[n]). [1] is determined to be “1” with a probability based on the number of bits m and the value of the first dithering data y[m], and is determined to be “0” in other cases, and the probability is made variable. The probability circuit 4 having a probability varying unit and the third display data Dout[n] generated by adding the second dithering data Y[1] to the second display data x[n] are displayed on the display device 6 And a second display data generating unit 5 for supplying In the configuration of FIG. 1A, reference numeral 2 indicates a dithering portion, reference numeral 3a indicates a storage portion of the second display data x in the data separating portion 3, and reference numeral 3b indicates the first dithering data y (=y [M]) is a storage unit. The second display data generation unit 5 is composed of an adder and the like.
 上記の構成により、以下の効果を奏する。第2のディザリングデータY[n]を確率をもって「1」または「0」に決定する確率回路4が、確率可変部を有していることから、種々の画像のディザリングを実施するにあたって高画質化が容易になるとともにその自由度が向上する。すなわち、種々の画像の画質を向上させることが容易になる。また、表示装置の各単位画素部で画像表示に用いられる駆動用の表示データとしての第3の表示データを生成し表示装置に直接的に供給できるので、表示メモリ等の表示データを一旦記憶する大容量のメモリが不要となる。その結果、表示装置に転送する表示データの転送速度が速くなるとともに、消費電力が低減され、さらには低コストな表示装置となる、という効果も奏する。なお、確率可変部は、図3Aに示すセレクタ10、ルックアップテーブル(LUT)(0)12、LUT(1)13~LUT(ymax)14から構成される部位に相当する。 With the above configuration, the following effects are achieved. Since the probability circuit 4 that determines the second dithering data Y[n] to “1” or “0” with a probability has a probability varying unit, it is high in performing dithering of various images. Image quality becomes easy and the degree of freedom is improved. That is, it becomes easy to improve the image quality of various images. Further, since the third display data as the driving display data used for image display in each unit pixel portion of the display device can be generated and directly supplied to the display device, the display data such as the display memory is temporarily stored. No need for large memory. As a result, the display data transferred to the display device can be transferred at a high speed, the power consumption can be reduced, and the display device can be manufactured at low cost. The probability varying unit corresponds to a part including the selector 10, the lookup table (LUT) (0) 12, and the LUT (1) 13 to LUT (ymax) 14 shown in FIG. 3A.
 なお、本実施の形態の表示データ生成装置は、基本的には或る単位画素部において実行されるディザリング処理に関するものである。従って、或る単位画素部の周辺の単位画素部の表示データを参照して行うディザリング処理に関するものではない。しかしながら、第1の表示データDin[n+m]を生成する第1の表示データ生成部1において、第1の表示データDin[n+m]に、周辺の単位画素部の表示データを断続的、周期的に含ませることによって、周辺の単位画素部の表示データを参照してディザリング処理を実行させることも可能である。 Note that the display data generation device of the present embodiment basically relates to dithering processing executed in a unit pixel unit. Therefore, it is not related to the dithering process performed by referring to the display data of the unit pixel portion around the certain unit pixel portion. However, in the first display data generation unit 1 that generates the first display data Din[n+m], the display data of the peripheral unit pixel portion is intermittently and periodically added to the first display data Din[n+m]. By including it, it is possible to execute the dithering process with reference to the display data of the peripheral unit pixel portion.
 本実施の形態の表示データ生成装置は、ディザリング処理プログラムがROM(Read Only Memory),RAM(Random Access Memory)等に格納されたIC,LSI等の駆動素子であってよく、またその駆動素子と周辺回路および電子素子を基板上に搭載した駆動回路装置であってもよい。また、駆動素子、駆動回路装置は、表示装置の内部に配置されていてもよいが、表示装置の外部に外付けの部品として配置されていてもよい。 The display data generation device of the present embodiment may be a driving element such as an IC or LSI in which the dithering processing program is stored in ROM (Read Only Memory), RAM (Random Access Memory), etc. It may be a drive circuit device in which a peripheral circuit and electronic elements are mounted on a substrate. Further, the driving element and the driving circuit device may be arranged inside the display device, but may be arranged as an external component outside the display device.
 nビット(nは2以上の整数)から成る2値化上位ビットデータと、mビット(mは自然数)から成る2値化下位ビットデータと、を有する第1の表示データDin[n+m]において、例えば2値化上位ビットデータは2ビット~12ビット程度である。12ビットを超えると、表示装置6の駆動回路等の各種回路が複雑化し、回路規模が大きくなる傾向がある。2値化下位ビットデータは、例えば1ビット~4ビット程度である。4ビットを超えると、ディザリング部2が複雑化するとともに確率回路4におけるLUT等の小容量のメモリサイズが大きくなっていく傾向がある。 In the first display data Din[n+m] having the binarized high-order bit data composed of n bits (n is an integer of 2 or more) and the binarized low-order bit data composed of m bits (m is a natural number), For example, the binarized high-order bit data is about 2 to 12 bits. If it exceeds 12 bits, various circuits such as the drive circuit of the display device 6 tend to be complicated and the circuit scale tends to increase. The binarized lower bit data is, for example, about 1 bit to 4 bits. When the number of bits exceeds 4 bits, the dithering unit 2 becomes complicated and the small-capacity memory size such as LUT in the probability circuit 4 tends to increase.
 図1Bは確率回路4において確率を決定する演算式である。この演算式に基づき、本実施の形態の確率回路4は以下のように動作する。確率回路4は、第1のディザリングデータy[m]のビット数をm(mは自然数)、第1のディザリングデータy[m]の10進法による値をym、第1のディザリングデータy[m]の10進法による最大値をymaxとしたとき、{ym/(ymax+1)}×100(%)の確率で第2のディザリングデータY[1]を「1」に決定する。 FIG. 1B is an arithmetic expression for determining the probability in the probability circuit 4. Based on this arithmetic expression, the stochastic circuit 4 of the present embodiment operates as follows. The probability circuit 4 sets the number of bits of the first dithering data y[m] to m (m is a natural number), the decimal value of the first dithering data y[m] to ym, and the first dithering. When ymax is the maximum value of the data y[m] in the decimal system, the second dithering data Y[1] is determined to be “1” with a probability of {ym/(ymax+1)}×100(%). ..
 図1Bの演算式によると、例えば第1のディザリングデータy[m]のビット数mが2である場合、第1のディザリングデータy[m]が「00」の場合に10進法で「0」、y[m]が「01」の場合に10進法で「1」、y[m]が「10」の場合に10進法で「2」、y[m]が「11」の場合に10進法で「3」であることから、第2のディザリングデータY[1]が「1」となる確率P(Y1)は、0%,1/4(25%),2/4(50%),3/4(75%)のいずれかの確率となる。 According to the arithmetic expression of FIG. 1B, for example, when the number of bits m of the first dithering data y[m] is 2, when the first dithering data y[m] is “00”, the decimal system is used. When "0" and y[m] are "01", the decimal number is "1". When y[m] is "10", the decimal number is "2" and y[m] is "11". In this case, since the decimal value is “3”, the probability P(Y1) that the second dithering data Y[1] is “1” is 0%, ¼ (25%), 2 The probability is either /4 (50%) or 3/4 (75%).
 従って、第1のディザリングデータy[m]のビット数mと10進法による値ymと10進法による最大値ymaxとを種々に設定することによって、確率を可変にすることができる。また、確率は最大でも{ymax/(ymax+1)}×100(%)となり、100(%)にはならないので、100(%)に相当するルックアップテーブル(LUT)の小容量のメモリを省いたり、常時動作させないようにすることができる。その結果、確率回路4の中に用いるルックアップテーブル(LUT)等の小容量のメモリの数を抑えたり、消費電力を抑えることができる。 Therefore, the probability can be made variable by variously setting the bit number m of the first dithering data y[m], the decimal value ym, and the decimal maximum value ymax. Further, the maximum probability is {ymax/(ymax+1)}×100(%), which is not 100(%). Therefore, a small memory of a lookup table (LUT) corresponding to 100(%) can be omitted. , It can be disabled at all times. As a result, the number of small-capacity memories such as a look-up table (LUT) used in the probability circuit 4 can be suppressed, and power consumption can be suppressed.
 図2は、本実施の形態の表示データ生成装置について実施の形態の他例を示すものであり、4フレームに1回の割合でディザリング処理を行うことを説明する表である。図2に示すように、本実施の形態の表示データ生成装置の確率回路4は、選択された(ymax+1)個のフレームのうちym個のフレームにおいて、第2のディザリングデータY[1]を「1」に決定することがよい。この場合、選択されたフレームにおいてディザリング処理を実施することができるので、種々の画像の高画質化に関してその自由度が向上する。なお、mが2でy[m]が「00」の場合には、10進法による値ymは0であるから、選択された(ymax+1)=4個のフレームのうちym=0個のフレームにおいて第2のディザリングデータY[1]を「1」に決定する。mが2でy[m]が「01」の場合には、10進法による値ymは1であるから、選択された(ymax+1)=4個のフレームのうちym=1個のフレームにおいて第2のディザリングデータY[1]を「1」に決定する。mが2でy[m]が「10」の場合には、10進法による値ymは2であるから、選択された(ymax+1)=4個のフレームのうちym=2個のフレームにおいて第2のディザリングデータY[1]を「1」に決定する。mが2でy[m]が「11」の場合には、10進法による値ymは3であるから、選択された(ymax+1)=4個のフレームのうちym=3個のフレームにおいて第2のディザリングデータY[1]を「1」に決定する。図2に示す構成は、mが2でy[m]が「01」の場合であり、10進法による値ymは1であるから、選択された(ymax+1)=4個のフレームのうちym=1個のフレームにおいて第2のディザリングデータY[1]を「1」に決定する場合に相当する。 FIG. 2 shows another example of the display data generation device according to the present embodiment, and is a table for explaining that the dithering process is performed once every four frames. As shown in FIG. 2, the probability circuit 4 of the display data generating apparatus according to the present embodiment outputs the second dithering data Y[1] in ym frames of the selected (ymax+1) frames. It is better to decide "1". In this case, since the dithering process can be performed on the selected frame, the degree of freedom in improving the image quality of various images is improved. Note that when m is 2 and y[m] is “00”, the decimal value ym is 0, so ym=0 frames among the selected (ymax+1)=4 frames In, the second dithering data Y[1] is determined to be "1". When m is 2 and y[m] is “01”, the decimal value ym is 1, and therefore, in the ym=1 frame among the selected (ymax+1)=4 frames, The dithering data Y[1] of 2 is determined to be "1". When m is 2 and y[m] is “10”, the decimal value ym is 2, and therefore the first value in ym=2 frames out of the selected (ymax+1)=4 frames. The dithering data Y[1] of 2 is determined to be "1". When m is 2 and y[m] is “11”, the decimal value ym is 3, and therefore, in the selected (ymax+1)=4 frames, ym=3 The dithering data Y[1] of 2 is determined to be "1". The configuration shown in FIG. 2 is a case where m is 2 and y[m] is “01”, and the decimal value ym is 1. Therefore, ym of the selected (ymax+1)=4 frames is ym. This corresponds to the case where the second dithering data Y[1] is determined to be “1” in one frame.
 図2は、第1の表示データDin[8+2]が、8ビットから成る2値化上位ビットデータと、2ビットから成る2値化下位ビットデータと、を有する場合を示す。なお、2値化上位ビットデータは、表示装置の駆動用の第3の表示データDout[n]に相当するデータである。2値化下位ビットデータは、第2のディザリングデータY[1]に相当し、第2の表示データx[n]に加算されることによって、最終的には削減されることとなる。 FIG. 2 shows a case where the first display data Din[8+2] has binarized high-order bit data of 8 bits and binarized low-order bit data of 2 bits. The binarized high-order bit data is data corresponding to the third display data Dout[n] for driving the display device. The binarized lower-order bit data corresponds to the second dithering data Y[1], and is added to the second display data x[n] to be finally reduced.
 図2の例においては、第1フレーム~第4フレームのうち、第3フレームにおいてディザリング処理が実行されている。また、第5フレーム~第8フレームのうち、第5フレームにおいて「1」を加算するディザリング処理が実行されている。 In the example of FIG. 2, the dithering process is executed in the third frame of the first to fourth frames. Further, the dithering process of adding “1” is executed in the fifth frame of the fifth to eighth frames.
 また本実施の形態の表示データ生成装置は、図2に示すように、(ymax+1)個のフレーム(例えば、4個のフレーム)は、連続した(ymax+1)個のフレームであることがよい。この場合、すべてのフレームをディザリング処理の対象とすることができるので、より効果的に高画質化ができる。 Also, in the display data generation device of the present embodiment, as shown in FIG. 2, (ymax+1) frames (for example, four frames) may be consecutive (ymax+1) frames. In this case, since all the frames can be the target of the dithering process, the image quality can be improved more effectively.
 また本実施の形態の表示データ生成装置は、図3Aに示すように、確率回路4は、乱数発生回路11を備えており、乱数発生回路11は、(ymax+1)個のフレームのうち、第2のディザリングデータY[1]を「1」に決定するフレームを選択することがよい。この場合、表示画像において不自然なグラデーション、色ムラが発生することを効果的に抑えることができる。また乱数発生回路11は、(ymax+1)個のフレームのうち、第2のディザリングデータY[1]を「1」に決定するフレームを、確率を可変として選択することもできる。 As shown in FIG. 3A, the display data generation device according to the present embodiment includes a random number generation circuit 11 in the probability circuit 4, and the random number generation circuit 11 is the second of the (ymax+1) frames. It is preferable to select the frame that determines the dithering data Y[1] of “1”. In this case, it is possible to effectively suppress the occurrence of unnatural gradation and color unevenness in the display image. Further, the random number generation circuit 11 can also select a frame in which the second dithering data Y[1] is determined to be “1” from among the (ymax+1) frames with variable probability.
 図3Aの確率回路4において、セレクタ10は、第1のディザリングデータy[m]のビット数mと値(2進法による値)によって、OUT1,OUT2~OUTymax+1のいずれかの出力信号を選択する。mが2でy[m]が「00」の場合、出力信号OUT1が選択される。mが2でy[m]が「01」の場合、出力信号OUT2が選択される。mが2でy[m]が「11」(=ymax:10進法で3)の場合、出力信号OUTymax+1が選択される。 In the probability circuit 4 of FIG. 3A, the selector 10 selects an output signal OUT1, OUT2 to OUTymax+1 according to the bit number m of the first dithering data y[m] and the value (value in binary). To do. When m is 2 and y[m] is "00", the output signal OUT1 is selected. When m is 2 and y[m] is “01”, the output signal OUT2 is selected. When m is 2 and y[m] is “11” (=ymax: 3 in decimal), the output signal OUTymax+1 is selected.
 そして、出力信号OUT1,OUT2~OUTymax+1のいずれかは、LUT(0),LUT(1)~LUT(ymax)のいずれかのイネーブルEN端子に入力されて、LUT(0),LUT(1)~LUT(ymax)のいずれか1つを活性化(起動)し動作させる。出力信号OUT1はLUT(0)のイネーブル端子ENに入力されてLUT(0)を活性化する。出力信号OUT2はLUT(1)のイネーブル端子ENに入力されてLUT(1)を活性化する。出力信号OUTymax+1はLUT(ymax)のイネーブル端子ENに入力されてLUT(ymax)を活性化する。 Then, any one of the output signals OUT1 and OUT2 to OUTymax+1 is input to one of the enable EN terminals of the LUT(0) and LUT(1) to LUT(ymax), and LUT(0) and LUT(1) to Any one of the LUTs (ymax) is activated (started) and operated. The output signal OUT1 is input to the enable terminal EN of the LUT(0) and activates the LUT(0). The output signal OUT2 is input to the enable terminal EN of the LUT(1) and activates the LUT(1). The output signal OUTymax+1 is input to the enable terminal EN of the LUT(ymax) and activates the LUT(ymax).
 セレクタ10からの出力信号OUT1,OUT2~OUTymax+1のいずれかの出力とともに、乱数発生回路11からLUT(0),LUT(1)~LUT(ymax)の各入力端子INに、ランダム選択信号を入力する。ランダム選択信号は、図4A、図4Bおよび図4Cに示すように、LUT(0),LUT(1)~LUT(ymax)のうちの活性化した1つにおいて、1個のOUTデータを選択させる。 A random selection signal is input from the random number generation circuit 11 to each of the input terminals IN of the LUT(0) and LUT(1) to LUT(ymax) together with any one of the output signals OUT1 and OUT2 to OUTymax+1 output from the selector 10. .. As shown in FIGS. 4A, 4B, and 4C, the random selection signal causes one of the LUT(0) and LUT(1) to LUT(ymax) to be activated and select one OUT data. ..
 例えば、LUT(0)が活性化している場合、図4Aに示すように、LUT(0)のOUTデータは全て「0」であるので、OUTデータは必ず「0」になる。すなわち、LUT(0)は、図3BのLUT(0)の欄に示すように、{0/(ymax+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定する。 For example, when the LUT(0) is activated, the OUT data of the LUT(0) is all “0” as shown in FIG. 4A, so the OUT data is always “0”. That is, the LUT(0) has a probability of {0/(ymax+1)}×100(%) as shown in the column of LUT(0) in FIG. 3B, and the second dithering data Y[1] is “ 1”.
 LUT(1)が活性化している場合、図4Bに示すように、LUT(1)のOUTデータは1個だけ「1」で残りは全て「0」であるので、OUTデータは{1/(ymax+1)}×100(%)の確率で「1」となる。すなわち、LUT(1)は、図3BのLUT(1)の欄に示すように、{1/(ymax+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定する。 When the LUT(1) is activated, as shown in FIG. 4B, only one OUT data of the LUT(1) is “1” and the rest is “0”, so the OUT data is {1/( ymax+1)}×100(%) with a probability of “1”. That is, the LUT(1) has a probability of {1/(ymax+1)}×100(%) as shown in the column of LUT(1) in FIG. 3B, and the second dithering data Y[1] is “ 1”.
 LUT(ymax)が活性化している場合、図4Cに示すように、LUT(ymax)のOUTデータは1個だけ「0」で残りは全て「1」であるので、OUTデータは{ymax/(ymax+1)}×100(%)の確率で「1」となる。すなわち、LUT(ymax)は、図3BのLUT(ymax)の欄に示すように、{ymax/(ymax+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定する。 When the LUT(ymax) is activated, as shown in FIG. 4C, only one OUT data of the LUT(ymax) is “0” and the rest is “1”, so the OUT data is {ymax/( ymax+1)}×100(%) with a probability of “1”. That is, as shown in the LUT(ymax) column of FIG. 3B, the LUT(ymax) has the probability of {ymax/(ymax+1)}×100(%) and the second dithering data Y[1] is “ 1”.
 このように、LUT(0),LUT(1)~LUT(ymax)のうちの活性化したいずれか1つが、その固有の確率でもって第2のディザリングデータY[1]を「1」に決定する。換言すれば、確率を変動させるためには、LUT(0),LUT(1)~LUT(ymax)のうちいずれか1つを活性化させればよいこととなる。 As described above, any one of the activated LUT(0) and LUT(1) to LUT(ymax) sets the second dithering data Y[1] to “1” with its unique probability. decide. In other words, in order to change the probability, any one of LUT(0) and LUT(1) to LUT(ymax) may be activated.
 図5A、図5B、図5Cおよび図5Dは、第1のディザリングデータy[m]のビット数mが2、10進法による値ymが0~3、10進法による最大値ymaxが3である場合に、図3Aの確率回路に含まれる4つのLUT(0)~LUT(3)のそれぞれの動作を説明する表である。LUT(0)は、{0/(3+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定するように動作する。LUT(1)は、{1/(3+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定するように動作する。LUT(2)は、{2/(3+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定するように動作する。LUT(3)は、{3/(3+1)}×100(%)の確率で、第2のディザリングデータY[1]を「1」に決定するように動作する。このように、LUT(0)~LUT(3)のいずれかを活性化させることにより、0(%),25(%),50(%),75(%)のいずれかの確率で、第2のディザリングデータY[1]を「1」に決定することができる。すなわち、第2のディザリングデータY[1]を「1」に決定する確率を、0(%),25(%),50(%),75(%)のいずれかに可変とすることができる。 5A, 5B, 5C and 5D show that the bit number m of the first dithering data y[m] is 2, the decimal value ym is 0 to 3, and the decimal maximum value ymax is 3. 3B is a table for explaining the operation of each of the four LUT(0) to LUT(3) included in the probability circuit of FIG. 3A. The LUT(0) operates to determine the second dithering data Y[1] to be “1” with a probability of {0/(3+1)}×100(%). The LUT(1) operates to determine the second dithering data Y[1] to be “1” with a probability of {1/(3+1)}×100(%). The LUT(2) operates to determine the second dithering data Y[1] to be “1” with a probability of {2/(3+1)}×100(%). The LUT(3) operates to determine the second dithering data Y[1] to be “1” with a probability of {3/(3+1)}×100(%). In this way, by activating any of LUT(0) to LUT(3), with the probability of any of 0(%), 25(%), 50(%), and 75(%), The dithering data Y[1] of 2 can be determined to be "1". That is, the probability of determining the second dithering data Y[1] as “1” can be made variable to any of 0(%), 25(%), 50(%), and 75(%). it can.
 本実施の形態の表示装置は、上記本実施の形態の表示データ生成装置を備える表示装置であって、表示データ生成装置で生成した第3の表示データDout[n]を取り込むか否かを選択する選択部を備えている構成である。この構成により、ディザリング処理を実行するか否かの選択が可能となり、種々の画像に対する画像処理の自由度がさらに向上する。選択部は、図1Aの構成において、例えば第3の表示データ生成部5と表示装置6との間の伝送線に直列に挿入配置することができる。選択部をスイッチ回路とし、スイッチ回路を閉状態(オン状態)とすることによって第3の表示データDout[n]を取り込むようにすることができる。スイッチ回路を開状態(オフ状態)とすることによって第3の表示データDout[n]を取り込まないようにすることができる。また、第3の表示データDout[n]を取り込まない場合、ディザリング処理をしていない表示データを表示装置6に入力してもよい。また、スイッチ回路を常時閉状態(オン状態)とすることによって第3の表示データDout[n]を常時取り込むようにすることができる。 The display device of the present embodiment is a display device including the display data generation device of the present embodiment, and selects whether to take in the third display data Dout[n] generated by the display data generation device. It is the structure provided with the selection part. With this configuration, it is possible to select whether or not to execute the dithering process, and the degree of freedom of image processing for various images is further improved. In the configuration of FIG. 1A, the selection unit can be inserted and arranged in series in the transmission line between the third display data generation unit 5 and the display device 6, for example. It is possible to capture the third display data Dout[n] by setting the selection unit as a switch circuit and closing the switch circuit (ON state). By setting the switch circuit to the open state (off state), the third display data Dout[n] can be prevented from being taken in. Further, when the third display data Dout[n] is not captured, the display data that has not been subjected to the dithering process may be input to the display device 6. Further, the third display data Dout[n] can be always taken in by setting the switch circuit to the normally closed state (on state).
 本開示の表示装置は、複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置であればよく、例えばLCD,有機EL(Electro Luminescence)装置、無機EL装置、プラズマディスプレイ、FED(Field Emitting Display)、SED(Surface-conduction Electron-emitter Display)、GLV(Grating Light Valve)装置、PDP(Plasma Display)装置、DMD(Digital micro Mirror Device)、圧電セラミックディスプレイ、マイクロLEDディスプレイなどの表示装置であってもよい。 The display device of the present disclosure may be a display device having a plurality of unit pixel portions and driven by an active matrix method, and may be, for example, an LCD, an organic EL (Electro Luminescence) device, an inorganic EL device, a plasma display, an FED (Field). Emitting Display), SED (Surface-conduction Electron-emitter Display), GLV (Grating Light Valve) device, PDP (Plasma Display) device, DMD (Digital micro Mirror Device), piezoelectric ceramic display, micro LED display, etc. It may be.
 なお、本開示の表示データ生成装置および表示装置は、上記実施の形態に限定されるものではなく、適宜の設計的な変更、改良を含んでいてもよい。 Note that the display data generation device and the display device of the present disclosure are not limited to the above-mentioned embodiment, and may include appropriate design changes and improvements.
 本開示は、次の実施の形態が可能である。 The present disclosure can have the following embodiments.
 本開示の表示データ生成装置は、複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置の前記単位画素部のそれぞれに、ディザリングデータを含む表示データを生成し供給する表示データ生成装置であって、複数ビットから成る2値化上位ビットデータと、1ビット以上から成る2値化下位ビットデータと、を有する第1の表示データを、生成する第1の表示データ生成部と、前記2値化上位ビットデータを第2の表示データとし、前記2値化下位ビットデータを第1のディザリングデータとして分離するデータ分離部と、前記第2の表示データに加算する第2のディザリングデータを、前記第1のディザリングデータのビット数および値に基づく確率で「1」に決定し、それ以外の場合は「0」に決定するとともに、前記確率を可変とする確率可変部を有する確率回路と、前記第2の表示データに前記第2のディザリングデータを加算して生成した第3の表示データを、前記表示装置に供給する第2の表示データ生成部と、を備える構成である。 A display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method. A first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more; A data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data. The ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided. And a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device. Is.
 本発明の表示データ生成装置は、前記確率回路は、前記第1のディザリングデータのビット数をm(mは自然数)、前記第1のディザリングデータの10進法による値をym、前記第1のディザリングデータの10進法による最大値をymaxとしたとき、{ym/(ymax+1)}×100(%)の確率で第2のディザリングデータを「1」に決定してもよい。 In the display data generating device of the present invention, the probability circuit is configured such that the number of bits of the first dithering data is m (m is a natural number), the decimal value of the first dithering data is ym, and the first dithering data is ym. When ymax is the maximum value of the dithering data of 1 in the decimal system, the second dithering data may be determined to be "1" with a probability of {ym/(ymax+1)}×100(%).
 また本開示の表示データ生成装置は、前記確率回路は、選択された(ymax+1)個のフレームのうちym個のフレームにおいて、前記第2のディザリングデータを「1」に決定してもよい。 In the display data generation device of the present disclosure, the probability circuit may determine the second dithering data to be “1” in ym frames of the selected (ymax+1) frames.
 また本開示の表示データ生成装置は、前記確率回路は、乱数発生部を備えており、前記乱数発生部は、前記(ymax+1)個のフレームのうち、前記第2のディザリングデータを「1」に決定するフレームを選択してもよい。 Further, in the display data generation device according to the present disclosure, the probability circuit includes a random number generation unit, and the random number generation unit sets the second dithering data to “1” in the (ymax+1) frames. The frame to be determined may be selected.
 また本開示の表示データ生成装置は、前記(ymax+1)個のフレームは、連続した(ymax+1)個のフレームであってもよい。 In the display data generation device of the present disclosure, the (ymax+1) frames may be continuous (ymax+1) frames.
 本開示の表示装置は、上記本開示の表示データ生成装置を備える表示装置であって、前記表示データ生成装置で生成した前記第3の表示データを取り込むか否かを選択する選択部を備えている構成である。 A display device according to the present disclosure is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure.
 本開示の表示データ生成装置は、複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置の前記単位画素部のそれぞれに、ディザリングデータを含む表示データを生成し供給する表示データ生成装置であって、複数ビットから成る2値化上位ビットデータと、1ビット以上から成る2値化下位ビットデータと、を有する第1の表示データを、生成する第1の表示データ生成部と、前記2値化上位ビットデータを第2の表示データとし、前記2値化下位ビットデータを第1のディザリングデータとして分離するデータ分離部と、前記第2の表示データに加算する第2のディザリングデータを、前記第1のディザリングデータのビット数および値に基づく確率で「1」に決定し、それ以外の場合は「0」に決定するとともに、前記確率を可変とする確率可変部を有する確率回路と、前記第2の表示データに前記第2のディザリングデータを加算して生成した第3の表示データを、前記表示装置に供給する第2の表示データ生成部と、を備える構成であることから、以下の効果を奏する。第2のディザリングデータを確率をもって「1」または「0」に決定する確率回路が、確率可変部を有していることから、種々の画像のディザリングを実施するにあたって、高画質化が容易になるとともにその自由度が向上する。すなわち、種々の画像の画質を向上させることが容易になる。また、表示装置の各画素部で画像表示に用いられる駆動用の表示データとしての第3の表示データを生成し表示装置に直接的に供給できるので、表示メモリ等の表示データを一旦記憶する大容量のメモリが不要となる。その結果、表示装置に転送する表示データの転送速度が速くなるとともに、消費電力が低減され、さらには低コストな表示装置となる、という効果も奏する。 A display data generation device of the present disclosure generates a display data including dithering data and supplies the display data including the dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method. A first display data generation unit for generating first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more; A data separating unit that separates the binarized upper bit data into second display data and the binarized lower bit data as first dithering data, and a second dither that adds the binarized lower bit data to the second display data. The ring data is determined to be “1” with a probability based on the number of bits and the value of the first dithering data, and is determined to be “0” in other cases, and a probability variable unit that makes the probability variable is provided. And a second display data generation unit that supplies third display data generated by adding the second dithering data to the second display data to the display device. Therefore, the following effects are achieved. Since the probability circuit that determines the second dithering data to “1” or “0” with probability has the probability varying unit, it is easy to improve the image quality when performing dithering of various images. The degree of freedom increases as That is, it becomes easy to improve the image quality of various images. Further, since it is possible to generate the third display data as the driving display data used for image display in each pixel portion of the display device and directly supply the third display data to the display device, it is possible to temporarily store the display data in the display memory or the like. Eliminates the capacity of memory. As a result, the display data transferred to the display device can be transferred at a high speed, the power consumption can be reduced, and the display device can be manufactured at low cost.
 本開示の表示データ生成装置は、前記確率回路は、前記第1のディザリングデータのビット数をm(mは自然数)、前記第1のディザリングデータの10進法による値をym、前記第1のディザリングデータの10進法による最大値をymaxとしたとき、{ym/(ymax+1)}×100(%)の確率で第2のディザリングデータを「1」に決定する場合、第1のディザリングデータのビット数mと10進法による値ymと10進法による最大値ymaxとを種々に設定することによって、確率を可変にすることができる。また、確率は最大でも{ymax/(ymax+1)}×100(%)となり、100(%)にはならないので、確率回路の中に用いるルックアップテーブル(LUT)等の小容量のメモリの数を抑えることができる。 In the display data generating device according to the present disclosure, the probability circuit is configured such that the number of bits of the first dithering data is m (m is a natural number), the decimal value of the first dithering data is ym, and When ymax is the maximum value of the dithering data of 1 in the decimal system, when the second dithering data is determined to be “1” with a probability of {ym/(ymax+1)}×100(%), The probability can be made variable by variously setting the bit number m of the dithering data, the decimal value ym, and the decimal maximum value ymax. Further, the maximum probability is {ymax/(ymax+1)}×100(%), which is not 100(%). Therefore, the number of small-capacity memories such as a lookup table (LUT) used in the probability circuit is Can be suppressed.
 また本開示の表示データ生成装置は、前記確率回路は、選択された(ymax+1)個のフレームのうちym個のフレームにおいて、前記第2のディザリングデータを「1」に決定する場合、選択されたフレームにおいてディザリング処理を実施することができる。その結果、ディザリング処理による高画質化の自由度が向上する。 Further, the display data generation device according to the present disclosure is selected when the probability circuit determines the second dithering data to be “1” in ym frames of the selected (ymax+1) frames. The dithering process can be performed on the selected frame. As a result, the degree of freedom in improving the image quality by the dithering process is improved.
 また本開示の表示データ生成装置は、前記確率回路は、乱数発生部を備えており、前記乱数発生部は、前記(ymax+1)個のフレームのうち、前記第2のディザリングデータを「1」に決定するフレームを選択する場合、不自然なグラデーション、色ムラが発生することを効果的に抑えることができる。 Further, in the display data generation device according to the present disclosure, the probability circuit includes a random number generation unit, and the random number generation unit sets the second dithering data to “1” in the (ymax+1) frames. When selecting the frame to be determined to, it is possible to effectively suppress the occurrence of unnatural gradation and color unevenness.
 また本開示の表示データ生成装置は、前記(ymax+1)個のフレームは、連続した(ymax+1)個のフレームである場合、すべてのフレームをディザリング処理の対象とすることができる。その結果、より効果的な高画質化ができる。 Further, in the display data generation device of the present disclosure, when the (ymax+1) frames are continuous (ymax+1) frames, all the frames can be the target of the dithering process. As a result, more effective image quality can be achieved.
 本開示の表示装置は、上記本開示の表示データ生成装置を備える表示装置であって、前記表示データ生成装置で生成した前記第3の表示データを取り込むか否かを選択する選択部を備えている構成である。この構成により、ディザリング処理を実行するか否かの選択が可能となり、種々の画像に対する画像処理の自由度がさらに向上する。 A display device according to the present disclosure is a display device including the display data generation device according to the present disclosure, and includes a selection unit that selects whether to capture the third display data generated by the display data generation device. It has a structure. With this configuration, it is possible to select whether or not to execute the dithering process, and the degree of freedom of image processing for various images is further improved.
 本開示の表示データ生成装置および表示装置は各種の電子機器に適用できる。その電子機器としては、自動車経路誘導システム(カーナビゲーションシステム)、船舶経路誘導システム、航空機経路誘導システム、スマートフォン端末、携帯電話、タブレット端末、パーソナルデジタルアシスタント(PDA)、ビデオカメラ、デジタルスチルカメラ、電子手帳、電子書籍、電子辞書、パーソナルコンピュータ、複写機、ゲーム機器の端末装置、テレビジョン、商品表示タグ、価格表示タグ、産業用のプログラマブル表示装置、カーオーディオ、デジタルオーディオプレイヤー、ファクシミリ、プリンター、現金自動預け入れ払い機(ATM)、自動販売機、ヘッドアップディスプレイ装置、プロジェクタ装置、デジタル表示式腕時計、スマートウォッチ、頭部装着型画像表示装置(Head Mounted Display device :HMD)などがある。 The display data generation device and display device of the present disclosure can be applied to various electronic devices. The electronic devices include car route guidance system (car navigation system), ship route guidance system, aircraft route guidance system, smartphone terminal, mobile phone, tablet terminal, personal digital assistant (PDA), video camera, digital still camera, electronic device. Notebooks, electronic books, electronic dictionaries, personal computers, copiers, terminal devices for game machines, televisions, product display tags, price display tags, industrial programmable display devices, car audio, digital audio players, facsimiles, printers, cash There are automatic teller machines (ATM), vending machines, head-up display devices, projector devices, digital display watches, smart watches, head mounted image display devices (Head Mounted Display device: HMD), etc.
 本開示は、その精神または主要な特徴から逸脱することなく、他のいろいろな形態で実施できる。したがって、前述の実施形態はあらゆる点で単なる例示に過ぎず、本開示の範囲は特許請求の範囲に示すものであって、明細書本文には何ら拘束されない。さらに、特許請求の範囲に属する変形や変更は全て本開示の範囲内のものである。 The present disclosure can be implemented in various other forms without departing from the spirit or the main feature. Therefore, the above-described embodiments are merely examples in all respects, and the scope of the present disclosure is set forth in the claims and is not bound by the specification text. Furthermore, all modifications and changes belonging to the scope of the claims are within the scope of the present disclosure.
1 第1の表示データ生成部
2 ディザリング部
3 データ分離部
4 確率回路
5 第2の表示データ生成部
6 表示装置
1 1st display data generation part 2 Dithering part 3 Data separation part 4 Stochastic circuit 5 2nd display data generation part 6 Display device

Claims (6)

  1.  複数の単位画素部を有しアクティブマトリックス方式で駆動される表示装置の前記単位画素部のそれぞれに、ディザリングデータを含む表示データを生成し供給する表示データ生成装置であって、
     複数ビットから成る2値化上位ビットデータと、1ビット以上から成る2値化下位ビットデータと、を有する第1の表示データを、生成する第1の表示データ生成部と、
     前記2値化上位ビットデータを第2の表示データとし、前記2値化下位ビットデータを第1のディザリングデータとして分離するデータ分離部と、
     前記第2の表示データに加算する第2のディザリングデータを、前記第1のディザリングデータのビット数および値に基づく確率で「1」に決定し、それ以外の場合は「0」に決定するとともに、前記確率を可変とする確率可変部を有する確率回路と、
     前記第2の表示データに前記第2のディザリングデータを加算して生成した第3の表示データを、前記表示装置に供給する第2の表示データ生成部と、を備える表示データ生成装置。
    A display data generation device that generates and supplies display data including dithering data to each of the unit pixel units of a display device having a plurality of unit pixel units and driven by an active matrix method,
    A first display data generation unit that generates first display data having binarized high-order bit data composed of a plurality of bits and binarized low-order bit data composed of 1 bit or more;
    A data separation unit that separates the binarized upper bit data as second display data and the binarized lower bit data as first dithering data;
    The second dithering data to be added to the second display data is determined to be "1" with a probability based on the number of bits and the value of the first dithering data, and is determined to be "0" in other cases. And a stochastic circuit having a probability varying unit for varying the probability,
    A display data generation device comprising: a second display data generation unit that supplies the second display data with the third display data generated by adding the second dithering data to the display device.
  2.  前記確率回路は、前記第1のディザリングデータのビット数をm(mは自然数)、前記第1のディザリングデータの10進法による値をym、前記第1のディザリングデータの10進法による最大値をymaxとしたとき、{ym/(ymax+1)}×100(%)の確率で第2のディザリングデータを「1」に決定する請求項1に記載の表示データ生成装置。 The stochastic circuit sets the number of bits of the first dithering data to m (m is a natural number), the decimal value of the first dithering data to ym, and the first dithering data to the decimal system. The display data generating device according to claim 1, wherein the second dithering data is determined to be "1" with a probability of {ym/(ymax+1)}×100(%), where ymax is a maximum value according to.
  3.  前記確率回路は、選択された(ymax+1)個のフレームのうちym個のフレームにおいて、前記第2のディザリングデータを「1」に決定する請求項2に記載の表示データ生成装置。 The display data generation device according to claim 2, wherein the probability circuit determines the second dithering data to be "1" in ym frames of the selected (ymax+1) frames.
  4.  前記確率回路は、乱数発生部を備えており、
     前記乱数発生部は、前記(ymax+1)個のフレームのうち、前記第2のディザリングデータを「1」に決定するフレームを選択する請求項3に記載の表示データ生成装置。
    The stochastic circuit includes a random number generator,
    The display data generation device according to claim 3, wherein the random number generation unit selects a frame that determines the second dithering data to be “1” from the (ymax+1) frames.
  5.  前記(ymax+1)個のフレームは、連続した(ymax+1)個のフレームである請求項3または4に記載の表示データ生成装置。 The display data generation device according to claim 3 or 4, wherein the (ymax+1) frames are continuous (ymax+1) frames.
  6.  請求項1~5のいずれか1項に記載の表示データ生成装置を備える表示装置であって、
     前記表示データ生成装置で生成した前記第3の表示データを取り込むか否かを選択する選択部を備えている表示装置。
    A display device comprising the display data generating device according to claim 1.
    A display device comprising a selection unit for selecting whether or not to capture the third display data generated by the display data generation device.
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Citations (2)

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Publication number Priority date Publication date Assignee Title
US20150279319A1 (en) * 2014-03-26 2015-10-01 Ati Technologies Ulc Spatial dithering for a display panel
WO2018104993A1 (en) * 2016-12-05 2018-06-14 Eizo株式会社 Information processing apparatus and program

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150279319A1 (en) * 2014-03-26 2015-10-01 Ati Technologies Ulc Spatial dithering for a display panel
WO2018104993A1 (en) * 2016-12-05 2018-06-14 Eizo株式会社 Information processing apparatus and program

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