WO2020160016A1 - Sacrificial protection layer for environmentally sensitive surfaces of substrates - Google Patents
Sacrificial protection layer for environmentally sensitive surfaces of substrates Download PDFInfo
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- WO2020160016A1 WO2020160016A1 PCT/US2020/015451 US2020015451W WO2020160016A1 WO 2020160016 A1 WO2020160016 A1 WO 2020160016A1 US 2020015451 W US2020015451 W US 2020015451W WO 2020160016 A1 WO2020160016 A1 WO 2020160016A1
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/68—Organic materials, e.g. photoresists
- H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0431—Apparatus for thermal treatment
- H10P72/0436—Apparatus for thermal treatment mainly by radiation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6508—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a liquid
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
- H10P14/6538—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
- H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P52/40—Chemomechanical polishing [CMP]
- H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0406—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0448—Apparatus for applying a liquid, a resin, an ink or the like
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/08—Planarisation of organic insulating materials
Definitions
- the present disclosure relates to substrate processing, and more particularly to systems and methods for adding and removing sacrificial protective layers to environmentally sensitive surfaces of substrates.
- Semiconductor processing systems may be used to perform treatments on substrates such as semiconductor wafers. During processing, the substrates are transported to and from different substrate processing tools for different treatments. During transfer and/or storage, surfaces of the substrates may be exposed to contaminants, ambient air, light, moisture, etc. Exposure during transfer and/or storage may cause defects, material modifications, and/or otherwise adversely impact a downstream process.
- a method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by using stimuli selected from a group consisting of ultraviolet (UV) light and heat.
- the co-polymer comprises a poly(aldehyde) co-polymer.
- the ceiling temperature is lower than room temperature.
- the method includes dispensing a casting solvent on the substrate prior to dispensing the solution on the substrate.
- the method includes adding a thermal catalyst to the solution prior to dispensing the solution.
- the thermal catalyst is selected from a group consisting of a thermal acid generator and a thermal base generator.
- the method includes adding a photocatalyst to the solution prior to dispensing the solution.
- the photocatalyst is selected from a group consisting of a photo acid generator and a photo base generator.
- the method includes adding a dye to the photocatalyst.
- d) includes dl) dispensing a thermal catalyst onto the sacrificial protective layer; and d2) heating the substrate to a temperature that is greater than a catalyzed co-polymer degradation temperature and less than an un-catalyzed co-polymer temperature.
- the method includes repeating dl) and d2) one or more times until the sacrificial protective layer is removed.
- the method includes d3) heating the substrate to a temperature that is greater than the un-catalyzed co-polymer temperature to remove remaining portions of the sacrificial protective layer.
- the thermal catalyst is selected from a group consisting of a thermal acid generator and a thermal base generator.
- the first treatment process is selected from a group consisting of deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, or modification of electrical properties of the substrate.
- the second treatment process is selected from a group consisting of deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, or modification of electrical properties of the substrate.
- a method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by exposing the substrate to an acidic vapor.
- the ceiling temperature is lower than room temperature.
- the method includes dispensing a casting solvent on the substrate prior to dispensing the solution on the substrate.
- the method includes, prior to b), performing a first treatment process on the substrate in a first substrate processing tool; performing a) and b) in the first substrate processing tool; performing d) in a second substrate processing tool; and performing a second treatment process on the substrate in the second substrate processing tool.
- the first treatment process is selected from a group consisting of deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, or modification of electrical properties of the substrate.
- the second treatment process is selected from a group consisting of deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, or modification of electrical properties of the substrate.
- FIG. 1 is a functional block diagram of an example of a substrate processing system including multiple substrate processing tools and a storage buffer according to the present disclosure
- FIG. 2A is a side cross-sectional view of an example of a substrate according to the present disclosure.
- FIG. 2B is a side cross-sectional view of an example of a substrate including a sacrificial protective layer according to the present disclosure
- FIG. 3A is a side cross-sectional view of an example of a substrate including a sacrificial protective layer and a first catalyst layer according to the present disclosure
- FIG. 3B is a side cross-sectional view of an example of a substrate including the sacrificial protective layer that is partially removed according to the present disclosure
- FIG. 3C is a side cross-sectional view of an example of a substrate including the sacrificial protective layer and a second catalyst layer according to the present disclosure
- FIG. 3D is a side cross-sectional view of an example of a substrate including the sacrificial protective layer that is further removed according to the present disclosure
- FIG. 4 is a flowchart of an example of a method for adding and removing a sacrificial protective layer from a substrate according to the present disclosure
- FIG. 5 is a flowchart of an example of a method for adding and removing a sacrificial protective layer from a substrate in steps to prevent collapse using a catalyst according to the present disclosure
- FIG. 6 is a functional block diagram of an example of a substrate processing chamber for adding and removing the sacrificial protective layer according to the present disclosure.
- FIG. 7 is a graph illustrating a thermographic analysis of an example of a process window for removing the sacrificial protective layer in steps using a catalyst according to the present disclosure.
- Substrate surfaces may be exposed to ambient conditions during semiconductor fabrication. Many of the substrate surfaces are sensitive to modification due to ambient or environmental exposure. The surface changes that occur can adversely impact a subsequent process and/or degrade device performance. This exposure phenomena may be referred to herein as queue time effects.
- FOUPS front opening unified pods
- FOUP may be modified to provide a controlled atmosphere during transfers of the substrates between the substrate processing tools.
- the FOUP may provide a molecular nitrogen atmosphere.
- Polymers have been used as barriers in several industries including food packaging and pharmaceuticals.
- the polymer film is applied and then later removed.
- the polymer film can be used to protect the surfaces of the substrates from environmental threats. At some point, however, the polymer film needs to be removed.
- Common removal processes include both dry plasma and/or wet clean processes. However, the removal processes tend to be aggressive and usually modify the surfaces of the substrates.
- Polymers that are stable at room temperature have been used in sacrificial polymer applications.
- poly(carbonates) can be used.
- relatively high temperatures are needed (i.e. 160°C to 300°C) to assist in chemical bond-breaking because the polymers are stable at room temperature.
- the removal process is slow because each chemical unit needs to be activated.
- these types of polymers include inadvertent, non-carbonate bonds (e.g. ether linkages) which, when decomposed, create non-volatile residues.
- inadvertent, non-carbonate bonds e.g. ether linkages
- these polymers have limited usefulness in applications where monolayer impurities cannot be tolerated. Pure poly(carbonates) are not currently available.
- T c is the equilibrium temperature between the co-polymer and its monomers.
- the term low T c refers T c values below room temperature.
- the co-polymers are thermodynamically unstable at room temperature. Instead, the low T c co-polymer is kinetically trapped to allow prolonged storage at room temperature. In some examples, the stable storage period is on the order of months or years.
- Low Tc co-polymers will rapidly de-polymerize to its monomer constituents if an end-group or main chain bond is broken. Thus, the co-polymer de-polymerizes in response to stimuli such as ultraviolet (UV) light, heat, or an acidic basic catalyst.
- UV ultraviolet
- the sacrificial protection layer provides protection for the exposed surfaces of the substrates during integrated circuit (IC) fabrication and/or after processing.
- the sacrificial protection layer protects sensitive thin film for extended periods when the substrate is exposed to ambient conditions by acting as a diffusion barrier to ambient contaminants and by blocking reactive surface sites.
- the sacrificial protection layer is removed at relatively low temperature without requiring the use of plasma or wet processing (which cause surface modification). The heat, UV light, and/or acidic basic catalysts trigger spontaneous de-polymerization and vaporization of the sacrificial protection layer. This type of removal process minimizes the impact on the sensitive surfaces of the substrate.
- substrate surfaces that can be sensitive to environmental queue time effects include silicon, silicon germanium, and germanium structures such as fins and nano wires, tungsten contacts, and/or other structures and materials.
- the low T c co-polymers are thermodynamically unstable at room temperature. Below T c , the material is a co-polymer. Above T c , the material includes two or more volatile monomers. Low T c co-polymers can be kinetically trapped at temperatures well above T c with excellent shelf- life. Stability is achieved by kinetically inhibiting the mechanism of de-polymerization.
- the low T c co-polymers include poly(aldehydes).
- a sacrificial protective layer including the low T c co-polymer onto environmentally sensitive surfaces of substrates such as semiconductor wafers.
- the sacrificial protective layer provides a barrier against atmospheric contaminants such as oxygen and water.
- the sacrificial protective layer provides a barrier against halogens such as fluorine which can outgas from FOUP carriers.
- the surfaces of the substrates have extended queue time stability by slowing the permeation (sorption and diffusion) of undesired contaminants to the surface.
- the sacrificial protective layer can block reactive sites on the surface.
- the low-T c co-polymers described herein can be readily removed at moderate temperatures ( ⁇ 150°C) by exposure to heat, UV light, acidic/basic catalysts, and/or acidic vapors.
- the catalyst includes a photocatalyst or a thermal catalyst.
- the photocatalyst includes a photo acid generator (PAG) or a photo base generator.
- the thermal catalyst includes thermal acid generator (TAG) or a thermal base generator.
- the catalysts cause the sacrificial protective layer to de-polymerize into volatile monomers in response to UV light and/or heat.
- the solution forming the co polymer is mixed with the photocatalysts or thermal catalysts when they are cast.
- a dye may be added to the solution before casting to control photon penetration depth and hence degradation depth when the PAG catalyst is used.
- the TAG or PAG catalyst is added as an additional layer above an un-catalyzed co-polymer layer prior to the removal of the sacrificial co-polymer layer.
- the un-catalyzed co-polymer has a higher degradation temperature than the catalyzed co-polymer. Therefore, partial degradation can be performed to prevent collapse of HAR structures.
- the temperature of the substrate is increased above the degradation temperature of the catalyzed co-polymer but below the degradation temperature of the un-catalyzed co-polymer.
- the volume of the catalyst that is applied may be used to control the vertical thickness of the un-catalyzed co-polymer that is removed in a step.
- the degraded monomer is removed faster than the diffusion/reaction of the catalyst.
- Low T c co-polymers have several advantages when used for the sacrificial protection layer.
- the low T c co-polymers such as poly(aldehydes) are simple to synthesize and only poly(aldehydes) are formed with no unwanted side products. Therefore, residue- free vaporization of the low T c co-polymer can be achieved.
- the sacrificial protective layer is applied in a substrate processing tool after processing and prior to exposure to ambient conditions during transfer or storage.
- the substrates may be exposed to ambient conditions during transfer to and/or storage in a storage buffer or other location. In other examples, the substrates may be exposed to ambient conditions during transfer from one substrate processing chamber or tool to another substrate processing chamber or tool.
- the sacrificial protective layer is removed. In some examples, removal of the sacrificial protective layer is performed in a substrate processing tool and then other processes are performed on the substrate in the same substrate processing tool without exposure to ambient conditions. In some examples, a single substrate has the sacrificial protection layer applied and removed a plurality of times during substrate processing.
- a substrate processing system 100 includes one or more substrate processing tools 102 (substrate processing tools 102-1 and 102-2 are shown for illustration purposes) and substrate buffer 130 or other substrate storage.
- Each of the substrate processing tools 102-1 and 102-2 includes a plurality of processing chambers 104-1, 104-2, ... and 104-M (collectively processing chambers 104) (where M is an integer greater than one).
- each of the processing chambers 104 may be configured to perform a substrate treatment.
- the substrates may be loaded into one of the processing chambers 104, processed, and then moved to one or more other ones of the processing chambers 104 and/or removed from the substrate processing tool 100 (e.g., if all perform the same treatment).
- Substrates to be processed are loaded into the substrate processing tools 102-1 and 102-2 via ports of a loading station of an atmosphere-to-vacuum (ATV) transfer module 108.
- the ATV transfer module 108 includes an equipment front end module (EFEM).
- EFEM equipment front end module
- the substrates are then transferred into one or more of the processing chambers 104.
- a transfer robot 112 is arranged to transfer substrates from loading stations 116 to load locks 120.
- a vacuum transfer robot 124 of a vacuum transfer module 128 is arranged to transfer substrates from the load locks 120 to the various processing chambers 104.
- the substrates may be transported outside of a vacuum environment.
- the substrates may be moved to a location for storage (such as the substrate buffer 130).
- the substrates may be moved directly from the substrate processing tool to another substrate processing tool for further processing or from the storage buffer 130 to another substrate processing tool for further processing.
- the sacrificial protective layer is applied in the substrate processing tool prior to transferring the substrate to the substrate buffer for storage or to another substrate processing tool. In other examples, the sacrificial protective layer is applied in another processing chamber (not associated with the substrate processing tool).
- the sacrificial protective layer Prior to performing another treatment on the substrate, the sacrificial protective layer is removed.
- the substrate may be transferred to the substrate processing tool 102-2 after a period of storage in the storage buffer 130 or after processing in the substrate processing tool 102-1.
- the sacrificial protective layer may be removed by one of the processing chambers in the substrate processing tool 102-2 or another processing chamber (not associated with the substrate processing tool 102-2).
- the sacrificial protective layer is applied by a processing chamber in the same substrate processing tool (that performed substrate treatment) prior to exposure to ambient conditions. Since the substrate processing tool operates at vacuum, exposure of the substrate to ambient conditions is prevented.
- the sacrificial layer is deposited after a wet clean process.
- oxides and residues may be removed by the wet clean process and the sacrificial layer is deposited in sequence prior to drying the wafer. In some examples, this process is not done under vacuum and is done without any exposure of the dry pristine surface to the ambient.
- the substrate is transported from the substrate processing tool to another processing chamber located outside of the substrate processing tool that adds the sacrificial protective layer.
- Using this approach limits or reduces the period of exposure of the substrate to ambient conditions. Exposure is limited to a brief period of transport from the substrate processing tool to the processing chamber where the sacrificial protective layer is applied. Storage of the substrate may be performed for longer periods without additional exposure to ambient conditions.
- the sacrificial protective layer may be removed prior to further processing.
- the sacrificial protective layer is removed in another substrate processing tool under vacuum conditions prior to substrate treatment in processing chambers of the same substrate processing tool.
- the substrate is transported to a processing chamber that removes the sacrificial protective layer and then to the substrate processing tool for further processing. This approach also limits exposure to ambient conditions between the processing chamber and the substrate processing tool or other environment.
- a sacrificial protective layer can be added to a substrate to prevent or reduce the effect of exposure of the substrate to ambient conditions.
- FIG. 2A a substrate 200 is shown.
- the substrate includes a layer 204 arranged on one or more underlying layers 212.
- the layer 204 includes features such as pillars 216 and trenches 220.
- the layer 204 can be planar and/or can have other types of features. As can be appreciated, a single material or two or more different types of materials or films may be exposed.
- a sacrificial protective layer 224 is deposited on the substrate 200 and covers the layer 204.
- the substrate 200 can be transported and/or stored in ambient conditions for extended periods with a significant reduction in or elimination of contamination ⁇
- the sacrificial protective layer 224 is removed by applying heat, UV light, exposing the substrate to acidic vapor and/or using a catalyst, as will be described further below.
- the sacrificial protective layer can be removed in one step as shown in FIGs. 2A and 2B or removed in steps to prevent collapse of features.
- a substrate 300 is shown to include a layer 304 arranged on one or more underlying layers 312.
- the layer 304 includes high aspect ratio (HAR) features such as pillars 316 and trenches 320.
- HAR high aspect ratio
- a sacrificial protective layer 324 (similar to FIG.2B) is deposited on the substrate 300 and covers the layer 304. After the sacrificial protective layer 324 is added, the substrate 300 can be transported and/or stored in ambient conditions for extended periods with a significant reduction in or elimination of contamination.
- a catalyst layer 310 is cast, sprayed, applied or deposited onto the sacrificial protective layer 324.
- the volume of catalyst solution that is used is determined by how much of the sacrificial protective layer 324 is to be removed.
- the substrate 300 is exposed to heat or UV light to activate the catalyst layer 310.
- the catalyst layer 310 locally lowers a temperature that is needed to remove a portion 340 of the sacrificial protective layer 324.
- the portion 340 of the sacrificial protective layer 224 is removed as shown in FIG. 3B.
- the process of incrementally removing the sacrificial protective layer 324 may include additional cycles of depositing the catalyst layer and/or may be done with a single catalyst layer by controlling the top down diffusion of catalyst and removing other portions of the sacrificial protective layer 324.
- a catalyst layer 344 is cast, sprayed, applied or deposited.
- heat or UV light is applied and another portion 350 of the sacrificial protective layer 324 is removed. The process continues until all of the sacrificial protective layer 324 is removed.
- the process for incrementally removing the sacrificial protective layer in a controlled manner reduces or prevents damage (such as collapse) to the features that otherwise may occur with a single step removal process. Collapse may occur as the triggered degradation causes the sacrificial protective layer to temporarily transition to a liquid-like material that collapses HAR structures due to capillary force prior to evaporation of the monomers.
- a method 400 for adding and removing the sacrificial protective layer from the substrate is shown.
- a process is performed on the substrate 200.
- the process includes deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, modification of electrical properties (e.g. doping and optionally annealing or exposure to ultraviolet (UV) light to alter the dielectric constant) or another process.
- the substrate is cleaned by performing a post processing rinse with a post rinse solution.
- dilute hydrofluoric (HF) acid or another solution is used to remove native oxide.
- the post rinse solution is optionally displaced by a casting solvent.
- a solution that will form the sacrificial protective layer is cast, sprayed, applied or deposited on the substrate.
- the solution includes the TAG catalyst.
- the solution includes the PAG catalyst and/or the dye.
- the substrate is optionally rotated or spun to dry the substrate.
- the substrate is transported and/or stored in an ambient environment.
- the method determines whether the sacrificial protective layer needs to be removed (e.g. when the substrate is ready for additional processing). If 436 is true, the substrate is transported to a processing chamber or substrate processing tool at 438. At 440, the sacrificial protective layer is removed.
- the sacrificial protective layer is removed using heat at a temperature in a predetermined temperature range from 50° C to 300° C. In some examples, the sacrificial protective layer is removed using heat at a temperature in a predetermined temperature range from 50° C to 150° C. In some examples, the sacrificial protective layer is removed using exposure to ultraviolet (UV) light.
- the catalyst is added to the solution forming the co-polymer. In some examples, the dye is also added to the solution when the photocatalyst is added to control degradation of the co-polymer. In other examples, an un-catalyzed co-polymer is deposited and the catalyst is dispensed onto the substrate during removal of the sacrificial protection layer (see FIG.
- the sacrificial protective layer is removed by exposure to an acidic vapor species.
- the acidic vapor includes hydrogen bromide (HBr) or other acidic vapor.
- HBr hydrogen bromide
- the temperature of the substrate is maintained at a pressure in a range from 5mT to 5000mT) and a temperature in a range from 0°C to 100°C.
- the temperature of the substrate is maintained at a pressure in a range from 750mT to 1500mT) and a temperature in a range from 35°C to 70°C.
- the temperature of the substrate is maintained at a pressure of lOOOmT and a temperature of 60°C.
- further processing of the substrate may be performed in a substrate processing tool, processing chamber or other location.
- a method 500 for adding the sacrificial protective layer to the substrate and sequentially removing the sacrificial protective layer in steps is shown.
- a process is performed on the substrate.
- the process includes deposition, etching, stripping, cleaning, chemical mechanical planarization (CMP), patterning, modification of electrical properties (e.g. doping and optionally annealing or exposure to ultraviolet (UV) light to alter the dielectric constant) or another substrate treatment process.
- the substrate is cleaned by performing a post processing rinse.
- the post rinse solution is optionally displaced with a casting solvent.
- a solution that will form the sacrificial protective layer is cast, sprayed, applied or deposited on the substrate.
- the substrate is optionally rotated or spun to dry the substrate.
- the substrate is ready to be transported and/or stored in an ambient environment.
- the method determines whether the substrate is ready for the sacrificial protective layer to be removed (for example prior to further processing). If 436 is true, the substrate is transported to a processing chamber or substrate processing tool at 438 where the sacrificial protective layer is removed. At 510, a solution that will form a catalyst layer is cast, sprayed, applied or deposited to the sacrificial protective layer. At 514, the sacrificial protective layer is partially removed by exposing the substrate to heat or UV light. At 518, the method determines whether the sacrificial protective layer has been fully removed. If not, the method continues at 520 and removes the remaining portion of the sacrificial protective layer using stimuli such as light or heat. In some examples, the heat or light is sufficient to remove the remaining portion of the sacrificial protecting layer in the absence of the catalyst. In other examples, the method returns to step 510 one or more times until the protective layer is gone.
- the un-catalyzed co-polymer has a higher degradation temperature than the catalyzed co-polymer. Therefore, partial degradation can be performed to prevent collapse of HAR structures.
- the temperature of the substrate is increased above the degradation temperature of the catalyzed co-polymer but below the degradation temperature of the un-catalyzed co-polymer.
- the dye can be used to limit degradation.
- a substrate processing chamber 600 for adding and removing the sacrificial protective layer is shown.
- a substrate processing chamber 604 includes a substrate support 608 that supports a substrate 610.
- a heater 622 may be used to heat the substrate support 608.
- the heater 622 includes one or more resistive heaters.
- coolant may be used alone or in combination with the heater 622 to heat and/or cool the substrate support 608.
- a motor 612 may be used to rotate the substrate support 608.
- a fluid delivery system 624 includes one or more fluid sources 626-1, 626-2, and 626-N (collectively fluid sources 626).
- the fluid sources 626 may supply liquid such as a solution that will form the sacrificial protective layer, a solution that will form the catalyst and/or other solutions.
- a vapor source 634 including an ampoule or bubbler can be used to supply a vapor such as HBr vapor via a valve 638.
- Outputs of the fluid sources 626 are delivered by valves 628-1, 628-2, ..., and 628-N (collectively valves 628) and a valve 630 to the processing chamber 604.
- a valve 652 and a pump 654 may be used to control pressure in the processing chamber 604 and/or to evacuate reactants from the processing chamber 604 as needed.
- a pressure sensor 658 may be used to sense pressure within the processing chamber 604.
- One or more light sources such as ultraviolet (UV) light sources 660 may be used to expose the substrate during processing.
- a controller 670 may be used to control the valve 652 and the pump 654, the valve 630, the valve 638, the fluid delivery system 624, the motor 612, and/or other components of the processing chamber 600. In some examples, the controller 670 controls pressure within the processing chamber based on feedback from sensors such as pressure sensors, temperature sensors and the like.
- a graph illustrates an example of a process window for removing a portion of the sacrificial protective layer using a catalyst.
- Portions of the sacrificial protective layer that are not catalyzed require a higher degradation temperature as compared to catalyzed portions of the sacrificial protective layer. Therefore, the catalyst layer can be used to incrementally remove portions of the sacrificial protective layer by controlling the temperature in a temperature window below the upper degradation temperature that will de-poly merize the sacrificial protective layer and above a lower degradation temperature that will de-poly merize the catalyzed sacrificial protective layer.
- the un-catalyzed co-polymer has a higher degradation temperature than the catalyzed co-polymer. Therefore, partial degradation can be performed to prevent collapse of HAR structures.
- the temperature of the substrate is increased above the degradation temperature of the catalyzed co-polymer but below the degradation temperature of the un-catalyzed co-polymer.
- the PAG catalyst is used with dye, the degradation using UV light is also limited by the dye.
- the catalyst is applied a limited number of times (e.g. once or a predetermined number of times) and the substrate is heated to the degradation temperature of the catalyzed co-polymer (once or a predetermined number of times), respectively. If the protective layer remains after a last one of the predetermined number of catalyst applications, the temperature of the substrate can be raised to the degradation temperature of the un-catalyzed co-polymer if needed to remove the remaining portion of the protective layer.
- a controller is part of a system, which may be part of the above-described examples.
- Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate.
- the electronics may be referred to as the“controller,” which may control various components or subparts of the system or systems.
- the controller depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
- temperature settings e.g., heating and/or cooling
- pressure settings e.g., vacuum settings
- power settings e.g., radio frequency (RF) generator settings
- RF matching circuit settings e.g., frequency settings, flow rate settings, fluid delivery settings, positional and operation settings
- the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like.
- the integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software).
- Program instmctions may be instmctions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system.
- the operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
- the controller in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof.
- the controller may be in the“cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing.
- the computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.
- a remote computer e.g.
- a server can provide process recipes to a system over a network, which may include a local network or the Internet.
- the remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer.
- the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control.
- the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein.
- An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
- example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- ALE atomic layer etch
- the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
Landscapes
- Formation Of Insulating Films (AREA)
- Chemical & Material Sciences (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Organic Chemistry (AREA)
- Wood Science & Technology (AREA)
- Materials Engineering (AREA)
- Engineering & Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Micromachines (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (7)
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| JP2021544131A JP7588078B2 (en) | 2019-01-29 | 2020-01-28 | Sacrificial protective layer for environmentally sensitive surfaces of substrates |
| KR1020257038903A KR20250172705A (en) | 2019-01-29 | 2020-01-28 | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
| CN202080011611.XA CN113366617B (en) | 2019-01-29 | 2020-01-28 | Sacrificial protective layer for environmentally sensitive surfaces of substrates |
| US17/310,303 US12119218B2 (en) | 2019-01-29 | 2020-01-28 | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
| KR1020217027191A KR102890564B1 (en) | 2019-01-29 | 2020-01-28 | Sacrificial protective layer for environmentally sensitive surfaces of substrates |
| SG11202108294UA SG11202108294UA (en) | 2019-01-29 | 2020-01-28 | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
| US18/826,414 US20240429040A1 (en) | 2019-01-29 | 2024-09-06 | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
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| US201962798015P | 2019-01-29 | 2019-01-29 | |
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| US18/826,414 Continuation US20240429040A1 (en) | 2019-01-29 | 2024-09-06 | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
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| US (2) | US12119218B2 (en) |
| JP (1) | JP7588078B2 (en) |
| KR (2) | KR102890564B1 (en) |
| CN (1) | CN113366617B (en) |
| SG (1) | SG11202108294UA (en) |
| TW (1) | TWI874349B (en) |
| WO (1) | WO2020160016A1 (en) |
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| JP2023539512A (en) * | 2020-09-01 | 2023-09-14 | 東京エレクトロン株式会社 | How to control semiconductor film thickness |
| US12119218B2 (en) | 2019-01-29 | 2024-10-15 | Lam Research Corporation | Sacrificial protection layer for environmentally sensitive surfaces of substrates |
| US12322588B2 (en) | 2019-09-04 | 2025-06-03 | Lam Research Corporation | Stimulus responsive polymer films and formulations |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20240173100A (en) | 2023-06-02 | 2024-12-10 | 김지훈 | Industrial Safety Locks |
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| KR102890564B1 (en) | 2025-11-24 |
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