WO2020159878A1 - Systèmes de connecteurs de câbles - Google Patents

Systèmes de connecteurs de câbles Download PDF

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Publication number
WO2020159878A1
WO2020159878A1 PCT/US2020/015224 US2020015224W WO2020159878A1 WO 2020159878 A1 WO2020159878 A1 WO 2020159878A1 US 2020015224 W US2020015224 W US 2020015224W WO 2020159878 A1 WO2020159878 A1 WO 2020159878A1
Authority
WO
WIPO (PCT)
Prior art keywords
connector
package
electrical
substrate
package surface
Prior art date
Application number
PCT/US2020/015224
Other languages
English (en)
Inventor
Norman S. Mcmorrow
Jonathan E. Buck
John A. Mongold
Chadrick P. Faith
Randall E. Musser
Original Assignee
Samtec, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2019/041356 external-priority patent/WO2020014449A1/fr
Priority claimed from PCT/US2019/055139 external-priority patent/WO2020076785A1/fr
Application filed by Samtec, Inc. filed Critical Samtec, Inc.
Publication of WO2020159878A1 publication Critical patent/WO2020159878A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/75—Coupling devices for rigid printing circuits or like structures connecting to cables except for flat or ribbon cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10356—Cables
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to connector systems. More specifically, the present invention relates to a connector system that allows connectors, with or without signal conditioning, to be connected to a substrate, such as a die package substrate.
  • Cable connector systems that connect cables to a host printed circuit board (PCB) are known.
  • the known cable connector systems include a board connector and a cable connector.
  • the known board connector is connected to the host PCB, and the known cable connector connects to the board connector. If more cables need to be connected to the host PCB, then more board connectors are added to the PCB, taking up valuable space on the host PCB.
  • embodiments of the present invention provide cutouts in a substrate that allow cable connectors to be connected in a stacked or nested configuration to a board connector mounted to a die package, while reducing the footprint and stack height required by the board connector.
  • embodiments of the present invention can be used in groups of connectors positioned on one or both opposed surfaces of a die package substrate or on one or both opposed sides of a second substrate that carries a die package and is attached to a host substrate.
  • the embodiments of the present invention can be used to collectively transmit at least 50 terabytes of data with frequency domain crosstalk of -40dB or better on a standard 70 mm by 70 mm die package, a 75mm by 75mm die package, a 120 mm by 120 mm die package, a 150 mm by 150 mm die package, or other sized die package.
  • Embodiments of the present invention can have a height, measured from a mounting surface of the PCB to a top surface of any one of the connectors described herein of about 1.5 mm to about 2.5 mm.
  • a connector system includes a host substrate with at least one cut out and a die package mounted on the host substrate and including a package substrate including a first package surface and a second package surface opposed to the first package surface, a die mounted on the first package surface, and an electrical connector mounted on the second package surface.
  • the electrical connector is located within the at least one cut out of the host substrate.
  • the connector system can further include an additional electrical connector mounted on the first package surface.
  • the connector system can further include a heatsink in thermal connection with the die.
  • the at least one cut out can be a through hole.
  • the at least one cut out can be a depression defined in the first package surface.
  • the electrical connector can be a board connector that is configured to receive a card edge of a second connector, the second connector can include signal conditioners, and the host substrate can be devoid of signal conditioners proximate to a radial area of approximately 10-mm around the electrical connector.
  • the electrical connector can be a board connector connected to the first package surface and a cable connector releasably connected to the board connector.
  • the connector system can further include cables, wherein each of the cables can include a first end connected to the cable connector and a second end connected to a corresponding first electrical panel connector.
  • the connector system can further include at least one stiffener arranged around the at least one cut out.
  • the die package can be mounted to the package substrate without an interposer.
  • the connector system can further include additional electronic components mounted to the second package surface.
  • a cable assembly includes a first electrical connector, a second electrical connector including an internal printed circuit board, and a cable electrically connecting the first and second electrical connectors.
  • the second electrical connector includes passive and/or active signal conditioners, including at least one of a DC capacitor, a DC resistor, or a transistor, positioned on the internal printed circuit board or inside a body of the second electrical connector.
  • the first electrical connector can include thirty-two differential signal pairs.
  • the cable assembly can further include thirty-one additional first electrical connectors, wherein the first electrical connector and the thirty-one additional first electrical connectors can fit within a panel area of 14.75 inch by 1.5 inch.
  • a host substrate includes circuit traces and a cut out that extends through a first surface and a second surface of the host substrate.
  • the cut out can be sized to receive an electrical connector attached to a die package substrate.
  • the electrical connector does not have to physically connect to the circuit traces of the host substrate.
  • the electrical connector does not have to physically touch the host substrate.
  • a die package includes electrical connectors positioned on a first package surface and a second package surface.
  • the electrical connectors fit within corresponding cut outs of a host substrate.
  • a die package includes a die package substrate including a first package surface and a second package surface, a die attached to the first package surface, a ball grid array attached to the second package surface, and electrical connectors attached to the second package surface but not the ball grid array.
  • Fig. 1 shows a host substrate, a die package with electrical connectors positioned on two opposing surfaces of a die package substrate, and a heat sink.
  • Fig. 2 shows a host substrate that defines cutouts and electrical connectors attached to a die package substrate.
  • Fig. 3 shows the host substrate of Figs. 1 and 2.
  • Figs. 4 and 5 show a first embodiment electrical connector that includes a first embodiment cable connector mated to a first embodiment board connector.
  • FIGs. 6 and 7 show a second embodiment electrical connector that includes a second embodiment cable connector mated to a second embodiment board connector.
  • Fig. 8 shows a third embodiment electrical connector that includes the second embodiment cable connector mated to a third embodiment board connector.
  • Fig. 9 shows a fourth embodiment electrical connector that includes the second embodiment cable connector mated to a fourth embodiment board electrical connector.
  • Fig. 10 shows a fifth embodiment electrical connector that includes the second embodiment cable connector mated to a fifth embodiment board connector.
  • FIG. 11 shows a sixth embodiment electrical connector that includes the second embodiment cable connector mated to a sixth embodiment board electrical connector.
  • Fig. 12 shows one of the second embodiment cable connectors.
  • Fig. 13 shows a front panel connector that can be attached via cable to any of the cable connector embodiments of Figs. 1-12.
  • Fig. 14 shows a cable system.
  • Fig. 1 shows a host substrate 5, cut outs 7 defined by the host substrate 5, optional stiffeners 9, electrical connectors 10, optional electrical components 13, a die package 15, a ball grid or SMT array 16, a die 17, a die package substrate 18, optional other chips 19, and an optional heat sink 20.
  • the die package 15 can include the die 17 and the die package substrate 18.
  • the die 17 and the other chips 19 can be electrically connected to a first package surface PI of the die package substrate 18.
  • a ball grid array 16 can be positioned on a second package surface P2 of the die package substrate 18.
  • the first package surface PI and the second package surface P2 of the die package substrate 18 can be parallel to one another and can be spaced apart from one another.
  • Electrical connectors 10 can be attached to one or both of the first and second package surfaces PI, P2 of the die package substrate 18.
  • the die package 15 can be attached to a first surface SI of a host substrate 5, and electrical components 13, such as bypass capacitors, can be attached to an opposing second surface S2 of the host substrate 5.
  • the optional other chips 19 can be serializer/deserializer (SERDES) chips.
  • the SERDES chips can include 16-by-16- lanes each, or any suitable number of lanes.
  • Electrical connectors 10, shown schematically in Fig. 1, can be connected to one or both of the first and second package surfaces PI, P2 of the die package 15 or die package substrate 18.
  • Each electrical connector 10 can include a vertical or right angle board connector attached to the die package substrate 18 and a cable connector attached to the board connector, as discussed below with respect to Figs. 4-12.
  • each electrical connector 10 can be a direct-attach cable connector attached to the die package substrate 18, such as the direct-attach cable connector disclosed in U.S. Patent Pub. No. 2019/0267732, hereby incorporated by reference in its entirety.
  • the heat sink 20 can be thermally connected to the die 17 and other chips 19, if used.
  • the electrical connectors 10 can be connected to the die package substrate 18 between the die package substrate 18 and the heat sink 20.
  • the host substrate 5 can be reinforced with stiffeners 9 around the cut outs 7, but the stiffeners 9 are not necessary.
  • At least one electrical connector 10 can be in electrical contact with the die 17 through the die package substrate 18. Placing the electrical connectors 10 directly on the die package 15 can eliminate trace losses from traces on or in the host substrate 5.
  • the first package surface PI can include a first group of electrical connectors 10, and the second package surface P2 can include a second group of electrical connectors 10.
  • the second package surface P2 can also define a pin or pad field that is electrically connected to the die 17 by ball grid array 16, surface mount, pin field, etc.
  • the pin or pad field can mate electrically with a power source, compression connector, pin connector, interposer, etc. (not shown).
  • the compression or pin connector can exclusively carry power, control, or other sideband signals to the die 17 or can carry high-speed signals as well.
  • components 13 can include SERDES (serializer/deserializer) chips, such as 16-by-16 lane SERDES chips.
  • SERDES serializer/deserializer
  • First and second edges of the die package substrate 18, which can be perpendicular or parallel to one another, can have the same respective lengths or can have different lengths.
  • the die package substrate 18 can be any suitable size, including approximately 145-mm-by-145- mm, measured along two intersecting first and second edges of the die package substrate 18.
  • the die package substrate 18 can have other sizes, including, for example, 70-mm-by-70-mm, 85-mm-by-85-mm, 120-mm-by-120-mm, 150-mm-by-150-mm, a 230-mm-by-230-mm, or any other suitable sizes including any particular size in the range of 70-mm to 230-mm square or 75- mm to 230-mm square.
  • the die package 15 and the die package substrate 18 are preferably square, but do not have to have sides of equal lengths and can have other shapes. The larger the area of the die package substrate 18, the more electrical connectors 10 can be added to the first and second package surfaces PI, P2.
  • Fig. 2 shows a total of eight electrical connectors 10 on the first package surface PI, with two electrical connectors 10 along each of the four edges of the die package substrate 18.
  • Fig. 2 includes, but does not show, another eight electrical connectors 10 on the second package surface, with two electrical connectors 10 along each of the four edges of the die package substrate 18. It is also possible to use more electrical connectors 10.
  • the first package surface PI can be populated with the die 17 and thirty-two electrical connectors 10, in two rows of four electrical connectors 10 per side of the die package substrate 18; and the second package surface P2 can also be populated with thirty-two electrical connectors 10, with two rows of four electrical connectors 10 per side of the die package substrate 18.
  • the electrical connectors 10 can each include one, two, three, or four rows of four differential signal pairs, or any other number of rows, contacts, or differential pairs.
  • the host substrate 5 can be, for example, a printed circuit board (PCB), and can include cut outs 7 arranged around where the die package 15 is attached to the host substrate 5.
  • Each cut out 7 may be a through hole in the die package substrate 18 that extends from the first package surface PI to the second package surface P2. Any number of cut outs 7 can be used.
  • each cut out 7 can be at least one depression in either of the first package surface PI or the second package surface P2, or a pair of depressions, one depression in the first package surface PI and other in the second package surface P2.
  • PCB printed circuit board
  • the cut outs 7 can provide relief for a corresponding electrical connector 10 positioned on a first package surface PI of the die package substrate 18. As shown in Fig. 2, one, two, or more than two electrical connectors 10 can be positioned within the perimeter of a corresponding cut out 7.
  • Fig. 3 shows the host substrate 5 of Figs. 1 and 2, with structures removed. Cut outs 7 are configured to receive at least one corresponding electrical connector 10, as discussed above.
  • Land grid array 21 is configured to receive a ball grid array 16 of the die package 15 or a power source, compression connector, pin connector, interposer, etc., as discussed above.
  • Figs. 4-11 show non-limiting, exemplary electrical connectors that can be used with cut outs 7 in a host substrate 5.
  • cable connectors discussed below can releasably mate with a corresponding board connector to electrically connect the cable connector to the die package 15, or cable connectors can physically connect to the die package substrate 18.
  • Another end of the cables of a respective one of the cable connectors can be connected to a front panel connector 1200, for example, shown in Fig. 12, to form a finished cable assembly.
  • the finished cable assembly can be attached on a first assembly end to a die package substrate 18 or a corresponding board connector and to a front panel of an enclosure on an opposed second assembly end.
  • Fig. 4 shows an electrical connector 10A that can include a board connector 110, a first embodiment first cable connector 120, a first embodiment second cable connector 130, and a plurality of cables 140.
  • the board connector 110 can attached to a suitable substrate (not shown but which could be the die package substrate 18 in Fig. 1), including, for example, a printed circuit board.
  • the board connector 110 can define a stair step shape, with a first connector mating interface 150 offset from and elevated from a second connector mating interface 160.
  • First board connector 110 can also be a right angle connector.
  • Each cable 140 can include a dielectric 142, a cable shield 144, and one or more cable conductors 190.
  • the first cable connector 120 can include six differential signal cables 140, and a second cable connector 130 can include six differential signal cables, for a total of twelve differential signal cables removably or permanently attached to each board connector 110.
  • the mated height H of the two-row electrical connector 10A can be approximately 3-mm.
  • a one-row electrical connector 10A can have a mated height H of approximately 1.5-mm.
  • a three-row electrical connector 10A can have a mated height of approximately 4.5-mm and a four-row electrical connector 10 can have a mated height H of approximately 6-mm. Height H can be measured orthogonally from a mounting interface 170 (Fig. 5) of a board connector 110 to the highest point on the board connector 110 that is parallel to the mounting interface 170.
  • Figs. 6 and 7 show an electrical connector 20A that can include a board connector 210 and four second embodiment cable connectors 240.
  • the board connector 210 can be attached to a suitable substrate (not shown in Figs. 6 and 7 but could be package substrate 18 in Fig. 1), including, for example, a PCB.
  • the board connector 210 can include a housing that can include a top housing 220 and a bottom housing 230.
  • the cable connectors 240 can include shielded, twin axial cables 250, and can be connected to the board connector 210, in order starting with the cable connector 240 closest to the substrate, or the cable connectors 240 can be simultaneously mated to the board connector 210.
  • the cable connectors 240 can be connected to the board connector 210 by inserting the cable connectors 240 from a direction parallel or substantially parallel, within manufacturing tolerances, to the surface of the substrate on which the board connector 210 is mounted.
  • Fig. 8 shows an electrical connector 40A that is similar to the electrical connector BOA shown in Figs. 6 and 7.
  • the electrical connector 40A can include a board connector 410 and four second embodiment cable connectors 440 with at least one differential signal cable 444.
  • the board connector 410 is attached to a suitable substrate 405, including, for example, a PCB or the package substrate 18 in Fig. 1.
  • the board connector 410 can include a top housing 420 and a bottom housing 430.
  • Fig. 9 show an electrical connector 50A that is similar to the electrical connector 40A shown in Fig. 8, except that the electrical connector 50A of Fig. 9 can include an overhang 590.
  • the electrical connector 50A in Fig. 9 can include a board connector 510 and four second embodiment cable connectors 540 with cables 544.
  • the board connector 510 can be attached to a suitable substrate 505, including, for example, a PCB or the package substrate 18 in Fig. 1.
  • the board connector 510 can include a top housing 520 and a bottom housing 540.
  • the height above the substrate 505 of the electrical connector 50A with the overhang 590 can be reduced compared to the height above the substrate of the electrical connector 40A without the overhang 590.
  • Fig. 10 shows an electrical connector 60A that is similar to the electrical connector 40A shown in Fig. 8, except that the electrical connector 60A only includes two second embodiment cable connectors 640, a board connector 610, and extruded, shielded twin axial cables 644.
  • the board connector 600 can be attached to a suitable substrate 605, including, for example, a PCB or the package substrate 18 in Fig. 1.
  • the board connector 600 can include a front housing 620 and a back housing 630.
  • Fig. 11 shows an electrical connector 70A that is similar to the electrical connector 60A shown in Fig. 10, except electrical connector 70A of Fig. 11 can include an overhang 790.
  • the electrical connector 70A can include a board connector 710 and two second embodiment cable connectors 740 including cables 744.
  • the board connector 710 can be attached to a suitable substrate 705, including, for example, a PCB or the package substrate 18 in Fig. 1.
  • the board connector 710 can include a front housing 720 and a back housing 730.
  • An overall height above the substrate 705 of the electrical connector 70A or the board connector 710, with the overhang 790, can be reduced compared to the height above the substrate 705 of the electrical connector 60A without the overhang.
  • Fig. 12 shows a second embodiment cable connector 440, such as those described herein with respect to Figs. 1-3 and 6-11.
  • the cable connector can be approximately 1-mm in height, and can include a main housing 412, a strain relief housing 414 that can include EMI absorbing material, cables 444, such as those described herein, a ground plane 460, and electrical signal conductors 470 than can be differential or single-ended.
  • the second assembly end of a finished cable assembly can be a first electrical panel connector 1200.
  • the first electrical panel connector 1200 can be, but is not required to be, a member of the ACCELERATE I/O connector family, commercially available from SAMTEC, Inc.
  • Cable 140 can be any of the cables described above.
  • each cable 140 can have a maximum outer diameter of 26-gauge, 27-guage 28-gauge, 29-guage, 30- gauge, 31-guage, 32-gauge, 33-gauge, 34-gauge, 35-gauge, or 36-gauge.
  • Each cable 140 can have a maximum diameter of about 2 mm to about 2.8 mm, within manufacturing tolerances.
  • a cable assembly can include a cable connector (Figs. 4-12) with a height approximately equal to 1.0 ⁇ 0.5 mm, a first electrical panel connector 1200, and a cable 140 electrically connected to both the electrical panel connector 1200 and the cable connector.
  • the cable 140 can have a maximum diameter of 34 or 35 or 36 gauge.
  • Frequency domain NEXT crosstalk of the cable assembly can be between -40 dB to -60 dB through frequencies up to and including 30 GHz, 35 GHz, or 40 GHz or under -40 dB through frequencies up to and including approximately 30 GHz.
  • Data rate is approximately equal to two times the frequency, so the cable assembly can pass approximately 60 Gbits/sec with under -40 dB of NEXT crosstalk.
  • the first electrical panel connector 1200 can be configured not to receive an edge card.
  • Fig. 14 shows a schematic of a cable system 1330.
  • the cable system 1330 can include a 1RU 1300 or other panel populated with first connectors 1310, such as the front panel connector 1200 shown in Fig. 13 or as described in connection with Fig. 13.
  • the first connectors 1310 are preferably devoid of internal printed circuit boards or paddle cards and do not receive printed circuit boards or paddle cards.
  • a first connector 1310 can have thirty-two differential signal pairs. Attached to the first connectors 1310 is a cable 1340, such as a shielded thirty-four gauge differential signal twin axial cable or any other cable described herein.
  • Second connectors 1320 Attached to opposite ends of the cables 1340 are second connectors 1320, such as electrical connectors having internal printed circuit boards or paddle cards or card edge plug type cable connectors.
  • Second connectors 1320 can include, but are not limited to, SFP, SFP+, QSFP, QSFP+, QSFP DD, or OSFP transceivers.
  • Electronic conditioning elements can be included on the internal printed circuit board or boards of the transceivers, instead of being included in the first connectors 9210 or on a host printed circuit board that carries the SFP, SFP+, QSFP, QSFP+,
  • the electronic conditioning elements can include passive elements such DC capacitors or resistors and/or can include active elements such as transistors.
  • a cable assembly according to Fig. 14 can therefore include a first connector 1310, a second connector 1320 that includes an internal printed circuit board, and a cable 1340 electrically connecting the first connector and the second connector.
  • the second connector 1320 can include passive signal conditioners, such as DC capacitors, DC resistors, etc., and/or can include active signal conditioners, such as transistors, etc. positioned on the internal printed circuit board or otherwise inside a body of the second connector 1320.
  • a benefit of this arrangement is that signal conditioning can be moved from the host substrate or printed circuit board or other electrical connectors that do not contain a PCB and put on the removable, finished cable assembly. This allows the system to be electrically tweaked by replacing the finished cable assembly and makes removing or changing the signal conditioners in the electrical path easier than reconfiguring the host substrate.
  • an electrical connector can be a board connector that is configured to receive a card edge of a second connector.
  • the second connector can include signal conditioners, and a host substrate can be devoid of signal conditions proximate to a radial area of at least or approximately 5-mm, 10-mm, 15-mm, 20-mm, 25-mm, 30-mm, 35- mm, 40-mm, etc. around the second connector.
  • a host substrate can be devoid of signal conditions proximate to a radial area of at least or approximately 5-mm, 10-mm, 15-mm, 20-mm, 25-mm, 30-mm, 35- mm, 40-mm, etc. around the second connector.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)

Abstract

L'invention concerne un système de connecteurs qui inclut un substrat hôte pourvu d'au moins une découpe et d'un groupe de puces monté sur le substrat et incluant un substrat de groupe incluant une première surface de groupe et une deuxième surface de groupe opposée à la première surface de groupe, une puce montée sur la première surface de groupe, et un connecteur électrique monté sur la deuxième surface de groupe. Le connecteur électrique est situé dans la ou les découpes du substrat hôte.
PCT/US2020/015224 2019-01-28 2020-01-27 Systèmes de connecteurs de câbles WO2020159878A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201962704052P 2019-01-28 2019-01-28
US62/704,052 2019-01-28
US201962813102P 2019-03-03 2019-03-03
US62/813,102 2019-03-03
US201962840731P 2019-04-30 2019-04-30
US62/840,731 2019-04-30
PCT/US2019/041356 WO2020014449A1 (fr) 2018-07-12 2019-07-11 Système de connecteur de câble
USPCT/US2019/041356 2019-07-11
PCT/US2019/055139 WO2020076785A1 (fr) 2018-10-09 2019-10-08 Systèmes connecteurs de câble
USPCT/US2019/055139 2019-10-08

Publications (1)

Publication Number Publication Date
WO2020159878A1 true WO2020159878A1 (fr) 2020-08-06

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3982400A1 (fr) * 2020-10-09 2022-04-13 Juniper Networks, Inc. Appareil, système et procédé d'utilisation de raidisseurs d'emballage pour fixer des ensembles câbles sur des circuits intégrés

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