WO2020157961A1

WO2020157961A1 - Artificial neural network learning device, distortion compensation circuit, and signal processing device

Info

Publication number: WO2020157961A1
Application number: PCT/JP2019/003645
Authority: WO
Inventors: 安藤　暢彦
Original assignee: 三菱電機株式会社
Priority date: 2019-02-01
Filing date: 2019-02-01
Publication date: 2020-08-06
Also published as: JPWO2020157961A1; JP6877662B2

Abstract

An artificial neural network learning device (31) is provided with: a signal supply unit (40) that supplies a plurality of training signals to a signal processing circuit (11); a signal memory (55) that stores a response signal output from the signal processing circuit (11); a memory control unit (51) that reads, from the signal memory (55), a plurality of selected signals which were randomly or pseudo-randomly selected, and supplies the plurality of selected signals to an artificial neural network structure (41) to cause a plurality of back distortion signals to be output from the artificial neural network structure (41); and a learning control unit (61). The learning control unit (61) updates a parameter group of the artificial neural network structure (41) by using a plurality of error signals indicating a difference between the plurality of selected signals and a plurality of teaching signals corresponding, respectively, to the plurality of back distortion signals, and executing adaptive processing based on a back propagation learning algorithm.

Description

Artificial neural network learning device, distortion compensation circuit and signal processing device

The present invention relates to a technique for learning an artificial neural network structure, and a technique for compensating for signal distortion generated in a signal processing circuit such as a high frequency circuit using the artificial neural network structure.

In recent years, artificial neural networks (Artificial Neural Networks) that imitate the neural network of the brain (Neural Networks) have been used in various technical fields such as image recognition, voice recognition, natural language processing, and machine translation. In the field of wireless communication, a communication module such as a wireless communication device includes a high frequency circuit including circuit elements such as a power amplifier and a filter, and the high frequency circuit is caused by the frequency characteristic of the high frequency circuit and the nonlinear input/output characteristic. Distortion (signal distortion) may occur in the output signal of the circuit. In order to suppress the deterioration of signal quality due to such signal distortion, a distortion compensation technique for canceling (compensating) the signal distortion generated in the high frequency circuit is generally used. In recent years, many distortion compensation techniques using artificial neural networks have been proposed. Hereinafter, the artificial neural network will be simply referred to as “ANN”.

For example, in Non-Patent Document 1 below, a distortion of a pre-distortion method that compensates for the non-linear characteristic of a power amplifier using a multi-layered ANN structure called RVTDNN (Real-Valued Time-Delay Neural Networks) is used. Compensation techniques are disclosed. The pre-distortion method is a distortion compensation technique of canceling the signal distortion generated in the high frequency circuit by previously applying distortion having an inverse characteristic to the signal to be input to the high frequency circuit.

The distortion compensation technique disclosed in Non-Patent Document 1 is an input layer (input layer) composed of a plurality of nodes, a hidden layer (hidden layer) composed of a plurality of nodes, and an output layer composed of two nodes. It uses a predistorter that operates based on the ANN structure configured with (output layer). The signal components respectively input to the plurality of nodes of the input layer propagate from the input layer to the nodes of the hidden layer, and then from the hidden layer to the nodes of the output layer. The weighting factors (weights) that determine the characteristics of the ANN structure are calculated by a machine learning algorithm called a back propagation algorithm (Back Propagation Learning Algorithm, BPLA).

In the conventional back-propagation learning algorithm, since the weighting coefficient of the ANN structure is updated based on the time series data output from the ANN structure, there is a problem that the learning efficiency (learning rate) of the ANN structure is low. Specifically, if the output signal of the ANN structure at a certain discrete time t _n (n is an integer) is represented by O(n), the output signals O(n), O( The weighting coefficient of the ANN structure is updated based on the time series data consisting of (n-1),..., O(n-Nb+1) (Nb is a positive integer). In general, the output signals O(i) and O(j) (i≠j) that are close in time are often highly correlated with each other. Therefore, if time series data is used when the conventional back propagation learning algorithm is executed, The weighting coefficient is updated using the output signal group having a high correlation. As a result, there is a problem that the convergence of the weighting coefficient of the ANN structure deteriorates, or the weighting coefficient of the ANN structure converges to a value that deviates from the solution that should originally converge.

In view of the above, an object of the present invention is to provide an artificial neural network learning device, a distortion compensation circuit, and a signal processing device that can improve the learning efficiency of the ANN structure.

An artificial neural network learning device according to an aspect of the present invention includes a signal supply unit that supplies a plurality of temporally continuous training signals to a signal processing circuit and outputs a plurality of response signals from the signal processing circuit, A signal memory that stores a response signal, and a plurality of selection signals that are randomly or pseudo-randomly selected from the plurality of response signals that are stored in the signal memory are read, and the plurality of selection signals are stored in an artificial neural network structure. A memory control unit that supplies a plurality of post-distortion signals from the artificial neural network structure and outputs a plurality of differences between the plurality of post-distortion signals and a plurality of teacher signals corresponding to the plurality of selection signals. And a learning control unit that updates the parameter group that determines the input/output characteristics of the artificial neural network structure by calculating an error signal and executing adaptive processing based on a back propagation learning algorithm using the plurality of error signals. It is characterized by

According to one aspect of the present invention, adaptive processing based on a back propagation learning algorithm is performed using a plurality of error signals indicating differences between a plurality of selection signals selected randomly or pseudo-randomly and a plurality of teacher signals. Therefore, the learning efficiency of the ANN structure can be improved.

It is a block diagram which shows schematic structure of the artificial neural network (ANN) learning system of Embodiment 1 which concerns on this invention. It is a figure showing the correspondence between processing time, a training signal, and a response signal. It is a figure showing an example of the correspondence of processing time, a response signal, a selection signal, a training signal, and a teacher signal (reference signal). It is a schematic diagram of a neural network model showing a specific example of an ANN structure. It is a figure for explaining an example of forward propagation processing. It is a schematic diagram of a neural network model showing another specific example of the ANN structure. 6 is a flowchart schematically showing an example of a procedure of learning processing according to the first embodiment. It is a block diagram which shows the schematic structure of the signal processing apparatus which has the learned ANN structure used as a distortion compensation circuit. It is a block diagram showing a schematic structure of a data processor which is an example of hardware constitutions of an ANN learning device. It is a block diagram which shows schematic structure of the signal processing apparatus of Embodiment 2 which concerns on this invention. It is a figure showing the correspondence between processing time, a pre-distortion signal, and a response signal. It is a figure showing an example of the correspondence of processing time, a response signal, a selection signal, a predistortion signal, and a reference signal. 9 is a flowchart schematically showing an example of a procedure of a learning process according to the second embodiment.

Hereinafter, various embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In addition, the components denoted by the same reference numerals throughout the drawings have the same configuration and the same function.

Embodiment 1.
FIG. 1 is a block diagram showing a schematic configuration of an artificial neural network (ANN) learning system 1 according to the first embodiment of the present invention. The artificial neural network learning system 1 shown in FIG. 1 includes a signal processing circuit 11 that performs digital signal processing and analog signal processing on an input signal, and an artificial neural network (ANN) including an artificial neural network (ANN) structure 41. The learning device 31 is provided. The ANN learning device 31 has a function of causing the ANN structure 41 to learn an inverse characteristic corresponding to a distortion characteristic that causes signal distortion in the signal processing circuit 11. The ANN structure 41 of the present embodiment is incorporated inside the ANN learning device 31, but instead of this, the ANN structure 41 may be arranged outside the ANN learning device 31.

As shown in FIG. 1, the signal processing circuit 11 includes a quadrature modulator (QM) 21, a D/A converter (DAC) 22, an up converter (UPC) 23, a high frequency circuit 24, a directional coupler 25, and a down converter. A converter (DNC) 26, an A/D converter (ADC) 27 and a quadrature demodulator (QD) 28 are provided. The quadrature modulator 21 receives a complex digital signal composed of an in-phase component and a quadrature component as input, and performs digital quadrature modulation on the complex digital signal to generate a digital modulation signal. The D/A converter 22 converts the digital modulation signal input from the quadrature modulator 21 into an analog signal, and the up converter 23 converts the analog signal into a high frequency band (for example, microwave band) signal. .. The high frequency circuit 24 performs analog signal processing on the output signal of the up converter 23 to generate a high frequency output signal TS. Examples of the high frequency circuit 24 include, but are not limited to, a high output power amplifier (High Power Amplifier, HPA).

A part of the high frequency output signal TS is fed back by the directional coupler 25. The down converter 26 converts the high frequency signal fed back from the directional coupler 25 into an analog signal in a lower frequency band, and the A/D converter 27 converts the analog signal into a digital signal. The quadrature demodulator 28 performs digital quadrature demodulation on the digital signal to generate a complex digital signal including an in-phase component and a quadrature component. The generated complex digital signal is transferred to the ANN learning device 31 as a response signal.

The configuration of the signal processing circuit 11 is not limited to the configuration shown in FIG. In the example of FIG. 1, a quadrature modulator 21 that performs digital quadrature modulation and a quadrature demodulator 28 that performs digital quadrature demodulation are used. There may be an embodiment in which the analog quadrature modulation circuit and the analog quadrature demodulation circuit are used without using the quadrature modulator 21 and the quadrature demodulator 28.

The ANN learning device 31 uses a signal memory 55 having a storage area 55a in which a plurality of temporally continuous training signals (discrete signals) are stored in advance for use in learning the ANN structure 41, and a signal of the signal memory 55. The memory control unit 51 controls the read operation and the signal write operation, and the signal supply unit 40 that supplies the training signal T(k) read from the signal memory 55 to the signal processing circuit 11. Here, the variable k of the training signal T(k) is an integer value representing discrete time, and the training signal T(k) is a complex digital signal composed of an in-phase component and a quadrature component. As the signal memory 55, for example, a non-volatile memory such as a flash memory and a volatile memory such as an SDRAM (Synchronous Dynamic Random Access Memory) may be used.

Between the signal processing circuit 11 and the ANN learning device 31, a wiring or a cable for transferring the training signal T(k) from the signal supply unit 40 of the ANN learning device 31 to the quadrature modulator 21 of the signal processing circuit 11 or the like. Transmission line (not shown) is provided.

The signal processing circuit 11 performs digital signal processing and analog signal processing on the series of training signals T(0), T(1), T(2),... Transferred from the signal supply unit 40 of the ANN learning device 31. A feedback signal, that is, response signals Y(0), Y(1), Y(2),... Is generated, and the response signals Y(0), Y(1), Y(2),. Forward. Between the ANN learning device 31 and the signal processing circuit 11, a transmission line such as a wire or a cable for transferring the response signal Y(k) from the quadrature demodulator 28 of the signal processing circuit 11 to the ANN learning device 31 (see FIG. (Not shown).

The ANN learning device 31 includes a signal receiving unit 60 that receives the response signal Y(k) transferred from the signal processing circuit 11. The signal memory 55 has a storage area 55b that stores the response signal Y(k) received by the signal receiving unit 60. As described later, the memory control unit 51 outputs the selection signal y _n (c) randomly or pseudo-randomly selected from the response signals Y(0), Y(1),... Stored in the storage area 55b. It is possible to read and supply the selection signal y _n (c) to the ANN structure 41 (c=0, 1,... ). The ANN structure 41 performs forward propagation processing on the selection signal y _n (c) input from the storage area 55b, and outputs the resulting complex digital signal as a post-distortion signal s _n (c). A specific example of the ANN structure 41 and the contents of the forward propagation processing will be described later.

FIG. 2 is a diagram showing the correspondence between the processing time t, the training signal T(k), and the response signal Y(k). Here, the processing time t is represented by an equation of t=T ₀ +k×ΔT. T ₀ is the reference time and ΔT is the processing time interval. In the example of FIG. 2, k is an integer in the range of 0 to K−1, and K is the response signal Y(0) to Y(K−1) stored in the storage area 55b of the signal memory 55. Is the number of As shown in the correspondence table of FIG. 2, the response signal Y(k) corresponding to the training signal T(k) is obtained at the processing time t=T ₀ +k×ΔT.

Referring to FIG. 1, the ANN learning device 31 further has a learning control unit 61. The learning control unit 61 has a function of updating the parameter group that defines the input/output characteristic (including the frequency characteristic) of the ANN structure 41 by executing the adaptive processing based on the back propagation learning algorithm. As shown in FIG. 1, the learning control unit 61 includes a subtractor 63, an adaptive processing unit 64, and a parameter setting unit 65.

When the adaptive processing is executed, the memory control unit 51 selects C pieces from the group of response signals Y(0) to Y(K-1) stored in the storage area 55b of the signal memory 55. The signals y _n (0) to y _n (C-1) are randomly or pseudo-randomly selected, and the selected signals y _n (0) to y _n (C-1) are supplied from the signal memory 55 to the ANN structure 41. .. Here, C is a positive integer smaller than the total number K of the response signals Y(0) to Y(K-1), and the subscript n is a positive integer indicating the number of iterations of the adaptive processing. The ANN structure 41 performs forward propagation processing on the selection signal y _n (c) input from the signal memory 55, and outputs the resulting complex digital signal as a post-distortion signal s _n (c). Further, the memory control unit 51 selects the selection signals y _n (0) to y _n (from the group of training signals T(0) to T(K−1) stored in the storage area 55a of the signal memory 55. C-1) corresponding to C training signals are selected, and the selected C training signals are used as teacher signals (reference signals) z _n (0) to z _n (C-1) in the signal memory 55. To the learning control unit 61.

FIG. 3 shows an example of a correspondence relationship among the processing time τ, the response signal Y(κ), the selection signal y _n (c), the training signal T(κ), and the teacher signal (reference signal) z _n (c). FIG. Here, the processing time τ is represented by an equation of τ=T ₀ +κ×ΔT, and κ is a random or pseudo-random integer (random number). The selection signal y _n (c) matches the response signal Y(κ) selected randomly or pseudo-randomly (y _n (c)=Y(κ)), and the teacher signal z _n (c) is the response signal It matches the training signal T(κ) corresponding to Y(κ) (z _n (c)=T(κ)).

The memory control unit 51 continuously generates a read address using a physical random number sequence or a pseudo random number sequence, and supplies the read address to the signal memory 55, thereby selecting the selection signal y _n (c) and the teacher signal z _n. The pair with (c) can be selected randomly or pseudo-randomly. When using the physical random number sequence, for example, the memory control unit 51 may read the data from the nonvolatile memory in which the data of the physical random number sequence is stored and use it. On the other hand, when the pseudo random number sequence is used, the memory control unit 51 only needs to have an arithmetic circuit or a function for calculating the pseudo random number sequence by a known pseudo random number generation algorithm. Such an arithmetic circuit can be realized by, for example, a random number generation circuit using a known linear feedback shift register, but is not limited to this.

Alternatively, the memory control unit 51 uses a physical random number sequence or a pseudo random number sequence to randomly or pseudo array the response signals Y(0) to Y(K-1) that are temporarily stored in the storage area 55b of the signal memory 55. You may rearrange in random order. Thus, the memory control unit 51 can obtain the selection signals y _n (0) to y _n (C-1) by reading C response signals from the signal memory 55 in the order of addresses.

The learning control unit 61 uses the selection signals y _n (0) to y _n (C-1) and the teacher signals z _n (0) to z _n (C-1) that are randomly or pseudo-randomly selected, The parameter group of the ANN structure 41 can be updated by executing the adaptive processing based on the back propagation learning algorithm. As a result, the learning control unit 61 can avoid performing adaptive processing using time-series data made up of highly correlated discrete signals, so that the convergence of the parameter group of the ANN structure 41 can be improved. .. Therefore, the learning efficiency of the ANN structure 41 can be improved.

Next, a specific example of the ANN structure 41 and forward propagation processing will be described before describing the back propagation learning algorithm. FIG. 4 is a schematic diagram showing a neural network model (NN model) 41A showing a specific example of the ANN structure 41.

The NN model 41A shown in FIG. 4 is a multi-layered neural network model composed of _P layers L ₁ to L _P. Here, P is an integer of 4 or more indicating the number of layers. The NN model 41A includes an input layer L _{1 to} which the in-phase component y _n ⁱ (c) and a quadrature component y _n ^q (c) of the input selection signal y _n (c) are input, and an intermediate layer (hidden layer) L 1. ₂ to L _P-1 and an output layer L _P that outputs the in-phase component s _n ⁱ (c) and the quadrature component s _n ^q (c) of the post-distortion signal s _n (c). In the example of FIG. 4, the number of intermediate layers is two or more, but one layer may be used instead.

Of the _P layers L ₁ to L _P in the NN model 41A, the p-th layer L _p has nodes N _p,1 to N _p,μ(p) imitating neurons of the neural network of the brain. And Here, the subscript p is a layer number, and the subscript μ(p) is a positive integer indicating the number of nodes in the p-th layer L _p . In the NN model 41A, the node of one layer and the node of the other layer of the two adjacent layers are coupled to each other, and a weighting factor (coupling weight) is assigned as the coupling strength between the nodes. A value called bias is assigned to each node. The parameter group that defines the input/output characteristics of the NN model 41A includes a weighting coefficient and a bias.

As shown in FIG. 4, the input layer L ₁ includes two nodes N _{1 to which} the in-phase component y _n ⁱ (c) and the quadrature component y _n ^q (c) of the selection signal y _n (c) are input, respectively. _{, 1} , N _{1, μ(1)} (μ(1)=2), the output layer L _P has an in-phase component s _n ⁱ (c) and a quadrature component of the post-distortion signal s _n (c). It has two nodes N _P,1 , N _P,μ(P ) that respectively output s _n ^q (c) (μ(P)=2).

FIG. 5 is a diagram for explaining an example of forward propagation processing. As shown in FIG. 5, the nodes N _p-1,1 to N _p-1,μ(p-1) in the p-1 th layer L _p-1 and the n th layer in the p th layer L _p The r-th node N _p,r is coupled. Here, r is an integer within the range of 1 to μ(p). As shown in FIG. 5, as the coupling strength between the nodes N _p-1,1 to N _p-1,μ(p-1) and the nodes N _p,r , the weighting factors w _r,1 ^{(p, p-1)} to w _r,μ(p-1) ^(p,p-1) are assigned. A bias b _r ^(p) is assigned to the node N _p,r .

At this time, the node N _p,r is the signal o propagated in the forward direction from the nodes N _p-1,1 to N _p-1,μ(p-1) in the p-1 th layer L _p-1 . Weighting factors w _r,1 ^(p,p-1) to w _r,μ(p-1) ^(p,p ⁾ for ₁ ^(p-1) to o _μ(p-1) ^(p-1) , respectively. ^-1) is multiplied, and the multiplication result and the bias b _r ^(p) are added. Further, the node N _p,r causes the activation function f[] to act on the addition result. As a result, node _{N p, r,} all the nodes _{_{N p + 1,1 ~ N p +}} 1 signals _{o r} ^(p) expressed by the equation, in the p + 1 th layer _{L p + 1} shown in FIG. _{5, mu (p + 1 )} To the forward direction. As the activation function f[], for example, a known activation function such as a sigmoid function or a hyperbolic tangent function may be used. The variable i in the mathematical formula shown in FIG. 5 is an integer in the range of 1 to μ(p−1).

The nodes N _P,1 , N _P,μ(P) (μ(P)=2) in the output layer L _P shown in FIG. 4 have the same phase component s as the signals o ₁ ^(P) and o ₂ ^(P) , respectively. _It is output as _n ⁱ (c) and the orthogonal component s _n ^q (c).

FIG. 6 is a schematic diagram showing a neural network model (NN model) 41B showing another specific example of the ANN structure 41. The NN model 41B shown in FIG. 6 is a multi-layered neural network model including delay elements D ₁ to D _M connected in series and P layers L ₁ to L _P. Here, M is a positive integer representing the number of delay elements D ₁ to D _M.

The group of delay elements D ₁ to D _M in the NN model 41B has M delay signals y _n (c-1) to y _n (c) with respect to the selection signal y _n (c) input to the NN model 41B. -M) is generated. The layered structure of the NN model 41B has in-phase components y _n ⁱ (c) to y _n ⁱ (c−M) and quadrature components y _n ^q (c) of signals y _n (c−1) to y _n (c−M). ) To y _n ^q (c−M) are input to the input layer L ₁ , intermediate layers (hidden layers) L ₂ to L _P−1, and the in-phase component s _n ⁱ (of the post-distortion signal s _n (c)). c) and an output layer L _P that outputs the orthogonal component s _n ^q (c). In the example of FIG. 6, the number of intermediate layers is two or more, but one layer may be used instead.

Similar to the case of the NN model 41A shown in FIG. 4, the p-th layer L _p of the _P layers L ₁ to L _P in the NN model 41B is a node N that imitates a neuron of the neural network of the brain. _p,1 to N _p,μ(p) . In the NN model 41B, a weighting factor (coupling weight) is assigned as the coupling strength between the node of one layer and the node of the other layer of the two adjacent layers. A value called bias is assigned to each node. The parameter group that defines the input/output characteristics of the NN model 41B includes a weighting coefficient and a bias.

Next, the operation of the ANN learning device 31 according to the first embodiment will be described below with reference to FIG. FIG. 7 is a flowchart schematically showing an example of the procedure of the learning process executed by the ANN learning device 31. When the ANN structure 41 tries to learn for the first time, the parameter group of the ANN structure 41 is initialized to a random value.

First, a process for obtaining a response signal group corresponding to the training signal group is executed (steps ST11 to ST13). At this time, the learning control unit 61 does not operate. Referring to FIG. 7, the memory control unit 51 reads the training signal T(k) from the storage area 55 a of the signal memory 55, and the signal supply unit 40 supplies the read training signal to the signal processing circuit 11. (Step ST11). At this time, the signal processing circuit 11 performs digital signal processing and analog signal processing on the training signal T(k) input from the ANN learning device 31 to generate a response signal Y(k), and the response signal Y(k). ) To the ANN learning device 31. The signal receiving unit 60 of the ANN learning device 31 receives the response signal Y(k) transferred from the signal processing circuit 11.

The memory control unit 51 stores the response signal Y(k) received by the signal receiving unit 60 in the storage area 55b of the signal memory 55 (step ST12).

Next, it is determined whether to start the adaptive processing (step ST13). For example, the memory control unit 51 counts the number of response signals Y(k) stored in the storage area 55b of the signal memory 55, and when the number reaches a predetermined number, determines to start the adaptive processing. Can be performed (YES in step ST13). When it is determined that the adaptive processing is not started (NO in step ST13), steps ST11 to ST12 are repeatedly executed. As a result, a series of training signals T(0), T(1), T(2),... Is supplied to the signal processing circuit 11, and a series of training signals T(0), T(1), T(2). A series of response signals Y(0), Y(1), Y(2),... Corresponding to,... Are stored in the storage area 55b of the signal memory 55.

When it is determined that the adaptive processing is started (YES in step ST13), the memory control unit 51 and the learning control unit 61 start the adaptive processing. When the first adaptation process is executed, the value of the iteration count n is initialized to 1.

Specifically, the memory control unit 51 reads the selection signals y _n (0) to y _n (C-1) selected at random or pseudo-randomly from the storage area 55b of the signal memory 55, and selects the selection signal y. supplying _n and _{(0) ~ y n (C} -1) to the ANN structure 41 (step ST14). As a result, the post-distortion signals s _n (0) to s _n (C-1) are output from the ANN structure 41. Further, the memory controller 51, from the storage area 55a of the signal memory 55, selection signal _y n _{(0) ~} _y n teacher signal _z n ₍₀₎ corresponding to the (C-1) ~ z n (C-1) Is read and the teacher signals z _n (0) to z _n (C-1) are supplied to the learning control unit 61 (step ST15). The subtractor 63 in the learning control unit 61 calculates the difference between the post-distortion signals s _n (0) to s _n (C-1) and the teacher signals z _n (0) to z _n (C-1). calculating an error signal indicating _{_{e n (0) ~ e n}} (C-1) ( step ST16). Note that in the example of FIG. 7, steps ST14, ST15, and ST16 are executed in this order for convenience of description, but the present invention is not limited to this. Steps ST14, ST15, ST16 may be executed in parallel with each other.

Then, the adaptive processing section 64 calculates a new parameter group of ANN structure 41 by executing the adaptive processing based on the back propagation learning algorithm using the error signal _{e n (0) ~ e n} (C-1) (Step ST17). Next, the parameter setting unit 65 updates the parameter group of the ANN structure 41 by setting the new parameter group as the parameter group of the ANN structure 41 (step ST18). As the back-propagation learning algorithm at this time, for example, a known algorithm such as a gradient descent method (Gradient Descent algorithm), a Gauss Newton algorithm (Gauss Newton algorithm) or a Levenberg-Marquardt algorithm is used. However, it is not particularly limited.

In step ST17, the adaptive processing unit 64 uses the new weighting factor as an element based on the n-th weighting factor group w _n having the current weighting factor as an element, for example, in accordance with the following equation (1). The weighting coefficient group w _n+1 can be calculated.
_{_{w n + 1 = w n -G}} [μ, e n] (1)
Here, the current weighting coefficient group w _n and the new weighting coefficient group w _n+1 can be expressed by a vector or a matrix, μ is a learning coefficient, and e _n is an error signal e _n (0) to e G(] is a vector having _n (C-1) as an element, and G[] is a function that determines the update amount by the back propagation learning algorithm.

After that, the adaptation processing unit 64 determines whether or not the iterative processing is to be ended (step ST19). When it is determined that the iterative process is not ended (NO in step ST19), the memory controller 51 and the learning controller 61 repeatedly execute steps ST14 to ST18. For example, if the number of iterations n reaches a predetermined number, or if a convergence condition indicating that the parameter group has sufficiently converged is satisfied, the adaptive processing unit 64 determines to end the iterative processing. Good (YES in step ST19). As the convergence condition, for example, the condition that the error evaluation value representing the magnitude of the error signal _{e n (0) ~ e n} (C-1) is equal to or less than a predetermined value continuously for a predetermined number of times and the like. For example, the error evaluation value, may be used absolute value or a value of the square of the absolute value obtained by adding the c = 0 ~ C-1 of the error signal e _{n (c).}

If it is determined that the iterative process is to be ended (YES in step ST19), and if learning of the ANN structure 41 is to be continued (NO in step ST20), the learning control unit 61 repeats the learning process after step ST11. Execute. When the learning of the ANN structure 41 is completed (YES in step ST20), the learning control unit 61 ends the learning process.

When the learning of the ANN structure 41 is completed, the learned ANN structure 41 can be used as a distortion compensation circuit. FIG. 8 is a block diagram showing a schematic configuration of a signal processing device 2 having an ANN structure 41 used as a distortion compensation circuit. The ANN structure 41 can previously compensate for signal distortion generated by the frequency characteristic and the nonlinear input/output characteristic of the high frequency circuit 24, and also compensates for a quadrature error (quadrature modulation error) generated in the quadrature modulator 21. can do. Ideally, the in-phase component and the quadrature component of the output signal of the quadrature modulator 21 should be in a state of being orthogonal to each other, but due to factors such as temperature conditions, the in-phase component and the quadrature component of the output signal may differ from the actual state. There may be an error from the ideal state. Such an error is an orthogonality error.

As described above, in the ANN learning system 1 according to the first embodiment, the ANN learning device 31 includes the selection signals y _n (0) to y _n (C-1) and the teacher signal z that are randomly or pseudo-randomly selected. _{Since the} adaptive processing based on the back propagation learning algorithm is executed using the error signals e _n (0) to e _n (C-1) indicating the difference between _n (0) to z _n (C-1), It is possible to avoid a decrease in the convergence of the parameter group of the ANN structure 41, or to prevent the parameter group from converging to a value that deviates from the solution that should originally converge. As a result, the learning efficiency of the ANN structure 41 can be improved.

Note that all or some of the functions of the ANN learning device 31 described above include, for example, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Integrated Circuit) integrated semiconductor circuit. Alternatively, it can be realized by a plurality of processors. Alternatively, all or some of the functions of the ANN learning device 31 are implemented by one or more processors including a computing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) that executes program code of software or firmware. May be realized. Alternatively, all or part of the functions of the ANN learning device 31 can be realized by a single processor or a plurality of processors including a combination of a semiconductor integrated circuit such as DSP, ASIC or FPGA and an arithmetic unit such as CPU or GPU. is there.

FIG. 9 is a block diagram showing a schematic configuration of a data processing device 80 which is a hardware configuration example of the ANN learning device 31. The data processing device 80 shown in FIG. 9 includes a processor 81, an input/output interface 84, a memory 82, a storage device 83, and a signal path 85. The signal path 85 is a bus for connecting the processor 81, the input/output interface 84, the memory 82, and the storage device 83 to each other. The input/output interface 84 can output the signal transferred from the processor 81 to the signal processing circuit 11 (FIG. 1) and has a function of transferring the signal input from the signal processing circuit 11 to the processor 81.

The memory 82 includes a work memory used when the processor 81 executes digital signal processing, and a temporary storage memory in which data used in the digital signal processing is expanded. For example, the memory 82 may be composed of a semiconductor memory such as a flash memory and an SDRAM. The memory 82 can be used as the signal memory 55 of FIG. Further, the storage device 83 can be used as a storage area for storing a program code of software or firmware to be executed by the arithmetic device when the processor 81 includes an arithmetic device such as a CPU or a GPU. For example, the storage device 83 may be composed of a non-volatile semiconductor memory such as a flash memory or a ROM (Read Only Memory).

In the example of FIG. 9, the number of processors 81 is one, but the number is not limited to this. The hardware configuration of the ANN learning device 31 may be realized by using a plurality of processors that operate in cooperation with each other.

Embodiment 2.
Next, a second embodiment according to the present invention will be described. FIG. 10 is a block diagram showing a schematic configuration of the signal processing device 3 according to the second embodiment of the present invention. The signal processing device 3 shown in FIG. 10 includes a signal processing circuit 11 that executes digital signal processing and analog signal processing on an input signal, and a distortion compensation circuit 13 that pre-compensates for signal distortion generated in the signal processing circuit 11. Is configured. The configuration of the signal processing circuit 11 shown in FIG. 10 is the same as the configuration of the signal processing circuit 11 shown in FIG. 1, so detailed description thereof will be omitted.

The distortion compensating circuit 13 of the present embodiment is a distortion compensating circuit including a so-called indirect learning mechanism (Indirect Learning Architecture). As shown in FIG. 3, the distortion compensation circuit 13 has a set of ANN structures, that is, a first ANN structure 42 and a second ANN structure 43. In the distortion compensation circuit 13, the input/output characteristic of the first ANN structure 42 (including the frequency characteristic) and the input/output characteristic of the second ANN structure 43 (including the frequency characteristic) match each other. By updating the parameter group defining the input/output characteristic and the parameter group defining the input/output characteristic of the second ANN structure 43, the first ANN structure 42 can be made to learn the inverse characteristic corresponding to the distortion characteristic of the signal processing circuit 11. .. The first ANN structure 42 and the second ANN structure 43 of this embodiment are configured by the same neural network model. A specific example of the neural network model is the

NN model

41A or 41B shown in FIG. 4 or 5, but the neural network model is not limited to this.

As shown in FIG. 10, the distortion compensation circuit 13 includes a signal receiving unit 60, a signal memory 55, a memory control unit 52, and a learning control unit 62 in addition to the first ANN structure 42 and the second ANN structure 43. The memory control unit 52 can control the signal reading operation and the signal writing operation of the signal memory 55.

An input signal (discrete signal) X(k), which is a complex digital signal including an in-phase component and a quadrature component, is supplied to the first ANN structure 42 from an external signal source (not shown). Here, the variable k of the input signal X(k) is an integer value representing discrete time. The first ANN structure 42 performs forward propagation processing on a plurality of time-sequential input signals X(0), X(1),..., And the complex digital signal obtained as a result is predistorted signal Z(0), Output as Z(1),.... The predistorted signals Z(0), Z(1),... Are transferred to the signal processing circuit 11 and the signal memory 55. The memory control unit 52 stores the predistorted signal Z(k) transferred from the first ANN structure 42 in the storage area 55 a of the signal memory 55.

The signal processing circuit 11 performs digital signal processing and analog signal processing on the series of pre-distorted signals Z(0), Z(1), Z(2),... Transferred from the first ANN structure 42 to provide a feedback signal, that is, a response. The signals Y(0), Y(1), Y(2),... Are generated and the response signals Y(0), Y(1), Y(2),. A transmission line (not shown) such as a wire or a cable for transferring the predistortion signal Z(k) and the response signal Y(k) is provided between the signal processing circuit 11 and the distortion compensation circuit 13. Has been.

When the signal receiving unit 60 receives the response signal Y(k) transferred from the signal processing circuit 11, the memory control unit 52 stores the response signal Y(k) in the storage area 55b of the signal memory 55. As will be described later, the memory control unit 52 outputs the selection signal y _n (c) randomly or pseudo-randomly selected from the response signals Y(0), Y(1),... Stored in the storage area 55b. The selected signal y _n (c) can be read and supplied to the second ANN structure 43 (c=0, 1,... ). The second ANN structure 43 performs forward propagation processing on the selection signal y _n (c) input from the storage area 55b, and outputs the resulting complex digital signal as a post-distortion signal s _n (c). ..

FIG. 11 is a diagram showing the correspondence between the processing time t, the pre-distortion signal Z(k) and the response signal Y(k). Here, the processing time t is represented by an equation of t=T ₀ +k×ΔT. T ₀ is the reference time and ΔT is the processing time interval. In the example of FIG. 11, k is an integer in the range of 0 to K−1, and K is the response signal Y(0) to Y(K−1) stored in the storage area 55b of the signal memory 55. Is the number of As shown in the correspondence table of FIG. 11, the predistortion signal Z(k) and the response signal Y(k) have a one-to-one correspondence.

The learning control unit 62 shown in FIG. 10 has a function of updating the parameter group of the first ANN structure 42 and the parameter group of the second ANN structure 43 by executing the adaptive processing based on the back propagation learning algorithm. The learning control unit 62 includes a subtractor 63, an adaptive processing unit 64, and a parameter setting unit 66. The configuration of the learning control unit 62 is the same as the configuration of the learning control unit 61 of the first embodiment, except that the parameter setting unit 65 of FIG. 1 is replaced by the parameter setting unit 66 of FIG. 10.

When the adaptive processing is executed, the memory control unit 52 selects C responses from the group of response signals Y(0) to Y(K-1) stored in the storage area 55b of the signal memory 55. The signal is randomly or pseudo-randomly selected, and the C selected response signals are supplied from the signal memory 55 to the second ANN structure 43 as selection signals y _n (0) to y _n (C-1). Here, C is a positive integer smaller than the total number K of the response signals Y(0) to Y(K-1), and the subscript n is a positive integer indicating the number of iterations of the adaptive processing. The second ANN structure 43 performs forward propagation processing on the selection signal y _n (c) input from the signal memory 55, and outputs the resulting complex digital signal as a post-distortion signal s _n (c). .. In addition, the memory control unit 52 selects C signals corresponding to the selection signals y _n (0) to y _n (C-1) from the group of predistortion signals stored in the storage area 55a of the signal memory 55. The pre-distortion signals of C are selected, and the selected C pre-distortion signals are output from the signal memory 55 to the learning control unit 62 as reference signals z _n (0) to z _n (C-1).

FIG. 12 is a diagram showing an example of a correspondence relationship among the processing time τ, the response signal Y(κ), the selection signal y _n (c), the predistortion signal Z(κ), and the reference signal z _n (c). is there. Here, the processing time τ is represented by an equation of τ=T ₀ +κ×ΔT, and κ is a random or pseudo-random integer (random number). The selection signal y _n (c) matches the response signal Y(κ) randomly or pseudo-randomly selected (y _n (c)=Y(κ)), and the reference signal z _n (c) is the response signal. It matches the pre-distortion signal Z(κ) corresponding to Y(κ) (z _n (c)=Z(κ)).

Like the memory control unit 51 of the first embodiment, the memory control unit 52 continuously generates the read address using the physical random number sequence or the pseudo random number sequence, and supplies the read address to the signal memory 55. , The selection signal y _n (c) and the reference signal z _n (c) can be selected randomly or pseudo-randomly. Alternatively, the memory control unit 52 randomly or pseudo-randomizes the array of the response signals Y(0) to Y(K-1) temporarily stored in the storage area 55b of the signal memory 55 using a physical random number sequence or a pseudo random number sequence. You may rearrange in random order. Thus, the memory control unit 52 can obtain the selection signals y _n (0) to y _n (C-1) by reading C response signals from the signal memory 55 in the order of addresses.

The learning control unit 62 uses the selection signals y _n (0) to s _n (C-1) selected randomly or pseudo-randomly and the reference signals z _n (0) to z _n (C-1). The parameter group of the first ANN structure 42 and the parameter group of the second ANN structure 43 can be updated by executing the adaptive processing based on the back propagation learning algorithm. As a result, the learning control unit 62 can avoid performing adaptive processing using time-series data made up of highly correlated discrete signals, and thus the convergence of the parameter groups of the first ANN structure 42 and the second ANN structure 43. Can be improved. Therefore, the learning efficiency of the first ANN structure 42 and the second ANN structure 43 can be improved.

Next, the operation of the learning process in the distortion compensation circuit 13 of the second embodiment will be described below with reference to FIG. FIG. 13 is a flowchart schematically showing an example of the procedure of the learning process executed by the distortion compensation circuit 13. When the first ANN structure 42 and the second ANN structure 43 try to learn for the first time, the parameter groups of the first ANN structure 42 and the second ANN structure 43 are initialized to random values.

The learning process is started when the first ANN structure 42 performs the forward propagation process on the input signal X(k) to generate the predistorted signal Z(k) (k=0, 1, 2,... ). The pre-distortion signal Z(k) is transferred to the signal processing circuit 11 and the signal memory 55. The memory control unit 52 of the distortion compensation circuit 13 stores the pre-distortion signal Z(k) generated by the first ANN structure 42 in the storage area 55a of the signal memory 55 (step ST21). When the signal receiving unit 60 receives the response signal Y(k) output from the signal processing circuit 11, the memory control unit 52 stores the response signal Y(k) in the storage area 55b of the signal memory 55 (step ST22). ).

Next, it is determined whether to start the adaptive processing (step ST23). For example, the memory control unit 52 counts the number of response signals Y(k) stored in the storage area 55b of the signal memory 55, and when the number reaches a predetermined number, determines to start the adaptive processing. Can be performed (YES in step ST23). When it is determined that the adaptive processing is not started (NO in step ST23), steps ST21 to ST22 are repeatedly executed. As a result, a series of pre-distortion signals Z(0), Z(1), Z(2),... Are stored in the storage area 55a of the signal memory 55, and a series of pre-distortion signals Z(0), Z(1). , Z(2),... A series of response signals Y(0), Y(1), Y(2),... Are stored in the storage area 55b of the signal memory 55.

When it is determined that the adaptive processing is started (YES in step ST23), the memory control unit 52 and the learning control unit 62 start the adaptive processing. When the first adaptation process is executed, the value of the iteration count n is initialized to 1.

Specifically, the memory control unit 52 reads the selection signals y _n (0) to y _n (C-1) selected at random or pseudo-randomly from the storage area 55b of the signal memory 55, and selects the selection signal y. _n _{(0) ~} y supplies n the (C-1) to the 2ANN structure 43 (step ST24). As a result, the post-distortion signals s _n (0) to s _n (C-1) are output from the second ANN structure 43. Further, the memory control unit 52 causes the reference signals z _n (0) to z _n (C-1) corresponding to the selection signals y _n (0) to y _n (C-1) from the storage area 55a of the signal memory 55. Is read and the reference signals z _n (0) to z _n (C-1) are supplied to the learning control unit 62 (step ST25). The subtracter 63 in the learning control unit 62 calculates the difference between the post-distortion signals s _n (0) to s _n (C-1) and the reference signals z _n (0) to z _n (C-1). calculating an error signal indicating _{_{e n (0) ~ e n}} (C-1) ( step ST26). Note that in the example of FIG. 13, steps ST24, ST25, and ST26 are executed in this order for convenience of description, but the present invention is not limited to this. Steps ST24, ST25, ST26 may be executed in parallel with each other.

Then, the adaptive processing unit 64, as in step ST17 in the first embodiment, executes the adaptive processing based on the back propagation learning algorithm using the error signal _{_{e n (0) ~ e n}} (C-1) Thereby, a new parameter group of the second ANN structure 43 is calculated (step ST27). Next, the parameter setting unit 66 updates the parameter group of the first ANN structure 42 and the second ANN structure 43 by setting the new parameter group as the parameter group of the first ANN structure 42 and the second ANN structure 43 (step ST28).

After that, the adaptation processing unit 64 determines whether or not to end the iterative processing (step ST29). When it is determined that the iterative process is not ended (NO in step ST29), the memory control unit 52 and the learning control unit 62 repeatedly execute steps ST24 to ST28. For example, if the number of iterations n reaches a predetermined number, or if a convergence condition indicating that the parameter group has sufficiently converged is satisfied, the adaptive processing unit 64 determines to end the iterative processing. Good (YES in step ST29). As the convergence condition, for example, the condition that the error evaluation value representing the magnitude of the error signal _{e n (0) ~ e n} (C-1) is equal to or less than a predetermined value continuously for a predetermined number of times and the like. For example, the error evaluation value, may be used absolute value or a value of the square of the absolute value obtained by adding the c = 0 ~ C-1 of the error signal e _{n (c).}

If it is determined that the iterative process is to be ended (YES in step ST29), if learning of the first ANN structure 42 and the second ANN structure 43 is to be continued (NO in step ST30), the learning control unit 62 causes the learning control unit 62 to perform step ST21. The subsequent learning process is executed again. When the learning of the first ANN structure 42 and the second ANN structure 43 is completed (YES in step ST30), the learning control unit 62 ends the learning process.

As described above, in the signal processing device 3 according to the second embodiment, the distortion compensation circuit 13 includes the selection signals y _n (0) to y _n (C-1) selected randomly or pseudo-randomly and the reference signal z. _{Since the} adaptive processing based on the back propagation learning algorithm is executed using the error signals e _n (0) to e _n (C-1) indicating the difference between _n (0) to z _n (C-1), The learning efficiency of the first ANN structure 42 and the second ANN structure 43 can be improved.

Note that all or some of the functions of the distortion compensation circuit 13 described above can be realized by a single or multiple processors having a semiconductor integrated circuit such as DSP, ASIC, or FPGA. Alternatively, all or some of the functions of the distortion compensation circuit 13 may be implemented by one or more processors including a computing device such as a CPU or GPU that executes program code of software or firmware. Alternatively, all or part of the function of the distortion compensation circuit 13 can be realized by one or more processors including a combination of a semiconductor integrated circuit such as DSP, ASIC or FPGA and an arithmetic unit such as CPU or GPU. is there. The hardware configuration of the distortion compensation circuit 13 may be realized by the data processing device 80 shown in FIG.

Although

various Embodiments

1 and 2 according to the present invention have been described with reference to the drawings,

Embodiments

1 and 2 are examples of the present invention, and various Embodiments other than

Embodiments

1 and 2 There can be forms. Within the scope of the present invention, it is possible to freely combine the first and second embodiments, modify any constituent element of each embodiment, or omit any constituent element of each embodiment.

For example, specific examples of the ANN structure 41, the first ANN structure 42, and the second ANN structure 43 are not limited to the

NN models

41A and 41B shown in FIGS. 4 and 6. For example, in place of the

NN models

41A and 41B, a known recurrent neural network model having feedback coupling (Recurrent Neural Network Model, RNN Model) may be used.

An artificial neural network (ANN) learning device, a distortion compensating circuit, and a signal processing device according to the present invention are, for example, high frequency radio transmitters or receivers in wireless communication systems such as mobile communication systems, digital broadcasting systems, and satellite communication systems. It can be used in a circuit (for example, a power amplifier).

1 artificial neural network (ANN) learning system, 2, 3 signal processing device, 11 signal processing circuit, 13 distortion compensation circuit, 21 quadrature modulator (QM), 22 D/A converter (DAC), 23 up converter (UPC) ), 24 high frequency circuit, 25 directional coupler, 26 down converter (DNC), 27 A/D converter (ADC), 28 quadrature demodulator (QD), 31 artificial neural network (ANN) learning device, 40 signal supply Part, 41 artificial neural network (ANN) structure, 41A, 41B neural network model (NN model), 42 first ANN structure, 43 second ANN structure, 51, 52 memory control unit, 55 signal memory, 55a, 55b storage area, 60 Signal receiving unit, 61, 62 learning control unit, 63 subtractor, 64 adaptive processing unit, 65, 66 parameter setting unit, 80 data processing device, 81 processor, 82 memory, 83 storage device, 84 input/output interface, 85 signal path ..

Claims

A signal supply unit that supplies a plurality of temporally continuous training signals to a signal processing circuit and outputs a plurality of response signals from the signal processing circuit,
A signal memory for storing the plurality of response signals,
From the plurality of response signals stored in the signal memory, a plurality of selection signals randomly or pseudo-randomly selected are read out, and the plurality of selection signals are supplied to the artificial neural network structure to output from the artificial neural network structure. A memory control unit for outputting a plurality of post-distortion signals,
An adaptive process based on a back-propagation learning algorithm is calculated by calculating a plurality of error signals indicating a difference between the plurality of post-distortion signals and a plurality of teacher signals corresponding to the plurality of selection signals. And a learning control unit that updates a parameter group that determines the input/output characteristics of the artificial neural network structure.
The artificial neural network learning device according to claim 1, wherein the learning control unit uses a plurality of signals selected from the plurality of training signals as the plurality of teacher signals. Neural network learning device.
The artificial neural network learning device according to claim 1 or 2, wherein the learning control unit sets the parameter groups so as to reduce the magnitudes of the plurality of error signals based on the back propagation learning algorithm. An artificial neural network learning device characterized by updating.
4. The artificial neural network learning device according to claim 3, wherein the memory control unit and the learning control unit read the plurality of selection signals from the signal memory, and the plurality of selection signals by the artificial neural network. An artificial neural network learning device, characterized in that the parameter group is converged by repeatedly executing the process of supplying the structure, the process of calculating the plurality of error signals, and the adaptive process.
The artificial neural network learning device according to any one of claims 1 to 4,
The artificial neural network structure includes a plurality of layers including an input layer to which the selection signal is input, an intermediate layer including at least one layer, and an output layer that outputs the post-distortion signal,
The learning control unit updates a weighting factor weighted for a signal propagating between the plurality of layers as the parameter group,
An artificial neural network learning device characterized by the above.
A first artificial neural network structure for generating a plurality of pre-distortion signals by inputting a plurality of temporally continuous discrete signals and outputting the generated plurality of pre-distortion signals to a signal processing circuit;
A signal memory that stores the plurality of pre-distortion signals and that stores the plurality of response signals output by the signal processing circuit in response to the input of the plurality of pre-distortion signals,
A second artificial neural network structure,
The plurality of selection signals randomly or pseudo-randomly selected from the plurality of response signals are read out from the signal memory, and the plurality of selection signals are supplied to the second artificial neural network structure to supply the second artificial neural network. A memory control unit that outputs a plurality of post-distortion signals from the structure and reads out, from the signal memory, a plurality of reference signals selected as signals corresponding to the plurality of selection signals from the plurality of pre-distortion signals,
An adaptive process based on a back propagation learning algorithm that calculates a plurality of error signals indicating a difference between the plurality of selection signals and the plurality of reference signals read from the signal memory and uses the plurality of error signals. And a learning control unit that updates the parameter groups that define the input/output characteristics of the first artificial neural network structure and the second artificial neural network structure.
7. The distortion compensation circuit according to claim 6, wherein the learning control unit sets the parameter groups so that the input/output characteristics of the first artificial neural network structure and the second artificial neural network structure match each other. A distortion compensation circuit characterized by updating.
The distortion compensation circuit according to claim 6 or 7, wherein the learning control unit updates the parameter group based on the back propagation learning algorithm so that the magnitudes of the plurality of error signals become small. A distortion compensation circuit characterized by the above.
The distortion compensation circuit according to claim 8, wherein the memory control unit and the learning control unit read the plurality of selection signals from the signal memory, and the plurality of selection signals are used in the second artificial neural network. The parameter group is converged by repeatedly executing a process of supplying the structure, a process of reading the plurality of reference signals from the signal memory, a process of calculating the plurality of error signals, and the adaptive process. A distortion compensation circuit characterized by the above.
The distortion compensation circuit according to any one of claims 6 to 9,
The first artificial neural network structure includes a first input layer to which the discrete signal is input, a first intermediate layer including at least one layer, and a first output layer to output the predistortion signal. Including multiple layers,
The second artificial neural network structure includes a second input layer to which the selection signal is input, a second intermediate layer including at least one layer, and a second output layer to output the post-distortion signal. Including multiple layers,
The learning control unit weights a signal propagating between the plurality of layers of the first artificial neural network structure and a signal that propagates between the plurality of layers of the second artificial neural network structure. And a weighting coefficient to be weighted to the parameter group are updated as the parameter group.
A distortion compensation circuit according to any one of claims 6 to 10,
A signal processing device comprising the signal processing circuit.
The signal processing device according to claim 11, wherein the signal processing circuit includes a power amplifier that amplifies the power of the plurality of predistorted signals.