WO2020152524A1

WO2020152524A1 - Semiconductor device and method for producing semiconductor device

Info

Publication number: WO2020152524A1
Application number: PCT/IB2019/060012
Authority: WO
Inventors: 山崎舜平; 佐藤優一; 種村和幸; 恵木勇司
Original assignee: 株式会社半導体エネルギー研究所
Priority date: 2019-01-25
Filing date: 2019-11-21
Publication date: 2020-07-30

Abstract

The present invention provides a semiconductor device which has a large On-state current. A semiconductor device which comprises a transistor, and which is configured such that the transistor comprises: a first conductor; a first insulating body that is arranged on the first conductor; a first oxide that is arranged on the first insulating body; a second conductor and a third conductor, which are arranged on the first oxide; a second oxide that is arranged on the first oxide so as to be positioned between the second conductor and the third conductor; a second insulating body that is arranged on the second oxide; and a fourth conductor that is arranged on the second insulating body. This semiconductor device is also configured such that: the upper surface of the first oxide in a region that overlaps with the fourth conductor is lower than the bottom surfaces of the second conductor and the third conductor; and the height difference between the upper surface of the second oxide in a region that overlaps with the fourth conductor and the bottom surface of the second conductor or the third conductor is smaller than the film thickness of the second oxide in the region that overlaps with the fourth conductor.

Description

Semiconductor device and method for manufacturing semiconductor device

One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Further, one embodiment of the present invention relates to a method for manufacturing a semiconductor device. Further, one embodiment of the present invention relates to a semiconductor wafer and a module.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one mode of the semiconductor device. It can be said that a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like has a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Further, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

-Technology for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has been receiving attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

In oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found (see Non-Patent Document 1 and Non-Patent Document 2).

Non-Patent Document 1 and Non-Patent Document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

One object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device in which variations in transistor characteristics are small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

Note that the description of these issues does not prevent the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that problems other than these are obvious from the description of the specification, drawings, claims, etc., and problems other than these can be extracted from the description of the specification, drawings, claims, etc. Is.

One embodiment of the present invention is a semiconductor device including a transistor, which includes a first conductor, a first insulator over the first conductor, and a first insulator over the first insulator. Between the oxide, the second conductor, and the third conductor on the first oxide, and on the first oxide, and between the second conductor and the third conductor. A second oxide, a second insulator over the second oxide, and a fourth conductor over the second insulator; and a first region in a region overlapping with the fourth conductor. Top surface of the second oxide is lower than bottom surfaces of the second conductor and the third conductor, and the top surface of the second oxide in a region overlapping with the fourth conductor and the second conductor or the third conductor. Difference from the bottom surface of the conductor is smaller than the film thickness of the second oxide in the region overlapping with the fourth conductor.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first conductor, a first insulator over the first conductor, and a first insulator over the first insulator. First oxide, a second conductor on the first oxide, and a third conductor, and a first oxide on the second conductor, and a third conductor A second oxide on the second oxide, a second insulator on the second oxide, and a fourth conductor on the second insulator, and overlaps with the fourth conductor. The top surface of the first oxide in the region is lower than the bottom surfaces of the second conductor and the third conductor, and the top surface of the first oxide in the region overlapping with the fourth conductor and the second conductor. The difference between the body and the bottom surface of the third conductor is 1 nm or more and 7 nm or less, and the thickness of the second oxide in a region overlapping with the fourth conductor is 1 nm or more and 5 nm or less.

In the above semiconductor device, the second oxide preferably contains indium.

In the above semiconductor device, the second oxide contains indium, an element M (M is gallium, aluminum, yttrium, or tin) and zinc, and the second oxide contains a main component. It is preferable that the atomic ratio of indium to the metallic element that is is larger than the sum of the atomic ratio of element M to the metallic element that is the main component and the atomic ratio of zinc to the metallic element that is the main component. .. The second oxide is In:Ga:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=10:1:3 [atomic ratio] or A metal oxide having a composition in the vicinity thereof is preferable.

In the above semiconductor device, the first oxide contains indium, the element M (M is gallium, aluminum, yttrium, or tin) and zinc, and the second oxide contains the main component. It is preferable that the atomic ratio of indium to the metal element that is is larger than the atomic ratio of indium to the metal element that is the main component in the first oxide.

Further, in the above semiconductor device, the second insulator has a structure in which the first insulating layer and the second insulating layer are sequentially stacked, and the first insulating layer contains silicon and the second insulating layer It is preferable that the insulating layer of (1) has one or both of hafnium and zirconium.

In addition, in the above semiconductor device, it is preferable that the semiconductor device has a region where the first insulator and the second insulator are in contact with each other in a cross-sectional view in the channel width direction of the transistor.

According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Further, according to one embodiment of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Further, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Further, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Further, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Further, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other effects from the description of the specification, drawings, claims, etc. Is.

FIG. 1A is a top view of a semiconductor device which is one embodiment of the present invention. 1B to 1D are cross-sectional views of a semiconductor device which is one embodiment of the present invention.
2A to 2C are cross-sectional views of a semiconductor device which is one embodiment of the present invention.
FIG. 3A is a diagram illustrating classification of crystal structures of IGZO. FIG. 3B is a diagram illustrating an XRD spectrum of quartz glass. FIG. 3C is a diagram illustrating an XRD spectrum of crystalline IGZO.
FIG. 4A is a top view of a semiconductor device which is one embodiment of the present invention. 4B to 4D are cross-sectional views of the semiconductor device which is one embodiment of the present invention.
FIG. 5A is a top view of a semiconductor device which is one embodiment of the present invention. 5B to 5D are cross-sectional views of the semiconductor device which is one embodiment of the present invention.
FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 13A is a top view illustrating a manufacturing method of a semiconductor device which is one embodiment of the present invention. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
15A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
16A and 16B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
FIG. 17 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
18 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
FIG. 19 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
20 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
21A and 21B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
22 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
FIG. 23 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
24A is a block diagram illustrating a structural example of a memory device according to one embodiment of the present invention. FIG. 24B is a schematic diagram illustrating a configuration example of the memory device according to one embodiment of the present invention.
25A to 25H are circuit diagrams each illustrating a structural example of a memory device according to one embodiment of the present invention.
FIG. 26 is a diagram showing various storage devices layer by layer.
FIG. 27A is a block diagram of a semiconductor device according to one embodiment of the present invention. FIG. 27B is a schematic diagram of a semiconductor device according to one embodiment of the present invention.
28A and 28B are diagrams illustrating an example of an electronic component.
29A to 29E are schematic views of a memory device according to one embodiment of the present invention.
30A to 30H are diagrams illustrating electronic devices according to one embodiment of the present invention.

Embodiments will be described below with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different modes, and the form and details can be variously changed without departing from the spirit and the scope thereof. It Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Also, in the drawings, the size, the layer thickness, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, or the like may be unintentionally reduced due to a process such as etching, but this may not be reflected in the drawing for easy understanding. In the drawings, the same reference numerals are commonly used in different drawings for the same portions or portions having similar functions, and repeated description thereof may be omitted. Further, when referring to the same function, the hatch patterns may be the same and may not be given a reference numeral in particular.

In addition, in order to facilitate understanding of the invention, in some cases, particularly in top views (also referred to as “plan views”) and perspective views, description of some components may be omitted. In addition, description of some hidden lines may be omitted.

Also, in this specification and the like, the ordinal numbers given as the first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, “first” can be replaced with “second” or “third” as appropriate. In addition, the ordinal numbers described in this specification and the like may be different from the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification and the like, terms such as “above” and “below” indicating a layout are used for convenience in order to explain the positional relationship between components with reference to the drawings. Further, the positional relationship between the components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, and can be paraphrased appropriately according to the situation.

For example, in this specification and the like, when it is explicitly described that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function The case where they are electrically connected and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also disclosed in the drawing or the text. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And a region (hereinafter also referred to as a channel formation region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), A current can flow between the source and the drain via the channel formation region. Note that in this specification and the like, a channel formation region refers to a region in which a current mainly flows.

Also, the functions of the source and drain may be switched when adopting transistors of different polarities or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be interchanged in some cases.

Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or a source in a channel formation region. The distance between (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the channel formation region.

The channel width is, for example, in a top view of a transistor, in a channel length direction in a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other or a channel formation region. Refers to the length of the channel formation region in the vertical direction. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the channel formation region.

Note that in this specification and the like, depending on the structure of a transistor, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and a channel width shown in a top view of the transistor. (Hereinafter, also referred to as “apparent channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and the effect thereof may not be negligible. For example, in a transistor which is fine and whose gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the semiconductor shape is known. Therefore, it is difficult to measure the effective channel width accurately when the shape of the semiconductor is not known accurately.

In this specification, when simply described as channel width, it may indicate an apparent channel width. Alternatively, in this specification, when simply described as a channel width, it may indicate an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that the impurities of the semiconductor refer to, for example, components other than the main constituents of the semiconductor. For example, an element whose concentration is less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main component, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity. In addition, oxygen vacancies (may be referred to as V 2 _O ) may be formed in the oxide semiconductor due to the mixture of impurities.

Note that in this specification and the like, silicon oxynitride has a higher oxygen content than nitrogen as its composition. Further, silicon oxynitride has a composition that contains more nitrogen than oxygen.

In addition, in this specification and the like, the term “insulator” can be restated as an insulating film or an insulating layer. In addition, the term "conductor" can be referred to as a conductive film or a conductive layer. Further, the term "semiconductor" can be restated as a semiconductor film or a semiconductor layer.

In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 degrees to 10 degrees. Therefore, a case of -5 degrees or more and 5 degrees or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 degrees or more and 30 degrees or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. In addition, “generally vertical” means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the term “OS transistor” is used, it can be referred to as a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 μm of the channel width flowing in the transistor is 1×10 ⁻ at room temperature. ^It means ²⁰ A or less, 1×10 ⁻¹⁸ A or less at 85° C., or 1×10 ⁻¹⁶ A or less at 125° C.

(Embodiment 1)
In this embodiment, an example of a semiconductor device including the transistor 200 of one embodiment of the present invention and a manufacturing method thereof will be described.

<Example of configuration of semiconductor device>
1A to 1D are a top view and a cross-sectional view of a semiconductor device including a transistor 200. FIG. 1A is a top view of the semiconductor device. 1B to 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction. 1C is a cross-sectional view of a portion indicated by dashed-dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. Further, FIG. 1D is a cross-sectional view of a portion indicated by an alternate long and short dash line of A5-A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for the sake of clarity.

A semiconductor device of one embodiment of the present invention includes an insulator 211 over a substrate (not shown), an insulator 212 over the insulator 211, an insulator 214 over the insulator 212, and a transistor 200 over the insulator 214. And an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, and an insulator 284 over the insulator 283. The insulator 211, the insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 function as an interlayer film. Further, the conductor 240 (the conductor 240a and the conductor 240b) which is electrically connected to the transistor 200 and serves as a plug is included. Note that the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with the side surface of the conductor 240 which functions as a plug. Further, a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and serves as a wiring is provided over the insulator 284 and the conductor 240. An insulator 286 is provided over the conductor 246 and the insulator 284.

The insulator 241a is provided in contact with the inner walls of the openings of the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, and the insulator 284, and the conductor 240a is provided in contact with the side surface of the insulator 241a. The first conductor is provided, and the second conductor of the conductor 240a is further provided inside. Further, the insulator 241b is provided in contact with the inner walls of the openings of the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, and the insulator 284, and the conductor is provided in contact with the side surface of the insulator 241b. The first conductor of 240b is provided, and the second conductor of the conductor 240b is provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 in a region overlapping with the conductor 246 can be approximately the same. Although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may have a single-layer structure or a stacked structure including three or more layers. When the structure has a laminated structure, an ordinal number may be given in order of formation to distinguish them.

[Transistor 200]
As illustrated in FIGS. 1A to 1D, the transistor 200 includes an insulator 216 over an insulator 214, an insulator 214, or a conductor 205 (a conductor 205a and a conductor 205) provided so as to be embedded in the insulator 216. 205b), insulator 216 and insulator 222 on conductor 205, insulator 224 on insulator 222, oxide 230a on insulator 224, oxide 230b on oxide 230a, The conductor 242 (the conductor 242a and the conductor 242b) and the oxide 230c over the oxide 230b, the insulator 250 over the oxide 230c, and a portion of the oxide 230c which is located over the insulator 250 and Overlapping conductor 260 (conductor 260a and conductor 260b), part of the top surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, the top surface of the conductor 242a, and the conductivity. The insulator 272 is in contact with the side surface of the body 242b and the top surface of the conductor 242b, and the insulator 273 over the insulator 272. The oxide 230c is in contact with the side surface of the conductor 242a and the side surface of the conductor 242b, respectively. Here, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 is arranged so as to substantially match the upper surfaces of the insulator 250 and the oxide 230c. The insulator 282 is in contact with the top surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280, respectively.

An opening reaching the oxide 230b is provided in the insulator 280, the insulator 273, and the insulator 272. The oxide 230c, the insulator 250, and the conductor 260 are arranged in the opening. Further, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, and the oxide 230c are provided between the conductor 242a and the conductor 242b. The insulator 250 has a region overlapping with a side surface of the conductor 260 and a region overlapping with a bottom surface of the conductor 260. The oxide 230c has a region in contact with the oxide 230b, a region overlapping with a side surface of the conductor 260 with the insulator 250 interposed therebetween, and a region overlapping with a bottom surface of the conductor 260 with the insulator 250 interposed therebetween.

The oxide 230 is disposed over the insulator 224, the oxide 230b, the oxide 230b, the oxide 230b, the oxide 230b, and the oxide 230b. And the oxide 230c in contact therewith. By including the oxide 230a under the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed below the oxide 230a can be suppressed. In addition, by including the oxide 230c over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.

Note that, in the transistor 200, the oxide 230 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked; however, the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. Each of the object 230a, the oxide 230b, and the oxide 230c may have a laminated structure.

The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 222 and the insulator 224 function as a second gate insulator. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of a source and a drain. In addition, the oxide 230 functions as a channel formation region.

In the transistor 200, a metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, and the oxide 230c). ..

The metal oxide that functions as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap in this manner, off-state current of the transistor can be reduced.

A transistor using a metal oxide in a channel formation region has a very small leak current in a non-conduction state, so that a semiconductor device with low power consumption can be provided. Since the metal oxide can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

When an oxide semiconductor is used for a channel formation region of a transistor, it is preferable to use an i-type (intrinsic) or substantially i-type oxide semiconductor having a low carrier concentration. By using an oxide semiconductor having a low carrier concentration in a channel formation region of a transistor, off-state current of the transistor can be suppressed low and reliability of the transistor can be improved.

As described later, in the case where an element contained in the conductive layer 242b provided so as to be in contact with the oxide 230b has a function of absorbing oxygen of the oxide 230b, the oxide is present between the oxide 230b and the conductive layer 242b or is oxidized. A low resistance region may be partially formed in the vicinity of the surface of the object 230b. That is, the element may serve as an impurity in the oxide semiconductor. In this case, impurities or impurities (hydrogen, nitrogen, metal elements, or the like) that enter oxygen vacancies function as donors in the low-resistance region, and the carrier concentration might increase.

Also, if impurities are mixed in the oxide semiconductor, defect levels or oxygen vacancies may be formed. Therefore, when impurities are mixed in the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor including the oxide semiconductor are likely to change and reliability may be deteriorated. If the channel formation region contains oxygen vacancies, the transistor is likely to have normally-on characteristics (a characteristic that a channel exists and current flows in the transistor even if voltage is not applied to the gate electrode).

For example, in a cross-sectional view in the channel length direction of a transistor, by providing a groove in the oxide 230b, the above impurities are removed, a low resistance region near the surface of the oxide 230b is reduced, and generation of a parasitic channel is suppressed. You can However, by providing the groove portion in the oxide 230b, the effective channel length becomes longer than the channel length of the transistor in plan view, which might lead to reduction in on-state current and field-effect mobility of the transistor.

Therefore, in the transistor according to one embodiment of the present invention, it is preferable that a groove be provided in the oxide 230b and the oxide 230c serving as a main carrier path be embedded in the oxide 230b in a cross-sectional view in the channel length direction of the transistor. At this time, the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the groove. Further, the film thickness of the oxide 230c is preferably about the same as the depth of the groove.

With the above structure, a channel is formed in the oxide 230c, and an effective channel length can be approximately equal to the channel length of the transistor in plan view. As a result, the on-current and field effect mobility of the transistor can be increased. Therefore, a semiconductor device with a large on-current can be provided.

Further, by providing a groove in the oxide 230b, the above impurities can be removed, and a semiconductor device with less variation in transistor characteristics and favorable reliability can be provided.

2A is an enlarged cross-sectional view of the transistor 200 shown in FIG. 1B and the vicinity thereof.

As shown in FIG. 2A, the depth of the groove provided in the oxide 230b is D1 in the cross-sectional view of the transistor in the channel length direction. Note that the depth D1 is also a difference between the top surface of the oxide 230b in a region overlapping with the conductor 242a or the conductor 242b and the top surface of the oxide 230b in a region overlapping with the conductor 260. The depth D1 is typically greater than 0 nm and 10 nm or less, preferably 1 nm or more and 7 nm or less, and more preferably 2 nm or more and 5 nm or less.

Further, as shown in FIG. 2A, the thickness (film thickness) of the oxide 230c in a region overlapping with the conductor 260 is D2 in a cross-sectional view in the channel length direction of the transistor. The thickness D2 is typically 0.5 nm or more and 7 nm or less, preferably 1 nm or more and 5 nm or less, and more preferably 2 nm or more and 4 nm or less.

Here, as shown in FIG. 2A, in a structure where the top surface of the oxide 230c in a region overlapping with the conductor 260 is lower than the bottom surface of the conductor 242a or the conductor 242b, the insulating functioning as the first gate insulator is obtained. When a channel is formed at the interface between the body 250 and the oxide 230c, the channel formation region formed between the source and the drain has a concave or U-shaped shape.

In addition, as illustrated in FIG. 2B, in a structure where the top surface of the oxide 230c in a region overlapping with the conductor 260 is approximately the same as the bottom surface of the conductor 242a or the conductor 242b, it functions as a first gate insulator. When a channel is formed at the interface between the insulator 250 and the oxide 230c, the channel formation region formed between the source and the drain has a flat shape.

Note that as illustrated in FIG. 2C, the top surface of the oxide 230c in a region overlapping with the conductor 260 may be higher than the bottom surface of the conductor 242a or the conductor 242b.

The insulator 250 may be arranged so as to cover the inner wall of the groove via the oxide 230c depending on the depth of the groove. Further, the conductor 260 may be arranged so as to fill the groove portion with the oxide 230c and the insulator 250 interposed therebetween.

Further, in a cross-sectional view of the transistor 200 in the channel length direction, the side wall of the groove may be substantially aligned with the side wall of the opening.

Further, as shown in FIG. 1C, in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be provided between a side surface of the oxide 230b and an upper surface of the oxide 230b. That is, the edge of the side surface and the edge of the upper surface may be curved (hereinafter, also referred to as round shape).

The radius of curvature on the curved surface is preferably larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface. Specifically, the radius of curvature on the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. With such a shape, coverage of the insulator 250 and the conductor 260 to be formed in a later step with the groove can be increased. Further, it is possible to prevent a decrease in the length of the region having no curved surface and suppress a decrease in on-current and mobility of the transistor 200. Therefore, a semiconductor device having favorable electrical characteristics can be provided.

As the oxide 230, for example, an In-M-Zn oxide containing indium, element M, and zinc (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium). , One or more selected from zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) may be used. Alternatively, as the oxide 230, an In—Ga oxide, an In—Zn oxide, or an indium oxide may be used.

The oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element serving as the main component of the metal oxide used for the oxide 230b corresponds to that of the element M to the metal element serving as the main component. It is preferably larger than the atomic number ratio. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

Note that in order to use the oxide 230c as a main path of carriers, the atomic ratio of indium to the metal element which is a main component in the oxide 230c is the number of indium atoms to the metal element which is a main component in the oxide 230b. It is preferably larger than the ratio. By using a metal oxide containing a large amount of indium for the channel formation region, the on-state current of the transistor can be increased. Therefore, in the oxide 230c, the atomic ratio of indium to the metal element which is the main component is made higher than the atomic ratio of indium to the metal element which is the main component in the oxide 230b, so that the oxide 230c becomes a carrier. Can be the main route of

Further, it is preferable that the bottom of the conduction band of the oxide 230c be farther from the vacuum level than the bottoms of the conduction bands of the

oxides

230a and 230b. In other words, the electron affinity of the oxide 230c is preferably higher than the electron affinity of the oxide 230a and the oxide 230b. At this time, the main path of carriers is the oxide 230c.

As the oxide 230c, specifically, In:M:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=10:1:3 [atomic ratio] or It is preferable to use a metal oxide, indium oxide, or the like having a composition in the vicinity thereof.

Further, the oxide 230c provided so as to be in contact with the insulator 250 is a metal oxide such as indium oxide which does not contain the element M as a main component, or In:M:Zn=5:1:3 [number of atoms]. Ratio] or a composition in the vicinity thereof, or In:M:Zn=10:1:3 [atomic ratio] or a metal oxide having a small ratio of the element M such as a metal oxide in a composition in the vicinity thereof. Thus, the reliability of the transistor can be improved.

As a parameter for evaluating the reliability of the transistor, for example, there is a shift voltage (ΔVsh) measured by a +GBT (Gate Bias Temperature) stress test of the transistor. The shift voltage (Vsh) is defined by Vg at which the tangent line at the point where the slope on the curve is the maximum in the drain current (Id)-gate voltage (Vg) curve of the transistor intersects the straight line of Id=1 pA. Further, the amount of change in Vsh is represented as ΔVsh.

In the +GBT stress test of the transistor, ΔVsh may shift in the negative direction over time. Further, ΔVsh may exhibit a behavior that it does not fluctuate in the − direction (for example, the negative direction) but fluctuates in both the negative direction and the positive direction. In this specification and the like, the above-mentioned behavior may be referred to as a jagged behavior of ΔVsh in the +GBT stress test.

By using a metal oxide which does not contain the element M as a main component or a metal oxide having a small ratio of the element M for the oxide 230c, for example, ΔVsh is reduced, jagged behavior of ΔVsh is suppressed, and reliability of the transistor is improved. It is possible to improve the sex.

Also, the oxide 230b and the oxide 230c preferably have crystallinity. For example, it is preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) which will be described later. An oxide having crystallinity such as CAAC-OS has few impurities and defects (such as oxygen vacancies) and has a high crystallinity and a dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even when heat treatment is performed, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in a manufacturing process.

Further, it is preferable to use CAAC-OS as the oxide 230c, and it is preferable that a c-axis of a crystal included in the oxide 230c is oriented substantially perpendicular to a formation surface or an upper surface of the oxide 230c. The CAAC-OS has a property of easily moving oxygen in a direction perpendicular to the c-axis. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

Note that when an indium oxide or an In-M-Zn oxide containing a small amount of the element M and zinc is used as the oxide 230c, the crystallinity of the oxide 230c may be low. The indium oxide film and the In-M-Zn oxide film having a low content of the element M and zinc may become a polycrystalline film by increasing the crystallinity. The polycrystalline film has a crystal grain boundary, and the crystal grain boundary serves as a defect level and may serve as a carrier trap or a carrier generation source. Therefore, a transistor including a polycrystalline In-M-Zn oxide has large variation in electric characteristics and may have low reliability.

Here, the lower end of the conduction band changes gently at the junction of the oxide 230a, the oxide 230b, and the oxide 230c. In other words, it can be said that the bottoms of the conduction bands at the junctions of the oxide 230a, the oxide 230b, and the oxide 230c are continuously changed or continuously joined. In order to do so, it is preferable that the density of defect states in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c be low.

Specifically, the oxide 230a and the oxide 230b and the oxide 230b and the oxide 230c have a common element as a main component in addition to oxygen, whereby a mixed layer with low defect level density can be formed. .. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a and the oxide 230c are In-M-Zn oxide, M-Zn oxide, oxide of element M, and In-Zn oxide. Alternatively, indium oxide or the like may be used.

Specifically, as the oxide 230a, In:M:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=1:1:0.5 [atomic ratio]. ] Or a metal oxide having a composition in the vicinity thereof may be used. In addition, as the oxide 230b, In:M:Zn=1:1:1 [atomic ratio] or a composition near it, or In:M:Zn=4:2:3 [atomic ratio] or a composition near it. A metal oxide having a composition may be used. As the oxide 230c, In:M:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=10:1:3 [atomic ratio] or a composition in the vicinity thereof is used. A metal oxide or indium oxide having a composition may be used. The composition in the vicinity includes a range of ±30% of a desired atomic number ratio. Further, it is preferable to use gallium as the element M.

Note that in the case where a metal oxide is formed by a sputtering method, the atomic ratio described above is not limited to the atomic ratio of the formed metal oxide and the atomic ratio of a sputtering target used for forming the metal oxide. May be

With the oxide 230a, the oxide 230b, and the oxide 230c having the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is low. can do. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can have high on-state current and high frequency characteristics.

The oxide 230c may have a laminated structure of two or more layers. For example, the oxide 230c may include the oxide 230c1 and the oxide 230c2 disposed over the oxide 230c1.

The oxide 230c2 preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230c1, and more preferably contains all the metal elements. For example, an In-M-Zn oxide, an In-Zn oxide, or an indium oxide is used as the oxide 230c1, and an In-M-Zn oxide, an M-Zn oxide, or the element M is used as the oxide 230c2. It is preferable to use the oxide of. Accordingly, the density of defect states at the interface between the oxide 230c1 and the oxide 230c2 can be reduced.

Further, it is preferable that the bottom of the conduction band of the oxide 230c2 is closer to the vacuum level than the bottom of the conduction band of the oxide 230c1. In other words, the electron affinity of the oxide 230c2 is preferably smaller than that of the oxide 230c1. In this case, the oxide 230c2 is preferably a metal oxide that can be used for the oxide 230a or the oxide 230b. At this time, the main path of carriers is the oxide 230c.

Specifically, as the oxide 230c1, In:M:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=10:1:3 [atomic ratio] or A metal oxide having a composition in the vicinity thereof or indium oxide is used, and as the oxide 230c2, In:M:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, M:Zn=2: A metal oxide having a composition of 1 [atomic ratio] or its vicinity, a composition of M:Zn=2:5 [atomic ratio] or its vicinity, or an oxide of the element M may be used.

Further, the oxide 230c2 is preferably a metal oxide that suppresses diffusion or permeation of oxygen as compared with the oxide 230c1. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, oxygen contained in the insulator 280 can be prevented from diffusing into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b through the oxide 230c1.

In the metal oxide used for the oxide 230c2, the atomic ratio of In to the metal element serving as the main component is smaller than the atomic ratio of In to the metal element serving as the main component in the metal oxide used for the oxide 230c1. By doing so, In can be suppressed from diffusing to the insulator 250 side. The insulator 250 functions as a gate insulator; therefore, when In is mixed in the insulator 250 or the like, the characteristics of the transistor are deteriorated. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, a highly reliable semiconductor device can be provided.

The insulator 211, the insulator 212, the insulator 214, the insulator 272, the insulator 273, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 contain impurities such as water and hydrogen from the substrate side. Alternatively, it preferably functions as a barrier insulating film which suppresses diffusion from above the transistor 200 into the transistor 200. Therefore, the insulator 211, the insulator 212, the insulator 214, the insulator 272, the insulator 273, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 are hydrogen atoms, hydrogen molecules, water molecules, and nitrogen. It is preferable to use an insulating material having a function of suppressing diffusion of impurities such as atoms, nitrogen molecules, nitric oxide molecules (N ₂ O, NO, NO _2, etc.), and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) (the above oxygen is less likely to permeate).

For example, silicon nitride or the like is used for the insulator 211, the insulator 212, the insulator 283, and the insulator 284, and aluminum oxide or the like is used for the insulator 214, the insulator 272, the insulator 273, and the insulator 282. Is preferred. Accordingly, impurities such as water and hydrogen can be suppressed from diffusing from the substrate side to the transistor 200 side through the insulator 211, the insulator 212, and the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side through the insulator 211, the insulator 212, and the insulator 214. Further, it is possible to suppress diffusion of impurities such as water and hydrogen from the insulator 280, the conductor 246, and the like which are arranged above the insulator 273 to the transistor 200 side through the insulator 272 and the insulator 273. You can As described above, the transistor 200 is insulated from the insulator 211, the insulator 212, the insulator 214, the insulator 272, the insulator 273, the insulator 282, and the insulator which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen. It is preferable that the structure surrounds the body 283 and the insulator 284.

In addition, it may be preferable to reduce the resistivity of the insulator 211, the insulator 284, and the insulator 286. For example, by setting the resistivity of the insulator 211, the insulator 284, and the insulator 286 to approximately 1×10 ¹³ Ωcm, the insulator 211, the insulator 284, and the insulator 284 in the process using plasma in the semiconductor device manufacturing process, In some cases, the insulator 286 can reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246. The resistivity of the insulator 211, the insulator 284, and the insulator 286 is preferably 1×10 ¹⁰ Ωcm or more and 1×10 ¹⁵ Ωcm or less.

Note that the insulator 211 or the insulator 212 may not necessarily be provided, and the insulator 283 or the insulator 284 may not necessarily be provided. For example, there is a case where the insulator 212 and the insulator 284 are formed by a chemical vapor deposition (CVD Chemical Deposition) method using a compound gas that does not contain hydrogen atoms or has a small hydrogen atom content.

Also, the

insulators

216 and 280 preferably have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 216 and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, empty Silicon oxide having holes may be used as appropriate.

The conductor 205 may function as the second gate electrode. In that case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, without changing the potential. In particular, by applying a negative potential to the conductor 205, Vth of the transistor 200 can be further increased and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.

The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided by being embedded in the insulator 214 or the insulator 216.

Note that as shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of a region of the oxide 230 which does not overlap with the conductor 242a and the conductor 242b. In particular, as illustrated in FIG. 1C, the conductor 205 is preferably extended also in a region outside the end portion of the oxide 230 which intersects with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator provided outside the side surface of the oxide 230 in the channel width direction. With such a structure, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode electrically surrounds the channel formation region of the oxide 230. You can In this specification, a structure of a transistor in which a channel formation region is electrically surrounded by an electric field of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.

Note that in this specification and the like, a transistor having an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by electric fields of one and the other of a pair of gate electrodes. In addition, in this specification and the like, in the S-channel structure, the side surface and the periphery of the oxide 230 which is in contact with the

conductors

242a and 242b functioning as a source electrode and a drain electrode are i-type like the channel formation region. It has characteristics. In addition, the side surface and the periphery of the oxide 230 which is in contact with the conductor 242a and the conductor 242b is in contact with the insulator 280 and thus can be i-type like the channel formation region. Note that in this specification and the like, type I can be treated as the same as high-purity intrinsic which will be described later. Further, the S-channel structure disclosed in this specification and the like is different from the Fin-type structure and the planar-type structure. By adopting the S-channel structure, resistance to a short channel effect can be increased, that is, a transistor in which a short channel effect is hard to occur can be obtained.

Further, as shown in FIG. 1C, the conductor 205 is extended so that it also functions as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.

Note that in the transistor 200, the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked; however, the present invention is not limited to this. For example, the conductor 205 may have a single-layer structure or a stacked structure including three or more layers. When the structure has a laminated structure, an ordinal number may be given in order of formation to distinguish them.

Here, the conductor 205a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N ₂ O, NO, NO _2, etc.), and copper atoms. It is preferable to use a conductive material that has. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.

By using a conductive material having a function of suppressing diffusion of oxygen for the conductor 205a, it is possible to prevent the conductivity of the conductor 205b from being reduced by oxidation. As a conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, the conductor 205a may be a single layer or a stacked layer of the above conductive material. For example, the conductor 205a may be a stack of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.

Further, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 205b. Although the conductor 205b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

The insulator 222 and the insulator 224 function as a gate insulator.

The insulator 222 preferably has a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules). In addition, the insulator 222 preferably has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen as compared with the insulator 224.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Function as a layer that suppresses Therefore, by providing the insulator 222, diffusion of impurities such as hydrogen into the inside of the transistor 200 and generation of oxygen vacancies in the oxide 230 can be suppressed. In addition, the conductor 205 can be prevented from reacting with the insulator 224 and oxygen contained in the oxide 230.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator. Alternatively, these insulators may be nitrided. Alternatively, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

The insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), (Ba,Sr)TiO ₃ (BST), or the like. An insulator including a so-called high-k material may be used in a single layer or a stacked layer. As transistors become finer and more highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

It is preferable that the insulator 224 in contact with the oxide 230 desorb oxygen by heating. For example, the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

As the insulator 224, specifically, an oxide material from which part of oxygen is released by heating, that is, an insulator material having an excess oxygen region is preferably used. An oxide film that desorbs oxygen by heating means that the amount of desorbed oxygen molecules is 1.0×10 ¹⁸ molecules/cm ³ or more, preferably 1.0×10 ¹⁹ molecules, in TDS (Thermal Desorption Spectroscopy) analysis. /Cm ³ or more, more preferably 2.0×10 ¹⁹ molecules/cm ³ or more, or 3.0×10 ²⁰ molecules/cm ³ or more. The surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

In addition, one or more treatments of heat treatment, microwave treatment, and RF treatment may be performed by contacting the oxide 230 with the insulator having the excess oxygen region. By performing the treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, a reaction bond defects that contains hydrogen to an oxygen vacancy (V O _H) is cut occurs, a reaction occurs that when other words "V _{_O H} → V _O ₊ _H", dehydrogenation Can be converted. Part of the hydrogen generated at this time may be combined with oxygen and converted into H ₂ O, which is removed from the oxide 230 or the insulator in the vicinity of the oxide 230. In addition, part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 242.

For the microwave treatment, it is preferable to use, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be generated. , And can be efficiently introduced into the oxide 230 or the insulator near the oxide 230. In the microwave treatment, the pressure may be 133 Pa or higher, preferably 200 Pa or higher, more preferably 400 Pa or higher. As a gas to be introduced into the apparatus for performing microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O ₂ /(O ₂ +Ar)) is 50% or less, preferably 10% or more 30 % Or less is recommended.

Further, in the manufacturing process of the transistor 200, heat treatment is preferably performed with the surface of the oxide 230 exposed. The heat treatment may be performed at 100 °C to 450 °C inclusive, more preferably 350 °C to 400 °C inclusive, for example. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 230 to reduce oxygen vacancies (V 2 _{O 3} ). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher in order to supplement desorbed oxygen after the heat treatment is performed in a nitrogen gas or inert gas atmosphere. Good. Alternatively, heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher, and then heat treatment may be continuously performed in a nitrogen gas or inert gas atmosphere.

Note that by performing the oxygen supplying treatment on the oxide 230, the oxygen vacancies in the oxide 230, is repaired by supplied oxygen, it is possible to accelerate the reaction of when other words "V _{O + O} → null" .. Further, by reacting oxygen supplied to hydrogen remaining in the oxide 230, the hydrogen can be removed (dehydrated) as H ₂ O. Thus, the hydrogen remained in the oxide 230 can be prevented from recombine V _{O H} is formed by oxygen vacancies.

Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

The conductor 242 (the conductor 242a and the conductor 242b) is provided on the oxide 230b. The conductor 242a and the conductor 242b each function as a source electrode or a drain electrode of the transistor 200.

As the conductor 242 (the conductor 242a and the conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, It is preferable to use a nitride containing titanium and aluminum. In one aspect of the present invention, nitride containing tantalum is particularly preferable. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

Note that when the conductor 242 is in contact with the oxide 230b or the oxide 230c, oxygen in the oxide 230b or the oxide 230c may diffuse into the conductor 242 and the conductor 242 may be oxidized. Oxidation of the conductor 242 is likely to reduce the conductivity of the conductor 242. Note that diffusion of oxygen in the oxide 230b or the oxide 230c to the conductor 242 can be restated as absorption of the oxygen in the oxide 230b or the oxide 230c by the conductor 242.

Oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, so that the conductor 242a and the oxide 230b are separated from each other and the conductor 242b and the oxide 230b are separated from each other. Alternatively, a layer may be formed between the conductor 242a and the oxide 230c and between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, it is presumed that the layer has an insulating property. At this time, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure including metal-insulator-semiconductor, and MIS (Metal). It can be regarded as a diode junction structure mainly including a -Insulator-Semiconductor structure or a MIS structure.

Note that hydrogen contained in the oxide 230b, the oxide 230c, or the like might diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen is diffused. May combine with nitrogen contained in the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b, the oxide 230c, or the like might be absorbed by the conductor 240a or the conductor 242b.

Also, there may be a curved surface between the side surface of the conductor 242 and the upper surface of the conductor 242. That is, the side end and the upper end may be curved. The curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end portion of the conductor 242. By not having the corners at the ends, the coverage of the film in the subsequent film forming process is improved.

The insulator 272 is provided in contact with the top surface of the conductor 242 and preferably functions as a barrier layer. With such a structure, absorption of excess oxygen in the insulator 280 by the conductor 242 can be suppressed. Further, by suppressing the oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have favorable electrical characteristics and reliability.

Therefore, it is preferable that the insulator 272 has a function of suppressing diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing diffusion of oxygen as compared with the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator 272, for example, an insulator containing aluminum nitride may be used.

In some cases, oxygen can be supplied to the insulator 224 when the insulator 272 is formed. Since the insulator 224 is sealed by the insulator 272 and the insulator 273, oxygen supplied to the insulator 224 can be prevented from diffusing outward and can be efficiently supplied to the oxide 230. .. Further, hydrogen in the insulator 224 may be absorbed by the insulator 273, which is preferable.

Note that the insulator 272 and the insulator 273 may not be provided, and an insulator functioning as a barrier layer may be provided between the top surface of the conductor 242 and the insulator 280. With such a structure, absorption of excess oxygen in the insulator 280 by the conductor 242 can be suppressed. Further, by suppressing the oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have favorable electrical characteristics and reliability.

Therefore, it is preferable that the insulator has a function of suppressing diffusion of oxygen. For example, the insulator preferably has a function of suppressing diffusion of oxygen as compared with the insulator 280.

As the insulator, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. In particular, it is preferable to form an aluminum oxide film by an atomic layer deposition (ALD: Atomic Layer Deposition) method. By using the ALD method, a dense film can be formed in which defects such as cracks and pinholes are reduced or which has a uniform thickness. As the insulator, for example, an insulator containing aluminum nitride may be used.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with at least part of the oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, vacant silicon oxide, or the like is used. Can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

Like the insulator 224, the insulator 250 is preferably formed using an insulator from which oxygen is released by heating. By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with at least part of the oxide 230c, oxygen is effectively supplied to the channel formation region of the oxide 230b and the oxide 230b is removed. Oxygen deficiency in the channel formation region can be reduced. Therefore, it is possible to provide a transistor which suppresses variation in electric characteristics, has stable electric characteristics, and has improved reliability. Further, similarly to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 be reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Although the insulator 250 is illustrated as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers. When the insulator 250 has a two-layer stacked structure, the lower layer of the insulator 250 is formed using an insulator from which oxygen is released by heating, and the upper layer of the insulator 250 has a function of suppressing diffusion of oxygen. It is preferable to use an insulator that has. With such a structure, diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260 can be suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250 can be suppressed. For example, the lower layer of the insulator 250 can be provided using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided using a material similar to that of the insulator 222.

Note that when silicon oxide, silicon oxynitride, or the like is used for the lower layer of the insulator 250, an insulating material which is a high-k material with a high relative dielectric constant may be used for the upper layer of the insulator 250. When the gate insulator has a stacked structure of a lower layer of the insulator 250 and an upper layer of the insulator 250, a stacked structure having high heat stability and a high relative dielectric constant can be obtained. Therefore, the gate potential applied during the operation of the transistor can be reduced while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.

As the upper layer of the insulator 250, specifically, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. A metal oxide that can be used as the object or the oxide 230 can be used. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses diffusion of oxygen from the insulator 250 to the conductor 260. By providing the metal oxide which suppresses oxygen diffusion, oxygen diffusion from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

The metal oxide preferably has a function as a part of the first gate electrode. For example, a metal oxide that can be used as the oxide 230 can be used as the above metal oxide. In that case, by forming a film of the conductor 260a by a sputtering method, the electric resistance value of the metal oxide can be reduced to form a conductor. This can be called an OC (Oxide Conductor) electrode.

By including the above metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. In addition, by keeping the distance between the conductor 260 and the oxide 230 by the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 can be maintained. Can be suppressed. In addition, by providing the insulator 250 and the stacked structure with the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be reduced. It can be easily adjusted appropriately.

The conductor 260 functions as the first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b provided over the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom surface and the side surface of the conductor 260b. Further, as shown in FIGS. 1B and 1C, the top surface of the conductor 260 is substantially aligned with the top surface of the insulator 250 and the top surface of the oxide 230c. 1B and 1C, the conductor 260 is illustrated as a two-layer structure of the conductor 260a and the conductor 260b, but may have a single-layer structure or a stacked structure of three or more layers.

As the conductor 260a, it is preferable to use a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules, and copper atoms. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.

Further, since the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductivity of the conductor 260b from being reduced due to the oxygen contained in the insulator 250 from oxidizing the conductor 260b. As a conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

Since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can be formed using a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor 260b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material.

In addition, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill the opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without alignment.

Further, as shown in FIG. 1C, in the channel width direction of the transistor 200, the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap is preferably lower than the bottom surface of the oxide 230b. The conductor 260 functioning as a gate electrode covers the side surface and the upper surface of the channel formation region of the oxide 230b with the insulator 250 or the like interposed therebetween, whereby the electric field of the conductor 260 is changed to the channel formation region of the oxide 230b. It becomes easy to act on the whole. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved. Difference between the height of the bottom surface of the conductor 230 and the height of the bottom surface of the oxide 230b in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 when the bottom surface of the insulator 222 is used as a reference. Is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 242, and the insulator 273. Further, the upper surface of the insulator 280 may be flattened.

The insulator 280 functioning as an interlayer film preferably has a low dielectric constant. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. The insulator 280 is preferably provided using a material similar to that of the insulator 216, for example. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having pores is preferable because a region containing oxygen which is released by heating can be easily formed.

Also, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 be reduced. The insulator 280 preferably has a low hydrogen concentration and has an excess oxygen region or excess oxygen, and may be provided using a material similar to that of the insulator 216, for example. The insulator 280 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed thereover by a CVD method. do it. Further, silicon nitride may be further stacked thereover.

The insulator 282 or the insulator 283 preferably functions as a barrier insulating film which suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. Further, the insulator 282 or the insulator 283 preferably functions as a barrier insulating film which suppresses permeation of oxygen. As the insulator 282 and the insulator 283, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example. For example, aluminum oxide having a high blocking property with respect to oxygen may be used as the insulator 282, and silicon nitride having a high blocking property with respect to hydrogen may be used as the insulator 283.

For the conductor 240a and the conductor 240b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

In the case where the conductor 240 has a stacked-layer structure, the insulator 284, the insulator 283, the insulator 282, the insulator 280, the insulator 273, and the conductor in contact with the insulator 272 contain impurities such as water and hydrogen. It is preferable to use a conductive material having a function of suppressing transmission. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used as a single layer or a stacked layer. By using the conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the

conductors

240a and 240b. In addition, impurities such as water and hydrogen contained in a layer above the insulator 284 can be prevented from entering the oxide 230 through the

conductors

240a and 240b.

As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 273 and the insulator 272, impurities such as water and hydrogen contained in the insulator 280 and the like are transferred to the oxide 230 through the conductor 240a and the conductor 240b. Mixing can be suppressed. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

Further, the conductors 246 (the

conductors

246a and 246b) which function as wirings may be provided in contact with the top surfaces of the

conductors

240a and 240b. The conductor 246 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in the opening provided in the insulator.

The insulator 286 is provided on the conductor 246 and the insulator 284. Accordingly, the top surface of the conductor 246 and the side surface of the conductor 246 are in contact with the insulator 286, and the bottom surface of the conductor 246 is in contact with the insulator 284. That is, the conductor 246 can be configured to be surrounded by the insulator 284 and the insulator 286. With such a structure, permeation of oxygen from the outside can be suppressed and oxidation of the conductor 246 can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from the conductor 246 to the outside, which is preferable.

<Constituent material of semiconductor device>
The constituent materials that can be used for the semiconductor device will be described below.

<< substrate >>
As a substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon and germanium, a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulating region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate provided with an element may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

<<insulator>>
Examples of the insulator include an insulating oxide, a nitride, an oxynitride, a nitrided oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide.

For example, as transistors become finer and highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative dielectric constant for the insulator functioning as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material may be selected depending on the function of the insulator.

As the insulator having a high relative dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium, are used. And the like, or a nitride containing silicon and hafnium.

Further, as the insulator having a low relative dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, empty Silicon oxide having holes, resin, or the like is used.

Also, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium. The insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or as a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, A metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used.

Also, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating. For example, with the structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

<< conductor >>
As the conductor, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, and the like. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. It is preferable. Further, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when absorbing oxygen is preferable. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

Alternatively, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be used. Further, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be used. Further, a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing the above metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode. Is preferred. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed, as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

<< metal oxide >>
As the oxide 230, a metal oxide (oxide semiconductor) which functions as a semiconductor is preferably used. The metal oxide applicable to the oxide 230 according to the present invention will be described below.

The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc. Note that the element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium. However, as the element M, it may be acceptable to combine a plurality of the aforementioned elements.

Note that, in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Structure of metal oxide]
The oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, for example, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), And an amorphous oxide semiconductor.

CAAC-OS has a crystal structure having c-axis orientation and a plurality of nanocrystals connected in the ab plane direction and having strain. Note that the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where the plurality of nanocrystals are connected.

　Nanocrystals are basically hexagonal, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, the strain may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary (grain boundary) even in the vicinity of strain. That is, it is found that the distortion of the lattice arrangement suppresses the formation of crystal grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to substitution with a metal element, or the like. This is because.

The CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M,Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced with indium, it can be expressed as an (In,M,Zn) layer. When the indium in the In layer is replaced with the element M, it can be expressed as an (In,M) layer.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, in the CAAC-OS, since it is difficult to confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary does not easily occur. In addition, the crystallinity of a metal oxide may be reduced due to entry of impurities, generation of defects, and the like; therefore, the CAAC-OS can be referred to as a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide containing CAAC-OS is highly heat resistant and highly reliable.

Nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

Note that In-Ga-Zn oxide (hereinafter referred to as IGZO), which is a kind of metal oxide containing indium, gallium, and zinc, may have a stable structure by using the above-described nanocrystal. is there. In particular, IGZO tends to have difficulty in crystal growth in the atmosphere, and thus a smaller crystal (for example, the above-mentioned nanocrystal) is used than a large crystal (here, a crystal of several mm or a crystal of several cm). However, it may be structurally stable.

The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

In addition to the oxide semiconductors described above, a CAC (Cloud-Aligned Composite)-OS may be used.

CAC-OS has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. Note that when the CAC-OS is used for an active layer of a transistor, a conductive function is a function of allowing electrons (or holes) serving as carriers to flow, and an insulating function is a function of not allowing electrons serving as carriers to flow. is there. The CAC-OS can be provided with a switching function (On/Off function) by causing the conductive function and the insulating function to act in a complementary manner. By separating each function in the CAC-OS, both functions can be maximized.

Also, the CAC-OS has a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. The conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed by blurring the periphery and connecting in a cloud shape.

In the CAC-OS, the conductive region and the insulating region may be dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

CAC-OS is composed of components having different band gaps. For example, it is composed of a CAC-OS, a component having a wide gap due to the insulating region, and a component having a narrow gap due to the conductive region. In the case of the structure, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Further, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS is used for a channel formation region of a transistor, a high current drivability, that is, a large on-current and a high field-effect mobility can be obtained when the transistor is on.

That is, the CAC-OS can also be referred to as a matrix composite material or a metal matrix composite material.

Also, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, classification of crystal structures in an oxide semiconductor will be described with reference to FIG. 3A. FIG. 3A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

As shown in FIG. 3A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. Moreover, completeness amorphous is included in Amorphous. In addition, CAAC, nc, and CAC are included in Crystalline. In addition, single crystal and poly crystal are included in Crystal.

Note that the structure in the thick frame shown in FIG. 3A belongs to the New crystalline phase. The structure is in the boundary region between Amorphous and Crystal. That is, it can be said that the energy-unstable Amorphous and Crystalline are completely different structures.

The crystal structure of the film or substrate can be evaluated by using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, XRD spectra of quartz glass and IGZO having a crystal structure classified into Crystalline (also referred to as crystalline IGZO) are shown in FIGS. 3B and 3C. Further, FIG. 3B is an XRD spectrum of quartz glass and FIG. 3C is an XRD spectrum of crystalline IGZO. The crystalline IGZO shown in FIG. 3C has a composition of In:Ga:Zn=4:2:3 [atomic ratio]. Further, the crystalline IGZO shown in FIG. 3C has a thickness of 500 nm.

As shown by the arrow in FIG. 3B, the peak of the XRD spectrum of quartz glass is almost symmetrical. On the other hand, as shown by the arrow in FIG. 3C, in crystalline IGZO, the peak of the XRD spectrum is asymmetric. The left-right asymmetry of the XRD spectrum peaks clearly indicates the presence of crystals. In other words, unless the peak of the XRD spectrum is symmetrical, it cannot be said to be Amorphous.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

When impurities are mixed in the oxide semiconductor, defect levels or oxygen vacancies may be formed. Therefore, when impurities are mixed in the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor including the oxide semiconductor are likely to change and reliability may be deteriorated. If the channel formation region contains oxygen vacancies, the transistor is likely to have normally-on characteristics (a characteristic that a channel exists and current flows in the transistor even if voltage is not applied to the gate electrode).

　Transistors using metal oxides tend to have normally-on characteristics because their electrical characteristics fluctuate due to impurities and oxygen vacancies in the metal oxides. In addition, when the transistor is driven in a state where excess amount of oxygen exceeds an appropriate amount in the metal oxide, the valence of excess oxygen atoms is changed and the electrical characteristics of the transistor are changed. , Reliability may deteriorate.

Therefore, in the transistor, it is preferable to use a metal oxide having a low carrier concentration in the channel formation region. In the case of reducing the carrier concentration of the metal oxide, the concentration of impurities in the metal oxide may be lowered and the density of defect states may be lowered. In this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that in this specification and the like, the case where the carrier concentration of the metal oxide in the channel formation region is 1×10 ¹⁶ cm ⁻³ or less is defined as substantially high-purity intrinsic.

The carrier concentration of the metal oxide in the channel formation region is preferably 1×10 ¹⁸ cm ⁻³ or less, more preferably 1×10 ¹⁷ cm ⁻³ or less, and 1×10 ¹⁶ cm ^−3. It is more preferably the following or less, still more preferably less than 1×10 ¹³ cm ⁻³ , further preferably less than 1×10 ¹² cm ⁻³ . The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but can be set to, for example, 1×10 ⁻⁹ cm ⁻³ .

The impurities in the metal oxide include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like. In particular, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to be water, which may cause oxygen vacancies in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor might have normally-on characteristics. Further, when containing the hydrogen to oxygen vacancies in the metal oxide, there is a case where oxygen vacancies and hydrogen combine to form a V _{O H.} Defects containing hydrogen to an oxygen vacancy (V O _H) serves as a donor, sometimes electrons serving as carriers are generated. In addition, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Further, hydrogen in the metal oxide easily moves due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the metal oxide, reliability of the transistor might be deteriorated.

In one aspect of the present invention to reduce as much as possible V _{O H} in the oxide 230, it is preferable that the highly purified intrinsic or substantially highly purified intrinsic. Thus, the V O _H to obtain a sufficiently reduced metal oxide, to remove moisture in the metal oxide, the impurities such as hydrogen (dehydration, may be described as dehydrogenation.) Then, it is important to supply oxygen to the metal oxide to fill oxygen vacancies (sometimes referred to as oxygenation treatment). The metal oxide impurities is sufficiently reduced such V O _H By using the channel formation region of the transistor, it is possible to have stable electrical characteristics.

Defects containing hydrogen to an oxygen vacancy (V O _H) can function as a donor of the metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, the metal oxide may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, the carrier concentration which is assumed to be a state where no electric field is applied may be used as the parameter of the metal oxide, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases. Further, the “carrier concentration” described in this specification and the like can be restated as the “carrier density”.

Therefore, it is preferable that hydrogen in the metal oxide be reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectroscopy (SIMS) is less than 1×10 ²⁰ atoms/cm ³ , preferably 1×10 ¹⁹ atoms/cm 3. ^{It is} less than ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , and even more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using a metal oxide in which impurities such as hydrogen are sufficiently reduced in a channel formation region of a transistor, stable electric characteristics can be given.

Also, the above defect levels may include trap levels. The charge trapped in the trap level of the metal oxide takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor including a metal oxide having a high trap level density in a channel formation region may have unstable electrical characteristics.

Further, when impurities are present in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region may be lowered, and the crystallinity of the oxide provided in contact with the channel formation region may be lowered. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to be deteriorated. Further, when the crystallinity of the oxide provided in contact with the channel formation region is low, an interface state is formed, which might deteriorate the stability or reliability of the transistor.

Therefore, in order to improve the stability or reliability of the transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and in the vicinity thereof. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

Specifically, in the channel formation region of the oxide semiconductor and in the vicinity thereof, the concentration of the impurity obtained by SIMS is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less. To do. Alternatively, in the channel formation region of the oxide semiconductor and in the vicinity thereof, the concentration of the impurity obtained by element analysis using energy scattering X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) is 1.0 atomic%. Below. Note that when an oxide containing the element M is used as the oxide semiconductor, the concentration ratio of the impurity to the element M in the channel formation region of the oxide semiconductor and the vicinity thereof is less than 0.10, preferably 0.05. Less than Here, the concentration of the element M used when calculating the concentration ratio may be the concentration in the same region as the region in which the concentration of the impurities is calculated, or may be the concentration in the oxide semiconductor.

Also, since the metal oxide having a reduced impurity concentration has a low defect level density, the trap level density may be low.

In addition, in a transistor including an oxide semiconductor, if an impurity and oxygen vacancies are present in a channel formation region in the oxide semiconductor, the oxide semiconductor may have low resistance. In addition, the electrical characteristics are likely to fluctuate, and the reliability may deteriorate.

For example, silicon has a larger binding energy with oxygen than indium and zinc. For example, in the case of using an In-M-Zn oxide as the oxide semiconductor, when silicon is mixed in the oxide semiconductor, oxygen contained in the oxide semiconductor is taken away by the silicon, so that oxygen near the indium or zinc is generated. Defects may be formed.

In a transistor including an oxide semiconductor in a channel formation region, when a low resistance region is formed in the channel formation region, a leakage current (parasitic channel) between a source electrode and a drain electrode of the transistor is generated in the low resistance region. Likely to happen. Further, due to the parasitic channel, defective characteristics of the transistor are likely to occur such as normally-on of the transistor, increase of leak current, and variation (shift) of threshold voltage due to stress application. Further, when the processing accuracy of the transistor is low, the parasitic channel varies from transistor to transistor, resulting in variations in transistor characteristics.

Therefore, it is preferable that the impurities and oxygen vacancies in the channel formation region of the oxide semiconductor and the vicinity thereof be reduced as much as possible.

<<Other semiconductor materials>>
The semiconductor material that can be used for the oxide 230 is not limited to the above metal oxide. As the oxide 230, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance functioning as a semiconductor (also referred to as an atomic layer substance, a two-dimensional material, or the like) is preferably used as a semiconductor material. In particular, it is preferable to use a layered substance that functions as a semiconductor as a semiconductor material.

Here, in the present specification and the like, the layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by a covalent bond or an ionic bond are stacked via a bond weaker than the covalent bond or the ionic bond, such as Van der Waals force. The layered material has high electric conductivity in the unit layer, that is, two-dimensional electric conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with high on-state current can be provided.

Layered substances include graphene, silicene, chalcogenides, etc. A chalcogenide is a compound containing chalcogen. Chalcogen is a general term for elements belonging to Group 16 and includes oxygen, sulfur, selenium, tellurium, polonium, and livermolium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

As the oxide 230, for example, a transition metal chalcogenide that functions as a semiconductor is preferably used. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe ₂ ). , Tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe ₂ ), hafnium sulfide (typically HfS ₂ ), hafnium selenide (typically) Specific examples thereof include HfSe ₂ ), zirconium sulfide (typically ZrS ₂ ), zirconium selenide (typically ZrSe ₂ ), and the like.

<Modification of semiconductor device>
An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 4A to 4D and FIGS. 5A to 5D.

4A and 5A are top views of the semiconductor device. Further, FIGS. 4B and 5B are cross-sectional views corresponding to the portion indicated by the alternate long and short dash line A1-A2 in FIGS. 4A and 5A, respectively. Further, FIGS. 4C and 5C are cross-sectional views corresponding to the portions indicated by dashed-dotted line A3-A4 in FIGS. 4A and 5A, respectively. Further, FIGS. 4D and 5D are cross-sectional views corresponding to the portions indicated by dashed-dotted line A5-A6 in FIGS. 4A and 5A, respectively. In the top views of FIGS. 4A and 5A, some elements have been omitted for clarity.

In the semiconductor devices shown in FIGS. 4A to 4D and FIGS. 5A to 5D, structures having the same functions as those of the structure of the semiconductor device shown in <Structure example of semiconductor device> are denoted by the same reference numerals. Also in this item, as the constituent material of the semiconductor device, the materials described in detail in <Structure example of semiconductor device> can be used.

<<First Modification of Semiconductor Device>>
The semiconductor device shown in FIGS. 4A to 4D is a modification of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device illustrated in FIGS. 4A to 4D is different from the semiconductor devices illustrated in FIGS. 1A to 1D in that the semiconductor device includes the oxide 243 (the oxide 243a and the oxide 243b). In addition, the shape of the oxide 230c is different.

The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing permeation of oxygen. By disposing the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electrical conductivity between the conductor 242 and the oxide 230b can be obtained. It is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 200 and reliability of the transistor 200 can be improved.

As the oxide 243, a metal oxide containing the element M may be used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. The oxide 243 preferably has a higher concentration of the element M than the oxide 230b. Alternatively, gallium oxide may be used as the oxide 243. Alternatively, as the oxide 243, a metal oxide such as an In-M-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. The thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be preferably suppressed. For example, if the oxide 243 has a hexagonal crystal structure or the like, release of oxygen in the oxide 230 can be suppressed in some cases.

The oxide 230c may be provided for each transistor 200. That is, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 do not need to be in contact with each other. Further, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be provided between the transistor 200 and the transistor 200 adjacent to the transistor 200.

In the semiconductor device in which the plurality of transistors 200 are arranged in the channel width direction, with the above structure, the oxides 230c are independently provided in the transistor 200. Therefore, a parasitic transistor is suppressed between the transistor 200 and the transistor 200 adjacent to the transistor 200, and a leakage path is suppressed between the transistor 200 and the transistor 200 adjacent to the transistor 200. can do. Therefore, it is possible to provide a semiconductor device having good electric characteristics and capable of being miniaturized or highly integrated.

For example, when the distance between the side end of the oxide 230c of the transistor 200 and the side end of the oxide 230c of the transistor 200 adjacent to the transistor 200 in the channel width direction of the transistor 200 is represented as L _1. , L ₁ is larger than 0 nm. Further, in the channel width direction of the transistor 200, face each other, and a side edge portion of the oxide 230a of the transistor 200, to represent the distance between the side edge portion of the oxide 230a of the transistor 200 adjacent to the transistor 200 as _{L 2} , the value of the ratio of _{L 1} _(L 1 / _{L 2)} for _{L 2} is preferably greater than 0 less than 1, more preferably 0.1 to 0.9, more preferably 0.2 to 0.8 Is. Note that L ₂ may be a distance between the side end portion of the oxide 230b of the transistor 200 and the side end portion of the oxide 230b of the transistor 200 which is adjacent to the transistor 200 and face each other.

By reducing the ratio of _{L 1} to the above _{_{_{L 2 (L 1 / L 2}}} ), oxides 230c is a transistor 200, the positional deviation of the arrangement that are not regions between the transistors 200 adjacent to the transistor 200 Even if it occurs, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 can be separated from each other.

Further, by increasing the ratio of _{L 1} to the above _{_{_{L 2 (L 1 / L 2}}} ), the transistor 200, even by narrowing the interval between the transistor 200 adjacent to the transistor 200, the width of the minimum feature size This can be ensured, and further miniaturization or higher integration of the semiconductor device can be achieved.

Note that each of the conductor 260 and the insulator 250 may be commonly used between the adjacent transistors 200. That is, the conductor 260 of the transistor 200 has a region provided so as to be continuous with the conductor 260 of the transistor 200 which is adjacent to the transistor 200. In addition, the insulator 250 of the transistor 200 has a region which is provided so as to be continuous with the insulator 250 of the transistor 200 which is adjacent to the transistor 200.

With the above structure, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

Note that when the oxide 230c has a stacked-layer structure of the oxide 230c1 and the oxide 230c2, the oxide 230c1 and the oxide 230c2 of the transistor 200 are the same as the oxide 230c1 and the oxide 230c2 of the transistor 200 adjacent to the transistor 200. The oxide 230c1 of the transistor 200 may be separated from the oxide 230c1 of the transistor 200 adjacent to the transistor 200, and the oxide 230c2 of the transistor 200 may be separated from the oxide 230c2 of the transistor 200. The region may be continuous with the 200 oxide 230c2. At this time, the oxide 230c2 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

<<Modification 2 of Semiconductor Device>>
The semiconductor device shown in FIGS. 5A to 5D is a modification of the semiconductor device shown in FIGS. 4A to 4D. The semiconductor device illustrated in FIGS. 5A to 5D is different from the semiconductor devices illustrated in FIGS. 4A to 4D in shapes of an insulator 283 and an insulator 284. In addition, a difference is that the oxide 230d, the insulator 274, and the insulator 287 are included.

In the semiconductor device illustrated in FIGS. 5A to 5D, the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 273, the insulator 280, and the insulator 282 are patterned. The insulator 287 is provided in contact with the side surfaces of the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 273, the insulator 280, and the insulator 282. To be The insulator 283 and the insulator 284 are the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 273, the insulator 280, the insulator 282, and the insulator. The structure covers the body 287. That is, the insulator 283 is in contact with the top surface of the insulator 282, the top surface and side surfaces of the insulator 287, and the top surface of the insulator 211, and the insulator 284 is in contact with the top surface and side surfaces of the insulator 283. Accordingly, the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 273, the insulator 280, the insulator 282, and the insulator 287 including the oxide 230 and the like. Are isolated from the outside by the insulator 283, the insulator 284, and the insulator 211. In other words, the transistor 200 is arranged in a region sealed with the insulator 283 and the insulator 284 and the insulator 211.

For example, the insulator 212, the insulator 214, the insulator 287, and the insulator 282 are formed using a material having a function of capturing hydrogen and fixing hydrogen, and the insulator 211, the insulator 283, and the insulator 284. Is preferably formed using a material having a function of suppressing diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used for the insulator 212, the insulator 214, the insulator 287, and the insulator 282. Further, typically, silicon nitride can be used for the insulator 211, the insulator 283, and the insulator 284.

With the above configuration, it is possible to prevent hydrogen contained outside the sealed region from mixing into the sealed region.

Although the transistor 200 illustrated in FIGS. 5A to 5D has a structure in which the insulator 211, the insulator 283, and the insulator 284 are provided as a single layer, the present invention is not limited to this. For example, the insulator 211, the insulator 283, and the insulator 284 may each have a stacked structure of two or more layers.

The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. The insulator 274 can be provided using, for example, a material similar to that of the insulator 280.

The transistor 200 illustrated in FIGS. 5A to 5D includes the oxide 230d between the oxide 230c and the insulator 250.

The oxide 230d can be provided using, for example, the same material as the oxide 230c2.

5C, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 are separated from each other, and the oxide 230d of the transistor 200 is separated from the oxide 230c of the transistor 200. It may have a region continuous with 200 oxide 230d. At this time, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

<Method for manufacturing semiconductor device>
Next, a method for manufacturing the semiconductor device which is one embodiment of the present invention shown in FIGS. 4A to 4D will be described with reference to FIGS. 6A to 15D.

6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A show top views. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are shown in FIGS. 6A, 7A, 8A, 9A, and 10A, respectively. 11A, FIG. 12A, FIG. 13A, FIG. 14A, and FIG. 15A are cross-sectional views corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 15A, and are also cross-sectional views in the channel length direction of the transistor 200. 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, and 15C are shown in FIGS. 6A, 7A, 8A, 9A, and 10A, respectively. 11A, FIG. 12A, FIG. 13A, FIG. 14A, and FIG. 15A are cross-sectional views corresponding to the portion indicated by dashed-dotted line A3-A4 in FIG. 15A, and are also cross-sectional views in the channel width direction of the transistor 200. 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, and 15D are shown in FIGS. 6A, 7A, 8A, 9A, and 10A, respectively. It is sectional drawing of the site|part shown by the dashed-dotted line of A5-A6 in FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, and FIG. 15A. In the top views of FIGS. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A, some elements are omitted for clarity. I am

First, a substrate (not shown) is prepared, and the insulator 211 is formed on the substrate. The insulator 211 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an ALD method, or the like.

The CVD method can be classified into a plasma CVD method using plasma (PECVD: Plasma Enhanced CVD) method, a thermal CVD method using heat (TCVD: Thermal CVD) method, an optical CVD method using light (Photo CVD) method, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, the thermal CVD method is a film forming method which can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in a semiconductor device might be charged up by receiving electric charge from plasma. At this time, the accumulated charges may destroy wirings, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

Further, as the ALD method, a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like can be used.

Further, the ALD method utilizes the self-controllability, which is a property of atoms, and can deposit atoms one by one, so that it is possible to form an extremely thin film and to form a film with a high aspect ratio. It is possible to form a film with few defects such as holes, form a film with excellent coverage, and form a film at a low temperature. In the PEALD (Plasma Enhanced ALD) method, it is sometimes preferable that the film can be formed at a lower temperature by using plasma. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, a film formed by the ALD method may contain a large amount of impurities such as carbon as compared with a film formed by another film formation method. The impurities can be quantified by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike the film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has a good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for coating the surface of the opening having a high aspect ratio. However, since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas. In addition, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas during film formation. When film formation is performed while changing the flow rate ratio of the source gas, the time required for transfer and pressure adjustment is shorter than the case where film formation is performed using multiple film formation chambers. can do. Therefore, it may be possible to improve the productivity of the semiconductor device.

In this embodiment mode, silicon nitride is formed as the insulator 211 by a CVD method.

Next, the insulator 212 is formed over the insulator 211. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method.

In this manner, by using an insulator such as silicon nitride in which copper is less likely to permeate as the insulator 211 and the insulator 212, copper or the like is easily diffused into a conductor below the insulator 211 (not shown). Even if a metal is used, it is possible to prevent the metal from diffusing upward through the insulator 211 and the insulator 212. Further, by using an insulator such as silicon nitride in which impurities such as water and hydrogen do not easily pass, diffusion of impurities such as water and hydrogen contained in a layer below the insulator 211 can be suppressed.

Next, the insulator 214 is formed over the insulator 212. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

The hydrogen concentration of the insulator 212 is preferably lower than the hydrogen concentration of the insulator 211, and the hydrogen concentration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212. By depositing silicon nitride as the insulator 212 by a sputtering method, silicon nitride having a lower hydrogen concentration than the insulator 211 that deposits silicon nitride by a CVD method can be formed. When the insulator 214 is aluminum oxide, the hydrogen concentration can be lower than that of the insulator 212.

Although the transistor 200 is formed over the insulator 214 in a subsequent step, a film near the transistor 200 preferably has relatively low hydrogen concentration, and a film having relatively high hydrogen concentration is remote from the transistor 200. It is preferable to arrange them.

Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. In addition, the insulator 216 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 216 can be reduced.

Next, an opening reaching the insulator 214 is formed in the insulator 216. The openings include, for example, grooves and slits. In addition, the area where the opening is formed may be referred to as an opening. The openings may be formed by wet etching, but dry etching is preferable for fine processing. As the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 which forms the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214.

As a dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, the high frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a configuration may be adopted in which high frequency voltages having different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus can be used.

After forming the opening, a conductive film to be the conductor 205a is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, the conductive film to be the conductor 205a has a multi-layer structure. First, tantalum nitride is deposited by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride in the lower layer of the conductor 205b, even if a metal such as copper that easily diffuses is used as a conductive film to be the conductor 205b described later, the metal diffuses out of the conductor 205a. Can be prevented.

Next, a conductive film to be the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is formed as the conductive film.

Next, CMP treatment is performed to remove part of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, so that the insulator 216 is exposed. As a result, the

conductors

205a and 205b remain only in the openings. Accordingly, the conductor 205 whose top surface is flat can be formed (see FIGS. 6A to 6C). Note that the insulator 216 may be partly removed by the CMP treatment.

Although the conductor 205 is formed so as to be embedded in the opening of the insulator 216 in the above, the present embodiment is not limited to this. For example, the conductor 205 is formed over the insulator 214, the insulator 216 is formed over the conductor 205, and the insulator 216 is subjected to CMP treatment, whereby part of the insulator 216 is removed and the conductor 216 is removed. The surface of 205 may be exposed.

Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both oxides of aluminum and hafnium may be formed. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. The generation of oxygen vacancies in the oxide 230 can be suppressed.

The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, it is preferable to perform heat treatment. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 300 °C to 500 °C inclusive, and more preferably 320 °C to 450 °C inclusive. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. May be.

In this embodiment mode, as the heat treatment, after the insulator 222 is formed, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for one hour, and then continuously in an oxygen atmosphere at a temperature of 400° C. for one hour. Perform processing. By the heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Further, the heat treatment can be performed at a timing after the insulator 224 is formed.

Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulator 224, silicon oxide or silicon oxynitride is formed by a CVD method. The insulator 224 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 becomes the insulator 224 that is in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves, for example. Alternatively, the substrate side may have a power source for applying RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently introduced into the insulator 224. it can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to supplement desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by selecting appropriate conditions for the plasma treatment. In that case, heat treatment may not be performed.

Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP treatment may be performed until the insulator 224 is reached. By performing the CMP treatment, the surface of the insulator 224 can be planarized and smoothed. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, the end point of the CMP process can be easily detected. Although part of the insulator 224 may be polished by the CMP treatment to reduce the thickness of the insulator 224, the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, deterioration of the coverage of an oxide film to be formed later can be prevented in some cases and reduction in the yield of semiconductor devices can be prevented. In addition, oxygen can be added to the insulator 224 by depositing aluminum oxide over the insulator 224 by a sputtering method, which is preferable.

Next, an oxide film 230A and an oxide film 230B are sequentially formed over the insulator 224 (see FIGS. 6A to 6D). Note that the oxide film 230A and the oxide film 230B are preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. When the above oxide film is formed by the sputtering method, the above In-M-Zn oxide target or the like can be used.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or higher, preferably 80% or higher, more preferably 100%.

In the case where the oxide film 230B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is greater than 30% and 100% or less, preferably 70% or more and 100% or less, oxygen-excessive oxidation is performed. A physical semiconductor is formed. A transistor including an oxygen-excess type oxide semiconductor in a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this. When the oxide film 230B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is 1% to 30% inclusive, preferably 5% to 20% inclusive, an oxygen-deficient oxide semiconductor is formed. It A transistor including an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility. Further, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

In this embodiment, the oxide film 230A is formed by a sputtering method using an oxide target of In:Ga:Zn=1:3:4 [atomic ratio]. Further, the oxide film 230B is formed by a sputtering method using an oxide target of In:Ga:Zn=4:2:4.1 [atomic ratio]. Note that each oxide film may be formed in accordance with characteristics required for the oxide 230a and the oxide 230b by appropriately selecting film formation conditions and atomic ratios.

Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 6A to 6D). The oxide film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 243A preferably has an atomic ratio of Ga to In that is larger than an atomic ratio of Ga to In of the oxide film 230B. In this embodiment, the oxide film 243A is formed by a sputtering method using an oxide target of In:Ga:Zn=1:3:4 [atomic ratio].

Note that it is preferable that the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A be formed without being exposed to the air. For example, a multi-chamber deposition apparatus may be used.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed. In this embodiment mode, after a treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400° C. for 1 hour is continuously performed in an oxygen atmosphere.

Next, a conductive film 242A is formed over the oxide film 243A (see FIGS. 6A to 6D). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be continuously formed without being exposed to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A or the like is removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A are further reduced. be able to. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment mode, the temperature of the heat treatment is 200° C.

Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape by a lithography method to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B. Are formed (see FIGS. 7A to 7D). Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. Further, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be thin.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left with a developing solution to form a resist mask. Next, the conductor, the semiconductor, the insulator, and the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure. Further, an electron beam or an ion beam may be used instead of the above-mentioned light. If an electron beam or an ion beam is used, no mask is needed. Note that the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment.

Also, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereover, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the conductive film 242A may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductive film 242A, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least part of them overlaps with the conductor 205. In addition, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are preferably substantially perpendicular to the top surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are substantially perpendicular to the top surface of the insulator 222, the area and the size of the transistor 200 can be reduced when the plurality of transistors 200 are provided. Densification is possible. Alternatively, the angle between the side surface of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the top surface of the insulator 222 may be low. In that case, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 is preferably greater than or equal to 60 degrees and less than 70 degrees. With such a shape, the coverage with the insulator 272 and the like can be improved and defects such as voids can be reduced in the subsequent steps.

Moreover, a curved surface is provided between the side surface of the conductive layer 242B and the upper surface of the conductive layer 242B. That is, it is preferable that the end of the side surface and the end of the upper surface are curved. The curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end portion of the conductive layer 242B. By not having the corners at the ends, the coverage of the film in the subsequent film forming process is improved.

Next, an insulator 272 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 8B to 8D). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a film of aluminum oxide is formed as the insulator 272 by a sputtering method. By forming an aluminum oxide film by a sputtering method, oxygen can be injected into the insulator 224.

Next, the insulator 273 is formed over the insulator 272. The insulator 273 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the embodiment, as the insulator 273, silicon nitride is formed by a sputtering method (see FIGS. 8B to 8D).

Next, an insulating film to be the insulator 280 is formed over the insulator 273. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulating film, a silicon oxide film may be formed by a sputtering method and a silicon oxide film may be formed thereover by a PEALD method or a thermal ALD method. Further, the insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 280 can be reduced. Note that heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 273 and the like are removed, and the moisture concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 and The hydrogen concentration can be reduced. The heat treatment conditions described above can be used.

Next, CMP treatment is performed on the insulating film to form an insulator 280 having a flat upper surface (see FIGS. 8B to 8D). Note that similarly to the insulator 224, aluminum oxide may be formed over the insulator 280 by, for example, a sputtering method, and CMP treatment may be performed until the insulator 280 is reached.

Here, microwave treatment may be performed. The microwave treatment is preferably performed in an atmosphere containing oxygen and under reduced pressure. By performing the microwave treatment, the electric field insulator 280 by microwave, oxides 230b, given such an oxide 230a, oxides 230b, and an oxygen deficient _{V O} H in the oxide 230a and _{(V O)} It can be divided into hydrogen (H). At this time, a part of the hydrogen separated may be combined with oxygen contained in the insulator 280 to be removed as a water molecule. In addition, part of hydrogen may be gettered to the conductor 242 through the insulator 272 and the insulator 273.

Alternatively, the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

Further, by performing microwave treatment, the film quality of the insulator 280 can be modified, so that diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, hydrogen, water, impurities, and the like can be prevented from diffusing into the oxide 230 through the insulator 280 by a post-process after the formation of the insulator 280, a heat treatment, or the like.

Next, part of the insulator 280, part of the insulator 273, part of the insulator 272, part of the conductive layer 242B, and part of the oxide layer 243B are processed to reach the oxide 230b. To form. The opening is preferably formed so as to overlap with the conductor 205. The conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed by forming the opening (see FIGS. 9A to 9D).

Note that the upper portion of the oxide 230b may be slightly removed when forming the opening. A groove is formed in the oxide 230b by removing part of the oxide 230b. Depending on the depth of the groove, the groove may be formed in the step of forming the opening or in a step different from the step of forming the opening.

In addition, part of the insulator 280, part of the insulator 273, part of the insulator 272, part of the conductive layer 242B, part of the oxide layer 243B, and part of the oxide 230b are dry. An etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 is processed by a dry etching method, part of the insulator 273 is processed by a wet etching method, part of the insulator 272 is processed by a dry etching method, and one of the oxide layers 243B is processed. The portion, a part of the conductive layer 242B, and a part of the oxide 230b may be processed by a dry etching method. Further, part of the oxide layer 243B and part of the conductive layer 242B may be processed under different conditions from part of the oxide 230b.

By performing the conventional dry etching or the like, impurities caused by the etching gas or the like may adhere to the surface of the oxide 230a or the oxide 230b or diffuse into the surface. Examples of impurities include fluorine and chlorine.

-Perform a cleaning process to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in appropriate combination.

As the wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. diluted with carbonated water or pure water, pure water, or carbonated water. Further, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. In addition, these washings may be combined appropriately.

At this time, the film thickness of the insulator 224 may be thin in a region which overlaps with the opening and does not overlap with the oxide 230b.

A film of the insulator 224 in a region where the film thickness of the insulator 224 overlaps with the oxide 230b and does not overlap with the oxide 230b by a process such as dry etching or the above cleaning treatment. It may be thinner than the thickness.

Next, an oxide film 230C is formed (see FIGS. 10A to 10D). Heat treatment may be performed before the oxide film 230C is formed, and the heat treatment is preferably performed under reduced pressure and the oxide film 230C is continuously formed without being exposed to the air. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b or the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment mode, the temperature of the heat treatment is 200° C.

Here, the oxide film 230C includes at least the inner wall of the groove formed in the oxide 230b, part of the side surface of the oxide 243, part of the side surface of the conductor 242, part of the side surface of the insulator 272, and the insulator 273. Is preferably provided so as to be in contact with a part of the side surface of the insulator 280 and a part of the side surface of the insulator 280. Since the conductor 242 is surrounded by the oxide 243, the insulator 272, the insulator 273, and the oxide film 230C, the decrease in conductivity due to the oxidation of the conductor 242 in the subsequent steps can be suppressed.

The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed by a film formation method similar to that of the oxide film 230A or the oxide film 230B depending on the characteristics required for the oxide 230c. In this embodiment, as the oxide film 230C, an oxide target of In:Ga:Zn=5:1:3 [atomic ratio], In:Ga:Zn=10:1:3 [atomic number] is formed by a sputtering method. [Ratio] oxide target or indium oxide target.

Note that the oxide film 230C may be a laminated layer. For example, an oxide target of In:Ga:Zn=5:1:3 [atomic ratio], In:Ga:Zn=10:1:3 [atomic ratio], or indium is formed by a sputtering method. The oxide target may be used for film formation, and the oxide target of In:Ga:Zn=1:3:4 [atomic ratio] may be continuously used for film formation.

When forming the oxide film 230C, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, part of oxygen contained in the sputtering gas may be supplied to the insulator 280 when the oxide film 230C is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or higher, preferably 80% or higher, more preferably 100%.

Next, a mask is formed on the oxide film 230C by a lithography method. Note that a hard mask or a resist mask may be used as the mask.

Next, part of the oxide film 230C is selectively removed using the mask. Note that part of the oxide film 230C may be removed by a wet etching method or the like. Through this step, part of the oxide film 230C located between the transistors 200 adjacent in the channel width direction can be removed.

Note that the surface of the insulator 224 and the surface of the insulator 280 are exposed in the region where part of the oxide film 230C is removed by the above process. At this time, the thickness of the insulator 224 and the thickness of the insulator 280 in the region may be thin. Further, the insulator 224 in the region may be removed and the surface of the insulator 222 may be exposed. The step of forming the mask may also serve as the step of removing a part of the oxide film 230C.

Next, the mask is removed (see FIGS. 11A, 11C and 11D). Note that the mask may be removed by an etching method or the like.

Next, the insulating film 250A is formed (see FIGS. 12A to 12D). Heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure and the insulating film 250A may be continuously formed without being exposed to the air. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C or the like are removed, and moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C are further reduced. be able to. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film forming method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 that is in contact with the oxide 230c in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

Note that when the insulator 250 has a two-layer stacked structure, the insulating film which is a lower layer of the insulator 250 and the insulating film which is an upper layer of the insulator 250 may be formed successively without being exposed to an atmospheric environment. preferable. By forming the film without exposing to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulating film which is the lower layer of the insulator 250 and the insulating film which is the upper layer of the insulator 250. The vicinity of the interface between the insulating film which is the lower layer of the insulator 250 and the insulating film which is the upper layer of the insulator 250 can be kept clean.

Here, after forming the insulating film 250A, microwave treatment may be performed in an atmosphere containing oxygen and under reduced pressure. By performing microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230C, the oxide 230b, the oxide 230a, and the like, so that V in the oxide film 230C, the oxide 230b, and the oxide 230a is reduced. _OH can be divided into V 2 _O and hydrogen. At this time, part of the hydrogen which is separated may be combined with oxygen and converted into H ₂ O, which is removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. In addition, part of hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). By thus performing the microwave treatment, the hydrogen concentration in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. In addition, oxygen is supplied to V _O that may exist after the V _O H in the oxide 230a, the oxide 230b, and V _O H in the oxide film 230C is divided into V _O and hydrogen, so that V _O is restored. You can

Alternatively, the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed. In addition, part of hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, the step of performing heat treatment may be repeated a plurality of times while maintaining the reduced pressure state after the microwave treatment. By repeating the heat treatment, hydrogen in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be removed more efficiently. Note that the heat treatment temperature is preferably higher than or equal to 300 °C and lower than or equal to 500 °C.

Further, by performing microwave treatment, the quality of the insulating film 250A is modified, so that diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, hydrogen, water, impurities, or the like diffuse into the oxide 230b, the oxide 230a, or the like through the insulator 250 by a post-process such as formation of a conductive film to be the conductor 260 or a post-treatment such as heat treatment. Can be suppressed.

Next, a conductive film 260A and a conductive film 260B are sequentially formed (see FIGS. 13A to 13D). The

conductive films

260A and 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP treatment until the insulator 280 is exposed. The body 260a and the conductor 260b) are formed (see FIGS. 14A to 14D). Accordingly, the oxide 230c is arranged so as to cover the opening reaching the oxide 230b and the inner wall (side wall and bottom surface) of the groove portion of the oxide 230b. The insulator 250 is arranged so as to cover the opening and the inner wall of the groove via the oxide 230c. In addition, the conductor 260 is arranged so as to fill the opening and the groove portion with the oxide 230c and the insulator 250 interposed therebetween.

Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, moisture concentration and hydrogen concentration in the insulator 250 and the insulator 280 can be reduced. Note that after the heat treatment, the insulator 282 may be continuously formed without being exposed to the air.

Next, an insulator 282 is formed over the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 15B to 15D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, an aluminum oxide film is preferably formed by a sputtering method. By forming the insulator 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 282 while heating the substrate. In addition, by forming the insulator 282 in contact with the top surface of the conductor 260, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 260 in heat treatment performed later, which is preferable. ..

Next, the insulator 283 is formed over the insulator 282 (see FIGS. 15B to 15D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 283, silicon nitride or silicon nitride oxide is preferably formed. Further, the insulator 283 may have a multi-layer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed by a CVD method over the silicon nitride.

Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, oxygen added by forming the insulator 282 can be diffused into the insulator 280 and further supplied to the oxide 230a and the oxide 230b through the oxide 230c. Note that the heat treatment is not limited to after the insulator 283 is formed, and may be performed after the insulator 282 is formed.

Next, the insulator 284 may be formed over the insulator 283. The insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 284, for example, a silicon nitride film is preferably formed by a sputtering method.

Next, openings are formed in the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 to reach the conductor 242a and the conductor 242b. The opening may be formed by using a lithography method.

Next, an insulating film to be the insulator 241 (the insulator 241a and the insulator 241b) is formed, and the insulating film is anisotropically etched to form the insulator 241. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, an insulating film having a function of suppressing permeation of oxygen is preferably used. For example, it is preferable to form a silicon nitride film by using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

As the anisotropic etching of the insulating film that becomes the insulator 241, for example, a dry etching method may be used. By providing the insulator 241 on the sidewall portion of the opening, permeation of oxygen from the outside can be suppressed and oxidation of the conductor 240a and the conductor 240b which are formed next can be prevented. Further, impurities such as water and hydrogen can be prevented from diffusing outside from the conductor 240a and the conductor 240b.

Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive film preferably has a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP treatment is performed to remove part of the conductive films to be the

conductors

240a and 240b and expose the insulator 284. As a result, the conductor 240a and the conductor 240b whose top surfaces are flat can be formed by leaving the conductive film only in the openings (see FIGS. 4A to 4D). Note that part of the insulator 284 may be removed by the CMP treatment.

Next, a conductive film to be the conductor 246 is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b (see FIGS. 4A to 4D). ). At this time, the insulator 284 in a region where the conductor 246a and the conductor 246b do not overlap with the insulator 284 may be removed.

Next, an insulator 286 is formed over the conductor 246 and the insulator 284 (see FIGS. 4A to 4D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulator 286 may have a multi-layer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed by a CVD method over the silicon nitride.

Through the above steps, a semiconductor device including the transistor 200 illustrated in FIGS. 4A to 4D can be manufactured. As illustrated in FIGS. 6A to 15D, the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.

<Application example of semiconductor device>
In the following, a transistor 200 according to one embodiment of the present invention, which is different from the above-described <Structural example of semiconductor device> and <Modified example of semiconductor device> described above with reference to FIGS. 16A and 16B, is included. An example of a semiconductor device will be described. Note that in the semiconductor device illustrated in FIGS. 16A and 16B, a structure having the same function as the structure of the semiconductor device (see FIGS. 4A to 4D) illustrated in <<Modification 1 of semiconductor device>> is The same symbols are added. Note that in this item, as the constituent material of the transistor 200, the materials described in detail in <Structure example of semiconductor device> and <Modification example of semiconductor device> can be used.

16A and 16B show a structure in which a plurality of transistors (transistors 200_1 to 200_n) are collectively sealed with an insulator 283 and an insulator 211. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 16A and 16B, the invention is not limited thereto. The transistors 200_1 to 200_n may be arranged in the channel width direction or may be arranged in matrix. Further, they may be arranged without regularity depending on the design.

As illustrated in FIG. 16A, outside the plurality of transistors (transistors 200_1 to 200_n), a portion where the insulator 283 and the insulator 211 are in contact with each other (hereinafter, may be referred to as a sealing portion 265) is formed. .. The sealing portion 265 is formed so as to surround a plurality of transistors (also referred to as a transistor group). With such a structure, a plurality of transistors can be wrapped with the insulator 283 and the insulator 211. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

Further, a dicing line (may be referred to as a scribe line, a dividing line, or a cutting line) may be provided so as to overlap the sealing portion 265. Since the substrate is divided in the dicing line, the transistor group surrounded by the sealing portion 265 is taken out as one chip.

16A shows an example in which a plurality of transistors (transistors 200_1 to 200_n) are enclosed by one sealing portion 265, the present invention is not limited to this. As shown in FIG. 16B, a plurality of transistors may be surrounded by a plurality of sealing portions. In FIG. 16B, the plurality of transistors are surrounded by the sealing portion 265a and further surrounded by the outer sealing portion 265b.

By thus surrounding a plurality of transistors (transistors 200_1 to 200_n) with a plurality of sealing portions, a portion where the insulator 283 and the insulator 211 are in contact with each other is increased; thus, the insulator 283 and the insulator 211 are separated from each other. The adhesiveness can be further improved. Thereby, a plurality of transistors can be sealed more reliably.

In this case, the dicing line may be provided so as to overlap the sealing portion 265a or the sealing portion 265b, or the dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

As described above, the structures, methods, and the like described in this embodiment can be combined with the structures, methods, and the like described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[Memory device 1]
FIG. 17 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in any of the above embodiments can be used as the transistor 200.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the stored content can be held for a long time by using the transistor 200 in a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

In the semiconductor device illustrated in FIG. 17, the wiring 1001 is electrically connected to the source of the transistor 300 and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a first gate of the transistor 200, and the wiring 1006 is electrically connected to a second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. ..

The memory devices shown in FIG. 17 can be arranged in a matrix to form a memory cell array.

<Transistor 300>
The transistor 300 is provided over the substrate 311 and includes a conductor 316 which functions as a gate, an insulator 315 which functions as a gate insulator, a semiconductor region 313 which is a part of the substrate 311, and a low region which functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b. The transistor 300 may be either a p-channel type or an n-channel type.

Here, in the transistor 300 illustrated in FIG. 17, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to cover the conductor 316 with the insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material whose work function is adjusted. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

Note that the transistor 300 illustrated in FIG. 17 is an example, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

<Capacitance element 100>
The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

Further, for example, the conductor 112 provided on the conductor 246 and the conductor 110 can be formed at the same time. Note that the conductor 112 has a function as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

Although the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 17, the structure is not limited to this and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between the conductor having barrier property and the conductor having high conductivity.

The insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Etc. may be used, and they can be provided as a laminated layer or a single layer.

For example, it is preferable to use a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 has an insulator having a high dielectric constant (high-k), so that a sufficient capacity can be secured, and an insulator having a large dielectric strength improves the dielectric strength and the capacitance. Electrostatic breakdown of the device 100 can be suppressed.

Note that as a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, silicon, For example, an oxide containing hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

On the other hand, as a material having a high dielectric strength (a material having a low relative dielectric constant), silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen are used. Examples thereof include added silicon oxide, silicon oxide having pores, or resin.

<Wiring layer>
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design. Here, the conductor having a function as a plug or a wiring may have a plurality of structures collectively given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as a wiring, and part of the conductor may function as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film over the transistor 300. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328, a conductor 330, and the like which are electrically connected to the capacitor 100 or the transistor 200. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.

Also, the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to enhance planarity.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 17, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

Similarly, a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 211, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 has a function as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300. Further, an insulator 150 is provided over the conductor 120 and the insulator 130.

Here, similarly to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner walls of the openings formed in the insulator 210, the insulator 211, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218 and the insulator 210, the insulator 211, the insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205 in some cases.

As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 211, the insulator 212, the insulator 214, and the insulator 222, impurities such as water or hydrogen are transferred from the insulator 210 or the insulator 216, or the like. Mixing into the oxide 230 through the body 218 can be suppressed. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. Further, oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218.

The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a PEALD method may be used to form a silicon nitride film and anisotropic etching may be used to form an opening reaching the conductor 356.

The insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc., which have insulating properties.

For example, by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, the material may be selected depending on the function of the insulator.

For example, it is preferable that the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like have insulators with low relative permittivity. For example, the insulator may include silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, silicon oxide having holes, or a resin. preferable. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, or silicon oxide having holes. And a laminated structure of a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like.

Also, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 214, the insulator 211, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.

As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium. The insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or as a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium. A material containing at least one metal element selected from ruthenium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using any of the above materials. The conductive material of can be used as a single layer or a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.

<Wiring or plug in a layer provided with an oxide semiconductor>
Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.

For example, in FIG. 17, the insulator 241 is preferably provided between the insulator 240 and the insulator 280 having excess oxygen, and the conductor 240. When the insulator 241 is provided in contact with the insulator 222, the insulator 272, the insulator 273, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 have barrier properties. A structure for sealing can be formed with the insulator.

That is, by providing the insulator 241, the excess oxygen contained in the insulator 224 and the insulator 280 can be suppressed from being absorbed by the conductor 240. Further, with the insulator 241, hydrogen, which is an impurity, can be suppressed from diffusing into the transistor 200 through the conductor 240.

Note that as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferable. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. Besides, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used.

Further, similarly to the above embodiment modes, the transistor 200 is preferably sealed with the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. .. With such a structure, hydrogen contained in the insulator 274, the insulator 150, and the like can be prevented from entering the insulator 280 and the like.

Here, the conductor 240 penetrates the insulator 284, the insulator 283, and the insulator 282, and the conductor 218 penetrates the insulator 214, the insulator 212, and the insulator 211. The insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. Accordingly, hydrogen mixed in the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 through the conductor 240 and the conductor 218 is reduced. can do. In this manner, the transistor 200 is more reliably sealed with the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, the insulator 284, the insulator 241, and the insulator 217. However, impurities such as hydrogen contained in the insulator 274 and the like can be prevented from entering from the outside.

Further, the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described in the above embodiment. It is preferably formed. Accordingly, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.

In this way, the hydrogen concentration of the silicon-based insulating film near the transistor 200 can be reduced and the hydrogen concentration of the oxide 230 can be reduced.

<Dicing line>
Hereinafter, a dicing line (may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. .. As a dividing method, for example, first, after forming a groove (dicing line) for dividing a semiconductor element on a substrate, cutting may be performed at the dicing line to divide (divide) into a plurality of semiconductor devices.

Here, for example, as shown in FIG. 17, it is preferable to design so that a region where the insulator 283 and the insulator 211 are in contact with each other overlaps the dicing line. That is, the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, and the insulator 216 are provided in the vicinity of a region serving as a dicing line which is provided on the outer edge of the memory cell including the plurality of transistors 200. Openings are provided in the insulator 214 and the insulator 212.

That is, in the openings provided in the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212, the insulator 211, It contacts the insulator 283. In addition, openings are provided in the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 so that the insulator 212 and the insulator 283 are in contact with each other. May be. For example, at this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 with the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.

With the structure, the transistor 200 can be wrapped with the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. At least one of the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, by dividing the substrate for each circuit region in which the semiconductor element described in this embodiment is formed, even when processed into a plurality of chips, impurities such as hydrogen or water are generated from the side surface direction of the divided substrate. It is possible to prevent the contamination and the diffusion to the transistor 200.

Further, with the structure, excess oxygen in the insulator 280 and the insulator 224 can be prevented from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide forming the channel in the transistor 200. With the oxygen, oxygen vacancies in the oxide forming the channel in the transistor 200 can be reduced. Thus, the oxide in which the channel in the transistor 200 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

Note that, in the memory device illustrated in FIG. 17, the shape of the capacitor 100 is a planar type, but the memory device described in this embodiment is not limited to this. For example, as shown in FIG. 18, the shape of the capacitive element 100 may be a cylinder type. The structure of the memory device illustrated in FIG. 18 below the insulator 150 is similar to that of the semiconductor device illustrated in FIG.

The capacitor 100 illustrated in FIG. 18 includes the insulator 150 over the insulator 130, the insulator 142 over the insulator 150, and the conductor 115 arranged in the insulator 150 and the opening formed in the insulator 142. And an insulator 145 over the conductor 115 and the insulator 142, a conductor 125 over the insulator 145, and an insulator 152 over the conductor 125 and the insulator 145. Here, at least a part of the conductor 115, the insulator 145, and the conductor 125 is placed in the openings formed in the insulator 150 and the insulator 142.

The conductor 115 functions as a lower electrode of the capacitor 100, the conductor 125 functions as an upper electrode of the capacitor 100, and the insulator 145 functions as a dielectric of the capacitor 100. In the capacitor 100, in the openings of the insulator 150 and the insulator 142, the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface. The capacity can be increased. Therefore, the capacitance of the capacitive element 100 can be increased as the depth of the opening is increased. By thus increasing the capacitance per unit area of the capacitive element 100, miniaturization or high integration of the semiconductor device can be promoted.

As the insulator 152, an insulator that can be used for the insulator 280 may be used. Further, the insulator 142 preferably functions as an etching stopper when the opening of the insulator 150 is formed, and an insulator that can be used for the insulator 214 may be used.

The shape of the opening formed in the insulator 150 and the insulator 142 as viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a shape in which corners are curved in the polygonal shape. The shape may be circular including an ellipse. Here, it is preferable that the area where the opening and the transistor 200 overlap with each other in the top view is large. With such a structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

The conductor 115 is arranged in contact with the openings formed in the insulator 142 and the insulator 150. It is preferable that the top surface of the conductor 115 substantially match the top surface of the insulator 142. Further, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like. For example, a conductor that can be used as the conductor 205 may be used.

The insulator 145 is arranged so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and nitride. Hafnium or the like may be used and can be provided as a stacked layer or a single layer. For example, as the insulator 145, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used.

Further, it is preferable to use a material having a large dielectric strength such as silicon oxynitride or a material having a high dielectric constant (high-k) for the insulator 145. Alternatively, a stacked structure of a material having high dielectric strength and a high dielectric constant (high-k) material may be used.

Note that as a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, silicon, There are oxides containing hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like. By using such a high-k material, the capacitance of the capacitor 100 can be sufficiently secured even if the insulator 145 is thickened. By making the insulator 145 thick, a leak current generated between the conductor 115 and the conductor 125 can be suppressed.

On the other hand, as materials having high dielectric strength, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and holes are used. There are silicon oxide, resin, and the like. For example, laminated in the order of silicon nitride was deposited using ALD _(SiN x), silicon oxide was deposited using PEALD method _(SiO x), silicon nitride was deposited using ALD (SiN _x) Insulated film can be used. By using such an insulator having a large dielectric strength, the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

The conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 through the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like. For example, a conductor that can be used as the conductor 205 may be used.

The conductor 153 is provided on the insulator 154 and covered with the insulator 156. For the conductor 153, a conductor that can be used for the conductor 112 may be used, and for the insulator 156, an insulator that can be used for the insulator 152 may be used. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[Memory device 2]
FIG. 19 illustrates an example of a memory device using the semiconductor device which is one embodiment of the present invention. The memory device illustrated in FIG. 19 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.

The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this structure, the first gate-source voltage and the second gate-source voltage of the transistor 400 are 0V. In the transistor 400, since the drain currents when the second gate voltage and the first gate voltage are 0 V are extremely small, the second gate voltage of the transistor 200 can be reduced without supplying power to the transistor 200 and the transistor 400. The negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold the memory content for a long time.

Therefore, in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300 and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a first gate of the transistor 200, and the wiring 1006 is electrically connected to a second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the first gate of the transistor 400, the wiring 1009 is electrically connected to the second gate of the transistor 400, and the wiring 1010. Are electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

The memory device shown in FIG. 19 can form a memory cell array by arranging the memory device shown in FIG. 17 in a matrix, like the memory device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 400 may be provided in a smaller number than the transistor 200. In addition, the memory device illustrated in FIG. 19 is similar to the memory device illustrated in FIG. 17 except that the transistor 200 and the transistor 400 are replaced by an insulator 211, an insulator 212, an insulator 214, an insulator 287, and an insulator 282. It can be sealed with the insulator 283 and the insulator 284.

<Transistor 400>
The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460a and a conductor 460b) which functions as a first gate, a conductor 405 which functions as a second gate, an insulator 222 which functions as a gate insulating layer, and an insulator. 224, an insulator 450, an oxide 430d having a channel formation region, a conductor 442a, an oxide 443a, an oxide 431a, and an oxide 431b which function as a source, and a conductor 442b and an oxide which function as a drain. 443b, the oxide 432a, and the oxide 432b. Similarly to the transistor 200, a conductor functioning as a plug is provided in contact with the

conductors

442a and 442b.

The conductor 405 and the conductor 205 are formed in the same layer. The oxide 431a and the oxide 432a and the oxide 230a are formed in the same layer, and the oxide 431b and the oxide 432b and the oxide 230b are formed in the same layer. The conductor 442a, the conductor 442b, and the conductor 242 are formed in the same layer. The oxide 443a, the oxide 443b, and the oxide 243 are formed in the same layer. The oxide 430d and the oxide 230d are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer.

Note that structures formed on the same layer can be formed at the same time. For example, the oxide 430d can be formed by processing an oxide film to be the oxide 230d.

Like the oxide 230, the oxide 430d functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water. Accordingly, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely reduced.

In the transistor 400, it is preferable that the oxide film to be the oxide 230c in a region overlapping with the conductor 460 be removed and the oxide film to be the oxide 230d be formed and processed to form the oxide 430d. Note that the oxide film to be the oxide 230c in a region overlapping with the conductor 460 may be removed at a timing at which part of the oxide film 230C is removed by wet etching or the like.

[Memory device 3]
FIG. 20 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention.

<Memory device configuration example>
FIG. 20 is a cross-sectional view of a semiconductor device having the memory device 290. The memory device 290 illustrated in FIG. 20 includes a capacitor device 292 in addition to the transistor 200 illustrated in FIGS. 4A to 4D. 20 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

The capacitive device 292 includes a conductor 242b, an insulator 272 provided over the conductor 242b, an insulator 273, and a conductor 294 provided over the insulator 273. That is, the capacitance device 292 constitutes a MIM (Metal-Insulator-Metal) capacitance. Note that one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b can also serve as a source electrode or a drain electrode of the transistor. The dielectric layer included in the capacitor device 292 can also serve as a protective layer provided in the transistor, that is, the insulator 272 and the insulator 273. Therefore, part of the manufacturing process of the transistor 200 can be used in the manufacturing process of the capacitor device 292, so that the semiconductor device can have high productivity. In addition, one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b also serves as a source electrode or a drain electrode of the transistor 200; thus, the area where the transistor 200 and the capacitor device 292 are provided can be reduced. Is possible.

Note that as the conductor 294, for example, a material that can be used for the conductor 242 may be used.

<Modification of memory device>
Hereinafter, with reference to FIGS. 21A, 21B, 22, and 23, a transistor 200 and a capacitor device 292 according to one embodiment of the present invention, which are different from those described above in <Structure example of memory device>, are described. An example of a semiconductor device having a will be described. In the semiconductor devices shown in FIGS. 21A, 21B, 22, and 23, a structure having the same function as the structure of the semiconductor device shown in the above embodiment and <Structure example of memory device> is The same symbols are added. Note that in this item, as the constituent material of the transistor 200 and the capacitor device 292, the material described in detail in the above embodiment and <Structure example of memory device> can be used.

<<First Modification of Memory Device>>
Hereinafter, an example of the semiconductor device 600 including the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b according to one embodiment of the present invention will be described with reference to FIG. 21A.

FIG. 21A is a cross-sectional view in the channel length direction of a semiconductor device 600 including the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b. As shown in FIG. 21A, the semiconductor device 600 has a line-symmetrical structure with the dashed-dotted line A3-A4 as the axis of symmetry. The conductor 242c serves as one of a source electrode and a drain electrode of the transistor 200a and one of a source electrode and a drain electrode of the transistor 200b. In addition, the conductor 246 which functions as a wiring and the conductor 240 which also functions as a plug also serve as a connection between the transistor 200a and the transistor 200b. As described above, the two transistors, the two capacitive devices, and the connection between the wiring and the plug are configured as described above, whereby a semiconductor device which can be miniaturized or highly integrated can be provided.

For the configurations and effects of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b, the configuration example of the semiconductor device illustrated in FIGS. 4A to 4D and FIG. 20 can be referred to.

<<Modification 2 of Memory Device>>
Although the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b are given as examples of the structure of the semiconductor device in the above, the semiconductor device described in this embodiment is not limited to this. For example, as illustrated in FIG. 21B, the semiconductor device 600 and a semiconductor device having a structure similar to that of the semiconductor device 600 may be connected to each other through a capacitor portion. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b is referred to as a cell. For the structures of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b, the above description of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b can be referred to.

21B is a cross-sectional view in which a semiconductor device 600 including the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b, and a cell having a structure similar to that of the semiconductor device 600 are connected to each other through a capacitor portion.

As shown in FIG. 21B, the conductor 294b functioning as one electrode of the capacitor device 292b included in the semiconductor device 600 also serves as one electrode of the capacitor device included in the semiconductor device 601 having the same structure as the semiconductor device 600. Has become. Although not illustrated, the conductor 294a which functions as one electrode of the capacitor device 292a included in the semiconductor device 600 is provided on the left side of the semiconductor device 600, that is, in one of the capacitor devices of the semiconductor device which are adjacent to each other in the direction A1 in FIG. 21B. Also serves as an electrode. Further, the right side of the semiconductor device 601, that is, the cell in the A2 direction in FIG. 21B has the same configuration. That is, a cell array (also referred to as a memory device layer) can be formed. With such a cell array configuration, the interval between adjacent cells can be reduced, so that the projected area of the cell array can be reduced and high integration can be achieved. Further, by arranging the configuration of the cell array shown in FIG. 21B in a matrix, a matrix cell array can be constructed.

As described above, by forming the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b with the structure described in this embodiment, the area of the cell is reduced and a semiconductor device including a cell array is downsized or improved. It can be integrated.

Also, the cell arrays may be stacked not only on a plane. FIG. 22 shows a cross-sectional view of a structure in which the cell array 610 is laminated in n layers. As shown in FIG. 22, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be configured.

<<Modification 3 of Memory Device>>
FIG. 23 illustrates an example in which the memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

Each of the memory device layers 415_1 to 415_4 has a plurality of memory devices 420.

The memory device 420 is electrically connected to the memory device 420 included in the different memory device layer 415 and the transistor 200T included in the transistor layer 413 through the conductor 424 and the conductor 205.

The memory unit 470 is sealed by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 (hereinafter, referred to as a sealing structure for convenience). ). An insulator 274 is provided around the insulator 284. Further, a conductor 440 is provided in the insulator 274, the insulator 284, the insulator 283, and the insulator 211, and is electrically connected to the element layer 411.

Also, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen by heating. Alternatively, the insulator 280 has an excess oxygen region.

Note that the insulator 211, the insulator 283, and the insulator 284 are preferably materials having a function of high blocking property against hydrogen. Further, the insulator 214, the insulator 282, and the insulator 287 are preferably a material having a function of trapping hydrogen or fixing hydrogen.

For example, as the material having the function of having a high blocking property against hydrogen, silicon nitride, silicon nitride oxide, or the like can be given. Examples of the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

Note that, in the present specification, the barrier property is a function of suppressing diffusion of a corresponding substance (also referred to as low permeability). Alternatively, the corresponding substance has a function of capturing and fixing (also referred to as gettering).

Note that there is no particular limitation on a crystal structure of a material used for the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284; A structure having properties may be used. For example, an amorphous aluminum oxide film is preferably used as a material having a function of capturing hydrogen or fixing hydrogen. Amorphous aluminum oxide may have a larger amount of trapping and fixing hydrogen than aluminum oxide having high crystallinity.

Here, excess oxygen in the insulator 280 can be modeled as follows with respect to diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

Hydrogen existing in the oxide semiconductor diffuses to another structure through the insulator 280 which is in contact with the oxide semiconductor. The hydrogen reacts with excess oxygen in the insulator 280 to form an OH bond, and diffuses in the insulator 280 as OH. A hydrogen atom having an OH bond is an atom in the insulator 282 (e.g., a metal atom, etc.) when reaching a material (typically, the insulator 282) having a function of trapping hydrogen or fixing hydrogen. ), and is trapped or fixed in the insulator 282. On the other hand, it is presumed that the excess oxygen having the OH bond remains in the insulator 280 as excess oxygen. That is, it is highly possible that excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.

In order to satisfy the above model, the semiconductor device manufacturing process is one of the important factors.

As an example, the insulator 280 having excess oxygen is formed in the oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, more preferably 8 hours or longer.

By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280, the insulator 282, and the insulator 287. That is, the absolute amount of hydrogen existing in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

After the heat treatment, the insulator 283 and the insulator 284 are formed. The insulator 283 and the insulator 284 are materials having a function of high blocking property against hydrogen; therefore, hydrogen diffused outward or hydrogen existing outside can be stored inside, specifically, in an oxide semiconductor. Alternatively, it is possible to suppress the entry into the insulator 280 side.

Note that the above heat treatment has been described as an example of the structure performed after the insulator 282 is formed; however, the present invention is not limited to this. For example, the above heat treatment may be performed after each of the transistor layer 413 and the memory device layers 415_1 to 415_3. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413. Similarly, in the case where heat treatment is performed after formation of the memory device layers 415_1 to 415_3, hydrogen is diffused upward or laterally.

By the above manufacturing process, the insulator 211 and the insulator 283 are bonded to each other, whereby the above-described sealing structure is formed.

As described above, with the above structure and the above manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a highly reliable semiconductor device can be provided. Further, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided.

The structure, the method, and the like described in this embodiment can be combined with the structure, the structure, the method, and the like described in other embodiments as appropriate.

(Embodiment 3)
In this embodiment, with reference to FIGS. 24A, 24B, and 25A to 25H, a transistor including an oxide as a semiconductor (hereinafter, referred to as an OS transistor in some cases) according to one embodiment of the present invention, A storage device to which a capacitor is applied (hereinafter also referred to as an OS memory device in some cases) will be described. An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

<Structure example of storage device>
FIG. 24A shows an example of the configuration of the OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from the memory cell. Note that the wiring is a wiring connected to a memory cell included in the memory cell array 1470 and will be described later in detail. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 has a row decoder, a word line driver circuit, and the like, for example, and can select a row to be accessed.

A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the storage device 1400 as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.

The memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the structure of the memory cell MC, the number of memory cells MC in one column, and the like. Further, the number of wirings that connect the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.

Note that although FIG. 24A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 24B, a memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

25A to 25H, an example of the configuration of a memory cell applicable to the above memory cell MC will be described.

[DOSRAM]
25A to 25C show examples of circuit configurations of DRAM memory cells. In this specification and the like, a DRAM including a 1-OS transistor 1-capacitive element memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 illustrated in FIG. 25A includes the transistor M1 and the capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected. Are connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable to apply a low-level potential to the wiring CAL at the time of writing and reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Here, the memory cell 1471 shown in FIG. 25A corresponds to the storage device shown in FIG. That is, the transistor M1 corresponds to the transistor 200 and the capacitor CA corresponds to the capacitor device 292.

Also, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, in the memory cell MC, like the memory cell 1472 illustrated in FIG. 25B, the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL. Further, for example, the memory cell MC may be a memory cell including a transistor having a single-gate structure, that is, a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG. 25C.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leak current of the transistor M1 can be made extremely small. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced and the storage capacity of the memory cell can be reduced.

[NOSRAM]
25D to 25G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 illustrated in FIG. 25D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (may be simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell in which an OS transistor is used as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected. Are connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data retention, and during data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

Here, the memory cell 1474 shown in FIG. 25D corresponds to the storage device shown in FIG. That is, the transistor M2 is the transistor 200, the capacitor CB is the capacitor 100, the transistor M3 is the transistor 300, the wiring WBL is the wiring 1003, the wiring WOL is the wiring 1004, the wiring BGL is the wiring 1006, and the wiring CAL is the wiring. 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

The memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, in the memory cell MC, like the memory cell 1475 illustrated in FIG. 25E, the back gate of the transistor M2 may be connected to the wiring WOL instead of the wiring BGL. Further, for example, the memory cell MC may be a memory cell including a transistor having a single gate structure, that is, a transistor M2 having no back gate, like the memory cell 1476 shown in FIG. 25F. Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL like the memory cell 1477 illustrated in FIG. 25G.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leak current of the transistor M2 can be made extremely small. Accordingly, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is very small, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter, also referred to as Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by being stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.

Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be formed using only n-type transistors.

Further, FIG. 25H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 illustrated in FIG. 25H includes transistors M4 to M6 and a capacitor CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL. The wiring GNDL is a wiring which gives a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

The transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-type transistors.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5, M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leak current of the transistor M4 can be made extremely small.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

Generally, in semiconductor devices such as computers, various storage devices (memory) are used depending on the application. FIG. 26 shows various storage devices for each hierarchy. A storage device located in the upper layer is required to have a high access speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density. In FIG. 26, a memory, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory that are mixedly mounted as a register in an arithmetic processing unit such as a CPU are shown in order from the top layer.

The memory that is embedded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and so is frequently accessed by the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required. The register also has a function of holding setting information of the arithmetic processing unit.

SRAM is used for cache, for example. The cache has a function of copying a part of the information held in the main memory and holding it. By duplicating frequently used data in the cache, the access speed to the data can be increased.

The DRAM is used as, for example, a main memory. The main memory has a function of holding programs and data read from the storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit/mm ² .

The 3D NAND memory is used for storage, for example. The storage has a function of holding data that needs to be stored for a long time, various programs used in the arithmetic processing device, and the like. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density. The storage density of a storage device used for storage is approximately 0.6 to 6.0 Gbit/mm ² .

The storage device of one embodiment of the present invention has high operation speed and can hold data for a long time. The storage device of one embodiment of the present invention can be preferably used as a storage device located in a boundary area 901 including both a hierarchy where a cache is located and a hierarchy where a main memory is located. Further, the storage device of one embodiment of the present invention can be favorably used as a storage device located in the boundary area 902 including both the hierarchy where the main memory is located and the hierarchy where the storage is located.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 4)
In this embodiment mode, an example of a chip 1200 in which a semiconductor device of the present invention is mounted is shown with reference to FIGS. 27A and 27B. A plurality of circuits (systems) are mounted on the chip 1200. The technique of integrating a plurality of circuits (systems) on a single chip in this manner may be referred to as a system on chip (SoC).

As shown in FIG. 27A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

A bump (not shown) is provided on the chip 1200, and is connected to a first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 27B. A plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the mother board 1203.

The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in any of the above embodiments can be used as the DRAM 1221. Further, for example, the NOSRAM described in the above embodiment can be used for the flash memory 1222.

The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention or a product-sum operation circuit, image processing and product-sum operation can be performed with low power consumption.

Since the CPU 1211 and the GPU 1212 are provided in the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories included in the CPU 1211 and the GPU 1212, Further, after the calculation in the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

The analog operation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog-calculation unit 1213 may be provided with the product-sum calculation circuit.

The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.

The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit 1216 has a network circuit such as a LAN (Local Area Network). In addition, a circuit for network security may be included.

The above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be called a GPU module 1204.

Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. Moreover, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, portable (carry-out) game machines, and the like. Further, a product-sum operation circuit using the GPU 1212 allows deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), self-encoders, deep Boltzmann machines (DBM), deep belief networks ( The chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module because a technique such as DBN) can be performed.

(Embodiment 5)
This embodiment mode shows an example of an electronic component and an electronic device in which the memory device or the like described in the above embodiment mode is incorporated.

<Electronic parts>
First, an example of an electronic component in which the memory device 720 is incorporated will be described with reference to FIGS. 28A and 28B.

FIG. 28A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. The electronic component 700 shown in FIG. 28A has a storage device 720 in a mold 711. 28A, part of the electronic component 700 is omitted in order to show the inside thereof. The electronic component 700 has a land 712 outside the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by the wire 714. The electronic component 700 is mounted on the printed board 702, for example. The mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them to each other on the printed board 702.

The storage device 720 has a drive circuit layer 721 and a storage circuit layer 722.

28B shows a perspective view of the electronic component 730. The electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package board 732 (printed board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.

The electronic component 730 shows an example in which the storage device 720 is used as a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or a multilayer. In addition, the interposer 731 has a function of electrically connecting an integrated circuit provided over the interposer 731 to an electrode provided over the package substrate 732. From these things, an interposer may be called a "redistribution board" or an "intermediate board." In addition, a through electrode may be provided in the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode. In the silicon interposer, TSV (Through Silicon Via) can also be used as the through electrode.

It is preferable to use a silicon interposer as the interposer 731. Since the silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.

In HBM, it is necessary to connect many wirings in order to realize a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use the silicon interposer as the interposer for mounting the HBM.

Also, with SiP and MCM that use a silicon interposer, it is difficult for reliability to decrease due to the difference in expansion coefficient between the integrated circuit and the interposer. Further, since the silicon interposer has a high surface flatness, a poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 730. When the heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are uniform. For example, in the electronic component 730 described in this embodiment, it is preferable that the memory device 720 and the semiconductor device 735 have the same height.

An electrode 733 may be provided on the bottom of the package substrate 732 to mount the electronic component 730 on another substrate. FIG. 28B shows an example in which the electrode 733 is formed of a solder ball. BGA (Ball Grid Array) mounting can be realized by providing solder balls in a matrix on the bottom of the package substrate 732. Alternatively, the electrode 733 may be formed of a conductive pin. PGA (Pin Grid Array) mounting can be realized by providing conductive pins in a matrix on the bottom of the package substrate 732.

The electronic component 730 can be mounted on another board by using various mounting methods other than BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad-on-adhesive) method or QFN (Quad-on-Flade) method. be able to.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, application examples of a memory device including any of the semiconductor devices described in the above embodiments will be described. The semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (eg, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, and the like). Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in any of the above embodiments is applied to various removable storage devices such as a memory card (eg, an SD card), a USB memory, an SSD (solid state drive), and the like. 29A to 29E schematically show some configuration examples of the removable storage device. For example, the semiconductor device described in any of the above embodiments is processed into a packaged memory chip and used for various storage devices and removable memories.

FIG. 29A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like.

FIG. 29B is a schematic diagram of the external appearance of the SD card, and FIG. 29C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, the memory chip 1114 and the controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided over the substrate 1113. As a result, the data in the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 or the like.

FIG. 29D is a schematic diagram of the external appearance of the SSD, and FIG. 29E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 or the like.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 7)
The semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. 30A to 30H show specific examples of electronic devices each including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.

<Electronic devices and systems>
The GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic device include a relatively large screen such as a television device, a monitor for a desktop or notebook information terminal, a digital signage (digital signage), a large game machine such as a pachinko machine, and the like. In addition to electronic devices including, a digital camera, a digital video camera, a digital photo frame, an electronic book reader, a mobile phone, a portable game machine, a personal digital assistant, a sound reproducing device, and the like. By providing the electronic device with the GPU or the chip according to one embodiment of the present invention, artificial intelligence can be mounted on the electronic device.

The electronic device of one embodiment of the present invention may include an antenna. By receiving the signal with the antenna, images, information, and the like can be displayed on the display portion. When the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It has a function of measuring voltage, electric power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light).

The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like. 30A to 30H show examples of electronic devices.

[Information terminal]
FIG. 30A illustrates a mobile phone (smartphone) that is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. A touch panel is provided in the display portion 5102 and a button is provided in the housing 5101 as an input interface.

By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute an application utilizing artificial intelligence. As an application using artificial intelligence, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5102, recognizes a character or a figure input by a user on a touch panel included in the display unit 5102, An application displayed on the display portion 5102, an application for biometric authentication such as a fingerprint or a voiceprint, and the like can be given.

FIG. 30B shows a notebook information terminal 5200. The laptop information terminal 5200 includes a main body 5201 of the information terminal, a display portion 5202, and a keyboard 5203.

Like the information terminal 5100 described above, the notebook information terminal 5200 can execute an application utilizing artificial intelligence by applying the chip of one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook information terminal 5200, new artificial intelligence can be developed.

Note that, in the above description, although a smartphone and a notebook information terminal are illustrated as an electronic device in FIGS. 30A and 30B, respectively, information terminals other than the smartphone and the notebook information terminal can be applied. Examples of information terminals other than smartphones and notebook information terminals include PDA (Personal Digital Assistant), desktop information terminals, workstations, and the like.

[game machine]
FIG. 30C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The

housings

5302 and 5303 can be removed from the housing 5301. By attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), an image output to the display portion 5304 can be output to another video device (not shown). it can. At this time, the housing 5302 and the housing 5303 can each function as an operation portion. This allows a plurality of players to play the game at the same time. The chip described in any of the above embodiments can be incorporated in chips provided on the substrates of the

housings

5301, 5302, and 5303.

Further, FIG. 30D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

By applying the GPU or the chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 or the stationary game machine 5400, a game machine with low power consumption can be realized. In addition, low power consumption can reduce heat generation from a circuit, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

Further, by applying the GPU or the chip of one embodiment of the present invention to the mobile game machine 5300, the mobile game machine 5300 having artificial intelligence can be realized.

Originally, expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program included in the game. However, by applying artificial intelligence to the portable game machine 5300, , It is possible to express without being limited to the game program. For example, it is possible to express that the content of the question asked by the player, the progress of the game, the time, and the behavior of the person appearing in the game changes.

Further, when a plurality of players play a necessary game on the portable game machine 5300, the artificial intelligence can configure the game player as an anthropomorphic person. You can play games.

30C and 30D illustrate a portable game machine and a stationary game machine as examples of the game machine, the game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto. As a game machine to which the GPU or the chip of one embodiment of the present invention is applied, for example, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a batting practice pitching machine installed in a sports facility, or the like. Are listed.

[Large computer]
The GPU or chip of one embodiment of the present invention can be applied to a large computer.

FIG. 30E is a diagram showing a super computer 5500, which is an example of a large computer. FIG. 30F is a diagram showing a rack mount computer 5502 included in the super computer 5500.

The super computer 5500 has a rack 5501 and a plurality of rack mount computers 5502. The plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or the chip described in any of the above embodiments can be mounted on the substrates.

Super computer 5500 is a large computer mainly used for scientific and technological calculations. Scientific calculation requires high-speed processing of a huge amount of calculation, resulting in high power consumption and high chip heat generation. By applying the GPU or the chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, low power consumption can reduce heat generation from a circuit, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

30E and 30F illustrate a supercomputer as an example of a large computer, the large computer to which the GPU or the chip of one embodiment of the present invention is applied is not limited to this. Examples of large-sized computers to which the GPU or chip of one embodiment of the present invention is applied include computers (servers) that provide services, large-sized general-purpose computers (mainframes), and the like.

[Mobile]
The GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving object and around the driver's seat of the automobile.

FIG. 30G is a diagram showing the vicinity of the windshield in the interior of an automobile, which is an example of a moving body. FIG. 30G illustrates the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard, and the display panel 5704 attached to the pillar.

The display panels 5701 to 5703 can provide various other information by displaying speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, and the like. The display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as a lighting device.

By displaying an image from an image pickup device (not shown) provided on the automobile on the display panel 5704, the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying the image from the image pickup device provided outside the automobile, the blind spot can be compensated and the safety can be improved. In addition, by displaying an image that complements the invisible portion, it is possible to confirm the safety more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system of an automobile. In addition, the chip can be used for a system that performs road guidance, danger prediction, and the like. Information such as road guidance and risk prediction may be displayed on the display panels 5701 to 5704.

In the above, a car is described as an example of the moving body, but the moving body is not limited to the car. For example, as the moving object, a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), or the like can be given, and the chip of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be added.

[Electronics]
FIG. 30H shows an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.

By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the food items stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuff, and the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature to match the food.

Although an electric refrigerator-freezer is described as an example of the electric appliance, other electric appliances include, for example, a vacuum cleaner, a microwave oven, a microwave oven, a rice cooker, a water heater, an IH cooker, a water server, an air conditioner including an air conditioner, Examples include washing machines, dryers and audiovisual equipment.

The electronic device described in this embodiment, the function of the electronic device, the application example of the artificial intelligence, the effect, and the like can be appropriately combined with the description of other electronic devices.

100: capacitive element, 110: conductor, 112: conductor, 115: conductor, 120: conductor, 125: conductor, 130: insulator, 140: conductor, 142: insulator, 145: insulator, 150: insulator, 152: insulator, 153: conductor, 154: insulator, 156: insulator, 200: transistor, 200_n: transistor, 200_1: transistor, 200a: transistor, 200b: transistor, 200T: transistor, 205 : Conductor, 205a: conductor, 205b: conductor, 210: insulator, 211: insulator, 212: insulator, 214: insulator, 216: insulator, 217: insulator, 218: conductor, 222 : Insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230c1: oxide, 230c2: oxide, 230C : Oxide film, 230d: oxide, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A : Conductive film, 242b: conductive material, 242B: conductive layer, 242c: conductive material, 243a: oxide, 243A: oxide film, 243b: oxide film, 243B: oxide layer, 246: conductive material, 246a: conductor, 246b: conductor, 250: insulator, 250A: insulating film, 260: conductor, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 265: sealing part 265a: sealing part, 265b: sealing part, 272: insulator, 273: insulator, 274: insulator, 280: insulator, 282: insulator, 283: insulator, 284: insulator, 286: Insulator, 287: Insulator, 290: Memory device, 292: Capacitance device, 292a: Capacitance device, 292b: Capacitance device, 294: Conductor, 294a: Conductor, 294b: Conductor, 300: Transistor, 311: Substrate 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 411: Element layer, 413: Transistor layer, 415: Memory Device layer, 415_1: memory device Vise layer, 415_3: memory device layer, 415_4: memory device layer, 420: memory device, 424: conductor, 430d: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: conductor, 442a: conductor, 442b: conductor, 443a: oxide, 443b: oxide, 450: insulator, 460: conductor, 460a: conductor, 460b: conductor, 470: memory unit, 600: semiconductor device, 601: semiconductor device, 610: cell array, 610_1: cell array, 610_n: cell array, 700: electronic component, 702: printed board, 704: mounting board, 711: mold, 712: land, 713: electrode pad, 714: Wire, 720: Storage device, 721: Drive circuit layer, 722: Storage circuit layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 901: Border region, 902 : Boundary area, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 1008: wiring, 1009: wiring, 1010: wiring, 1100: USB memory, 1101 : Housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: PCB, 1202: bump, 1203 : Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog operation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: Storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell, 1474: memory cell. , 1475: memory cell, 1476: memory cell, 14 77: memory cell, 1478: memory cell, 5100: information terminal, 5101: housing, 5102: display portion, 5200: notebook information terminal, 5201: main body, 5202: display portion, 5203: keyboard, 5300: portable game machine 5301: housing, 5302: housing, 5303: housing, 5304: display portion, 5305: connection portion, 5306: operation keys, 5400: model game machine, 5402: controller, 5500: super computer, 5501: rack, 5502: Calculator, 5504: Substrate, 5701: Display panel, 5702: Display panel, 5703: Display panel, 5704: Display panel, 5800: Electric freezer/refrigerator, 5801: Housing, 5802: Refrigerator door, 5803: Freezer room Door

Claims

A semiconductor device having a transistor,
The transistor is
A first conductor,
A first insulator on the first conductor;
A first oxide on the first insulator;
A second conductor and a third conductor on the first oxide;
A second oxide on the first oxide and between the second conductor and the third conductor;
A second insulator on the second oxide;
A fourth conductor on the second insulator,
A top surface of the first oxide in a region overlapping with the fourth conductor is lower than bottom surfaces of the second conductor and the third conductor,
A difference between a top surface of the second oxide in a region overlapping with the fourth conductor and a bottom surface of the second conductor or the third conductor is a region overlapping with the fourth conductor. Smaller than the film thickness of the second oxide of
Semiconductor device.
A semiconductor device having a transistor,
The transistor is
A first conductor,
A first insulator on the first conductor;
A first oxide on the first insulator;
A second conductor and a third conductor on the first oxide;
A second oxide on the first oxide and between the second conductor and the third conductor;
A second insulator on the second oxide;
A fourth conductor on the second insulator,
A top surface of the first oxide in a region overlapping with the fourth conductor is lower than bottom surfaces of the second conductor and the third conductor,
The difference between the top surface of the first oxide and the bottom surface of the second conductor and the third conductor in a region overlapping with the fourth conductor is 1 nm or more and 7 nm or less,
The film thickness of the second oxide in the region overlapping with the fourth conductor is 1 nm or more and 5 nm or less,
Semiconductor device.
In claim 1 or claim 2,
The second oxide comprises indium,
Semiconductor device.
In claim 1 or claim 2,
The second oxide includes indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc,
In the second oxide, the atomic ratio of indium to the main metal element is the atomic ratio of element M to the main metal element and the atomic ratio of zinc to the main metal element. Greater than,
Semiconductor device.
In claim 4,
The second oxide is In:Ga:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=10:1:3 [atomic ratio] or its composition. A metal oxide having a composition in the vicinity,
Semiconductor device.
In any one of Claim 3 thru|or 5,
The first oxide includes indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc,
In the second oxide, the atomic ratio of indium to the metal element as the main component is higher than the atomic ratio of indium to the metal element as the main component in the first oxide,
Semiconductor device.
In any one of Claim 1 thru|or Claim 6,
The second insulator has a structure in which a first insulating layer and a second insulating layer are sequentially stacked,
The first insulating layer has silicon,
The second insulating layer has one or both of hafnium and zirconium,
Semiconductor device.
In any one of Claim 1 thru|or Claim 7,
In a cross-sectional view of the transistor in the channel width direction, the transistor has a region where the first insulator and the second insulator are in contact with each other.
Semiconductor device.