Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • G06N10/80—Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing

Definitions

• the present invention relates generally to variational algorithms using quantum computing. More particularly, the present invention relates to a method for incremental generation of quantum circuits.
• a "Q” prefix in a word of phrase is indicative of a reference of that word or phrase in a quantum computing context unless expressly distinguished where used.
• a conventional computer uses a conventional processor fabricated using semiconductor materials and technology, a semiconductor memory, and a magnetic or solid-state storage device, in what is known as a Von Neumann architecture.
• the processors in conventional computers are binary processors, i.e., operating on binary data represented in 1 and 0.
• a quantum processor uses the odd nature of entangled qubit devices (compactly referred to herein as "qubit,” plural “qubits”) to perform computational tasks.
• qubit entangled qubit devices
• particles of matter can exist in multiple states—such as an "on” state, an “off” state, and both "on” and “off” states simultaneously.
• binary computing using semiconductor processors is limited to using just the on and off states (equivalent to 1 and 0 in binary code)
• a quantum processor harnesses these quantum states of matter to output signals that are usable in data computing.
• Quantum computers encode information in bits. Each bit can take the value of 1 or 0. These 1s and 0s act as on/off switches that ultimately drive computer functions.
• Quantum computers are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both a 1 and a 0 at the same time.
• Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is a 1 or a 0 or both) can depend on the state of another, and that there is more information that can be ascertained about the two qubits when they are entangled than when they are treated individually.
• qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers.
• IBM has successfully constructed and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines corporation in the United States and in other countries.)
• Quantum algorithms apply quantum operations (quantum gates) on subsets of qubits.
• Quantum gates are analogous to instructions in a classical computing program.
• a quantum circuit is a representation of a quantum algorithm using quantum gates.
• the illustrative embodiments recognize that presently available quantum computing models require quantum algorithms to be specified as quantum circuits on idealized hardware, instead of an actual quantum computer.
• the illustrative embodiments further recognize that quantum algorithms require mapping into a representation that an actual quantum computer can execute, through a process known as quantum circuit compilation.
• compilation often requires adding additional gates to move qubit states to locations where a desired gate acts upon the qubit state due to the physical constraints of the actual quantum computer.
• quantum processors can perform variational algorithms which conventional processors are incapable of performing.
• the illustrative embodiments further recognize that presently available quantum variational algorithms require quantum circuit compilation for each iteration
• a conventional processor performs an optimization algorithm that varies the parameters of the wavefunction.
• a quantum processor computes the corresponding total energy of the wavefunction.
• the illustrative embodiments recognize that compilation of each quantum circuit represents a significant amount of the overall run time for the quantum algorithm.
• the illustrative embodiments further recognize that many quantum algorithms are composed of structurally identical quantum circuits.
• the illustrative embodiments further recognize that a quantum circuit compiler never changes a temporal order in which a given gate appears on a given set of qubits.
• an uncompiled quantum circuit can comprise a first and second measure gate on a first qubit. After compilation, the compiled quantum circuit will comprise a first and second measure gate on the first qubit and executed in the same order as the uncompiled quantum circuit.
• a method includes compiling, in response to determining a structural inequality of the first quantum circuit and the second quantum circuit, the first quantum circuit.
• a structural inequality includes a number of a specific type of quantum logic gate of the first set of quantum logic gates differs from a number of the specific type of quantum logic gate of the second set of quantum logic gates.
• a method includes storing a set of previously compiled quantum circuits in a database.
• a structural equality includes a number of each specific type of quantum logic gate of the first set of quantum logic gates equals a number of the same specific type of quantum logic gate of the second set of quantum logic gates.
• the method is embodied in a computer program product comprising one or more computer-readable storage devices and computer-readable program instructions which are stored on the one or more computer-readable tangible storage devices and executed by one or more processors.
• An embodiment includes a computer usable program product.
• the computer usable program product includes a computer-readable storage device, and program instructions stored on the storage device.
• An embodiment includes a computer system.
• the computer system includes a processor, a computer- readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.
• Figure 1 depicts a block diagram of a network of data processing systems in which illustrative embodiments may be implemented;
• Figure 2 depicts a block diagram of a data processing system in which illustrative embodiments may be implemented;
• Figure 3 depicts a block diagram of an example configuration for incremental generation of quantum circuits in accordance with an illustrative embodiment
• Figure 4 depicts a block diagram of an example configuration for incremental generation of quantum circuits in accordance with an illustrative embodiment
• Figure 5 depicts a flowchart of an example method for incremental generation of quantum circuits in accordance with an illustrative embodiment.
• the illustrative embodiments used to describe the invention generally address and solve the above- described problems of quantum circuit compilation.
• the illustrative embodiments provide a method for incremental generation of quantum circuits.
• An embodiment provides a method for incremental generation of quantum circuits.
• Another embodiment provides a quantum computer usable program product comprising a computer-readable storage device, and program instructions stored on the storage device, the stored program instructions comprising a method for incremental generation of quantum circuits. The instructions are executable using a conventional or quantum processor.
• Another embodiment provides a computer system comprising a conventional or quantum processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions comprising a method for incremental generation of quantum circuits.
• hybrid quantum algorithms such as variational algorithms
• hybrid quantum algorithms include a handoff between a classical computer generating inputs or modifications to a quantum circuit, running the circuit on a quantum computer, and using the output to serially generate a subsequent quantum circuit.
• the Variational Quantum Eigensolver (VQE) is one non-limiting example of a variational algorithm performed with quantum computers.
• An embodiment detects a first quantum circuit submitted for compilation.
• the first quantum circuit is an uncompiled quantum circuit.
• An embodiment compares the first quantum circuit to a previously compiled quantum circuit. For example, an embodiment generates a first list of a first set of quantum gates of the first quantum circuit, each quantum gate acting on a corresponding set of qubits of the first quantum circuit.
• the embodiment also generates a second list of a second set of quantum gates of the previously compiled quantum circuit, each quantum gate acting on a corresponding set of qubits of the previously compiled quantum circuit.
• the embodiment compares the first list to the second list to determine a structural similarity between the first circuit and the previously compiled circuit.
• the first circuit and the previously compiled circuit are structurally equal when the number of gates of each type in the first list match the number of gates of each type in the second list.
• the embodiment can determine the number of gates of a first gate type in the first list differs from the number of gates of the first gate type in the second list.
• the embodiment determines the first circuit and the previously compiled circuit fail to be structurally equal.
• the embodiment compiles, in response to determining the first circuit and the previously compiled circuit fail to be structurally equal, the first circuit.
• the embodiment parameterizes, in response to determining the first quantum circuit and the previously compiled circuit are structurally equal, the previously compiled circuit with a set of parameters for the first quantum circuit.
• FIG. 1 depicts a block diagram of a network of data processing systems in which illustrative embodiments may be implemented.
• Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented.
• Data processing environment 100 includes network 102.
• Network 102 is the medium used to provide communications links between various devices and computers connected together within data processing environment 100.
• Network 102 may include connections, such as wire, wireless communication links, or fiber optic cables.
• Server 106 couples to network 102 along with storage unit 108.
• Server 106 is a conventional data processing system.
• Storage unit 108 includes database 109.
• Database 109 stores a set of previously compiled quantum circuit representations for executing quantum computing processes thereon.
• Quantum processing system 140 couples to network 102.
• Quantum processing system 140 is a quantum data processing system.
• Software applications may execute on any quantum data processing system in data processing environment 100. Any software application described as executing in quantum processing system 140 in Figure 1 can be configured to execute in another quantum data processing system in a similar manner.
• quantum processing system 140 in Figure 1 Any data or information stored or produced in quantum processing system 140 in Figure 1 can be configured to be stored or produced in another quantum data processing system in a similar manner.
• a quantum data processing system such as quantum processing system 140, may contain data and may have software applications or software tools executing quantum computing processes thereon.
• Figure 1 depicts certain components that are usable in an example implementation of an embodiment.
• server 106, and clients 110, 112, 114 are depicted as servers and clients only as example and not to imply a limitation to a client-server architecture.
• an embodiment can be distributed across several conventional data processing systems, quantum data processing systems, and a data network as shown, whereas another embodiment can be implemented on a single conventional data processing system or single quantum data processing system within the scope of the illustrative embodiments.
• Conventional data processing systems 106, 110, 112, and 114 also represent example nodes in a cluster, partitions, and other configurations suitable for implementing an embodiment.
• Device 132 is an example of a conventional computing device described herein.
• device 132 can take the form of a smartphone, a tablet computer, a laptop computer, client 110 in a stationary or a portable form, a wearable computing device, or any other suitable device.
• Any software application described as executing in another conventional data processing system in Figure 1 can be configured to execute in device 132 in a similar manner.
• Any data or information stored or produced in another conventional data processing system in Figure 1 can be configured to be stored or produced in device 132 in a similar manner.
• Server 106, storage unit 108, quantum processing system 140, and clients 110, 112, and 114, and device 132 may couple to network 102 using wired connections, wireless communication protocols, or other suitable data connectivity.
• Clients 110, 112, and 114 may be, for example, personal computers or network computers.
• server 106 may provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114.
• Clients 110, 112, and 114 may be clients to server 106 in this example.
• Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications.
• Data processing environment 100 may include additional servers, clients, and other devices that are not shown.
• memory 144 may provide data, such as boot files, operating system images, and applications to quantum processor 142.
• Quantum processor 142 may include its own data, boot files, operating system images, and applications.
• Data processing environment 100 may include additional memories, quantum processors, and other devices that are not shown.
• Memory 144 includes application 105 that may be configured to implement one or more of the functions described herein for converging a variational algorithm solution space for quantum computing in accordance with one or more embodiments.
• data processing environment 100 may be the Internet.
• Network 102 may represent a collection of networks and gateways that use the Transmission Control Protocol/Internet Protocol (TCP/IP) and other protocols to communicate with one another.
• TCP/IP Transmission Control Protocol/Internet Protocol
• At the heart of the Internet is a backbone of data communication links between major nodes or host computers, including thousands of commercial, governmental, educational, and other computer systems that route data and messages.
• data processing environment 100 also may be implemented as a number of different types of networks, such as for example, an intranet, a local area network (LAN), or a wide area network (WAN).
• Figure 1 is intended as an example, and not as an architectural limitation for the different illustrative embodiments.
• data processing environment 100 may be used for implementing a client-server environment in which the illustrative embodiments may be implemented.
• a client-server environment enables software applications and data to be distributed across a network such that an application functions by using the interactivity between a conventional client data processing system and a conventional server data processing system.
• Data processing environment 100 may also employ a service oriented architecture where interoperable software components distributed across a network may be packaged together as coherent business applications.
• Data processing environment 100 may also take the form of a cloud, and employ a cloud computing model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g. networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service.
• configurable computing resources e.g. networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services
• Data processing system 200 is an example of a conventional computer, such as servers 104 and 106, or clients 110, 112, and 114 in Figure 1 , or another type of device in which computer usable program code or instructions implementing the processes may be located for the illustrative embodiments.
• Data processing system 200 is also representative of a conventional data processing system or a configuration therein, such as conventional data processing system 132 in Figure 1 in which computer usable program code or instructions implementing the processes of the illustrative embodiments may be located.
• Data processing system 200 is described as a computer only as an example, without being limited thereto.
• Implementations in the form of other devices may modify data processing system 200, such as by adding a touch interface, and even eliminate certain depicted components from data processing system 200 without departing from the general description of the operations and functions of data processing system 200 described herein.
• data processing system 200 employs a hub architecture including North Bridge and memory controller hub (NB/MCH) 202 and South Bridge and input/output (I/O) controller hub (SB/ICH) 204.
• N/MCH North Bridge and memory controller hub
• SB/ICH South Bridge and input/output controller hub
• Processing unit 206, main memory 208, and graphics processor 210 are coupled to North Bridge and memory controller hub (NB/MCH) 202.
• Processing unit 206 may contain one or more processors and may be implemented using one or more heterogeneous processor systems.
• Processing unit 206 may be a multi-core processor.
• Graphics processor 210 may be coupled to NB/MCH 202 through an accelerated graphics port (AGP) in certain implementations.
• AGP accelerated graphics port
• data processing system 200 may be a personal digital assistant (PDA), which is generally configured with flash memory to provide non-volatile memory for storing operating system files and/or user-generated data.
• PDA personal digital assistant
• a bus system may comprise one or more buses, such as a system bus, an I/O bus, and a PCI bus. Of course, the bus system may be implemented using any type of communications fabric or architecture that provides for a transfer of data between different components or devices attached to the fabric or architecture.
• a communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter.
• a memory may be, for example, main memory 208 or a cache, such as the cache found in North Bridge and memory controller hub 202.
• a processing unit may include one or more processors or CPUs.
• data processing system 200 also may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile or wearable device.
• a computer or data processing system is described as a virtual machine, a virtual device, or a virtual component
• the virtual machine, virtual device, or the virtual component operates in the manner of data processing system 200 using virtualized manifestation of some or all components depicted in data processing system 200.
• processing unit 206 is manifested as a virtualized instance of all or some number of hardware processing units 206 available in a host data processing system
• main memory 208 is manifested as a virtualized instance of all or some portion of main memory 208 that may be available in the host data processing system
• disk 226 is manifested as a virtualized instance of all or some portion of disk 226 that may be available in the host data processing system.
• the host data processing system in such cases is represented by data processing system 200
• Component 304 generates a second index for a compiled quantum circuit stored in database 312.
• Quantum circuit analysis component 408 generates an index for quantum circuits of the quantum algorithm. In an embodiment, component 408 generates an index for a subset of a set 416 of previously compiled quantum circuits.
• connection can include an indirect “connection” and a direct “connection.”

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