WO2020125953A1

WO2020125953A1 - Linear wide-range variable gain amplifier for broadband applications

Info

Publication number: WO2020125953A1
Application number: PCT/EP2018/085586
Authority: WO
Inventors: Paolo Rossi; Luca Romano
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-12-18
Filing date: 2018-12-18
Publication date: 2020-06-25
Also published as: CN113196655A

Abstract

A variable gain amplifier (1) serves the purpose of amplifying an input signal (13) with a variable gain. The variable gain amplifier (1) comprises a first variable gain amplification stage (11) and a second variable gain amplification state (10). The first variable gain amplification stage (11) is adapted to amplify the input signal (13) within a first gain range of the variable gain. The second variable gain amplification stage (10) is adapted to amplify the input signal (13) within a second gain range of the variable gain. The first gain range extends from a minimum gain of the variable gain amplifier (1) to a boundary gain. The second gain range extends from the boundary gain to a maximum gain of the variable gain amplifier (1).

Description

LINEAR WIDE-RANGE VARIABLE GAIN AMPLIFIER FOR BROADBAND

APPLICATIONS

The invention relates to amplifiers, especially high frequency amplifiers with high efficiency.

For a great number of applications, variable gain amplifiers are used. Variable Gain

Amplifiers (VGAs) are amplifiers with adjustable gain, in which the gain can be adjusted through a control voltage or current. VGAs are widely used whenever a signal amplification chain needs some gain control mechanism.

The most common application of a VGA is an amplification chain where an Automatic Gain Control (AGC) feedback loop is used. A typical AGC feedback loop is composed of:

• Several amplification stages, where one of more of them are VGAs, i.e. they feature a gain control;

• A Peak Detector, i.e. a circuit that senses the signal’s amplitude at the output of the amplification chain;

• An error amplifier that amplifies the difference between the power detector output and a target value.

The AGC feedback loop regulates the VGA(s) gain such that the output signal amplitude is constant, regardless to the input signal amplitude, temperature, process variations, supply voltage, etc...

The most significant performance parameters (typically in trade-off) of a VGA for linear broadband applications are:

• Gain range (ratio between MAX gain and MIN gain);

• Linearity (or equivalently distortion, often measured as Total Harmonic Distortion - THD);

• Bandwidth.

Common to all VGAs, THD performance generally varies across the gain range in a way dependent on the implementation. A general issue encountered in VGAs is that the maximum THD across the gain range generally worsens as the gain range is extended , i.e. a wider-range VGA will generally have a poorer linearity performance.

In summary, many VGA topologies suffer from a severe gain range/linearity trade-off, and achieving both can be very demanding in terms of power consumption. Moreover many known solutions have only a small number of fixed programmable gain steps, or are limited to implementations where a very small input signal amplitude can be tolerated with good linearity.

Accordingly, the object of the invention is to provide a variable gain amplifier, which provides a very wide gain range and at the same time achieves a high linearity.

The object is solved by the features of claim 1 for the device. Dependent claims contain further developments.

A variable gain amplifier according to the present invention serves the purpose of amplifying an input signal with a variable gain. The variable gain amplifier comprises a first variable gain amplification stage and a second variable gain amplification stage. The first variable gain amplification stage is adapted to amplify the input signal within a first gain range of the variable gain. The second variable gain amplification stage is adapted to amplify the input signal within a second gain range of the variable gain. The first gain range extends from a minimum gain of the variable gain amplifier to a boundary gain. The second gain range extends from the boundary gain to a maximum gain of the variable gain amplifier. It is thereby possible to achieve a very broad gain range and a high linearity.

Advantageously, the first variable gain amplification stage may be a multiplier-like variable gain amplifier. The second variable gain amplification stage is a dual- stage variable gain amplifier. This allows for an especially high linearity throughout both amplification stages.

Further advantageously, the multiplier-like variable gain amplifier may be adapted to progressively steer an amplified signal away from a load, thereby reducing the gain of the multiplier-like variable gain amplifier. This allows for a seamless transition through the gain range.

The dual- stage variable gain amplifier may comprise a first amplification stage and a second amplification stage, both adapted to amplify the input signal. The first amplification stage comprises a greater gain and a lower linearity than the second amplification stage. The dual stage variable gain amplifier moreover comprises an adder, adapted to add an output of the first amplification stage and an output stage of the second amplification stage. This allows for an especially efficient amplification.

The adder may be adapted to add the output signal of the first amplification stage with variable weights depending upon the variable gain. This allows for a very simple seamless transition between the different amplification stages.

The first variable gain amplification stage and the second variable gain amplification stage may be based on bipolar transistor technology or field-effect transistor technology. This allows for a very simple implementation.

Advantageously, the first variable gain amplification stage and the second variable gain amplification stage may be based on differential bipolar transistor technology or differential field-effect transistor technology. This allows for a very simple amplification of differential signals.

Advantageously, the boundary gain may be pre-set to a value maximizing an average linearity performance of the variable gain amplifier over a total variable gain range of the variable gain amplifier. This achieves an especially beneficial performance of the variable gain amplifier.

Further advantageously, the first variable gain amplification stage may be adapted to amplify the input signal within the first gain range based upon a first control signal. The second variable gain amplification stage is adapted to amplify the input signal within the second gain range based upon a second control signal. The first control signal and the second control signal are based upon the variable gain. The first control signal is different from the second control signal. This allows for an especially effective control of the amplification. Advantageously, the variable gain amplifier may comprise a control signal generator, adapted to generate the first control signal and the second control signal based upon the variable gain. This allows for an especially efficient control of the amplification.

Further advantageously, the control signal generator may be based on bipolar transistor technology or field-effect transistor technology. This further simplifies the implementation.

An exemplary embodiment of the invention is now further explained with respect to the drawings, in which

FIG. 1 shows a first embodiment of the variable gain amplifier in a block diagram;

FIG. 2 shows performance diagrams of exemplary variable gain amplifiers and a performance diagram of a second embodiment of the inventive variable gain amplifier;

FIG. 3 shows a third embodiment of the inventive variable gain amplifier in a circuit diagram;

FIG. 4 shows control signals within a third exemplary embodiment of the inventive variable gain amplifier;

FIG. 5 shows a performance diagram of a fourth embodiment of the inventive variable gain amplifier;

FIG. 6 shows the operation of a fifth embodiment of the inventive variable gain amplifier in a first operating point;

FIG. 7 shows the fifth embodiment of the inventive variable gain amplifier in a second operating point, and

FIG. 8 shows the operation of the fifth embodiment of the variable gain amplifier in a third operating point. First, we demonstrate the general construction and function of an embodiment of the variable gain amplifier along FIG. 1 and FIG. 2. With regard to FIG. 3 - FIG. 8, further details of different embodiments and of the operation are explained. Similar entities and reference numbers in different figures have been partially omitted.

The general approach of the presented invention is to combine two different gain variation approaches to extend the VGA gain range for a given THD or equivalently improve the THD for a given gain range.

In FIG. 1, a first embodiment of the inventive variable gain amplifier 1 is shown. The variable gain amplifier 1 comprises a first variable gain amplification stage 11 and a second variable gain amplification stage 10. Both of these variable gain amplification stages 10, 11 are supplied with an input signal 13. Output signals of the variable gain amplification stages 10, 11 are added by an adder 12 to an output signal 14.

The first variable gain amplification stage 11 is optimized for low gain amplification. The second variable gain amplification stage 10 is optimized for high gain amplification. Both of the variable gain amplification stages 10, 11 are supplied with control signals 15, 16 by a control signal generator 17. The control signal generator 17 generates the control signals 15, 16 independently, so that the two variable gain amplification stages 10, 11 are supplied with separate and different control signals 15, 16. Especially, the control signals 15, 16 control which of the variable gain amplification stages 10, 11 performs the amplification of the input signal 13. Moreover, the control signal generator 17 is connected to an additional input 18, through which an external gain control signal is input.

Especially, the first variable gain amplification stage 11 can be implemented as a multiplier like variable gain amplifier. Also, the second variable gain amplification stage can be implemented as a dual- stage variable gain amplifier.

In case of the first amplification stage being implemented as a multiplier-like variable gain amplifier, the multiplier-like variable gain amplifier is adapted to progressively steer an amplified signal away from a load, thereby reducing the gain of the multiplier-like variable gain amplifier. In case of the second variable gain amplification stage being implemented as a dual- stage variable gain amplifier, it comprises a first amplification stage and a second amplification stage, both adapted to amplify the input signal. The first amplification stage comprises a greater gain and a lower linearity than the second amplification stage. The dual-stage variable gain amplifier then additionally comprises and adder, which is adapted to add output signals of the first and second amplification stages of the dual-stage variable gain amplifier. Especially, this adder can add the signals with variable weights.

In FIG. 2, the performance of an exemplary multiplier-like variable gain amplifier and the performance of an exemplary dual-stage variable gain amplifier are shown. Moreover, a resulting performance of an embodiment of the inventive variable gain amplifier is shown in the lower part of the figure. It can readily be seen from FIG. 2 that the total VGA gain range is split into two regions 20, 21.

Starting from Gmax, the VGA gain is reduced using a dual- stage technique in Region 21. A dual- stage technique consists on mixing with variable weights the outputs of two different gain stages, one with high gain and one with low gain but better linearity. This gain variation technique typically leads to a bell-shaped THD variation vs gain.

Then, after the high-gain stage is completely OFF, the gain of the low-gain stage is further reduced using a multiplier-like technique in Region 20. A multiplier- like gain reduction technique consists on progressively steering the RF signal generated by the gain stage away from the load, thus reducing the amplifier’s gain. This gain variation technique typically leads to a sharply increasing THD as the gain is reduced from MAX.

The boundary between the two regions is optimized in such a way that a minimum THDmax is achieved - namely, when THDmax has the same value in both regions.

A possible embodiment in bipolar technologies, suitable for broadband applications, is depicted in Fig. 3. A first variable gain amplification stage 11 comprises a low-gain input differential stage - formed by transistors Q2p-Q2n - that converts an input differential voltage signal Vin_p-Vin_n, which corresponds to the input signal 13 of Fig. 1, into a differential current. This differential stage can use some resistive degeneration Re_lg to improve its linearity performance. This low-gain stage has lower transconductance but higher linearity than a high-gain stage (being in general Re_lg>Re_hg), described in the following.

A second variable gain amplification stage 10 comprises a high-gain input differential stage - formed by transistors Qlp-Qln - that converts the input differential voltage signal Vin_p- Vin_n into a differential current. This differential stage can use some resistive degeneration Re_hg to improve its linearity performance.

The variable gain amplification stages 10, 11 share a gain variation network, composed of the transistors Q3p/n and Q4p/n, used to mix the differential currents generated by the high- gain and low-gain stages into the resistive loads. The bases of the transistors Q3p/n and Q4p/n are connected to two separate differential gain control signals Vgcp_hg-Vgcn_hg and Vgcp_lg-Vgcn_lg. These control signals correspond to the control signal 15, 16 of Fig. 1. The connection of the outputs of the gain variation network correspond to the adder 12 of Fig. 1.

Load resistors RL convert the differential current to a differential output voltage (Vout_p- Vout_n), performing the input signal amplification. Dump resistors Rdump are present, where the“unused” differential currents are steered by transistors Q3p/n and Q4p/n. The resulting differential output signal Vout_p-Vout_n corresponds to the output signal 14 of Fig. 1.

The controls of the low-gain and high-gain stages are split, and two separate differential gain control signals Vgcp_hg-Vgcn_hg and Vgcp_lg-Vgcn_lg are used for the high-gain and low- gain stages, respectively. With respect to a VGA using only a dual-stage gain variation technique, the current consumption and the number of transistors connected to the output nodes are the same, thus achieving potentially the same bandwidth.

The expected shape of the gain control signals and the expected THD performance as a function of the VGA gain are sketched in Fig. 4. In Fig. 5, especially the performance in the two different gain regions can be seen. In FIG. 6, the situation when configured for maximum gain is shown. When configured to MAX gain, the high-gain stage differential gain control signal Vgcp_hg-Vgcn_hg must be positive and large and the low-gain stage differential gain control signal Vgcp_lg-Vgcn_lg must be negative and large. In this condition, transistors Q3p are ON, while transistors Q3n are OFF. The differential current generated by the high-gain stage Qlp/n is entirely steered into the load resistors RL, contributing to the output signal. On the other side, transistors Q4p are OFF, while transistors Q4n are ON, so that the differential current generated by the low-gain stage 11 is entirely steered to the dump resistors Rdump, contributing to no output signal.

In this condition, the VGA gain is maximum, and its linearity is completely determined by the high-gain stage 10.

In FIG. 7, the situation at the gain boundary is shown. Starting from the MAX gain condition, the two differential control signals are then moved to opposite directions, i.e. Vgcp_hg-Vgcn_hg moves from positive to negative, while Vgcp_lg-Vgcn_lg moves from negative to positive. As a consequence, the differential current of the high-gain stage 10 is progressively steered to the dump resistors, while the differential current of the low-gain stage 11 is progressively routed to the load resistors. This determines a reduction of the VGA gain. During the transition, the THD will follow a bell-like shape, reaching a maximum THD at some point. At the boundary between Region 20 and Region 21, the high-gain stage differential control signal is negative and large, while the low-gain stage differential control signal is positive and large. In this condition, only the differential current of the low-gain stage 11 is routed to the load resistors RL and contributes to the output signal. The linearity is completely determined by the low-gain stage.

Finally, in FIG. 8, the situation for minimal gain is depicted. Starting from the boundary between Region 1 and Region 2, the high-gain stage differential control signal is kept constant, i.e. negative and large, while the low-gain stage differential control signal is progressively reduced. The differential current generated by the high-gain stage 10 remains completely steered to the dump resistors, not contributing to the output signal. On the other hand, transistors Q4p progressively turn OFF, while transistors Q4n progressively turn ON. As a consequence, part of the differential current generated by the low-gain stage 11 is steered to the dump resistors, and the VGA gain is further reduced using the multiplier- like technique. While gain reduces, THD increases.

The VGA minimum gain depends on where the low-gain stage differential control signal Vgcp_lg-Vgcn_lg is stopped at the end of Region 20, and this is a design parameter that depends on the required VGA gain range.

In both regions, THD reaches a maximum value, somewhere within Region 21 and at the bottom end of Region 20. As already pointed out, the overall THD performance is optimized when the two maxima have the same value. This can be easily done by adjusting the transition point between Region 21 and Region 20, i.e. by deciding how much of the overall gain range R is performed using a the dual- stage gain reduction and how much is left to the multiplier-like gain reduction. The decision can be made with the help of a simple optimization done either during the design phase or during measurements.

The invention is not limited to the examples and especially not to a specific amplifier technology. The characteristics of the exemplary embodiments can be used in any advantageous combination.

Claims

1. Variable gain amplifier (1), for amplifying an input signal (13) with a variable gain, comprising:

- a first variable gain amplification stage (11), adapted to amplify the input signal (13) within a first gain range of the variable gain, and

- a second variable gain amplification stage (10), adapted to amplify the input signal (13) within a second gain range of the variable gain,

wherein the first gain range extends from a minimum gain of the Variable gain amplifier (1) to a boundary gain, and

wherein the second gain range extends from the boundary gain to a maximum gain of the Variable gain amplifier (1).

2. Variable gain amplifier (1) according to claim 1,

wherein the first variable gain amplification stage (11) is a multiplier- like variable gain amplifier, and

wherein the second variable gain amplification stage (10) is a dual- stage variable gain amplifier.

3. Variable gain amplifier (1) according to claim 2,

wherein the multiplier-like variable gain amplifier is adapted to progressively steer an amplified signal away from a load, thereby reducing the gain of the multiplier-like variable gain amplifier.

4. Variable gain amplifier (1) according to claim 2 or 3,

wherein the dual- stage variable gain amplifier comprises a first amplification stage and a second amplification stage, both adapted to amplify the input signal (13),

wherein the first amplification stage comprises a greater gain and a lower linearity than the second amplification stage, and

wherein the dual- stage variable gain amplifier comprises an adder, adapted to add an output signal of the first amplification stage and an output signal of the second amplification stage.

5. Variable gain amplifier (1) according to claim 4,

wherein the adder is adapted to add the output signal of the first amplification stage and the output signal of the second amplification stage with variable weights, depending upon the variable gain.

6. Variable gain amplifier (1) according to any of the claims 1 to 5,

wherein the first variable gain amplification stage (11) and the second variable gain amplification stage (10) are based on bipolar transistor technology or field effect transistor technology.

7. Variable gain amplifier (1) according to any of the claims 1 to 5,

wherein the first variable gain amplification stage (11) and the second variable gain amplification stage (10) are based on differential bipolar transistor technology or differential field effect transistor technology.

8. Variable gain amplifier (1) according to any of the claims 1 to 7,

wherein the boundary gain is pre-set to a value maximizing an average linearity performance of the Variable gain amplifier (1) over a total variable gain range of the Variable gain amplifier (1).

9. Variable gain amplifier (1) according to any of the claims 1 to 8,

wherein the first variable gain amplification stage (11) is adapted to amplify the input signal (13) within the first gain range based upon a first control signal (16, Vgcn_hg, Vgcp_hg), wherein the second variable gain amplification stage (10) is adapted to amplify the input signal (13) within the second gain range based upon a second control signal (15, Vgcn_lg, Vgcpjg),

wherein the first control signal (16, Vgcn_hg, Vgcp_hg) and the second control signal (15, Vgcn_lg, Vgcpjg) are based upon the variable gain, and

wherein the first control signal (16, Vgcn_hg, Vgcp_hg) is different from the second control signal (15, Vgcnjg, Vgcpjg).

10. Variable gain amplifier (1) according to claim 9, wherein the Variable gain amplifier (1) comprises a control signal generator (17), adapted to generate the first control signal (16, Vgcn_hg, Vgcp_hg) and the second control signal (15, Vgcn_lg, Vgcp_lg) based upon the variable gain.

11. Variable gain amplifier (1) according to claim 9 or 10,

wherein the control signal generator (17) is based on bipolar transistor technology or field effect transistor technology.