WO2020124711A1 - 数据的传输方法、装置及计算机可读存储介质 - Google Patents

数据的传输方法、装置及计算机可读存储介质 Download PDF

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Publication number
WO2020124711A1
WO2020124711A1 PCT/CN2019/071376 CN2019071376W WO2020124711A1 WO 2020124711 A1 WO2020124711 A1 WO 2020124711A1 CN 2019071376 W CN2019071376 W CN 2019071376W WO 2020124711 A1 WO2020124711 A1 WO 2020124711A1
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Prior art keywords
data
signal
data transmission
data signal
potential
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English (en)
French (fr)
Inventor
王明良
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HKC Co Ltd
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HKC Co Ltd
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Priority to US17/037,787 priority Critical patent/US11088817B2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
    • H04L25/065—Binary decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Definitions

  • the present application relates to the field of communication technology, and in particular, to a data transmission method, device, and computer-readable storage medium.
  • differential signals With the increasing size and resolution of LCD TVs, and the need to transmit more and more data, differential signals have become popular as a high-speed transmission protocol.
  • the data signal In the process of data transmission with differential signals, the data signal is accompanied by a clock signal, and the data signal is relatively stable when the clock signal rises or falls. At this time, the receiving end obtains the target data in the data signal.
  • the main purpose of the present application is to provide a data transmission method, device and computer readable storage medium, aiming to solve that in the differential signal transmission process, both the data signal and the clock signal will be affected by reflection, and the influence of both Correlation, therefore, when acquiring data in the data signal according to the clock signal at this time, it is easy to cause technical problems of data acquisition errors.
  • the data transmission method includes the following steps:
  • the detection potential at each sampling point in the data signal within a time interval is obtained, wherein the time interval is half of the data period of the data signal;
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • the step of determining the logic level of the data signal within the time interval according to each detection potential includes:
  • the logic level of the data signal in the time interval is low.
  • the method before the step of acquiring the detection potential at each sampling point in the data signal within the time interval, the method further includes:
  • the data period is determined according to the clock period of the clock signal.
  • the step of determining the data period according to the clock period of the clock signal includes:
  • clock period of the clock signal be the data period.
  • the method further includes:
  • the detection potential at each detection time point in the data signal in the data period is obtained using the current time point as the starting time point.
  • the data driver for data transmission has a delay element, and the preset time interval is obtained through the delay element.
  • the device involved in the data transmission method has a potential detection element, and the step of real-time monitoring the zero-volt time point at which the potential of the clock signal is zero volts includes:
  • the time point at which the potential detected by the potential detection element is zero volts is the zero volt time point of the clock signal.
  • the method before the step of determining the data period according to the clock period of the clock signal, the method further includes:
  • the step of acquiring the clock period of the clock signal includes:
  • the zero-volt time point of the clock signal is obtained, and the clock period of the clock signal is obtained according to the time interval between two adjacent zero-volt time points.
  • the method further includes:
  • the data transmission method further includes:
  • the step of acquiring the detection potential at each sampling point in the data signal during the time interval includes:
  • the detection potential corresponding to each sampling point detected by the potential judgment element is acquired.
  • the preset amplitude is greater than or equal to 0.5 volts.
  • the present application also provides a data transmission device, wherein the data transmission device includes: a memory, a processor, and data stored on the memory and operable on the processor When the data transmission program is executed by the processor, the following steps of the data transmission method are implemented:
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • the present application also provides a computer-readable storage medium, wherein a data transmission program is stored on the computer-readable storage medium, and the data transmission program is implemented as follows when executed by a processor The steps of the mentioned data transmission method:
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • a data transmission method, device, and computer-readable storage medium proposed in the embodiments of the present application detect the detection potential of each data point at each sampling point in a half data period of a data signal when transmission of a data signal is detected.
  • the potential is used to obtain the logic level of the data signal within the half data period, and then, the data signal generation circuit regenerates a standard data signal according to the acquired logic level and a preset standard amplitude.
  • the regenerated standard data signal can meet the processing requirements of the internal processing circuit in the data driver for the data signal, and can effectively capture the data to avoid data acquisition errors.
  • FIG. 1 is a schematic diagram of a terminal structure of a hardware operating environment involved in an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of a data transmission method of this application.
  • FIG. 3 is a schematic waveform diagram of the data transmission method of this application.
  • FIG. 4 is another waveform diagram of the data transmission method of this application.
  • FIG. 5 is a schematic flowchart of another embodiment of a data transmission method of this application.
  • FIG. 6 is a schematic flowchart of still another embodiment of a data transmission method of this application.
  • FIG. 7 is a schematic flowchart of still another embodiment of a data transmission method according to this application.
  • FIG. 1 is a schematic diagram of a terminal structure of a hardware operating environment involved in a solution of an embodiment of the present application.
  • the terminal may be a data extraction device for data signals, or may be a television, a computer, or the like.
  • the terminal may include: a processor 1001, such as a central processing unit (Central Processing Unit) / Processor, referred to as CPU, memory 1002, communication bus 1003, data driver (Data Driver) 1004.
  • the communication bus 1003 is configured to implement connection communication between the components in the terminal.
  • the memory 1002 may be a high-speed random access memory or a stable memory (non-volatile memory), such as disk storage.
  • the memory 1002 may optionally be a storage device independent of the foregoing processor 1001.
  • the data driver 1004 performs data signal processing, and may include at least one of a frequency judgment circuit, a potential judgment circuit, a delay circuit, a data signal generation circuit, and an internal processing circuit.
  • FIG. 1 does not constitute a limitation on the terminal in the embodiments of the present application, and may include more or fewer components than those illustrated, or a combination of certain components, or different components. Layout.
  • the memory 1002 as a computer storage medium may include a data transmission program.
  • the processor 1001 can call the data transmission program stored in the memory 1002 and perform the following operations:
  • the detection potential at each sampling point in the data signal within a time interval is obtained, wherein the time interval is half of the data period of the data signal;
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the logic level of the data signal in the time interval is low.
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the data period is determined according to the clock period of the clock signal.
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the detection potential at each detection time point in the data signal in the data period is obtained using the current time point as the starting time point.
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the zero-volt time point of the clock signal is obtained, and the clock period of the clock signal is obtained according to the time interval between two adjacent zero-volt time points.
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the processor 1001 may call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the data transmission method includes:
  • Step S10 When a data signal is detected, the detection potential at each sampling point in the data signal within a time interval is obtained, where the time interval is half of the data period of the data signal.
  • Step S20 Determine the logic level of the data signal within the time interval according to each detection potential.
  • Step S30 and regenerating the data signal according to the logic level and the preset amplitude.
  • the upper part of the figure is the waveform of the data signal, and the lower part is the waveform generated by the clock signal.
  • Both the data signal and the clock signal will be affected by reflection, and the shapes of the data signal and the clock signal will change. However, the effects of the two are not related. Therefore, the amplitudes and positions of the waveforms of the data signal and the clock signal are not consistent.
  • the amplitude of the differential signal is insufficient at the time point in the data signal corresponding to the rising and/or falling edges of the clock signal, resulting in data recognition errors.
  • it causes abnormal display.
  • the present application provides a data transmission method.
  • Data driver Driver adds a potential judgment circuit, through which the detection potential corresponding to each sampling point can be obtained.
  • the data signal generating circuit outputs the standard data signal according to the acquired logic level and the preset amplitude value (the preset amplitude value is the output of the standard data signal Amplitude, the specific value is obtained by experiment, usually can be taken above 0.5V) to regenerate the standard data signal.
  • the regenerated standard data signal can meet the processing requirements of the internal processing circuit in the data driver for the data signal, and can effectively capture the data to avoid data acquisition errors.
  • the number of high potentials greater than the preset potential and the number of low potentials less than or equal to the preset potential in the detection potential are acquired, and further, when the number of high potentials is greater than the number of low potentials, It indicates that the logic level of the data signal is high during the detected half cycle; when the number of high potentials is smaller than the number of low potentials, it indicates that the logic level of the data signal is low during the detected half cycle level.
  • the preset potential is the critical value for signal judgment, usually 0-0.3V.
  • the detection potentials of the three sampling points A, B, and C in the half data period t2 are detected, the preset potential is 0.3V, the detection result is that the potentials of points A and C are greater than 0.3V, and the potential of point B is less 0.3V. Then, it is judged that the data signal above the 0V line is high level in t2 time. Similarly, the data signal below the 0V line is low level. Therefore, the data waveform as drawn by the solid line in FIG. 4 is regenerated according to the determined logic level and the preset amplitude (the broken line is the waveform diagram of the initial data signal). The regenerated data signal can meet the data processing requirements of the internal processing circuit in the data driver and avoid data acquisition errors.
  • the data signal generating circuit regenerates the standard data signal according to the acquired logic level and the preset standard amplitude.
  • the regenerated standard data signal can meet the processing requirements of the internal processing circuit in the data driver for the data signal, and can effectively capture the data to avoid data acquisition errors.
  • step S10 further includes:
  • Step S40 When a data signal is detected, obtain a clock signal corresponding to the data signal.
  • Step S50 Determine the data period according to the clock period of the clock signal.
  • a clock signal corresponding to the data signal is obtained, and a clock cycle is obtained from the clock signal. Since the clock signal is generated corresponding to the data signal, the clock cycle of the clock signal is equal to the data cycle of the data signal.
  • Data Driver In the data drive (Data Driver) is provided with a frequency judgment circuit, through which the frequency of the clock signal can be obtained. Since the period and the frequency are reciprocal to each other, the clock cycle of the clock signal can be obtained according to the obtained frequency.
  • the potential judgment circuit set in the Driver can obtain the zero-volt time point with a potential of 0V in the clock signal.
  • the time interval between two adjacent zero-volt time points in the clock signal is half a clock cycle. Therefore, according to the two The clock cycles are obtained at two adjacent zero volt time points.
  • the clock cycle of the clock signal can also be obtained in other ways, which will not be repeated here.
  • a clock signal corresponding to the data signal is acquired, and a clock period of the clock signal is acquired, so that the detection potential of each sampling point in the detected data signal is determined according to the clock period.
  • the determination of the interval provides a basis for subsequent judgment of the logic level of the data signal and regeneration of the data signal.
  • step S50 further includes:
  • step S60 a zero-volt time point at which the potential of the clock signal is zero volts is monitored in real time.
  • Step S70 When the zero-volt time point is delayed by a preset time interval, the detection potential at each sampling point in the data signal within the time interval is obtained using the current time point as a starting time point.
  • the potential detection circuit can detect the zero-volt time point of the clock signal at zero volts, and after the zero-volt time point of the clock signal is delayed by a preset time interval, the detection at each sampling point in the data signal within the time interval begins to be collected Potential.
  • a delay circuit is added to the data driver.
  • the time interval of judging the logic level is not the complete half of the data cycle of the data signal, and eventually leads to the regeneration of the wrong data signal, and the data transmission is disordered.
  • a potential detection circuit can be used to detect that the clock signal is at a zero volt time point of zero volts, and after the zero volt time point of the clock signal is delayed by a preset time interval, the data signal within the time interval starts to be collected The detection potential at each sampling point.
  • the time interval of judging the logic level is not the complete half of the data cycle of the data signal, and eventually leads to the regeneration of the wrong data signal, and the data transmission is disordered.
  • step S30 further includes:
  • Step S80 Acquire the data of the regenerated data signal according to the clock signal.
  • the data signal is generated by the data signal generation circuit in the data driver, the period and frequency of the data signal are not changed, so the valid data in the regenerated data signal can still be effectively captured according to the clock signal. Moreover, the regenerated data signal can be effectively processed by the internal processing circuit, which improves the accuracy of data capture.
  • the rising edge and/or the falling edge of the clock signal is acquired, the time point corresponding to the rising edge or the falling edge in the regenerated data signal is determined, and at the determined time Grab the data in the data signal at the point.
  • the rising edge and/or the falling edge of the clock signal is acquired, and the time point corresponding to the rising edge or the falling edge in the regenerated data signal is determined , And grab the data in the data signal at the determined time point.
  • Using the regenerated data signal can be effectively processed by internal processing elements to improve the accuracy of data capture.
  • An embodiment of the present application also provides a data transmission device, wherein the data transmission device includes: a memory, a processor, and a data transmission program stored on the memory and executable on the processor.
  • the data transmission program is executed by the processor, the following steps of the data transmission method are implemented:
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • embodiments of the present application also provide a computer-readable storage medium that stores a data transmission program on the computer-readable storage medium.
  • data transmission program When executed by a processor, data transmission as described below is implemented Method steps:
  • the data signal is regenerated according to the logic level and the preset amplitude.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware, but in many cases the former is better Implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM/RAM) as described above , Disk, CD), including several instructions to make a terminal device (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.

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Abstract

本申请公开一种数据的传输方法、装置及计算机可读存储介质，由数据信号中各个采样点处的检测电位确定数据信号的逻辑电平；根据逻辑电平和预设幅值重新生成所述数据信号。

Description

数据的传输方法、装置及计算机可读存储介质
相关申请
本申请要求2018年12月19日申请的，申请号为2010811559901.9，名称为“数据的传输方法、装置及计算机可读存储介质”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及通信技术领域，尤其涉及数据的传输方法、装置及计算机可读存储介质。
背景技术
随着液晶电视尺寸越来越大，解析度越来越高，需要传输的数据也日益增多，差分信号作为一种高速的传输协议得到普及。在以差分信号进行数据传输过程中，数据信号伴随着时钟信号，并在时钟信号上升沿或下降沿时数据信号相对稳定，此时，接收端获取到数据信号中的目标数据。
然而，在实际情况中，由于传输走线特征阻抗的不一致性，信号在传输的过程中会遇到反射现象，反射回来的信号再与初始信号进行叠加，导致实际的信号波形凹凸不平。在差分信号传输过程中，数据信号和时钟信号均会受到反射影响，且两者的影响并无关联，所以，此时根据时钟信号获取数据信号中的数据时，容易导致数据获取错误。
申请内容
本申请的主要目的在于提供一种数据的传输方法、装置及计算机可读存储介质，旨在解决在差分信号传输过程中，数据信号和时钟信号均会受到反射影响，且两者的影响并无关联，所以，此时根据时钟信号获取数据信号中的数据时，容易导致数据获取错误的技术问题。
为实现上述目的，本申请提供一种数据的传输方法，所述数据的传输方法包括以下步骤：
检测到数据信号时，获取时间间隔内所述数据信号中各个采样点处的检测电位，其中，所述时间间隔为所述数据信号的数据周期的一半；
根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
可选的，所述根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平的步骤包括：
获取所述检测电位中大于预设电位的高电位个数和小于或等于所述预设电位的低电位个数；
当所述高电位个数大于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为高电平；
当所述高电位个数小于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为低电平。
可选的，所述获取时间间隔内所述数据信号中各个采样点处的检测电位的步骤之前，还包括：
检测到数据信号时，获取所述数据信号对应的时钟信号；
根据所述时钟信号的时钟周期确定所述数据周期。
可选的，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤包括：
将所述时钟信号的时钟周期作为所述数据周期。
可选的，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤之后，还包括：
实时监测所述时钟信号的电位为零伏的零伏时间点；
在所述零伏时间点延迟预设时间间隔时，以当前时间点为起始时间点获取数据周期内所述数据信号中各个检测时间点处的检测电位。
可选的，数据传输的数据驱动器中具有延时元件，通过所述延时元件获取所述预设时间间隔。
可选的，所述数据的传输方法所涉及的装置具有电位检测元件，所述实时监测所述时钟信号的电位为零伏的零伏时间点的步骤包括：
实时检测所述电位检测元件检测到的所述时钟信号的电位；
所述电位检测元件检测到的所述电位为零伏的时间点为所述时钟信号的零伏时间点。
可选的，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤之前，还包括：
获取所述时钟信号的时钟周期。
可选的，所述获取所述时钟信号的时钟周期的步骤包括：
获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
可选的，所述根据所述逻辑电平以及预设幅值重新生成所述数据信号的步骤之后，还包括：
根据所述时钟信号获取重新生成的所述数据信号的数据。
可选的，所述数据的传输方法还包括：
获取所述时钟信号的上升沿和下降沿；
确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
以及，抓取所述数据信号中所述时间点对应的数据。
可选的，所述获取时间间隔内所述数据信号中各个采样点处的检测电位的步骤包括：
获取电位判断元件检测到的所述各个采样点对应的检测电位。
可选的，所述预设幅值大于或等于0.5伏。
此外，为实现上述目的，本申请还提供一种数据的传输装置，其中，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如下所述的数据的传输方法的步骤：
检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
此外，为实现上述目的，本申请还提供一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有数据的传输程序，所述数据的传输程序被处理器执行时实现如下所述的数据的传输方法的步骤：
检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
本申请实施例提出的一种数据的传输方法、装置及计算机可读存储介质，在检测到存在数据信号的传输时，检测数据信号在半个数据周期中各个采样点处的检测电位，根据检测电位来获取该数据信号在该半个数据周期内的逻辑电平，进而，数据信号生成电路根据获取到的逻辑电平和预设的标准幅值重新生成标准的数据信号。重新生成的标准的数据信号能够满足数据驱动器中内部处理电路对数据信号的处理要求，能够有效抓取数据，避免数据获取错误。
附图说明
图1是本申请实施例方案涉及的硬件运行环境的终端结构示意图；
图2为本申请数据的传输方法一实施例的流程示意图；
图3为本申请数据的传输方法的一波形示意图；
图4为本申请数据的传输方法的另一波形示意图；
图5为本申请数据的传输方法另一实施例的流程示意图；
图6为本申请数据的传输方法再一实施例的流程示意图；
图7为本申请数据的传输方法又一实施例的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
如图1所示，图1是本申请实施例方案涉及的硬件运行环境的终端结构示意图。
本申请实施例终端可以是一种数据信号的数据提取装置，也可以是电视机、计算机等。
如图1所示，该终端可以包括：处理器1001，例如中央处理器（Central Processing Unit / Processor ，简称CPU），存储器1002，通信总线1003，数据驱动器（Data Driver）1004。其中，通信总线1003设置为实现该终端中各组成部件之间的连接通信。存储器1002可以是高速随机存取存储器，也可以是稳定的存储器（non-volatile memory），例如磁盘存储器。存储器1002可选的还可以是独立于前述处理器1001的存储装置。数据驱动器1004进行数据信号的处理，可以是包括频率判断电路、电位判断电路、延时电路、数据信号生成电路和内部处理电路中的至少一个。
本领域技术人员可以理解，图1中示出的终端的结构并不构成对本申请实施例终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图1所示，作为一种计算机存储介质的存储器1002中可以包括传数据的传输程序。
在图1所示的服务器中，处理器1001可以调用存储器1002中存储的数据的传输程序，并执行以下操作：
检测到数据信号时，获取时间间隔内所述数据信号中各个采样点处的检测电位，其中，所述时间间隔为所述数据信号的数据周期的一半；
根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述检测电位中大于预设电位的高电位个数和小于或等于所述预设电位的低电位个数；
当所述高电位个数大于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为高电平；
当所述高电位个数小于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为低电平。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
检测到数据信号时，获取所述数据信号对应的时钟信号；
根据所述时钟信号的时钟周期确定所述数据周期。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
实时监测所述时钟信号的电位为零伏的零伏时间点；
在所述零伏时间点延迟预设时间间隔时，以当前时间点为起始时间点获取数据周期内所述数据信号中各个检测时间点处的检测电位。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟信号的时钟周期。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
根据所述时钟信号获取重新生成的所述数据信号的数据。
可选地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟信号的上升沿和下降沿；
确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
以及，抓取所述数据信号中所述时间点对应的数据。
参照图2，本申请数据的传输方法一实施例，所述数据的传输方法包括：
步骤S10，检测到数据信号时，获取时间间隔内所述数据信号中各个采样点处的检测电位，其中，所述时间间隔为所述数据信号的数据周期的一半。
步骤S20，根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平。
步骤S30，以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
在现今生活中，随着通信技术越来越发达，越来越多的采用信号传输的方式来实现数据的传输。以数字电视的技术领域为例，随着液晶电视尺寸越来越大，解析度越来越高，需要传输的数据也日益增多，差分信号作为数据信号中一种高速的传输协议便得到广泛普及。但在数据信号在实际传输的过程中，由于传输走线特征阻抗的不一致性，数据信号在传输的过程中会遇到反射现象，反射回来的数据信号再与初始的数据信号进行信号叠加，导致实际得到的数据信号的波形出现凹凸不平现象，如果这时再直接根据数据信号对应的时钟信号去提取该数据信号的数据，就可能会导致数据识别错误。
如图3所示，图中上方为数据信号的波形，下方为时钟信号产生的波形。数据信号以及时钟信号均会受到反射的影响，数据信号和时钟信号的形状都会发生变化，然而两者的影响没有关联，故，数据信号和时钟信号的波形的波动幅度和位置并不一致。此时，根据时钟信号抓取数据信号中的数据时，在时钟信号的上升沿和/或下降沿对应数据信号中的时间点处差分信号的幅值不足，导致数据识别错误，液晶显示屏在根据识别出的数据显示时，造成显示异常。
为避免上述差分信号中数据识别错误的问题，本申请提供一种数据的传输方法，在检测到存在数据信号的传输时，检测数据信号在半个数据周期中各个采样点处的检测电位，在数据驱动器（Data Driver）添加有电位判断电路，通过电位判断电路能够获取各个采样点对应的检测电位。根据检测电位来获取该数据信号在该半个数据周期内的逻辑电平，进而，数据信号生成电路根据获取到的逻辑电平和预设幅值（所述预设幅值为标准数据信号的输出幅值，具体数值由实验获取，通常可取0.5V以上）重新生成标准的数据信号。重新生成的标准的数据信号能够满足数据驱动器中内部处理电路对数据信号的处理要求，能够有效抓取数据，避免数据获取错误。
其中，在获取到检测电位后，获取检测电位中大于预设电位的高电位个数以及小于或等于预设电位的低电位个数，进而，当高电位个数比低电位个数大时，表明检测到的半个周期内，数据信号的逻辑电平为高电平；当高电位个数比低电位个数小时，表明检测到的半个周期内，数据信号的逻辑电平为低电平。预设电位为信号判断的临界值，通常可取0-0.3V。
例如，图3中检测半个数据周期t2内采样点A、B、C三点的检测电位，预设电位为0.3V，检测结果为A点和C点的电位大于0.3V，B点电位小于0.3V。则，判断t2时间内0V线上方的数据信号为高电平，同理，0V线下方的数据信号为低电平。因此，根据判定的逻辑电平和预设幅值重新生成如图4中实线所绘的数据波形（虚线为初始数据信号的波形图）。从重新生成的数据信号能够满足数据驱动器中内部处理电路对数据信号的处理要求，避免数据获取错误。
在本实施例中，在检测到存在数据信号的传输时，检测数据信号在半个数据周期中各个采样点处的检测电位，根据检测电位来获取该数据信号在该半个数据周期内的逻辑电平，进而，数据信号生成电路根据获取到的逻辑电平和预设的标准幅值重新生成标准的数据信号。重新生成的标准的数据信号能够满足数据驱动器中内部处理电路对数据信号的处理要求，能够有效抓取数据，避免数据获取错误。
进一步的，参照图5，本申请数据的传输方法另一实施例，基于上述实施例，所述步骤S10之前，还包括：
步骤S40，检测到数据信号时，获取所述数据信号对应的时钟信号。
步骤S50，根据所述时钟信号的时钟周期确定所述数据周期。
在检测到数据信号时，获取该数据信号对应的时钟信号，从时钟信号中获取时钟周期，由于，时钟信号与数据信号对应生成，所以时钟信号的时钟周期等于数据信号的数据周期。
在数据驱动器（Data Driver）中设置有频率判断电路，通过频率判断电路能够获取时钟信号的频率，由于周期与频率互为倒数，故根据获取到的频率即可得到时钟信号的时钟周期。
此外，通过数据驱动器（Data Driver）中设置的电位判断电路能够获取到时钟信号中电位为0V的零伏时间点，时钟信号中两个相邻的零伏时间点间的时间间隔为半个时钟周期，故，可根据两个相邻的零伏时间点获取时钟周期。还可以通过其他方式以获取时钟信号的时钟周期，在此将不再一一赘述。
在本实施例中，在检测到数据信号时，获取数据信号对应的时钟信号，获取时钟信号的时钟周期，以便于后续根据时钟周期确定检测数据信号中各个采样点的检测电位时，所述时间间隔的确定，为后续判断数据信号的逻辑电平以及重新生成数据信号提供基础。
进一步的，参照图6，本申请数据的传输方法再一实施例，基于上述实施例，所述步骤S50之后，还包括：
步骤S60，实时监测所述时钟信号的电位为零伏的零伏时间点。
步骤S70，在所述零伏时间点延迟预设时间间隔时，以当前时间点为起始时间点获取时间间隔内所述数据信号中各个采样点处的检测电位。
采用电位检测电路能够检测到时钟信号处于零伏的零伏时间点，在时钟信号的零伏时间点后延迟预设时间间隔后，开始采集所述时间间隔内数据信号中各个采样点处的检测电位。在数据驱动器中增加延时电路，数据信号与时钟信号错位时，能有效地根据时钟信号的周期起始时间点确定出数据信号中需要获取检测电位的所述时间间隔（即半个数据周期）的起始时间点。避免检测时间点的确定错位，导致时间间隔获取错误，判断逻辑电平的时间区间并非为数据信号的完整半个数据周期，最终导致重新生成错误的数据信号，数据传输错乱。
如图3中所示，在检测到时钟信号的零伏时间点时，延迟中t1时间后，获取t2（t2=Δt）时间段内各个采样点的检测电位。从而，实现在数据信号的完整半个数据周期中判断数据信号的逻辑电平，避免生成错误的数据信号，数据传输错乱。
在本实施例中，采用电位检测电路能够检测到时钟信号处于零伏的零伏时间点，在时钟信号的零伏时间点后延迟预设时间间隔后，开始采集所述时间间隔内数据信号中各个采样点处的检测电位。在数据驱动器中增加延时电路，避免数据信号与时钟信号错位时，能给有效地根据时钟信号的周期起始时间点确定出数据信号中需要获取检测电位的所述时间间隔（即半个数据周期）的起始时间点。避免检测时间点的确定错位，导致时间间隔获取错误，判断逻辑电平的时间区间并非为数据信号的完整半个数据周期，最终导致重新生成错误的数据信号，数据传输错乱。
进一步的，参照图7，本申请数据的传输方法又一实施例，基于上述任一实施例，所述步骤S30之后，还包括：
步骤S80，根据所述时钟信号获取重新生成的所述数据信号的数据。
虽然利用数据驱动器中的数据信号生成电路重新生成了数据信号，但是该数据信号的周期和频率均未受到改变，因此根据时钟信号依然能够有效抓取重新生成的数据信号中的有效数据。且，重新生成的数据信号更能够被内部处理电路有效处理，提高数据抓取的准确性。
在通过时钟信号抓取数据时，获取该时钟信号的上升沿和/或下降沿，确定重新生成的所述数据信号中与该上升沿或者所述下降沿对应的时间点，并在确定的时间点处抓取数据信号中的数据。
在本实施例中，在通过时钟信号抓取数据时，获取该时钟信号的上升沿和/或下降沿，确定重新生成的所述数据信号中与该上升沿或者所述下降沿对应的时间点，并在确定的时间点处抓取数据信号中的数据。利用重新生成的数据信号更能够被内部处理元件有效处理，提高数据抓取的准确性。
本申请实施例还提出一种数据的传输装置，其中，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如下所述的数据的传输方法的步骤：
检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
此外，本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有数据的传输程序，所述数据的传输程序被处理器执行时实现如下所述的数据的传输方法的步骤：
检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (15)

  1. 一种数据的传输方法，其中，所述数据的传输方法包括以下步骤：
    检测到数据信号时，获取时间间隔内所述数据信号中各个采样点处的检测电位，其中，所述时间间隔为所述数据信号的数据周期的一半；
    根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平；
    以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
  2. 如权利要求1所述的数据的传输方法，其中，所述根据各个所述检测电位确定所述数据信号在所述时间间隔内的逻辑电平的步骤包括：
    获取所述检测电位中大于预设电位的高电位个数和小于或等于所述预设电位的低电位个数；
    当所述高电位个数大于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为高电平；
    当所述高电位个数小于所述低电位个数时，所述时间间隔内所述数据信号的逻辑电平为低电平。
  3. 如权利要求1所述的数据的传输方法，其中，所述获取时间间隔内所述数据信号中各个采样点处的检测电位的步骤之前，还包括：
    检测到数据信号时，获取所述数据信号对应的时钟信号；
    根据所述时钟信号的时钟周期确定所述数据周期。
  4. 如权利要求3所述的数据的传输方法，其中，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤包括：
    将所述时钟信号的时钟周期作为所述数据周期。
  5. 如权利要求3所述的数据的传输方法，其中，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤之后，还包括：
    实时监测所述时钟信号的电位为零伏的零伏时间点；
    在所述零伏时间点延迟预设时间间隔时，以当前时间点为起始时间点获取数据周期内所述数据信号中各个检测时间点处的检测电位。
  6. 如权利要求5所述的数据的传输方法，其中，数据传输的数据驱动器中具有延时元件，通过所述延时元件获取所述预设时间间隔。
  7. 如权利要求5所述的数据的传输方法，其中，所述数据的传输方法所涉及的装置具有电位检测元件，所述实时监测所述时钟信号的电位为零伏的零伏时间点的步骤包括：
    实时检测所述电位检测元件检测到的所述时钟信号的电位；
    所述电位检测元件检测到的所述电位为零伏的时间点为所述时钟信号的零伏时间点。
  8. 如权利要求5所述的数据的传输方法，其中，所述根据所述时钟信号的时钟周期确定所述数据周期的步骤之前，还包括：
    获取所述时钟信号的时钟周期。
  9. 如权利要求8所述的数据的传输方法，其中，所述获取所述时钟信号的时钟周期的步骤包括：
    获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
    或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
  10. 如权利要求1所述的数据的传输方法，其中，所述根据所述逻辑电平以及预设幅值重新生成所述数据信号的步骤之后，还包括：
    根据所述时钟信号获取重新生成的所述数据信号的数据。
  11. 如权利要求10所述的数据的传输方法，其中，所述数据的传输方法还包括：
    获取所述时钟信号的上升沿和下降沿；
    确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
    以及，抓取所述数据信号中所述时间点对应的数据。
  12. 如权利要求1所述的数据的传输方法，其中，所述获取时间间隔内所述数据信号中各个采样点处的检测电位的步骤包括：
    获取电位判断元件检测到的所述各个采样点对应的检测电位。
  13. 如权利要求1所述的数据的传输方法，其中，所述预设幅值大于或等于0.5伏。
  14. 一种数据的传输装置，其中，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如下所述的数据的传输方法的步骤：
    检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
    根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
    以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
  15. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有数据的传输程序，所述数据的传输程序被处理器执行时实现如下所述的数据的传输方法的步骤：
    检测到数据信号时，获取数据周期内所述数据信号中各个检测时间点处的检测电位；
    根据各个所述检测电位确定所述数据信号在所述数据周期内的逻辑电平；
    以及，根据所述逻辑电平以及预设幅值重新生成所述数据信号。
PCT/CN2019/071376 2018-12-19 2019-01-11 数据的传输方法、装置及计算机可读存储介质 Ceased WO2020124711A1 (zh)

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