WO2020124142A1

WO2020124142A1 - Improved neuromodulation implant architecture

Info

Publication number: WO2020124142A1
Application number: PCT/AU2019/051392
Authority: WO
Inventors: Peter Scott Vallack SINGLE; Dean Michael Karantonis; Mark Andrew Bickerstaff
Original assignee: Saluda Medical Pty Ltd
Priority date: 2018-12-17
Filing date: 2019-12-17
Publication date: 2020-06-25

Abstract

A neuromodulation system has configurable therapy components for carrying out a multi-stage neural stimulation and neural recording process. A wide transition memory outputs a large plurality of control lines to configure the therapy components to transition through each stage of the multi-stage neural stimulation and neural recording process. The wide transition memory is controlled by a narrow state input for selecting the stage of stimulation. One or more stages of the stimulation and recording process are conducted while a microcontroller is in a low power state, by providing for timer control of the narrow state input, and/or direct memory access (DMA) static updates and ADC data storage.

Description

IMPROVED NEUROMODULATION IMPLANT ARCHITECTURE

Technical Field

[0001] The present invention relates to neurostimulation, and in particular to improved systems and methods for configurable neurostimulator implants.

Background of the Invention

[0002] Electrical neuromodulation is used or envisaged for use to treat a variety of disorders including chronic pain, Parkinson’s disease, and migraine, and to restore function such as hearing and motor function. A neuromodulation system applies an electrical pulse to neural tissue in order to generate a therapeutic effect. Such a system typically comprises an implanted electrical pulse generator, and a power source such as a battery that may be rechargeable by transcutaneous inductive transfer. An electrode array is connected to the pulse generator, and is positioned close to the neural pathway(s) of interest. An electrical pulse applied to the neural tissue by an electrode causes the depolarisation of neurons, which generates propagating action potentials whether antidromic, orthodromic, or both, to achieve the therapeutic effect.

[0003] When used to relieve chronic pain for example, the electrical pulse is applied to the dorsal column (DC) of the spinal cord and the electrode array is positioned in the dorsal epidural space. The dorsal column fibres being stimulated in this way inhibit the transmission of pain from that segment in the spinal cord to the brain.

[0004] In general, the electrical stimulus generated in a neuromodulation system triggers a neural action potential which then has either an inhibitory or excitatory effect. Inhibitory effects can be used to modulate an undesired process such as the transmission of pain, or excitatory effects can be used to cause a desired effect such as the contraction of a muscle or stimulation of the auditory nerve.

[0005] The action potentials generated among a large number of fibres sum to form a compound action potential (CAP). The CAP is the sum of responses from a large number of single fibre action potentials. When a CAP is electrically recorded, the measurement comprises the result of a large number of different fibres depolarising. The propagation velocity is determined largely by the fibre diameter and for large myelinated fibres as found in the dorsal root entry zone (DREZ) and nearby dorsal column the velocity can be over 60 ms ¹. The CAP generated from the firing of a group of similar fibres is measured as a positive peak PI in the recorded potential, then a negative peak Nl, followed by a second positive peak P2. This is caused by the region of activation passing the recording electrode as the action potentials propagate along the individual fibres, producing the typical three-peaked response profile.

Depending on stimulus polarity and the sense electrode configuration, the measured profile of some CAPs may be of reversed polarity, with two negative peaks and one positive peak.

[0006] To better understand the effects of neuromodulation and/or other neural stimuli, and for example to provide a stimulator controlled by neural response feedback, it is desirable to accurately detect and record a CAP resulting from the stimulus. Evoked responses are less difficult to detect when they appear later in time than the artefact, or when the signal-to-noise ratio is sufficiently high. The artefact is often restricted to a time of 1 - 2 ms after the stimulus and so, provided the neural response is detected after this time window, a response measurement can be more easily obtained. This is the case in surgical monitoring where there are large distances (e.g. more than 12 cm for nerves conducting at 60 ms ¹) between the stimulating and recording electrodes so that the propagation time from the stimulus site to the recording electrodes exceeds 2 ms.

[0007] However to characterize the responses from the dorsal columns, high stimulation currents and close proximity between electrodes are required. Similarly, any implanted neuromodulation device will necessarily be of compact size, so that for such devices to monitor the effect of applied stimuli the stimulus electrode(s) and recording electrode(s) will necessarily be in close proximity. In such situations the measurement process must overcome artefact directly. However, this can be a difficult task as an observed CAP signal component in the neural measurement will typically have a maximum amplitude in the range of microvolts. In contrast a stimulus applied to evoke the CAP is typically several volts and results in electrode artefact, which manifests in the neural measurement as a decaying output of several millivolts partly or wholly contemporaneously with the CAP signal, presenting a significant obstacle to isolating or even detecting the much smaller CAP signal of interest.

[0008] For example, to resolve a 10 pV CAP with 1 pV resolution in the presence of an input 5 V stimulus, for example, requires an amplifier with a dynamic range of 134 dB, which is impractical in implant systems. As the neural response can be contemporaneous with the stimulus and/or the stimulus artefact, CAP measurements present a difficult challenge of measurement amplifier design. In practice, many non-ideal aspects of a circuit lead to artefact, and as these mostly have a decaying exponential appearance that can be of positive or negative polarity, their identification and elimination can be laborious. [0009] The difficulty of this problem is further exacerbated when attempting to implement CAP detection in an implanted device. Typical implants have a power budget which permits a limited number, for example in the hundreds or low thousands, of processor instructions per stimulus, in order to maintain a desired battery lifetime. Accordingly, if a CAP detector for an implanted device is to be used regularly (e.g. of the order of once a second), then care must be taken that the detector should consume only a small fraction of the power budget.

[0010] One architecture for mixed signal systems, and other digital systems, is to break the system into sub-functions, then design a subsystem for each sub-function. However, if any of the subsystems have an error, then it must be fixed and new hardware made. If the hardware uses a custom ASIC, this can be expensive and time consuming. Debug cycles can be slow as a result. A neurostimulator with feedback, such as a spinal cord stimulator with feedback, has the following major functions: delivering a stimulus; recording the neural response to the stimulus, and converting that to a digital value; measuring the amplitude of the response to stimulation; and updating the control variable of a feedback loop. To provide an implanted neurostimulator capable of feedback operation thus requires a high degree of configurability, while operating under such constraints.

[0011] Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date of each claim of this application.

[0012] Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

[0013] In this specification, a statement that an element may be“at least one of’ a list of options is to be understood that the element may be any one of the listed options, or may be any combination of two or more of the listed options.

Summary of the Invention

[0014] According to a first aspect the present invention provides a neuromodulation system comprising: configurable therapy components for carrying out a multi-stage neural stimulation and neural recording process;

a wide transition memory outputting a plurality of control lines to configure the therapy components to transition through each stage of the multi-stage neural stimulation and neural recording process, the wide transition memory further comprising a narrow state input for selecting the stage of stimulation.

[0015] According to a further aspect the present invention provides a method for

neuromodulation, the method comprising:

selecting a stage of stimulation using a narrow state input of a transition memory;

the transition memory outputting a plurality of control lines to configure therapy components to transition through each stage of a multi-stage neural stimulation and neural recording process.

[0016] According to another aspect the present invention provides computer software for carrying out the method of the second aspect.

[0017] According to another aspect the present invention provides a computer program product comprising computer program code means to make a computer execute a procedure for neuromodulation, the computer program product comprising computer program code means for carrying out the method of the second aspect.

[0018] According to a further aspect the present invention provides a non-transitory computer readable medium for neuromodulation, comprising instructions which, when executed by one or more processors, causes performance of the method of the second aspect.

[0019] In some embodiments, the plurality of control lines output by the wide transition memory may comprise a first plurality of control lines, and the narrow state input may comprise a second plurality of input lines, wherein the first plurality is greater than the second plurality. In such embodiments the first plurality may be more than double the second plurality, more than four times the second plurality, more than 10 times the second plurality, or more than 40 times the second plurality. For example in some embodiments a control bus comprising the control lines output by the wide transition memory may comprise 320 bits, while a state bus comprising the narrow state input of the wide transition memory may comprise 7 bits. [0020] In some embodiments, the configurable therapy components may comprise one or more, or all, of a current source, multiplexor, amplifier, and an analog to digital converter, or more than one of each. In some embodiments, the configurable therapy components are all controlled by a single control bus comprising the plurality of control lines output by the wide transition memory.

[0021] In some embodiments the narrow state input of the wide transition memory comprises a state bus configured to select states of the neuromodulation system to effect a phase of stimulation and recording.

[0022] Some embodiments may further comprise a static memory holding configuration data which is not needed to change throughout a single cycle of stimulation and recording, the configuration data being accessible by the therapy components. In such embodiments, the static memory may be programmable via a programming interface, such as a 4-bit serial bus. The static memory may be updated after a single cycle of stimulation and recording is complete.

[0023] In some embodiments the transition memory may be programmable via a

programming interface, such as a 4 bit serial bus. The transition memory programming interface and static memory programming interface may comprise a single shared programming interface, such as a shared 4 bit serial bus.

[0024] In some embodiments the stimulus cycle is defined using a table with one row for each state, where each row contains a state bus value and a timer value.

[0025] In some embodiments the state bus, programming interface(s) and ADC output are controlled or handled by a low power microcontroller, such as a Texas Instruments MSP430 or the like. In such embodiments, the state bus is preferably clocked by the microcontroller while the microcontroller is in a low power state. In such embodiments, each stimulation preferably involves triggering a stimulation engine, with the stimulation proceeding while the

microcontroller is in a low power state and ceasing automatically when a direct memory access (DMA) of the microcontroller has finished transfers. In such embodiments, the microcontroller is preferably placed in an active mode, or high power mode, by an interrupt, and only remains in the active mode to compute a feedback variable and perform any required housekeeping tasks, before re-entering the low power mode where only the real time clock (RTC) and a timer are on. In such embodiments, ECAP detection may be performed by a dot-product filter template technique while the microcontroller is in a low power state. In such embodiments, data from an analog to digital output of the therapy components may be read into the microcontroller memory using DMA while the microcontroller is in a low power state.

[0026] References herein to estimation or determination are to be understood as referring to an automated process carried out on data by a processor operating to execute a predefined estimation or determination procedure. The approaches presented herein may be implemented in hardware (e.g., using application specific integrated circuits (ASICs)), or in software (e.g., using instructions tangibly stored on computer-readable media for causing a data processing system to perform the steps described above), or in a combination of hardware and software. The invention can also be embodied as computer-readable code on a computer-readable medium. The computer-readable medium can include any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include read-only memory ("ROM"), random-access memory ("RAM"), CD-ROMs, DVDs, magnetic tape, optical data storage device, flash storage devices, or any other suitable storage devices. The computer-readable medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Brief Description of the Drawings

[0027] An example of the invention will now be described with reference to the

accompanying drawings, in which:

Figure 1 schematically illustrates an implanted spinal cord stimulator;

Figure 2 is a block diagram of the implanted neurostimulator;

Figure 3 is a schematic illustrating interaction of the implanted stimulator with a nerve; Figure 4 illustrates stages of a multi-stage stimulation and recording phase;

Figure 5 illustrates control lines required to effect a multi-stage stimulation and recording phase;

Figure 6 illustrates a neurostimulation implant architecture in accordance with an embodiment of the invention;

Figure 7 provides a more detailed system overview of the control scheme of Figure 6; Figure 8 illustrates a memory with four addresses, to fit the dynamic memory in Figure 7; Figure 9 shows an embodiment in which the system comprises a pointer table;

Figure 10 illustrates a non-sequential memory with reduced redundancy; and

Figure 11 shows a method of another more compact embodiment of the invention. Description of the Preferred Embodiments

[0028] Figure 1 schematically illustrates an implanted spinal cord stimulator 100. Stimulator 100 comprises an electronics module 110 implanted at a suitable location in the patient’s lower abdominal area or posterior superior gluteal region, and an electrode assembly 150 implanted within the epidural space and connected to the module 110 by a suitable lead. Numerous aspects of operation of implanted neural device 100 are reconfigurable by an external control device 192. Moreover, implanted neural device 100 serves a data gathering role, with gathered data being communicated to external device 192.

[0029] Figure 2 is a block diagram of the implanted neurostimulator 100. Module 110 contains a battery 112 and a telemetry module 114. In embodiments of the present invention, any suitable type of transcutaneous communication 190, such as infrared (IR), electromagnetic, capacitive and inductive transfer, may be used by telemetry module 114 to transfer power and/or data between an external device 192 and the electronics module 110.

[0030] Module controller 116 has an associated memory 118 storing patient settings 120, control programs 122 and the like. Controller 116 controls a pulse generator 124 to generate stimuli in the form of current pulses in accordance with the patient settings 120 and control programs 122. Electrode selection module 126 switches the generated pulses to the appropriate electrode(s) of electrode array 150, for delivery of the current pulse to the tissue surrounding the selected electrode(s). Measurement circuitry 128 is configured to capture measurements of neural responses sensed at sense electrode(s) of the electrode array as selected by electrode selection module 126.

[0031] Figure 3 is a schematic illustrating interaction of the implanted stimulator 100 with a nerve 180, in this case the spinal cord however alternative embodiments may be positioned adjacent any desired neural tissue including a peripheral nerve, visceral nerve, parasympathetic nerve or a brain structure. Electrode selection module 126 selects a stimulation electrode 2 of electrode array 150 to deliver a triphasic electrical current pulse to surrounding tissue including nerve 180, although other embodiments may additionally or alternatively deliver a biphasic tripolar stimulus. Electrode selection module 126 also selects a return electrode 4 of the array 150 for stimulus current recovery to maintain a zero net charge transfer.

[0032] Delivery of an appropriate stimulus to the nerve 180 evokes a neural response comprising a compound action potential which will propagate along the nerve 180 as illustrated, for therapeutic purposes which in the case of a spinal cord stimulator for chronic pain might be to create paraesthesia at a desired location. To this end the stimulus electrodes are used to deliver stimuli at 30 Hz. To fit the device, a clinician applies stimuli which produce a sensation that is experienced by the user as a paraesthesia. When the paraesthesia is in a location and of a size which is congruent with the area of the user’s body affected by pain, the clinician nominates that configuration for ongoing use.

[0033] The device 100 is further configured to sense the existence and electrical profile of compound action potentials (CAPs) propagating along nerve 180, whether such CAPs are evoked by the stimulus from electrodes 2 and 4, or otherwise evoked. To this end, any electrodes of the array 150 may be selected by the electrode selection module 126 to serve as measurement electrode 6 and measurement reference electrode 8. The stimulator case may also be used as a measurement or reference electrode, or a stimulation electrode. Signals sensed by the measurement electrodes 6 and 8 are passed to measurement circuitry 128, which for example may operate in accordance with the teachings of International Patent Application Publication No. WO2012155183 by the present applicant, the content of which is incorporated herein by reference.

[0034] The present invention relates to the digital architecture of the analog only chip (AOC) and its method of control. In order to effect feedback control of neurostimulation, it is necessary that an amplifier will recover from the stimulus pulse at its input. In practice, as disclosed for example in the present Applicant’s application WO2012155183, a blanked amplifier is often used. This blanked amplifier needs to be blanked and enabled at precise times coordinated with the stimulus, electrodes need to be shorted together to recover charge on the electrodes from current source mismatch, among numerous other aspects of the complicated sequence of stimulation and recording, of which some aspects are shown in Fig. 4

[0035] The present system comprises four current sources so as to permit current steering, each with a coarse output control, an amplifier with two stages of blanking, a multiplexer that directs current to the outputs, and a range of other components, and consequently has

approximately 300 control lines whose value may change during a stimulus. A selection of these control lines are shown in Figure 5, where control signals are in italics. Note that the items in the dashed box are for a single current source and are thus duplicated four times (0..3), further increasing the number of unique control signals beyond those shown. This results in a situation where the device requires more control lines than can be controlled directly with a

microcontroller bus. Most microcontroller busses have less than 64 pins (for a parallel bus) or fewer for a serial bus. A parallel bus gives the microcontroller the ability to control timing with that bus, but if a serial bus is used, then a separate timing signal is required. There is clearly a mismatch between the number of outputs of the microcontroller and the requirements of the analog control.

[0036] During normal operation of a neuromodulator the only parameter that changes between one stimulus and the next is the current source current. The first and second phases of the stimulus use the same amplitude.

[0037] Figure 6 illustrates an implant architecture in accordance with one embodiment of the invention. A set of components (called the therapy components 610), that perform current source to electrode mapping, current generation, amplification and analog-to-digital conversion, are controlled by a single 320-bit wide control bus.

[0038] A wide memory, called the transition memory 620, is provided that controls the state of the therapy components 610.

[0039] A much smaller bus, the state bus, selects the states of the stimulation. This can be considered as an address bus for the transition memory 620. Figure 4 shows that six such states can effect a single stimulation and recording phase, though in practice some of the transitions require intermediate steps. Additional states can also be required for tri-phasic stimulation, for example as described in International Patent Publication No. WO 2017219096 Al, the contents of which are incorporated herein by reference. Additional states can also be required if some control signals need to be enabled a fixed time before another, for example to provide for amplifier settling. In practice around 15-20 states are required. The present embodiment advantageously provides for dynamic and carefully controlled transition between individual states.

[0040] An ADC output 630 connects to a microcontroller (not shown in Fig. 6). A“static” memory 640 stores configuration data, and is static in the sense that such data does not need to change during a stimulus. The static memory 640 and transition memory 620 are programmed using a separate programming interface, which can be a 4-bit serial bus.

[0041] To operate this system, the static memory and transition memory are loaded via the programming interface. For each stimulus, the state bus counts through the states of the stimulus and recording as illustrated in Figure 4. The ADC outputs can be captured by the microcontroller during the recording period. [0042] The stimulus cycle is defined using a table with one row for each state, where each row contains a state bus value and a timer value. After each stimulus, the static memory can be updated. Usually, the only parameter that is changed is the current control that sets the delivered current. The signal processing of the ADC output can occur when the stimulus ECAP has been captured (the“settling” phase of Figure 4.)

[0043] Figure 7 provides a more detailed system overview of the control scheme of Figure 6. The timing parameters 710 (pulse width or‘PW’, inter-phase gap or (TPG’) and stimulation rate (and similar parameters) are compiled into a table of times 720 which control how long any state of Figure 4 is to last. These states also are programmed into a dynamic memory 750 identifying the state of any control bit at any time. This task is performed by a (software) compiler. The system now operates as follows: Each time from the table of times 720 is loaded into a divide by n counter 730 in turn. This thus measures out the time for each state. Each time this counter 730 reaches the end count, it increments a second counter 740 which generates a set of sequential addresses to the dynamic memory 750. The data bits from the dynamic memory 750 control the stimulus generator 762, multiplexor (MUX) 764 and amplifier 766 selecting the required control signals for each state. The dynamic memory 750 can thus be thought of as a table of enables.

[0044] This system is now controlled by a single finite state machine that simply counts through the system states required for a stimulation and recording cycle. It is capable of generating any combination of control lines, and so it can advantageously be debugged entirely as a software exercise. This may be further understood with reference to Figure 8. This shows a memory with four addresses and is drawn to fit the dynamic memory in Figure 7. These four columns encode a biphasic stimulus going from Address 0 to Address 3. First the current source is disabled (‘0’). The polarity does not matter as there is no current, so the encoding can be‘0,0’. The current source is then enabled to deliver a positive current (‘1, 1’). The current source is then disabled (‘0,0’). Then a second stimulus is provided with opposite polarity (‘0, 1’).

[0045] In practice, more than 4 lines of memory are required. The number is a tradeoff between memory area and the number of lines required to make a full stimulus, enable amplifiers etc. A total of 128 is the preferred value in this embodiment.

[0046] Figure 11 shows a method of another embodiment, which is more compact than the embodiment of Figure 7. In this case an array of times is used to select an array of addresses. These are stored sequentially but need not be sequential. Inspecting Figure 8 indicates that two of the data rows are identical. Thus a table without this redundancy can be used - see Figure 10. The system must then count through a memory of addresses in turn, where addresses can be repeated. This is illustrated in Figure 9, which shows an embodiment in which the system comprises a pointer table. A software process generates a table of times 920 and a table of addresses 922 with the meaning‘use each address for the time allocated’. These addresses select columns of the memory 950 to sequence the stimulus generator 962, multiplexor 964, etc, through their steps.

[0047] The advantage of this system compared to prior art subsystem approaches is that it does not require state machines to control the individual blocks, and provides complete freedom on the timing of the control both in absolute terms (the time for each event) and relative terms (the time between each event). The preferred method of this aspect of the invention is illustrated in Figure 11. This follows Figure 7 or Figure 9 but shows the preferred values of the components, as well as some additional features.

[0048] A set of components 1110 (called the“therapy components”) that perform current source to electrode mapping (MUX), stimulus generation, amplification and analog-to-digital conversion, controlled by a single 320-bit wide“control bus”. A wide memory 1120, called the “transition memory” that controls the state of the therapy components 1110. A much smaller control bus called the“state bus” that selects the states of the stimulation. An ADC output 1130 that connects to a microcontroller. A static memory 1140 that stores configuration data that does not change during a stimulus. A set of flip-flops 1150 between the transition memory 1120, the static memory 1140 and the therapy components 1110, and clocked by the signal XLoad synchronize that the signal changes to the therapy components.

[0049] The static memory 1140 and transition memory 1120 are programmed using a separate programming interface, that can be a serial bus - a SPI bus is preferred. To operate this system, the static memory 1140 and transition memory 1120 are loaded via the programming interface. For each stimulus, the state bus counts through the states of the stimulus and recording as illustrated in Figure 4. The ADC outputs can be captured by the microcontroller during the recording period. The stimulus cycle is defined using a table with one row for each state, where each row contains a state bus value and a timer value. After each stimulus, the static memory 1140 can be updated. Usually, the only parameter that is changed is the current control that sets the delivered current. The signal processing of the ADC output can occur when the stimulus ECAP has been captured (the“settling” phase of Figure 4.) Using an MSP430 as the microcontroller 1170, the state bus can be controlled using timers. The ADC output can be read and transferred to memory using direct memory access (DMA). These can both be done while the MSP430 is in a low-power state, which presents considerable power savings in the execution of each stimulation cycle. The MSP430 enters its executing state to process ADC samples, calculate the current for the next stimulus and load this data into static memory 1140.

[0050] Thus, an important aspect of such embodiments of the invention relates to how the stimulus and data recording are coordinated by microcontroller 1170 while consuming minimal power. The present embodiment recognises that certain microcontrollers, including the MSP430 family from Texas Instruments, consume differing amounts of power depending on their state. They can have an active state, where they can execute instructions, but also have a variety of low- power states where they will consume lower power but may still provide simpler or a subset of functions including clocks, counters, and direct-memory access (DMA).

[0051] The hardware discussed in the embodiments described herein is implemented using a single ASIC. The state bus and programming interface can be clocked by the MSP430 microcontroller 1170 while it is in a low power state. To this end, all the DMA and tables are compiled prior to starting stimulation, so that for each stimulation it is necessary simply to trigger the stimulation engine, and the stimulation will then automatically stop when the DMA has finished transfers. Once stimulation is finished, an interrupt puts the MSP430 microcontroller 1170 in active mode, and the MSP430 microcontroller 1170 then computes the feedback variable and performs some housekeeping tasks, before once again entering the low power mode where only the real time clock (RTC) and a timer are on. This cycle then repeats to effect the desired therapeutic stimulation paradigm. In this embodiment, ECAP detection is performed by the dot- product filter template technique set forth in W02015074121, the contents of which are incorporated herein by reference. Advantageously, the dot product is also computed in low power state using the DMA and MAC. This allows a stimulation cycle to occur without intervention from the MSP430.

[0052] The ASIC ADC provides a 12-bit bus that can connect to a parallel bus provided by the MSP430. The data on the MSP430 bus can be clocked into the MSP430 memory using DMA, again without the MSP430 being required to execute any instructions i.e. the MSP430 can also remain in its low-power state during this entire time.

[0053] This allows construction of a low-power feedback system for spinal cord stimulation and other forms of neuromodulation. The ADC output is clocked using a dedicated signal - as the current sources etc are not altered during data gathering, there is no value in controlling the ADC through the transition memory. [0054] The system performs the feedback using the following steps. First, the MSP430, while executing instructions, loads the transition memory and the static memory with the data required for a complete feedback loop therapy. Second, the MSP430 also generates data tables that will control the state bus during the stimulation and recording cycle. These were described in Figure 7 through Figure 10, having both time data and address data. Third, the MSP430 enters a low-power state. Fourth, timers on the MSP430 change the state bus and XLoad clock at pre -determined intervals to orchestrate the stimulation cycle and the data recording. Fifth, during the data cycle, the data from the ADC is read into MSP430 memory using DMA. Sixth, when the stimulus and recording is complete, the MSP430 wakes from its low-power state, reads the ECAP data, calculates the stimulus current required for the next stimulus, loads this data into the static memory. Seventh, the cycle repeats from the third step.

[0055] This system, in this manner provides the following advantages. It contains no state machines that need to be debugged. The ASIC function is controlled completely outside the device using simple data tables that can be controlled by software. These tables contain timing and state information, so provision can be made for analog components whose exact characteristics are unclear when the ASIC is manufactured. It allows control by a commercial off-the-shelf microcontroller, but in a manner that is compatible with a battery-operated device.

[0056] Thus, by avoiding dedicated sub-system design, the present embodiment has the further advantage of avoiding the time and cost to correct errors by making new hardware and custom ASIC during debug cycles as can be required in subsystem finite state machines for example.

[0057] Using an MSP430, the state bus can be controlled using timers. The ADC output can be read and transferred to memory using direct memory access (DMA). These can both be done while the MSP430 is in a low-power state. The MSP430 enters its executing state to process ADC samples, calculate the current for the next stimulus and load this data into static memory.

[0058] It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present

embodiments are, therefore, to be considered in all respects as illustrative and not limiting or restrictive.

Claims

CLAIMS:

1. A neuromodulation system comprising:

configurable therapy components for carrying out a multi-stage neural stimulation and neural recording process;

2. The neuromodulation system of claim 1 wherein the plurality of control lines output by the wide transition memory comprises a first plurality of control lines, and wherein the narrow state input comprises a second plurality of input lines, and wherein the first plurality is greater than the second plurality.

3. The neuromodulation system of claim 2 wherein the first plurality is more than four times greater than the second plurality.

4. The neuromodulation system of claim 3 wherein the first plurality is more than 40 times greater than the second plurality.

5. The neuromodulation system of any one of claims 1 to 4 wherein a control bus comprising the control lines output by the wide transition memory comprises more than 200 bits.

6. The neuromodulation system of claim 5 wherein the control bus comprises 320 bits.

7. The neuromodulation system of any one of claims 1 to 6 wherein a state bus comprising the narrow state input of the wide transition memory comprises fewer than 20 bits.

8. The neuromodulation system of claim 7 wherein the state bus comprises 7 bits.

9. The neuromodulation system of any one of claims 1 to 8 wherein the configurable therapy components comprise at least one current source.

10. The neuromodulation system of claim 9 wherein the configurable therapy components comprise at least four current sources.

11. The neuromodulation system of any one of claims 1 to 10 wherein the configurable therapy components comprise a multiplexor.

12. The neuromodulation system of any one of claims 1 to 11 wherein the configurable therapy components comprise an analog to digital converter.

13. The neuromodulation system of any one of claims 1 to 12 wherein the configurable therapy components are all controlled by a single control bus comprising the plurality of control lines output by the wide transition memory.

14. The neuromodulation system of any one of claims 1 to 13 wherein the narrow state input of the wide transition memory comprises a state bus configured to select states of the neuromodulation system to effect a phase of stimulation and recording.

15. The neuromodulation system of any one of claims 1 to 14 further comprising a static memory holding configuration data.

16. The neuromodulation system of claim 15 wherein the configuration data comprises data which is not needed to change throughout a single cycle of stimulation and recording.

17. The neuromodulation system of claim 15 or claim 16, wherein the configuration data is accessible by the therapy components.

18. The neuromodulation system of any one of claims 15 to 17 wherein the static memory is programmable via a programming interface.

19. The neuromodulation system of claim 18 wherein the static memory is programmable via a 4-bit serial bus.

20. The neuromodulation system of any one of claims 15 to 19 wherein the static memory is configured to be updated after a single cycle of stimulation and recording is complete.

21. The neuromodulation system of any one of claims 1 to 20 wherein the transition memory is programmable via a programming interface.

22. The neuromodulation system of claim 21 wherein the transition memory is programmable via a 4 bit serial bus.

23. The neuromodulation system of claim 18 and claim 21, wherein the transition memory programming interface and static memory programming interface comprise a single shared programming interface.

24. The neuromodulation system of any one of claims 1 to 23 wherein a stimulus cycle is defined using a table with one row for each state, where each row contains a state bus value and a timer value.

25. The neuromodulation system of any one of claims 1 to 24 wherein the state bus, programming interface(s) and/or ADC output are controlled by a low power microcontroller.

26. The neuromodulation system of claim 25 wherein the state bus is clocked by the microcontroller while the microcontroller is in a low power state.

27. The neuromodulation system of claim 25 or claim 26 wherein each stimulation cycle involves triggering a stimulation engine, and wherein the stimulation cycle proceeds while the microcontroller is in a low power state and ceases automatically when a direct memory access (DMA) of the microcontroller has finished transfers.

28. The neuromodulation system of any one of claims 25 to 27 wherein the microcontroller is placed in an active mode by an interrupt and only remains in the active mode to compute a feedback variable and perform any required housekeeping tasks.

29. The neuromodulation system of any one of claims 25 to 28 wherein ECAP detection is performed by a dot-product filter template technique while the microcontroller is in a low power state.

30. The neuromodulation system of any one of claims 25 to 29 wherein data from an analog to digital output of the therapy components is read into the microcontroller memory using DMA while the microcontroller is in a low power state.

31. A method for neuromodulation, the method comprising:

32. A computer program product comprising computer program code means to make a computer execute a procedure for neuromodulation, the computer program product comprising computer program code means for carrying out the method of claim 31.