WO2020123248A1 - On-chip antenna test circuit for high freqency commmunication and sensing systems - Google Patents

Abstract

A dual use novel on chip antenna (OCA) test architecture and system that significantly increases the testability of communication, sensor and radar circuitry having integrated OCAs is provided. The novel OCA architecture and system reduces test time and test cost of the OCA without negatively impact the functionality and performance of the tested OCA, The OCA test data obtained enables quantitative OCA defect diagnosis and characterizations. In addition, the novel OCA test structure functions as an impedance tuning capability between the OCA and on chip communication circuits.

Description

On-chip antenna test circuit for High Frequency Communication and Sensing

Systems

CROSSTKEFERENCB TO RELATED APPLICATIONS

The present implication is related to, claims the earliest available effective filing date(s) from (e.g„ claims earliest available priority dates for other than provisional patent implications; claims benefits under 35 USC § 119(e) for provisional patent Applications), and incorporates by reference in its entirety all Subject matter of the following listed application^) (the“Related Applications") to the extent such subject matter is not inconsistent herewith; the present application also claims the earliest available effective filing date(s) from, and also incorporates by reference in its entirety all subject matter of any and all parent, grandparent, great-grandparent, etc, implications of the Related Application^) to the extent such subject matter is not inconsistent herewith:

United States provisional patent application 62/777,435, entitled“On-chip antenna test Circuit for High Frequency Communication and Sensing Systems” naming Tian Xia and Gttoan Wang as inventors, filed 19 December 2018.

Background

1. Field of Use

[0001] This invention relates to devices and methods for «sting integrated on chip antenna circuits (OCAs). 2. Description of Prior Art (Background)

[0002] With the rapid advancement of semiconductor technology, the enthusiastic pursuit of high-speed communication, ubiquitous sensing, and wide scope deployment of internet of tilings (foT), designing highly compact communication, sensor and radar system-on- chip (SoC) becomes extremely feasible and valuable.

[0003] Currently, many novel applications, i.e. 5G commumcation, autonomous vehicle, IoT, etc. are the driving forces of many innovations, such as artificial intelligence (AI), augmented reality (AR), cloud and edge computing, and so on. To realize all these innovations, many highly compact and multifunctional integrated circuits have been designed to lay the hardware foundations.

[0004] Among them, an important design technology is the antenna array beamformmg integrated circuit. To realize the beamforming, a set of antennas are embedded on a single chip. The phase and gain of signals feeding each antenna can be adaptively manipulated to control the overall performance of antenna array such as radiation pattern and gain.

[0005] In 2017, IBM and Ericsson demonstrated a 28 GHz 5G communication transceiver chip with 16 On Chip Antennas (GCAs). For smart vehicle anti-collision applications, TI, NXP and Infineon produce 77 GHz radar circuits where a set of antennas (i.e. 3 transmitter antennas and 4 receiver antennas) are embedded in the same circuit package. While integrating antenna arrays on a package significantly leverages circuit functionalities, it poses a challenge for large scale production testing.

[0006] For testing the OCAs, the existing methods employ radiation testing. However, such methods are complicated, costly and slowly, and not suitable for large volume production testing.

[0007] hi traditional communication and radar systems, the antenna is an off-chip component and its connection to the RF front end circuit is through a RF cable or a connector. The quality of the connection can be tested through s-parameter measurement. For instance, Si 1 measurement can effectively characterize the connection port impedance. If the impedance measurement result is off the specification, it reveals that there exists defect. However, such method is not feasible to test integrated antennas as the antenna and its connection are embedded inside the chip and not accessible for probing to perform S- parameter measurements. As a result, the testability of the integrated antenna is low.

[0008] An alternative OCA test method adopted by the semiconductor industry is a radiation measurement. An off-chip antenna connected to a test instrument, i.e. a network analyzer. During the test, a transceiver chip is configured to transmit RF signals through an OCA antenna under test. The off-chip antenna receives the signal and transmits it to the test instrument for characterization.

[0009] To minimize environmental noise interference, the transceiver chip and the off-chip antenna are located in an anechoic chamber. If the OCA under test is defect free, its emission signal will be received by the receiving antenna and the characterization results will meet specifications. Otherwise, the OCA radiation signal will he distorted which can be detected through the measurement.

[0010] While prior art radiation test can detect defective OCAs, the approach has several main drawbacks, including complicated test set up, long test time, and high test cost. Consequentially, it is not suitable for large volume production testing. Moreover, it provides limited information for quantitative defect diagnosis.

[0011] Therefore, a need exists for improved OCA testing that can reduce the test cost and improve test efficiency of on-chip integrated antennas.

Brief Summary

[0012] This invention is directed towards an improved On-Chip-Antenna (iOCA) architecture and device for improving the testability of the communication, sensor and radar circuitry integrated on the same chip as the transmitter and receiver circuit The iOCA architecture and device enables the enable quantitative defect diagnosis and characterizations. In addition, the embedded iOCA test architecture provides impedance tuning capability between the OCA and on chip communication circuits. Brief Description of the Drawings

[0013] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

[0014] FIG. 1 schematically depicts a the iQCA architecture and system according to one embodiment of tire present invention;

[0015] FIG 2 is a simulated test circui t of die invention shown in FIG 1 ;

[0016] FIG. 3 A is a schematic of the iOCA coupler in measurement mode;

[0017] FIG. 3B is a schematic of the iQCA coupler in operational mode where the coupler functions as a double stub impedance tuner for impedance tuning capability;

[0018] FIGs. 4A-4F are graphical S-parameter simulation results for varying port-2 impedances shown in FIG. 2; and

[0019] FIG. 5 is a graphical representation of S(3,l) variations for a wide range of frequencies for the iQCA shown in FIG, 1,

Detailed Description

[0020] The following brief definition of terms shall apply throughout the application:

[0021] The term “comprising” means including but not limited to, and should be interpreted in the manner it is typically used in the patent context;

[0022] The phrases“in one embodiment,”“according to one embodiment,” and the like generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention (importantly, such phrases do not necessarily refer to the same embodiment);

[0023] If the specification describes something as“exemplary” or an“example,” it should be understood that refers to a non-exclusive example; and

[0024] If the specification states a component or feature“may ,”“can,”“could,”“should,” “preferably,”“possibly,”“typically,”“optionally,”“for example,” or“might” (or other such language) be included or have a characteristic, that particular component or feature is not required to be included or to have the characteristic.

[0025] Referring now to FIG. 1 of the drawings, there is shown a schematically depicted iOCA architecture and system 10 according to one embodiment of the present invention. Fig. 1 illustrates the iOCA with a transceiver digital back end circuit 17, transceiver RF front end circuit 13, an on-chip 4-port hybrid coupler 12, an OCA 15, and detection circuit 19.

[0026] Also shown in FIG. 1 are transmission line 14 between ports 1 and 2 and transmission line 16 between ports 4 and 3. The transmission lines 14, 16 are composed of transmission lines and switches described in more detail herein. It will be appreciated that the location of the switches enables the IOCA to function as a double stub impedance tuner for impedance tuning capability.

[0027] Still referring to FIG. 1, ports 1 and 2 of the iOCA coupler 12 connect to transceiver RF front end circuit 13 and the OCA 15, respectively. For a defect free OCA with a good connection from the transceiver circuit 13 to the OCA 15, the terminal impedance is nominally 50 ohms, which indicates good impedance matching is achieved at port 2 H enee, a signal is transmitted from the transceiver circuit 13 over transmission line 14 to the OCA 15 with zero or very small signal reflections resulting zero or very small voltage standing wave ratio (VSWR). In other words, any signal power level coupled to transmission line 16 is known according to the design specifications of the coupler 12. [0028] If fee OCA 15, transmission line 14, or transceiver 13 impedances are not matched there is an impedance mismatch at port 2, As a result, power reflection occurs on fee transmission line between port 1 and port 2. In turn, significant coupling occurs between transmission line 14 to transmission line 16. The power level of signals at port 3 and port 4 will change to an out-of-specification value which can be detected by detection circuit 19. Detection circuit 19 may be any suitable detection circuit such as a power detector, an RMS detector or other measurement circuit. The detection circuit 19 output can connect to the chip test pin for probing. In alternate embodiments detector circuit 19 may digitize the signal to be sent through other inherent on chip test structures, such as the scan-chain to scan out the test results.

[0029] Referring also to FIG. 2 there is shown an example schematic of the ports and transmission lines of the invention shown in FIG. 1. In the example schematic, fee operating frequency is designed centering at 26 GHz, The impedances of Port 1, port 3 and port 4 all equal 50 ohm. While for port 2, as it connects to fee antenna, to emulate fee defect, its port impedance is set as a variable X. It will be appreciated that transceiver, transmission lines, and fee OCA may he any suitable impedance.

[0030] Referring also to FIG. 3A there is shown a schematic of the iOCA in measurement mode. Switches Si and S2 are only on during measurement mode. When switches Si, S2 are off the switches Si, S2, and transmission lines Tsi and T_&2, function as a double stub impedance tuner for impedance tuning capability as shown in FIG. 3B. It will be appreciated that switches Si, S¾ may be any suitable solid-state switch.

[0031] Referring also to FIGs. 4A-4F there are shown S-parameter simulation results for varying port-2 impedances shown in FIG. 2. When fee iOCA is defect free fee internal transmission and terminal impedances are matched. In fee examples shown in FIGs 4A- 4F the terminal impedance is 50 ohms, Thus, at fee center frequency 26 GHz, as shown in Fig. 4A, S (2,1) equals -3 dB as expected. Correspondingly, S (3,1) equals -3.024 dB. S (4,1) is as small as -56.1 dB since there is no power reflection.

[0032] If the iOCA is defective, transmission and terminal impedances are not matched, eg., not matched at 50 ohms, which leads to impedance mismatch and power reflections from tlie OCA, i.e. , standing waves. As shown in FIGs. 4B-4E, it is shown that S(4,l) value increases significantly, which indicates strong power reflections occurring within the coupler 12 and is measurable by detection circuit 19 shown in FIG. 1.

[0033] Referring also to FIG. 5 there is shown S(3,I) variations for a wide range of frequencies. As shown in FIGs 4A-4E S(3,l) value variation at the center frequency is small However, checking a wider range frequency spectmm, as shown in Fig. 5, it is clear that significant and measurable discrepancies occur.

[0034] It should be understood that the foregoing description is only illustrative of the invention. Thus, various alternatives and modifications can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances that fall within the scope of the appended claims.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC) comprising:

a transceiver circuit;

an on-chip antenna (OCA);

a detection circuit; and

a coupling circuit for coupling the transceiver circuit, detection circuit, and the OC A, and wherein the coupling circuit comprises a plurality of selectable circuit configurations, wherein the selectable circuit configurations comprise a test mode configuration circuit and an operational mode configuration circuit

2. The IC as in claim 1 wherein the coupling circuit comprises:

a first transmission line connecting the transceiver circuit and the OCA; and a second n ansmission line, wherein the second transmission line is connected to the detection circuit and is suitably position with respect to the first transmission line to sense standing waves on the first transmission line.

3. The IC as in claim 1 wherein the coupling circuit comprises an OCA double stub impedance tuner.

4. A second transmission line connected with a plurality of switches, wherein the second transmission line is connecting the detection circuit and the transceiver;

5. A third transmission line connected with a plurality of switches, wherein the third transmission line is connecting the OCA and the fourth transmission line;

6. A fourth transmission line connecting the third transmission line, second transmission line, and detection circuit.

7. A reconfigurable double-stub impedance tuner in the operation mode of the test circuit, wherein the length of the transmission line stubs are dependent on the location and operation mode of the switches providing various impedance tuning range.