WO2020113683A1 - 时序控制芯片、显示驱动组件和显示装置 - Google Patents

时序控制芯片、显示驱动组件和显示装置 Download PDF

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Publication number
WO2020113683A1
WO2020113683A1 PCT/CN2018/121916 CN2018121916W WO2020113683A1 WO 2020113683 A1 WO2020113683 A1 WO 2020113683A1 CN 2018121916 W CN2018121916 W CN 2018121916W WO 2020113683 A1 WO2020113683 A1 WO 2020113683A1
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spread
spectrum
clock signal
signal
frequency
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French (fr)
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王明良
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, in particular to a timing control chip, a display driving component, and a display device.
  • the display device is equipped with a display suitable for large-sized, high-resolution, and high-frame-rate displays Drive component, and the timing control chip (Timer) in the display drive component Control Register integrated circuit (TCON IC) outputs a clock signal to the data driver chip (Data Driver) in the display driver assembly IC) and Scan Driver (Gate Driver) IC) to achieve image display.
  • TCON IC timing control chip
  • Data Driver data Driver
  • Scan Driver Scan Driver
  • TCON Since the data involved in the display process is getting larger and larger, in order to ensure the transmission of all effective display data in a limited time, usually TCON
  • the IC will output two or more clock signals, for example, a clock signal to the left half of the display panel in the display device, and another clock signal to the right half.
  • EMI Electromagnetic Interference
  • TCON The clock signal output by the IC is spread-spectrum processed to disperse energy and meet EMI requirements.
  • the main purpose of the present application is to propose a timing control chip to improve the spreading processing effect on the clock signal, and to disperse the energy of the clock signal in the timing control chip to meet the requirements of electromagnetic interference.
  • the timing control chip proposed in this application includes at least two sets of mutually independent spread-spectrum circuits.
  • the spread-spectrum circuits are configured to convert the initial clock signal to a spread-spectrum clock signal, so that the timing control after the conversion
  • the sum of the signal strengths of all clock signals in the chip at any frequency is less than or equal to the preset strength threshold corresponding to the frequency.
  • a group of the spread spectrum circuits only generates one spread spectrum clock signal.
  • the frequency spreading circuit includes a frequency spreading signal generator and a voltage controlled oscillator, the frequency spreading signal generator is configured to generate a preset frequency spreading signal; the voltage controlled oscillator and the frequency spreading signal are generated Connected to the device, the voltage controlled oscillator is configured to convert the initial clock signal into a spread-spectrum clock signal corresponding to the preset spread-spectrum signal according to the preset spread-spectrum signal.
  • the spread spectrum signal generator includes at least one of a triangular spread spectrum signal generator, a sine spread spectrum signal generator, and a cosine spread spectrum signal generator.
  • the lowest frequency of at least one spread-spectrum clock signal is greater than or equal to the center frequency of the initial clock signal corresponding to the spread-spectrum clock signal.
  • the highest frequency of at least one spread-spectrum clock signal is less than or equal to the center frequency of the initial clock signal corresponding to the spread-spectrum clock signal.
  • the spread spectrum periods of at least two spread spectrum clock signals are not equal to each other.
  • an increase value of the tuning range of the spread spectrum clock signal relative to the tuning range of the initial clock signal is 0.5% to 3%.
  • the present application also proposes a display drive assembly, the display drive assembly includes a timing control chip, the timing control chip includes at least two sets of mutually independent frequency spreading circuits, the frequency spreading circuit is set to The clock signal is converted into a spread-spectrum clock signal, so that the sum of the signal strengths of all clock signals in the timing control chip at any frequency after the conversion is less than or equal to the preset intensity threshold corresponding to the frequency.
  • the present application further proposes a display device, the display device includes a display panel and a display drive component, the display drive component is connected to the display panel, the display drive component includes a timing control chip, the The timing control chip includes at least two sets of independent spread-spectrum circuits.
  • the spread-spectrum circuit is configured to convert the initial clock signal to a spread-spectrum clock signal, so that all the clock signals in the timing control chip at any frequency after conversion The sum of the signal strength is less than or equal to the preset strength threshold corresponding to the frequency.
  • the timing control chip includes at least two sets of mutually independent spread-spectrum circuits.
  • the spread-spectrum circuit is configured to convert the initial clock signal to a spread-spectrum clock signal, so that all clock signals in the sequence-controlled chip after conversion are at any frequency
  • the sum of the signal strengths on is less than or equal to the preset strength threshold corresponding to the frequency.
  • FIG. 1 is a schematic structural diagram of a timing control chip in an example
  • FIG. 2 is a frequency-time schematic diagram of the preset spread spectrum signal in FIG. 1;
  • FIG. 3 is a schematic diagram of the intensity-frequency of the initial clock signal and the spread spectrum clock signal in FIG. 1;
  • FIG. 4 is a schematic structural diagram of an embodiment of a timing control chip of the present application.
  • FIG. 5 is a schematic diagram of frequency-time when the preset spread spectrum signal is a triangular wave signal in another embodiment of the timing control chip of the present application;
  • FIG. 6 is a schematic diagram of the strength-frequency diagram of a spread-spectrum clock signal generated when the preset spread-spectrum signal is a triangular wave signal in another embodiment of the timing control chip of the present application;
  • FIG. 7 is a schematic diagram of frequency-time when a preset spread-spectrum signal is a sine wave signal or a cosine wave signal in another embodiment of the timing control chip of the present application;
  • FIG. 8 is a schematic diagram of the strength-frequency diagram of a spread-spectrum clock signal generated when the preset spread-spectrum signal is a sine wave signal or a cosine wave signal in another embodiment of the timing control chip of the present application;
  • FIG. 9 is a frequency-time schematic diagram of a first preset spread spectrum signal and a second preset spread spectrum signal in a specific example of a timing control chip of the present application;
  • FIG. 10 is a schematic diagram of the intensity-frequency of an original spread spectrum clock signal in an example and a new spread spectrum clock signal in a specific example of this application;
  • FIG. 11 is a schematic structural diagram of an embodiment of a display device according to this application.
  • first”, “second”, etc. are for descriptive purposes only, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the meaning of “and/or” appearing throughout the text includes three parallel plans. Taking “A and/or B” as an example, it includes plan A, or plan B, or plans that both A and B satisfy.
  • the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of those skilled in the art to realize. When the combination of technical solutions contradicts or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • TCON IC110' receives the display data from the front-end system, after internal data processing, then the initial clock signal CLK' is converted into the first spread-spectrum clock signal CLK1' and the second spread-spectrum clock signal CLK2' by the spread-spectrum circuit 111', and
  • the data driving chip (not shown in the figure) and the scan driving chip (not shown in the figure) output to the display device drive the display of images.
  • the first spread-spectrum clock signal CLK1' and the second spread-spectrum clock signal CLK2' are obtained by the common spread-spectrum circuit 111' converting the initial clock signal CLK', so usually the first spread-spectrum clock signal CLK1 'And the second spread spectrum clock signal CLK2' are completely consistent. As shown in FIG.
  • the frequency spreading circuit 111' includes a frequency spreading signal generator 111a' and a voltage controlled oscillator 111b', wherein the frequency spreading signal generator 111a' can generate a preset frequency spreading signal, and the voltage controlled oscillator 111b 'Connected to the spread spectrum signal generator 111a', and converts the initial clock signal CLK' into a first spread spectrum clock signal CLK1' and a second spread spectrum clock signal CLK2' according to a preset spread spectrum signal.
  • the spread-spectrum circuit 111' converts the initial clock signal CLK' into a first spread-spectrum clock signal CLK1' and a second spread-spectrum clock signal CLK2' according to the preset spread-spectrum signal shown in FIG.
  • the initial clock signal is converted into a spread-spectrum clock signal, where the dotted line in FIG. 3 represents the initial clock signal before conversion, and the solid line in FIG.
  • the first spread-spectrum clock signal CLK1' or the second spread-spectrum clock signal CLK2' is at any frequency
  • the signal strength of is less than the preset intensity threshold corresponding to the frequency, so when only the first spread-spectrum clock signal CLK1' or only the second spread-spectrum clock signal CLK2' is output, the EMI requirements can be met.
  • the first spread-spectrum clock signal CLK1' and the second spread-spectrum clock signal CLK2' are simultaneously output, then the first spread-spectrum clock signal at any frequency
  • the sum of the signal strength of CLK1' and the second spread spectrum clock signal CLK2' will be twice the signal strength when only the first spread spectrum clock signal CLK1' or the second spread spectrum clock signal CLK2' is output, especially at the center frequency FCON and its vicinity, TCON is likely to appear
  • the sum of the strengths of the clock signals in IC110' that is, the sum of the signal strengths of the first spread-spectrum clock signal CLK1' and the second spread-spectrum clock signal CLK2', is greater than the preset strength threshold, but cannot meet the EMI requirements.
  • the present application proposes a timing control chip, which independently sets at least two sets of spread-spectrum circuits to perform spread-spectrum processing on the initial clock signal to further disperse the signal energy to meet EMI requirements.
  • TCON IC110 includes at least two sets of independent spread-spectrum circuits.
  • the spread-spectrum circuit is configured to convert the initial clock signal to a spread-spectrum clock signal so that the converted TCON
  • the sum of the signal strengths of all clock signals in IC110 at any frequency is less than or equal to the preset strength threshold corresponding to the frequency.
  • TCON In IC110 multiple sets of independent spread-spectrum circuits can be set according to actual needs to convert the initial clock signal to the corresponding spread-spectrum clock signal to meet EMI requirements.
  • Frequency circuit 111 and second spread-spectrum circuit 112 The IC110 is used as an example to describe the technical solution of the present application in detail. For the TCON IC provided with more sets of spread-spectrum circuits, it will not be repeated here.
  • TCON IC110 receives the display data from the front-end system, after internal data processing, through the first frequency spreading circuit 111 and the second frequency spreading circuit 112, the initial clock signal CLK is converted into the first frequency spread clock signal CLK1 and the second frequency spread The clock signal CLK2 is also output to drive the display of the image.
  • the relative example TCONIC110' only includes a set of spread-spectrum circuits 111'.
  • the first spread-spectrum circuit 111 and the second spread-spectrum circuit 112 are set independently of each other, and each spread-spectrum circuit may have its own independent control architecture.
  • the spread-spectrum parameters thereby generating the first spread-spectrum clock signal CLK1 and the second spread-spectrum clock signal CLK2, respectively.
  • the type and parameters of the preset spread-spectrum signal based on the frequency range of the spread-spectrum clock signal obtained after spreading , Tuning range and spread spectrum period can be different.
  • different spreading clock signals can be obtained to adapt to various applications and expand TCONIC110
  • the frequency range of the output clock signal and it can avoid the superposition of the signal strength of the initial clock signal at or near the center frequency multiple times, effectively dispersing the TCON
  • the energy of the clock signal output by IC110 thereby improving the spread spectrum effect to meet EMI requirements.
  • a set of spread-spectrum circuits can generate only one spread-spectrum clock signal as shown in FIG.
  • TCON The specific setting method, combination method and the number of spread-spectrum clock signals generated by each set of spread-spectrum circuits in IC110 can be set according to actual needs. Several specific spread-spectrum circuits will be described in detail later.
  • TCON IC110 includes at least two sets of independent spread-spectrum circuits.
  • the spread-spectrum circuit is configured to convert the initial clock signal to a spread-spectrum clock signal so that the converted TCON The sum of the signal strengths of all clock signals in IC110 at any frequency is less than or equal to the preset strength threshold corresponding to the frequency.
  • the initial clock signal is spread-spectrum processed to output the corresponding spread-spectrum clock signal.
  • a set of spread spectrum circuits only generates a spread spectrum clock signal.
  • the first frequency spreading circuit 111 generates a first frequency spreading clock signal CLK1
  • the second frequency spreading circuit 112 generates a second frequency spreading clock signal CLK2.
  • the spread-spectrum circuit includes a spread-spectrum signal generator and a voltage-controlled oscillator, the spread-spectrum signal generator is set to generate a preset spread-spectrum signal; the voltage-controlled oscillator is connected to the spread-spectrum signal generator, and the voltage-controlled oscillator is set To convert the initial clock signal into a spread-spectrum clock signal corresponding to the preset spread-spectrum signal according to the preset spread-spectrum signal.
  • the voltage controlled oscillator is an oscillation circuit with a certain correspondence between the signal frequency and the signal voltage, including the inductance capacitor (LC) voltage controlled oscillator, the resistance capacitor (RC) voltage controlled oscillator and the crystal voltage controlled oscillator Waiting for the frequency modulation of the signal.
  • the first frequency spreading circuit 111 includes a connected first frequency spreading signal generator 111a and a first voltage controlled oscillator 111b
  • the second frequency spreading circuit 112 includes a connected second frequency spreading signal generator 112a and Second voltage controlled oscillator 112b.
  • the first spread-spectrum signal generator 111a is configured to generate a first preset spread-spectrum signal
  • the first voltage-controlled oscillator 111b is configured to convert the initial clock signal CLK to the first preset according to the first preset spread-spectrum signal
  • the first spread-spectrum clock signal CLK1 corresponding to the spread-spectrum signal that is, the initial clock signal CLK is frequency-modulated according to the first preset spread-spectrum signal to generate the first spread-spectrum clock signal CLK1; similarly, the second spread-spectrum signal occurs
  • the device 112a is configured to generate a second preset spread spectrum signal
  • the second voltage controlled oscillator 112b is set to convert the initial clock signal CLK into a second spread corresponding to the second preset spread spectrum signal according to the second preset spread spectrum signal Frequency clock signal CLK2, that is, the initial clock signal CLK is frequency-modulated according to the second preset spread spectrum signal to generate a second spread spectrum clock signal CLK2.
  • the spread-spectrum signal generator includes at least one of a triangular spread-spectrum signal generator, a sine spread-spectrum signal generator and a cosine spread-spectrum signal generator, and the combination is set according to actual needs.
  • the spread-spectrum clock signal generated in the case of a preset spread-spectrum signal in the form of a triangular wave signal and a preset spread-spectrum signal in the form of a sine-cosine wave signal will be analyzed in the following sections.
  • the spread spectrum signal generator is a triangular spread spectrum signal generator
  • the preset spread spectrum signal generated by it is a triangular wave signal as shown in FIG. 5, accordingly, the voltage controlled oscillator is based on The triangular wave signal frequency-modulates the initial clock signal to produce the spread-spectrum clock signal shown in FIG. 6. Since in the triangular wave signal, the change of the signal frequency with time is basically uniform, which is related to the slope of the line segment shown in FIG. 5, correspondingly, the intensity of the spread spectrum clock signal obtained by frequency modulation in each frequency band is also basically uniform, so The EMI effect of each frequency band is basically the same. Therefore, when the triangular wave signal is used as the preset spread spectrum signal, a better energy dispersion effect can be obtained.
  • the spread spectrum signal generator is a sine spread spectrum signal generator or a cosine spread spectrum signal generator
  • the generated spread spectrum signal is a sine wave signal or a cosine wave as shown in FIG. 7 Signal (where the determination of the sine wave signal and the cosine wave signal is related to the initial phase of the signal, but has little effect on the energy dispersion effect of the spread-spectrum clock signal discussed later, so for simplicity, it is described here in a unified manner)
  • the voltage-controlled oscillator modulates the initial clock signal according to the sine and cosine wave signals to generate the spread-spectrum clock signal shown in FIG. 8.
  • the signal strength of the generated spread-spectrum clock signal may have a sudden change with frequency, that is, in some frequency bands, the signal strength of the spread-spectrum clock signal is strong and may exceed
  • the intensity threshold is preset to fail to meet EMI requirements.
  • all triangular spread spectrum signal generators or all sine and cosine spread spectrum signal generators, or a combination of triangular spread spectrum signal generators and sine and cosine spread spectrum signal generators can be selected. Of course, other signal forms can also be selected.
  • Spread-spectrum signal generator frequency-modulate the initial clock signal to generate the corresponding spread-spectrum clock signal.
  • the minimum frequency of at least one spread-spectrum clock signal is greater than or equal to the center frequency of the initial clock signal corresponding to the spread-spectrum clock signal, that is, at least one spread-spectrum circuit only spreads the initial clock signal upward, spreads
  • the frequency range of the spread spectrum clock signal obtained after the frequency is above the center frequency of the initial clock signal; or, the highest frequency of at least one spread spectrum clock signal is less than or equal to the center frequency of the initial clock signal corresponding to the spread spectrum clock signal, or That is to say, at least one spread-spectrum circuit only spreads down the initial clock signal, and the frequency range of the spread-spectrum clock signal obtained after spreading is below the center frequency of the initial clock signal to expand the frequency of the final output clock signal in TCONIC110 Range to make the signal energy more dispersed.
  • a spread-spectrum circuit can also spread-spread and spread-spread the initial clock signal at the same time, and the spread-spectrum range of the spread-up and spread-down frequencies can be asymmetric, that is, the spread-spectrum clock signal obtained after spreading
  • the minimum frequency F1, the maximum frequency F2 and the center frequency F0 of the initial clock signal before spread spectrum satisfy F2-F0 ⁇ F0-F1.
  • the spreading periods of at least two spread-spectrum clock signals can also be unequal to each other to reduce the superposition of the center frequency of the initial clock signal and the signal strength in the vicinity thereof, thereby meeting EMI requirements.
  • the first preset spread spectrum signal generated by the first spread spectrum signal generator 111a is the spread spectrum period T1, the lowest frequency F1, and the highest frequency F0.
  • Triangular wave signal shown by the dotted line in FIG. 9
  • the second preset spread spectrum signal generated by the second spread spectrum signal generator 112a is a triangular wave signal with a spread spectrum period T2, a minimum frequency F0, and a maximum frequency F2 (see FIG. 9). Line).
  • the first voltage-controlled oscillator 111b converts the initial clock signal CLK into the first spread-spectrum clock signal CLK1 according to the first preset spread-spectrum signal, where the first spread-spectrum clock signal CLK1 spreads downward relative to the initial clock signal CLK Frequency, the frequency range is F1 ⁇ F0, and the spread spectrum period is T1;
  • the second voltage controlled oscillator 112b converts the initial clock signal CLK into the second spread spectrum clock signal CLK2 according to the second preset spread spectrum signal, where , The second spread-spectrum clock signal CLK2 is spread upward relative to the initial clock signal CLK, the frequency range is F0 ⁇ F2, the spread-spectrum period is T2, and T1 and T2 are not equal to each other, to avoid the first spread-spectrum clock signal CLK1 and The second spread-spectrum clock signal CLK2 produces an excessive signal superposition near the center frequency of the initial clock signal CLK.
  • the maximum frequency F2 is asymmetric with respect to F0, specifically
  • the energy of the spread-spectrum clock signal generated by the superposition of the signal CLK1' and the second spread-spectrum clock signal CLK2' will be more dispersed, and the concentration at the center frequency F0' or F0 is avoided, the maximum of the new spread-spectrum
  • the increase in the tuning range of the spread spectrum clock signal relative to the tuning range of the initial clock signal is 0.5% to 3%.
  • the tuning range of the clock signal refers to the difference between the maximum frequency and the minimum frequency of the clock signal.
  • the timing transmission is used to drive the display of the screen; when the tuning range of the clock signal is too small, it means that the energy of the spread-spectrum clock signal is relatively concentrated in the frequency domain, which may lead to failure to meet EMI requirements. Therefore, in this application, according to the experiment and calculation results, the increase of the tuning range of the optional spread spectrum clock signal relative to the tuning range of the initial clock signal is 0.5% ⁇ 3%, assuming that the minimum frequency of the spread spectrum clock signal is F1, the maximum frequency is F2, the minimum frequency of the initial clock signal is F1', the maximum frequency is F2', that is
  • the present application also proposes a display driving assembly.
  • the display driving assembly 100 includes a TCON IC 110, and the TCON
  • the TCON For the specific structure of the IC110, refer to the above embodiments, and no more details are given here.
  • the present application further proposes a display device.
  • the display device includes a display panel 200 and a display drive assembly 100.
  • the display drive assembly 100 is connected to the display panel 200.
  • the display driving assembly 100 includes TCON IC110, the specific structure of the TCON IC110 refers to the above embodiment, and no more details are given here.
  • the display driving assembly 100 further includes a data driving chip 120 and a scanning driving chip 130, TCON
  • the IC 110 outputs the spread-spectrum clock signal to the data driving chip 120 and the scanning driving chip 130 to drive the operation of the display panel 200, and realize normal display of the screen.

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Abstract

一种时序控制芯片（110）、显示驱动组件（100）和显示装置，其中，时序控制芯片（110）包括至少两组相互独立的展频电路（111，112），展频电路（111，112）设置为将初始时钟信号（CLK）转换为展频时钟信号（CLK1，CLK2），以使转换后时序控制芯片（110）中所有时钟信号（CLK1，CLK2）在任一频率上的信号强度之和小于或等于对应的预设强度阈值。

Description

时序控制芯片、显示驱动组件和显示装置
相关申请
本申请要求2018年12月5日，申请号为201811484655.5，申请名称为“时序控制芯片、显示驱动组件和显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，特别涉及一种时序控制芯片、显示驱动组件和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。随着生活水平的提高，大尺寸、高解析度、高帧频的显示装置越来越受欢迎，相应的，在显示装置中配备有适应于大尺寸、高解析度、高帧频显示的显示驱动组件，并由显示驱动组件中的时序控制芯片（Timer Control Register integrated circuit，TCON IC）输出时钟信号给显示驱动组件中的数据驱动芯片（Data Driver IC）和扫描驱动芯片（Gate Driver IC），实现图像的显示。由于显示过程中所涉及的数据越来越庞大，为了保证在有限的时间内实现全部有效的显示数据的传输，通常TCON IC会分别输出两个或两个以上的时钟信号，例如向显示装置中显示面板的左半部分输出一时钟信号，右半部分输出另一时钟信号。同时考虑到国家对电磁干扰（Electromagnetic Interference，EMI）有严格的限制，因此需要对TCON IC输出的时钟信号做展频处理，以分散能量，满足EMI的要求。然而，当对时钟信号做展频处理时，由于受到展频处理过程和显示数据的正常传输要求的限制，导致展频后EMI能量的分散十分有限，很容易出现展频效果不足而难以满足EMI要求的情形。
申请内容
本申请的主要目的是提出一种时序控制芯片，改善对时钟信号的展频处理效果，分散时序控制芯片中时钟信号的能量，以满足电磁干扰要求。
为实现上述目的，本申请提出的时序控制芯片，包括至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
可选地，一组所述展频电路仅产生一所述展频时钟信号。
可选地，所述展频电路包括展频信号发生器和压控振荡器，所述展频信号发生器设置为产生预设展频信号；所述压控振荡器与所述展频信号发生器相连，所述压控振荡器设置为根据所述预设展频信号将所述初始时钟信号转换为与所述预设展频信号相应的展频时钟信号。
可选地，所述展频信号发生器包括三角展频信号发生器、正弦展频信号发生器和余弦展频信号发生器中的至少一种。
可选地，至少一展频时钟信号的最低频率大于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
可选地，至少一展频时钟信号的最高频率小于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
可选地，至少两展频时钟信号的展频周期互不相等。
可选地，所述展频时钟信号的调谐范围相对所述初始时钟信号的调谐范围的增大值为0.5%~3%。
为实现上述目的，本申请还提出一种显示驱动组件，所述显示驱动组件包括时序控制芯片，所述时序控制芯片包括至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
为实现上述目的，本申请进一步提出一种显示装置，所述显示装置包括显示面板以及显示驱动组件，所述显示驱动组件与所述显示面板相连，所述显示驱动组件包括时序控制芯片，所述时序控制芯片包括至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
本申请技术方案中，时序控制芯片包括至少两组相互独立的展频电路，展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。通过设置至少两组相互独立的展频电路，对初始时钟信号分别进行展频处理，从而输出相应的展频时钟信号，一方面扩大了转换后所得的展频时钟信号的频率范围，另一方面也可以避免对应于初始时钟信号的中心频率及其附近的信号强度多次叠加，从而进一步分散了时序控制芯片中时钟信号的能量，有助于改善对时钟信号的展频处理效果，以满足电磁干扰要求。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为一范例中时序控制芯片的结构示意图；
图2为图1中预设展频信号的频率-时间示意图；
图3为图1中初始时钟信号和展频时钟信号的强度-频率示意图；
图4为本申请时序控制芯片一实施例的结构示意图；
图5为本申请时序控制芯片另一实施例中预设展频信号为三角波信号时的频率-时间示意图；
图6为本申请时序控制芯片另一实施例中预设展频信号为三角波信号时产生的展频时钟信号的强度-频率示意图；
图7为本申请时序控制芯片又一实施例中预设展频信号为正弦波信号或余弦波信号时的频率-时间示意图；
图8为本申请时序控制芯片又一实施例中预设展频信号为正弦波信号或余弦波信号时产生的展频时钟信号的强度-频率示意图；
图9为本申请时序控制芯片一具体示例中第一预设展频信号和第二预设展频信号的频率-时间示意图；
图10为一范例中原展频时钟信号和本申请一具体示例中新展频时钟信号的强度-频率示意图；
图11为本申请显示装置一实施例的结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为，包括三个并列的方案，以“A和/或B”为例，包括A方案，或B方案，或A和B同时满足的方案。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
在一范例中，如图1所示，TCON IC110’接收来自前端系统端的显示数据，经内部数据处理后，再经展频电路111’将初始时钟信号CLK’转换为第一展频时钟信号CLK1’和第二展频时钟信号CLK2’，并输出给显示装置的数据驱动芯片（图中未示出）和扫描驱动芯片（图中未示出），驱动图像的显示。其中，第一展频时钟信号CLK1’和第二展频时钟信号CLK2’都是由共用的展频电路111’转换初始时钟信号CLK’而得到的，因此通常情况下第一展频时钟信号CLK1’和第二展频时钟信号CLK2’是完全一致的。如图1所示，展频电路111’包括展频信号发生器111a’和压控振荡器111b’，其中，展频信号发生器111a’可以产生预设展频信号，而压控振荡器111b’与展频信号发生器111a’相连，根据预设展频信号将初始时钟信号CLK’转换为第一展频时钟信号CLK1’和第二展频时钟信号CLK2’。在一具体示例中，展频电路111’按照图2中所示的预设展频信号将初始时钟信号CLK’转换为第一展频时钟信号CLK1’和第二展频时钟信号CLK2’。其中，预设展频信号可以是三角波信号，其频率随时间以初始时钟信号的中心频率F0’为中心，在F1’~F2’之间对称循环变化，即F0’、F1’和F2’之间满足F2’-F0’=F0’-F1’，预设展频信号的周期为T1’。如图3所示，经过展频电路111’后，初始时钟信号转换为展频时钟信号，其中图3中虚线代表转换前的初始时钟信号，图3中实线代表转换后的展频时钟信号，原来集中在中心频率F0’及其附近的信号强度被分散到F1’~F2’的频率范围中，从而降低了时钟信号的最大强度，使原来在中心频率及其附近的超出预设强度阈值的信号强度下降，以满足EMI要求。当仅考虑第一展频时钟信号CLK1’或仅考虑第二展频时钟信号CLK2’时，根据图3可知，第一展频时钟信号CLK1’或第二展频时钟信号CLK2’在任一频率上的信号强度均小于该频率对应的预设强度阈值，因此仅输出第一展频时钟信号CLK1’或仅输出第二展频时钟信号CLK2’时，可以满足EMI要求。然而，在大尺寸、高解析度、高帧频显示装置中，若同时输出第一展频时钟信号CLK1’和第二展频时钟信号CLK2’，那么，在任一频率上第一展频时钟信号CLK1’和第二展频时钟信号CLK2’的信号强度之和将为仅输出第一展频时钟信号CLK1’或第二展频时钟信号CLK2’时的信号强度的两倍，特别是在中心频率F0’及其附近处，很可能出现TCON IC110’中的时钟信号强度之和，即第一展频时钟信号CLK1’和第二展频时钟信号CLK2’的信号强度之和大于预设强度阈值的情况，而不能满足EMI要求。
本申请提出一种时序控制芯片，通过独立设置至少两组展频电路，分别对初始时钟信号进行展频处理，以进一步分散信号能量，从而满足EMI要求。
在本申请的一实施例中，如图4所示，TCON IC110包括至少两组相互独立的展频电路，展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后TCON IC110中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
可以理解的是，在TCON IC110中可以根据实际需要设置多组独立的展频电路，将初始时钟信号转换为相应的展频时钟信号，从而满足EMI要求，而在后文中，将以图4中所示的包括第一展频电路111和第二展频电路112两组展频电路的TCON IC110为例，详细说明本申请的技术方案，对于设置有更多组展频电路的TCON IC，这里将不再赘述。如图4所示，TCON IC110接收来自前端系统端的显示数据，经内部数据处理后，分别经第一展频电路111和第二展频电路112，将初始时钟信号CLK转换为第一展频时钟信号CLK1和第二展频时钟信号CLK2并输出，以驱动图像的显示。其中，相对范例TCONIC110’仅包括一组展频电路111’的情形，本实施例中第一展频电路111和第二展频电路112相互独立设置，各个展频电路可以具有其独立的控制架构和展频参数，从而分别产生第一展频时钟信号CLK1和第二展频时钟信号CLK2。具体的，在第一展频电路111和第二展频电路112转换时钟信号的过程中，所依据的预设展频信号的种类及其参数，展频后所得的展频时钟信号的频率范围、调谐范围以及展频周期等的选择都可以是不同的。根据实际需要，通过设置相互独立的具有不同控制架构和展频参数的展频电路，实现多种展频方式的组合，可以得到不同的展频时钟信号，以适应多种应用场合，扩大了TCONIC110输出的时钟信号的频率范围，并且可以避免初始时钟信号的中心频率或其附近的信号强度多次叠加，有效分散了TCON IC110所输出的时钟信号的能量，从而改善展频效果，以满足EMI要求。当然，一组展频电路可以如图4中所示仅产生一个展频时钟信号；也可以在满足EMI要求的前提下由一组展频电路产生多个展频时钟信号，例如，第一展频电路同时产生第一时钟信号CLK1和第三时钟信号CLK3，第二展频电路产生第二时钟信号CLK2，从而尽可能减TCONIC中展频电路的组数，降低其成本。综上，TCON IC110中展频电路的具体设置方式、组合方式和每组展频电路所产生的展频时钟信号的数目等可以根据实际需求设置，后文中还将对几种具体的展频电路详细阐述。
在本实施例中，TCON IC110包括至少两组相互独立的展频电路，展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后TCON IC110中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。通过设置至少两组相互独立的展频电路，对初始时钟信号分别进行展频处理，从而输出相应的展频时钟信号，一方面扩大了转换后所得的展频时钟信号的频率范围，另一方面也可以避免对应于初始时钟信号的中心频率及其附近的信号强度多次叠加，从而进一步分散了时序控制芯片中时钟信号的能量，有助于改善对时钟信号的展频处理效果，以满足电磁干扰要求。
可选地，一组展频电路仅产生一展频时钟信号。如图4所示，第一展频电路111产生第一展频时钟信号CLK1，第二展频电路112产生第二展频时钟信号CLK2。在这种设置方式下，能够有效避免同一组展频电路中产生两个或两个以上完全一致的展频时钟信号，从而避免在部分频段处展频时钟信号相叠加而导致的能量不够分散的问题，有助于保障TCON IC110所输出的时钟信号满足EMI要求。
可选地，展频电路包括展频信号发生器和压控振荡器，展频信号发生器设置为产生预设展频信号；压控振荡器与展频信号发生器相连，压控振荡器设置为根据预设展频信号将初始时钟信号转换为与预设展频信号相应的展频时钟信号。
其中，压控振荡器是一种信号频率与信号电压之间存在一定对应关系的振荡电路，包括电感电容（LC）压控振荡器、电阻电容（RC）压控振荡器和晶体压控振荡器等，能够实现对信号的调频作用。如图4所示，第一展频电路111包括相连的第一展频信号发生器111a和第一压控振荡器111b，第二展频电路112包括相连的第二展频信号发生器112a和第二压控振荡器112b。其中，第一展频信号发生器111a设置为产生第一预设展频信号，第一压控振荡器111b设置为根据第一预设展频信号将初始时钟信号CLK转换为与第一预设展频信号相应的第一展频时钟信号CLK1，也就是根据第一预设展频信号对初始时钟信号CLK进行调频，以产生第一展频时钟信号CLK1；同理，第二展频信号发生器112a设置为产生第二预设展频信号，第二压控振荡器112b设置为根据第二预设展频信号将初始时钟信号CLK转换为与第二预设展频信号相应的第二展频时钟信号CLK2，也就是根据第二预设展频信号对初始时钟信号CLK进行调频，以产生第二展频时钟信号CLK2。
其中，第一预设展频信号和第二预设展频信号存在多种设置方式，可以是三角波信号、正弦波信号和余弦波信号中的至少一种，并可以根据实际需求进行组合。相应的，展频信号发生器包括三角展频信号发生器、正弦展频信号发生器和余弦展频信号发生器中的至少一种，并根据实际需求进行组合设置。为了简化起见，后文中将分别对三角波信号形式的预设展频信号和正余弦波信号形式的预设展频信号情形下，所产生的展频时钟信号进行分析。
在本申请的另一实施例中，展频信号发生器为三角展频信号发生器，其所产生的预设展频信号为如图5所示的三角波信号，相应的，压控振荡器根据三角波信号对初始时钟信号调频，产生图6中所示的展频时钟信号。由于在三角波信号中，信号频率随时间的变化基本是均匀的，与图5中所示的线段斜率有关，相应的，调频所得的展频时钟信号在每个频段的强度基本也是均匀的，因此每个频段的EMI效果也就基本一致，因此，采用三角波信号作为预设展频信号时，可以得到较好的能量分散效果。
在本申请的又一实施例中，展频信号发生器为正弦展频信号发生器或余弦展频信号发生器，其所产生的展频信号为如图7所示的正弦波信号或余弦波信号（其中，正弦波信号和余弦波信号的确定与信号的初始相位有关，而对后文中所讨论的展频时钟信号的能量分散效果的影响较小，故为了简便起见，这里进行统一描述），相应的，压控振荡器根据正余弦波信号对初始时钟信号调频，产生图8中所示的展频时钟信号。由于在正余弦波信号中，信号频率随时间的变化存在不均匀的地方，特别是在中心频率附近，信号频率随时间的变化比较剧烈，而在正余弦波信号的最大频率和最小频率附近，信号频率随时间的变化比较平缓，相应的，所产生的展频时钟信号中信号强度可能随频率存在突变，也就是说，在部分频段中，展频时钟信号的信号强度较强，可能会超出预设强度阈值而不能满足EMI要求。然而，考虑到正余弦波信号的产生往往相比三角波信号的产生更为方便，因此，在满足EMI要求的前提下，选用正余弦波信号作为预设展频信号，可以在一定程度上降低TCON IC110的设置成本。
在TCON IC110中，可以全部选用三角展频信号发生器、或全部选用正余弦展频信号发生器、或组合选用三角展频信号发生器和正余弦展频信号发生器，当然，也可以选用产生其他信号形式的展频信号发生器，对初始时钟信号进行调频，分别生成相应的展频时钟信号。可选地，至少一展频时钟信号的最低频率大于或等于与该展频时钟信号相应的初始时钟信号的中心频率，也就是说，至少一展频电路只对初始时钟信号向上展频，展频后所得的展频时钟信号的频率范围处于初始时钟信号的中心频率以上；或者，至少一展频时钟信号的最高频率小于或等于与该展频时钟信号相应的初始时钟信号的中心频率，也就是说，至少一展频电路只对初始时钟信号向下展频，展频后所得的展频时钟信号的频率范围处于初始时钟信号的中心频率以下，以扩TCONIC110中最终输出的时钟信号的频率范围，使信号能量更加分散。或者，一展频电路也可以同时对初始时钟信号向上展频和向下展频，且向上展频和向下展频的展频范围可以不对称，即展频后所得的展频时钟信号的最小频率F1、最大频率F2和展频前的初始时钟信号的中心频率F0之间满足F2-F0≠F0-F1。
当然，在TCON IC110中，至少两展频时钟信号的展频周期也可以互不相等，以减少初始时钟信号的中心频率及其附近的信号强度的叠加，从而满足EMI要求。
在本申请的一具体示例中，如图4和图9所示，第一展频信号发生器111a所产生的第一预设展频信号为展频周期T1、最低频率F1、最高频率F0的三角波信号（图9中虚线所示），第二展频信号发生器112a所产生的第二预设展频信号为展频周期T2、最低频率F0、最高频率F2的三角波信号（图9中实线所示）。相应的，第一压控振荡器111b根据第一预设展频信号将初始时钟信号CLK转换为第一展频时钟信号CLK1，其中，第一展频时钟信号CLK1相对初始时钟信号CLK向下展频，其频率范围为F1~F0，展频周期为T1；同理，第二压控振荡器112b根据第二预设展频信号将初始时钟信号CLK转换为第二展频时钟信号CLK2，其中，第二展频时钟信号CLK2相对初始时钟信号CLK向上展频，其频率范围为F0~F2，展频周期为T2，且T1和T2互不相等，以避免第一展频时钟信号CLK1和第二展频时钟信号CLK2在初始时钟信号CLK的中心频率附近产生过强的信号叠加。如图10所示，当本具体示例中初始时钟信号CLK的中心频率F0与范例中初始时钟信号CLK’的中心频率F0’相一致，且展频后所得的展频时钟信号的最小频率F1和最大频率F2关于F0不对称，具体为|F1|>|F2|，同时，第一展频时钟信号的展频周期T1大于第二展频时钟信号的展频周期T2，那么，新展频时钟信号（即本具体示例中第一展频时钟信号CLK1和第二展频时钟信号CLK2叠加后所产生的展频时钟信号）相对范例中的原展频时钟信号（即范例中第一展频时钟信号CLK1’和第二展频时钟信号CLK2’叠加后所产生的展频时钟信号）的能量将会更加分散，且避免了在中心频率F0’或F0处的集中，新展频时钟信号的最大信号强度相比原展频时钟信号的最大信号强度更低，能够更可靠地满足小于或等于预设强度阈值的要求，从而避免过强的电磁干扰。
可选的，在本申请的上述实施例中，展频时钟信号的调谐范围相对初始时钟信号的调谐范围的增大值为0.5%~3%。其中，时钟信号的调谐范围是指时钟信号的最大频率减最小频率的差值。当展频时钟信号的调谐范围过大时，意味着展频时钟信号相对初始时钟信号在频域上的改变较大，即时钟信号的频率发生了较大的改变，可能导致显示数据无法按照正常的时序传输以驱动画面的显示；当时钟信号的调谐范围过小时，意味着展频时钟信号的能量在频域上相对集中，而可能导致无法满足EMI要求。因此，在本申请中，根据实验和计算结果，可选的展频时钟信号的调谐范围相对初始时钟信号的调谐范围的增大值为0.5%~3%，假设展频时钟信号的最小频率为F1，最大频率为F2，初始时钟信号的最小频率为F1’，最大频率为F2’，即||F2-F1|-|F2’-F1’||/(|F2’-F1’|)的取值在0.5%~3%的范围内。
本申请还提出一种显示驱动组件，如图11所示，该显示驱动组件100包括TCON IC110，该TCON IC110的具体结构参照上述实施例，在此不再一一赘述。
本申请进一步提出一种显示装置，如图11所示，显示装置包括显示面板200以及显示驱动组件100，显示驱动组件100与显示面板200相连。该显示驱动组件100包括TCON IC110，该TCON IC110的具体结构参照上述实施例，在此不再一一赘述。其中，显示驱动组件100还包括数据驱动芯片120和扫描驱动芯片130，TCON IC110输出展频时钟信号至数据驱动芯片120和扫描驱动芯片130，以驱动显示面板200的运行，实现画面的正常显示。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种时序控制芯片，其中，所述时序控制芯片包括：
    至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
  2. 如权利要求1所述的时序控制芯片，其中，一组所述展频电路仅产生一所述展频时钟信号。
  3. 如权利要求1所述的时序控制芯片，其中，所述展频电路包括：
    展频信号发生器，所述展频信号发生器设置为产生预设展频信号；以及，
    压控振荡器，所述压控振荡器与所述展频信号发生器相连，所述压控振荡器设置为根据所述预设展频信号将所述初始时钟信号转换为与所述预设展频信号相应的展频时钟信号。
  4. 如权利要求3所述的时序控制芯片，其中，所述展频信号发生器包括三角展频信号发生器、正弦展频信号发生器和余弦展频信号发生器中的至少一种。
  5. 如权利要求1所述的时序控制芯片，其中，至少一展频时钟信号的最低频率大于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
  6. 如权利要求1所述的时序控制芯片，其中，至少一展频时钟信号的最高频率小于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
  7. 如权利要求1所述的时序控制芯片，其中，至少两展频时钟信号的展频周期互不相等。
  8. 如权利要求1所述的时序控制芯片，其中，所述展频时钟信号的调谐范围相对所述初始时钟信号的调谐范围的增大值为0.5%~3%。
  9. 一种显示驱动组件，其中，所述显示驱动组件包括时序控制芯片，所述时序控制芯片包括：
    至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
  10. 如权利要求9所述的显示驱动组件，其中，一组所述展频电路仅产生一所述展频时钟信号。
  11. 如权利要求9所述的显示驱动组件，其中，所述展频电路包括：
    展频信号发生器，所述展频信号发生器设置为产生预设展频信号；以及，
    压控振荡器，所述压控振荡器与所述展频信号发生器相连，所述压控振荡器设置为根据所述预设展频信号将所述初始时钟信号转换为与所述预设展频信号相应的展频时钟信号。
  12. 如权利要求11所述的显示驱动组件，其中，所述展频信号发生器包括三角展频信号发生器、正弦展频信号发生器和余弦展频信号发生器中的至少一种。
  13. 如权利要求9所述的显示驱动组件，其中，至少一展频时钟信号的最低频率大于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
  14. 如权利要求9所述的显示驱动组件，其中，至少一展频时钟信号的最高频率小于或等于与该展频时钟信号相应的初始时钟信号的中心频率。
  15. 如权利要求9所述的显示驱动组件，其中，至少两展频时钟信号的展频周期互不相等。
  16. 如权利要求9所述的显示驱动组件，其中，所述展频时钟信号的调谐范围相对所述初始时钟信号的调谐范围的增大值为0.5%~3%。
  17. 一种显示装置，其中，所述显示装置包括：
    显示面板；以及，
    显示驱动组件，所述显示驱动组件与所述显示面板相连，所述显示驱动组件包括时序控制芯片，所述时序控制芯片包括至少两组相互独立的展频电路，所述展频电路设置为将初始时钟信号转换为展频时钟信号，以使转换后所述时序控制芯片中所有时钟信号在任一频率上的信号强度之和小于或等于该频率对应的预设强度阈值。
  18. 如权利要求17所述的显示装置，其中，一组所述展频电路仅产生一所述展频时钟信号。
  19. 如权利要求17所述的显示装置，其中，所述展频电路包括：
    展频信号发生器，所述展频信号发生器设置为产生预设展频信号；以及，
    压控振荡器，所述压控振荡器与所述展频信号发生器相连，所述压控振荡器设置为根据所述预设展频信号将所述初始时钟信号转换为与所述预设展频信号相应的展频时钟信号。
  20. 如权利要求19所述的显示装置，其中，所述展频信号发生器包括三角展频信号发生器、正弦展频信号发生器和余弦展频信号发生器中的至少一种
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