WO2020112315A2 - Commande directe numérique sécurisée (sd) pour améliorer le débit avec une empreinte à mémoire réduite - Google Patents

Commande directe numérique sécurisée (sd) pour améliorer le débit avec une empreinte à mémoire réduite Download PDF

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Publication number
WO2020112315A2
WO2020112315A2 PCT/US2019/059913 US2019059913W WO2020112315A2 WO 2020112315 A2 WO2020112315 A2 WO 2020112315A2 US 2019059913 W US2019059913 W US 2019059913W WO 2020112315 A2 WO2020112315 A2 WO 2020112315A2
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Prior art keywords
client
host
bus
packet
metadata
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PCT/US2019/059913
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English (en)
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WO2020112315A3 (fr
Inventor
Kishalay Haldar
Chandan Pramod Attarde
Yogesh Garhewal
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Qualcomm Incorporated
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Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to CN201980078437.8A priority Critical patent/CN113168394A/zh
Priority to EP22150858.3A priority patent/EP4002137B1/fr
Priority to EP19835947.3A priority patent/EP3887963B1/fr
Publication of WO2020112315A2 publication Critical patent/WO2020112315A2/fr
Publication of WO2020112315A3 publication Critical patent/WO2020112315A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA

Definitions

  • the present disclosure generally relates to apparatuses incorporating integrated circuits (ICs). More specifically, aspects of the present disclosure relate to an unconventional use of secure digital (SD) direct commands for improving throughput with a reduced memory footprint.
  • SD secure digital
  • Communications links use different methods for controlling instruction flow of and data between interconnected devices. For example, one device may operate as a master of a communications link, while other devices operate as slaves on the communications link. In this master/slave configuration, the master device issues commands on the communications link that permit the slave devices to communicate. If a particular slave device does not receive an appropriate command, then the device does not transmit on the communications link. A single master device, therefore, controls the flow of commands and data on the communications link.
  • SDIO secure digital input/output
  • PC personal computer
  • SDIO host operates as the SDIO master and controls other SDIO slave devices connected to the SDIO host. Data flow is controlled and monitored by the SDIO host.
  • the SDIO protocol is entirely host/master driven. Slave devices operating according to the SDIO protocol cannot initiate any transfer of data because these slave devices are limited to raising an interrupt to the host/master. This lack of
  • SD secure digital
  • the method includes accessing, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command.
  • the method also includes reading a read packet over the data lines of the SD bus from the SD client with a second SD direct command.
  • the method further includes storing the read packet in a host buffer allocated according to the read metadata.
  • CMD command
  • CMD command
  • SD secure digital
  • the method includes pulling, during a packet transfer over data lines of the SD bus, write metadata from a host request queue, the write metadata including a request identification (ID) and a block count of a write data packet from an SD host.
  • the method also includes allocating, by an SD client, a client buffer according to the block count of the write data packet indicated by the write metadata.
  • the method further includes pushing response metadata into a host request queue (HRQ), the response metadata including at least the request ID.
  • HRQ host request queue
  • a apparatus configured to improve throughput of a secure digital (SD) bus.
  • the apparatus includes a memory and a processor(s) coupled to the memory.
  • the processor configured to access, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command.
  • the processor is also configured to read a read packet over the data lines of the SD bus from the SD client with a second SD direct command.
  • the processor is further configured to store the read packet in a host buffer allocated according to the read metadata.
  • a non-transitory computer-readable medium having program code recorded thereon for improving throughput of a secure digital (SD) bus is described.
  • the program code is executed by a processor.
  • the computer-readable medium includes program code to access, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command.
  • the computer-readable medium also includes program code to read a read packet over the data lines of the SD bus from the SD client with a second SD direct command.
  • the computer-readable medium further includes program code to store the read packet in a host buffer allocated according to the read metadata.
  • FIGURE 1 illustrates an example implementation of a system-on-a-chip (SOC), including a connectivity module, in accordance with certain aspects of the present disclosure.
  • SOC system-on-a-chip
  • FIGURE 2 is an example implementation illustrating signal pins for a secure digital (SD) host communicably coupled to SD slave devices in a host/slave SD input/output (SDIO) configuration, in accordance with aspects of the present disclosure.
  • SD secure digital
  • FIGURE 3 further illustrates the host/slave SDIO configuration of FIGURE 2, in accordance with aspects of the present disclosure.
  • FIGURE 4 is a flow diagram illustrating a method of improving receive path throughput over a secure digital (SD) bus interface, according to aspects of the present disclosure.
  • FIGURE 5 is a flow diagram illustrating a method of improving transmit path throughput over a secure digital (SD) bus, according to aspects of the present disclosure.
  • FIGURE 6 is a block diagram showing a wireless communications system in which a configuration of the disclosure may be advantageously employed.
  • SDIO secure digital input/output
  • PC personal computer
  • the SDIO protocol is entirely host/master driven. Slave devices operating according to the SDIO protocol cannot initiate data transfer on an SD bus
  • slave devices communicably coupling the slave devices and the host/master. Rather, these slave devices are limited to raising an interrupt to the host/master. This lack of initiation of data communications from the slave devices complicates optimal memory allocation by client device drivers and negatively affects data transfer throughput. It is, therefore, desirable to provide a system for permitting information exchange between slave devices and the SDIO host/master to improve throughput over the SD bus, while using a reduced memory footprint.
  • an SD direct command is used for communicating metadata between an SD master device and SD slave devices in parallel with data communications between the SD master device and an SD slave device.
  • This metadata may include data regarding upcoming transmit data between the SD master device and the SD slave device.
  • the metadata may also include data regarding upcoming read data between the SD master device and the SD slave device.
  • a stock SD host driver does not allow parallel issuance of direct commands over command and data lines of an SD bus, except for an ABORT command.
  • the stock SD Host driver is modified to support parallel SD direct commands over command and data lines of the SD bus.
  • FIGURE 1 illustrates an example implementation of a host system-on-a-chip (SOC) 100, which includes a connectivity block 110 configured to provide parallel secure digital (SD) direct commands over an SD bus, in accordance with aspects of the present disclosure.
  • the host SOC 100 includes processing blocks tailored to specific functions, such as a connectivity block 110.
  • the connectivity block 110 may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, Secure Digital (SD) connectivity, and the like.
  • 5G fifth generation
  • 4G LTE fourth generation long term evolution
  • Wi-Fi connectivity Wireless Fidelity
  • USB connectivity Wireless Fidelity
  • Bluetooth connectivity Secure Digital
  • the host SOC 100 includes various processing units that support multi-threaded operation.
  • the host SOC 100 includes a multi-core central processing unit (CPU) 102, a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit (NPU) 108.
  • the host SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, a navigation module 120, which may include a global positioning system, and a memory 118.
  • ISPs image signal processors
  • the multi-core CPU 102, the GPU 104, the DSP 106, the NPU 108, and the multi-media engine 112 support various functions such as video, audio, graphics, gaming, artificial networks, and the like.
  • Each processor core of the multi-core CPU 102 may be a reduced instruction set computing (RISC) machine, an advance RISC machine (ARM), a microprocessor, or some other type of processor.
  • RISC reduced instruction set computing
  • ARM advance RISC machine
  • the NPU 108 may be based on an ARM instruction set.
  • the instructions loaded into the multi-core CPU 102 may include program code to access, during a data transfer over data lines of a secure digital (SD) bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command.
  • the instructions loaded into the multi-core CPU 102 may also include program code to read a read packet over the data lines of the SD bus from the SD client with a second SD direct command.
  • the instructions loaded into the multi-core CPU 102 may include program code to store the read packet in a host buffer allocated according to the read metadata.
  • FIGURE 2 is an example implementation illustrating signal pins for a secure digital (SD) host communicably coupled to SD slave devices in a host/slave SD input/output (SDIO) configuration, in accordance with aspects of the present disclosure.
  • a host/master 200 may be the host SOC 100, or a block of the host SOC 100, such as the connectivity block 110 or other like block of the host SOC 100, including a secure digital (SD) controller/interface 210.
  • the host/master 200 includes the SD controller/interface 210, configured to communicate with client/slave devices 230 (230-1, ... , 230-N) over an SD bus 220.
  • the SD bus 220 is configured according to the SDIO protocol and carries a clock (CLK) signal, an SD command (CMD) signal, and a data signal (DAT[3:0]).
  • CLK clock
  • CMD SD command
  • DAT[3:0] data signal
  • the SDIO protocol is entirely driven by the host/master 200.
  • the client/slave devices 230 cannot initiate any data transfers. Instead, the client/slave devices 230 are limited to raising an interrupt to the host/master 200.
  • the host/master 200 uses SD direct commands for controlling data transfers as well as communications to/from the client/slave devices 230.
  • the host/master 200 uses a first SD direct command (e.g., command fifty-two (CMD52)) for performing byte reads and issuing abort commands.
  • the host/master 200 uses a second SD direct command (e.g., command fifty-three (CMD53)) for performing burst reads and writes from/to the client/slave devices 230.
  • the host/master 200 is generally configured to perform burst data transfers using the CMD53 command for performing both read and write operations.
  • a command header is communicated from the host/master 200 to one of the target client/slave devices 230 prior to data transfer.
  • the command header generally indicates a packet data size, and is immediately followed by the packet data.
  • a dataflow from the host/master 200 to the client/slave devices 230 may be referred to as a transmit direction.
  • a dataflow from the client/slave devices 230 to the host/master 200 may be referred to as a receive direction.
  • an ability of the client/slave devices 230 to accept incoming data from the host/master 200 is dependent on a dynamic memory scenario of a target of the client/slave devices 230.
  • a client device driver of the client/slave devices 230 is forced to use static memory allocation for the client/slave devices 230 to avoid data transfer throughput loss.
  • the buffer space of the client/slave devices 230 is specified to accommodate incoming packet data from the host/master 200.
  • the client/slave devices 230 are configured to allocate another (e.g., next) buffer space.
  • the next buffer space is allocated when a subsequent command header indicates a next packet from the host/master 200, while the previously allocated buffer space is being consumed by software.
  • the allocated buffer space is specified to accommodate a minimum of two maximum sized data packets for a given system (e.g., for a system with a block size of five hundred twelve (512) bytes, a single packet can be a maximum of two hundred fifty six (256) kilobytes (KB), thus specifying 512 kilobytes (KB) for buffer space allocation).
  • 256 two hundred fifty six
  • KB kilobytes
  • incoming packet is of the maximum size specified for buffer allocation.
  • maintaining a maximum buffer allocation size is a non-optimal usage of the limited memory resources available in a system. This non-optimal usage results in detrimental effects, including decreased system speed and increased system cost.
  • the client/slave devices 230 cannot communicate their current ability to accept the incoming transmit data.
  • the ability of the client/slave devices 230 to accept incoming transmit data depends on their dynamic memory scenario.
  • an alternative approach exists where, in current operation, after determining a packet data size from the command headers, the client/slave devices 230 attempt to delay the data transfer by asserting flow control until the predetermined amount of buffer space is allocated by the client device driver. This delay for allocating the buffer space leads to big gaps on the SD bus 220. The delay also decreases a transmit throughput on the SD bus 220.
  • the host/master 200 has multiple independent streams of different size data packets for the client/slave devices. Without any knowledge of the dynamic memory situation of the client/slave devices, the host/master 200 cannot intelligently select an efficient order of transmitting the independent data packet streams to the client/slave devices 230. That is, the static buffer management for configuring the buffer space of the client/slave devices 230 is simple but wasteful due to lack of advance information (e.g., metadata) from the host/master 200 and/or the client/slave devices 230.
  • advance information e.g., metadata
  • the host/master 200 In a receive direction (e.g., dataflow from client/slave device 230 to the host/master 200), the host/master 200 reads packet data from the client/slave devices 230.
  • the client/slave devices 230 may acquire data from another interface (e.g., a Bluetooth device and/or a wireless local area network (WLAN) through the connectivity block 110) for transfer to the host/master 200.
  • WLAN wireless local area network
  • the host/master 200 does not have an efficient means of determining a size of data being read from one of the client/slave devices 230.
  • the client/slave devices 230 interrupt the host/master 200 for read operations.
  • the host/master 200 performs several reads into the client/slave devices 230 to gather specified information before initiating the data read transactions over the SD bus 220 from one of the client/slave devices 230. These extra transactions over the SD bus 220 before performing the burst data transfer decrease read data throughput on the SD bus 220.
  • One option for reducing transmit path throughput loss is dynamic memory allocation by the client device drivers of the client/slave devices 230.
  • This solution offers a small memory footprint by using on demand memory allocation for the client/slave devices 230.
  • the client/slave devices 230 maintain a queue of descriptors and maintain a pool of small number of buffers, each of fixed small size (e.g., 512 bytes) for storing transmitted packet data from the host/master 200.
  • the client device driver for one of the target client/slave devices 230 allocates a target buffer from available memory. If the incoming data is larger than the buffer, the client driver keeps allocating buffers from the pool.
  • OOB out-of-buffer
  • the OOB condition alternatively persists until the client device driver adds additional buffers in the pool by allocating more memory from the system memory. Delay caused by the OOB descriptor scenario could be avoided if the client device driver was informed of buffer specifications for incoming packet data, rather than operating in a reactive mode.
  • Another option involves the client/slave devices 230 maintaining buffer state information for different memory channels (e.g., direct memory access (DMA) channels).
  • the client/slave devices 230 may communicate this buffer state information to the host/master 200 by issuing an interrupt to the host/master 200.
  • the host/master 200 may read metadata (e.g., the buffer state information) from the client/slave devices 230 using the second SDIO direct command (e.g., CMD53) over the data lines (e.g., DAT[3:0]).
  • the host/master 200 can then make intelligent scheduling decisions for packet transmission by knowing the buffer state information (e.g., metadata) of the client/slave devices 230.
  • This option introduces significant delay based on a write scheduling process for acquiring the limited amount of buffer state metadata over the data lines (e.g., DAT[3:0]) from the client/slave devices 230, performed before each data packet write.
  • This write scheduling process includes the interrupt from the client/slave devices 230 to hardware of the host/master 200 followed by interrupting of a host processor.
  • the host processor then initiates software thread activation for pushing a CMD53 read command to hardware of the host/master 200 and performing a CMD53 write operation to acquire the buffer state metadata.
  • This write scheduling process further includes providing the buffer state metadata to the device driver, making the write scheduling decision, and pushing a CMD53 write command to the hardware of the host/master 200 to transfer packet data to the client/slave devices 230.
  • the noted write scheduling process introduces significant delays. This results in an approximately three hundred (300) to three hundred and fifty (350) microsecond (ps) delay before data transfer on the SD bus 220 is initiated. For example, for a sixty-four (64) kilobyte (KB) packet, which takes a 0.7 milliseconds for complete data transfer on the SD bus 220, this additional 300-350 microseconds result in a significant (e.g., 35% to 50%) throughput loss. For a 256 KB packet, the throughput loss is reduced, but is not negligible (e.g., 13%).
  • the host processor then initiates software thread activation for pushing a CMD53 read command to hardware of the host/master 200 and performing a CMD53 read operation.
  • This metadata acquisition process further includes providing the read state metadata to the device driver, the device driver allocating a buffer, and pushing a CMD53 read command to the hardware of the host/master 200.
  • the noted metadata acquisition process introduces significant delays. This also results in an approximately three hundred (300) to three hundred and fifty (350) microsecond (ps) delay before data transfer on the SD bus 220 is initiated. For example, a sixty-four (64) kilobyte (KB) packet incurs a significant (e.g., 35% to 50%) throughput loss. This throughput loss is due to additional 300-350 microseconds required for metadata acquisition over and above the required 0.7 milliseconds for read data packet transfer over the SD bus 220. For a 256 KB packet, the throughput loss is also not negligible (e.g., 13%).
  • the memory footprint incurred by the metadata acquisition process is not an issue for the receive path (e.g., dataflow from the client/slave devices 230 to the host/master 200) because the host/master 200 learns the read data size before initiating a data transfer on the SD bus 220.
  • the SDIO protocol specifies a maximum data size for each packet (e.g., 256 KB per packet).
  • the metadata e.g., transmit path metadata and or receive path metadata
  • the metadata includes the number of blocks (e.g., 512 bytes/block) for data transfers (9 bits) and a direct memory access (DMA) channel number (2-4 bits).
  • DMA direct memory access
  • the SDIO protocol provides the CMD52 command to transact one byte between the host/master 200 and the client/slave devices 230 using only the command (CMD) pin of the SD bus 220.
  • the SDIO protocol conventionally prohibits the CMD52 command from being simultaneously active (e.g., performed in parallel) with the CMD53 command on the SD bus 220.
  • standard SD host drivers e.g., Linux standard SD host drivers
  • only an abort command is unblocked during an active CMD53 command. This abort command may be sent simultaneously with the CMD53 command for special handling.
  • an SD host driver of the host/master 200 is modified to enable activation of a CMD52 command simultaneously with an active CMD53 command on the SD bus 220, as desired.
  • This simultaneous activation of the CMD52 and CMD53 commands on the SD bus 220 conforms with the SD specification of the SDIO protocol.
  • the SD host driver of the host/master 200 is provided with two independent channels for communicating with the client/slave devices 230.
  • a meta-channel may refer to a CMD52 channel
  • a data-channel may refer to a CMD53 channel.
  • transferring one byte of metadata over the meta-channel by issuing a CMD52 command takes approximately one hundred and ninety-two (192) clock cycles to complete.
  • a CMD53 command for transferring one data block (e.g., 512 bytes) takes approximately one thousand, two hundred and thirty-two (1232) clock cycles on the SD bus 220 for end-to-end transfer.
  • the 1232 clock cycles provide sufficient time for successfully completing two CMD52 commands over the command (CMD) line and in parallel with the CMD53 data transfer command over the data lines (DAT[3:0]) of the SD bus 220.
  • the two CMD52 commands enable a meta-channel for communicating between the host/master 200 and the client/slave devices 230 to enable efficient use of the data-channel of the SD bus 220, for example, as shown in FIGURE 3.
  • FIGURE 3 shows a host/slave secure digital (SD) input/output (SDIO) configuration 300, further illustrating the host/slave SDIO configuration of FIGURE 2, in accordance with aspects of the present disclosure.
  • SDIO client interface 330 includes a host request queue (HRQ) 340 and a client request queue (CRQ) 350.
  • the SDIO client interface 330 also includes a first register space
  • SD host hardware 310 may access the Function-1 Register Space 320 and client hardware 370 (e.g., Local Host processor) may access the AHB Register Space 360.
  • client hardware 370 e.g., Local Host processor
  • the host request queue 340 (HRQ) and the client request queue 350 (CRQ) provide a medium for exchanging metadata between the SD host hardware 310 and the client hardware 370.
  • the host/slave SDIO configuration 300 may operate to perform a host to client transfer (e.g., a transmit path dataflow) as follows.
  • the SD host hardware 310 e.g., the host/master 200
  • the client hardware 370 e.g., client/slave devices 230
  • the SD host hardware 310 pushes a two-byte entry onto the host request queue 340 (e.g., HRQ Push).
  • the SD host hardware 310 pushes the two- byte entry onto the host request queue 340 by issuing two CMD52 commands on the command (CMD) pin of, for example, the SD bus 220 of FIGURE 2.
  • CMD command
  • This two-byte entry of metadata may include the block count (13 bits) and a request identification (ID) that is returned as response metadata from the client hardware 370 in response to the second CMD52.
  • the HRQ Push triggers an interrupt (e.g., Request Interrupt) to an interrupt request queue (IRQ) pin of the client hardware 370.
  • IRQ interrupt request queue
  • a client device driver (not shown) allocates a specified amount of requested buffer space according to the block count. Once allocated, the client device driver pushes response metadata in the client request queue 350 (e.g., CRQ TX Push).
  • the response metadata may include the request ID (4 bits) and a direct memory access (DMA) channel (e.g., 2 bits, assuming 4 DMA channels).
  • DMA direct memory access
  • the CRQ TX Push triggers an in-band interrupt sent to the SD host hardware 310. This in-band interrupt of the SD host hardware 310 does not affect any current data transfers on the data pins (e.g., DAT[3:0]) of the SD bus 220.
  • an SDIO interrupt is issued on a data pin (e.g., DAT[1]) of the SD host hardware 310, without affecting the current data transfer on the SD bus 220.
  • the SD host hardware 310 pulls (e.g. CRQ Pull) the response metadata from the client request queue 350 via a CMD52 command.
  • the SD host hardware 310 determines the client device driver has provisioned a specified buffer size as well as the DMA channel to be used.
  • the SD host hardware 310 awaits completion of the current data transfer over the SD bus 220.
  • the SD host hardware 310 triggers a packet write on the data pins (e.g., DAT[3:0]) of the SD bus 220 using a CMD53 command.
  • the end result is back-to-back packet data transfers on the data pins (e.g., DAT[3:0]) of the SD bus 220.
  • the back-to-back data transfers result in near bus level throughput at the device driver level.
  • the host/slave SDIO configuration 300 may operate to perform a client to host transfer (e.g., a receive path dataflow) as follows.
  • client hardware 370 e.g., client/slave devices 230
  • the client hardware 370 pushes a two-byte entry of read metadata onto the client request queue 350 (e.g., CRQ RX Push).
  • the client hardware 370 pushes the two-byte entry of read metadata onto the client request queue 350 to notify the SD host hardware 310 of the read data available from the client hardware 370.
  • This two-byte entry of read metadata may include the block count (13 bits) and a DMA channel number (2 bits).
  • An SDIO interrupt is issued on a data pin (e.g., DAT[1]) of the SD host hardware 310, without affecting the current data transfer on the SD bus 220.
  • the SD host hardware 310 pulls an entry (e.g. CRQ Pull) from the client request queue 350 via two CMD52 commands.
  • the SD host hardware 310 determines the client hardware 370 has a read packet for the SD host hardware 310 to pull.
  • an SD host driver of the SD host hardware 310 allocates a host buffer (based on the block count) in a memory space of the SD host hardware 310 and awaits completion of the current data transfer over the SD bus 220.
  • the SD host hardware 310 triggers a packet read on the data pins (e.g., DAT[3:0]) of the SD bus 220 using a CMD53 command to pull the read packet from the client hardware 370.
  • the end result is also back-to-back packet data transfers on the data pins (e.g., DAT[3:0]) of the SD bus 220.
  • the back-to-back data transfers also result in near bus level throughput at the device driver level.
  • FIGURE 4 is a flow diagram illustrating a method of improving receive path throughput over a secure digital (SD) bus interface, according to aspects of the present disclosure.
  • a method 400 begins at block 402, in which read metadata is accessed over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command during a data transfer over data lines of the SD bus.
  • CMD command
  • the SD host hardware 310 pulls an entry (e.g. CRQ Pull) from the client request queue 350 via a CMD52 command to retrieve read metadata from the client request queue 350.
  • pulling of the read metadata from the client request queue 350 is triggered by an SDIO interrupt issued on a data pin (e.g., DAT[1]) of the SD host hardware 310. This interrupt does not affect the current data transfer on the SD bus 220.
  • a host buffer is allocated in host memory, in which the host buffer has a size corresponding to buffer size information in the read metadata.
  • a read packet is read over the data lines of the SD bus from the SD client with a second SD direct command.
  • FIGURE 3 illustrates the SD host hardware 310 performing a packet read on the data pins (e.g., DAT[3:0]) of the SD bus 220 using a CMD53 command to pull the read packet from the client hardware 370.
  • This process is completed at block 408, when the read packet is stored in the host buffer allocated according to the read metadata.
  • the SD host hardware 310 stores the read packet in a host buffer allocated according to the read metadata.
  • FIGURE 5 is a flow diagram illustrating a method of improving transmit path throughput over a secure digital (SD) bus, according to aspects of the disclosure.
  • a method 500 begins at block 502, in which write metadata is pulled from a host request queue (HRQ) by an SD client during a packet transfer over data lines of the SD bus.
  • HRQ host request queue
  • the write metadata includes a request identification (ID) and a block count of a write data packet from an SD host. For example, as shown in FIGURE 3, when the SD host hardware 310 has a write packet to send the client hardware 370, the SD host hardware 310 pushes a two-byte entry onto the host request queue 340 (e.g., HRQ Push) to communicate the write metadata.
  • ID a request identification
  • block count a block count of a write data packet from an SD host.
  • an SD client allocates a client buffer according to the block count of the write data packet indicated by the write metadata.
  • an HRQ Push triggers an interrupt (e.g., Request Interrupt) to an interrupt request queue (IRQ) pin of the client hardware 370.
  • a client device driver allocates a specified amount of requested buffer space according to the block count.
  • the SD host writes the write data packet to the SD client over the SD bus.
  • response metadata is pushed into a client request queue (CRQ).
  • the response metadata includes at least the request ID.
  • the client device driver pushes response metadata in the client request queue 350 (e.g., CRQ TX Push).
  • FIGURE 6 is a block diagram showing an exemplary wireless communications system 600 in which a configuration of the disclosure may be advantageously employed.
  • FIGURE 6 shows three remote units 620, 630, and 650 and two base stations 640.
  • Remote units 620, 630, and 650 include IC devices 625A, 625B, and 625C, which include the disclosed SD bus interface. It will be recognized that any device containing an IC may also include the disclosed SD bus interface, including the base stations, switching devices, and network equipment.
  • FIGURE 6 shows forward link signals 680 from the base station 640 to the remote units 620, 630, and 650, and reverse link signals 690 from the remote units 620, 630, and 650 to base stations 640.
  • a remote unit 620 is shown as a mobile telephone
  • a remote unit 630 is shown as a portable computer
  • a remote unit 650 is shown as a fixed location remote unit in a wireless local loop system.
  • the remote units may be a mobile phone, a hand-held personal communications systems (PCS) unit, a portable data unit such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • PCS personal communications systems
  • a remote unit including the low power memory sub-system may be integrated within a vehicle control system, a server computing system or other like system specifying critical data integrity.
  • FIGURE 6 illustrates IC devices 625 A, 625B, and 625C, which include the disclosed SD bus interface, the disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in any device, which includes the SD bus interface.
  • the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the described functions. Any machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein.
  • software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit.
  • memory refers to any type of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to any particular type of memory or number of memories, or type of media upon which memory is stored.
  • the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium.
  • Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program.
  • Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer.
  • Such computer- readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • Disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD) and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
  • instructions and/or data may be provided as signals on transmission media included in a communications apparatus.
  • a communications apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general- purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a user terminal.
  • the processor and the storage medium may reside as discrete components in a user terminal.
  • the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communications media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a general-purpose or special- purpose computer.
  • such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specified program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • Disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD) and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer- readable media.
  • “at least one of: a, b, or c” is intended to cover: a; b; c; a and b; a and c; b and c; and a, b, and c.
  • All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims.
  • nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. ⁇ 112, sixth paragraph, unless the element is expressly recited using the phrase“means for” or, in the case of a method claim, the element is recited using the phrase“a step for.”

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé d'amélioration du débit d'un bus numérique sécurisé (SD). Le procédé consiste à accéder, pendant un transfert de données sur des lignes de données du bus SD, à lire des métadonnées sur une ligne de commande (CMD) du bus SD entre un hôte SD et un client SD avec une première commande directe SD. Le procédé comprend également la lecture d'un paquet lu sur les lignes de données du bus SD À partir du client SD avec une seconde commande directe SD. Le procédé consiste en outre à mémoriser le paquet lu dans un tampon hôte attribué en fonction des métadonnées lues.
PCT/US2019/059913 2018-11-29 2019-11-05 Commande directe numérique sécurisée (sd) pour améliorer le débit avec une empreinte à mémoire réduite WO2020112315A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201980078437.8A CN113168394A (zh) 2018-11-29 2019-11-05 用于利用减少的存储器占用来提高吞吐量的安全数字(sd)直接命令
EP22150858.3A EP4002137B1 (fr) 2018-11-29 2019-11-05 Commande directe numérique sécurisée (sd) pour améliorer le débit avec une empreinte à mémoire réduite
EP19835947.3A EP3887963B1 (fr) 2018-11-29 2019-11-05 Commande directe numérique sécurisée (sd) pour améliorer le débit avec une empreinte à mémoire réduite

Applications Claiming Priority (2)

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US16/204,969 US10467175B1 (en) 2018-11-29 2018-11-29 Secure digital (SD) direct command for improving throughput with a reduced memory footprint
US16/204,969 2018-11-29

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WO2020112315A2 true WO2020112315A2 (fr) 2020-06-04
WO2020112315A3 WO2020112315A3 (fr) 2020-07-23

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Publication number Publication date
EP3887963A2 (fr) 2021-10-06
CN113168394A (zh) 2021-07-23
EP3887963B1 (fr) 2023-07-19
WO2020112315A3 (fr) 2020-07-23
EP4002137B1 (fr) 2024-04-24
EP4002137A1 (fr) 2022-05-25
US10467175B1 (en) 2019-11-05

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