WO2020106214A1 - Semiconductor package and method of forming the same - Google Patents

Semiconductor package and method of forming the same

Info

Publication number
WO2020106214A1
WO2020106214A1 PCT/SG2019/050554 SG2019050554W WO2020106214A1 WO 2020106214 A1 WO2020106214 A1 WO 2020106214A1 SG 2019050554 W SG2019050554 W SG 2019050554W WO 2020106214 A1 WO2020106214 A1 WO 2020106214A1
Authority
WO
WIPO (PCT)
Prior art keywords
metallization layer
layer
magnetic stack
semiconductor package
carrier
Prior art date
Application number
PCT/SG2019/050554
Other languages
French (fr)
Inventor
Ravinder Pal Singh
Muthukumaraswamy Annamalai Arasu
King Jien Chui
Raju SALAHUDDIN
Original Assignee
Agency For Science, Technology And Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency For Science, Technology And Research filed Critical Agency For Science, Technology And Research
Publication of WO2020106214A1 publication Critical patent/WO2020106214A1/en

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Definitions

  • a magnetic layer has been used to improve the inductance and for reducing the number of turns for the given inductance.
  • a toroidal inductor in a post CMOS process is shown in FIG. 2. It uses a cobalt- zirconium-tantalite (CZT) based magnetic layer sandwiched between two copper layers.
  • CZT cobalt- zirconium-tantalite
  • Such an inductor is implemented on single wafer using 5pm thick copper (Cu) coils for redistribution layer (RDL) in BEOL process.
  • Cu 5pm thick copper
  • RDL redistribution layer
  • the reported inductor has limitations in achieving high quality factor (Q) with the best quality factor reported to be less than 10. This is due to the limited copper thickness which can be achieved in such a process.
  • the conventional inductor designs are either implemented without magnetic layer, which results in a smaller inductor density, or are implemented using magnetic core and would suffer from limitations in the thickness of metal which can be processed to realize the inductor.
  • Thicker metal layers are needed to improve the quality of the inductors; however, processing the thick metal twice on a same substrate has challenges of wafer warpage, de-lamination, etc. and hence is avoided for reliable integration.
  • Various embodiments may relate to a structure that make use of magnetic core for better inductor density and which uses a split structure which gives extra design freedom to increase the metal thickness.
  • Thicker metal traces may result in smaller dc- resistance in the inductor thereby improving the quality factor of the inductor.
  • the inductor includes two metal layers and a magnetic layer.
  • the dc-resistance of such an inductor may depend on the thickness of these metal or RDL layers on the inductor wafer/ substrate.
  • the dc-resistance may be reduced by making these metal lines thicker.
  • the thickness of the metal/RDL lines is limited, e.g. cannot be more than 20 /zm.
  • the stress induced during the processing of first thick metal results in wafer warpage. It may also result in de lamination or peeling effects, which inhibits or increases the difficulties of subsequent processing to complete the inductor structure.
  • the inductor can be realized using thinner copper layers, e.g. using the back end of the line in the CMOS process.
  • the structure suffers from high dc-resistance; thereby resulting in high ohmic loss and poor conversion efficiency in end applications.
  • Various embodiments may relate to an approach which improves the dc-resistance of the inductor by overcoming the limitations of copper thickness.
  • Various embodiments may relate to a structure which is fabricated using existing assembly flow, realizes thick metal with low dc-resistance, and improves the overall quality factor (Q) of the inductor.
  • FIG. 4 is a general illustration of a semiconductor package 400 according to various embodiments.
  • the semiconductor package 400 may include a carrier or carrier wafer 402 including a redistribution layer including a first metallization layer.
  • the semiconductor package 400 may further include a chip structure 404 (e.g. CMOS chip after BEOL) bonded to the carrier or carrier wafer 402.
  • the chip structure 404 may include a second metallization layer.
  • the semiconductor package 400 may further include a magnetic stack 406 between the first metallization layer and the second metallization layer.
  • the magnetic stack 406, the first metallization layer and the second metallization layer may form an inductor.
  • the package 400 may include an inductor having one part formed as part of the carrier 402, and another part formed as part of the chip structure 404.
  • the carrier 402 may include a first metallization of the inductor, while the chip structure 404 may include a second metallization of the inductor.
  • the magnetic stack 406 of the inductor may be part of the carrier 402 and/or part of the molded chip structure 404.
  • the chip structure 402 may include a semiconductor chip, and a redistribution layer in contact with the semiconductor chip.
  • the redistribution layer of the chip structure 402 may include the second metallization.
  • the chip structure 402 may be a molded chip structure further including an encapsulation layer in contact with the semiconductor chip.
  • the encapsulation layer may include a suitable mold compound.
  • the magnetic stack 406 may include one or more magnetic layers.
  • the magnetic stack 406 may be a laminated magnetic stack.
  • the magnetic stack 406 may include or consist of a single magnetic layer.
  • the magnetic layer or layers may include a magnetic material such as nickel-ferrite (NiFe) or cobalt-zirconium-tantalite (CZT).
  • the magnetic layer or layers may include any other suitable magnetic material.
  • the carrier wafer or carrier 402 may include the magnetic stack 406.
  • the redistribution layer of the carrier wafer or carrier 402 may include the magnetic stack.
  • the chip structure 404 may include the magnetic stack 406.
  • the redistribution layer of the chip structure 404 may include the magnetic stack.
  • the carrier wafer or carrier 402 e.g. the redistribution layer of the carrier wafer or carrier 402, may include a first portion of the magnetic stack 406.
  • the chip structure, the redistribution layer of the carrier wafer or carrier 402 may include a second portion of the magnetic stack 406.
  • the first metallization layer may be thicker than the second metallization layer.
  • the first metallization layer may have a thickness of any value more than 10 mhi
  • the second metallization layer may have a thickness of any value less than 10 mih, e.g. 5 mhi or 7 mih.
  • the second metallization layer may be thicker than the first metallization layer.
  • the second metallization layer may have a thickness of any value more than 10 mhi, while the first metallization layer may have a thickness of any value less than 10 mih, e.g. 5 mhi or 7 mih.
  • the first metallization layer may have a thickness of any value more than 10 mhi.
  • the second metallization layer may have a thickness of any value more than 10 mih.
  • the first metallization layer and/or the second metallization layer may include a suitable metal such as copper, aluminum, gold, tungsten, titanium, silver, or tin.
  • the first metallization layer and/or the second metallization layer may include a suitable alloy, such as an alloy of copper, aluminum, gold, tungsten, titanium, silver, or tin.
  • the semiconductor package 400 may include a plurality of first metal vias.
  • the semiconductor package 400 may also include a plurality of second metal vias.
  • the plurality of first metal vias and the plurality of second metal vias may connect the first metallization layer and the second metallization layer so that the magnetic stack 406 is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
  • the semiconductor package 400 may include a plurality of first interconnects and a plurality of second interconnects.
  • the plurality of first interconnects and the plurality of second interconnects may connect the first metallization layer and the second metallization layer so that the magnetic stack 406 is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first interconnects, and the plurality of second interconnects.
  • a first interconnect and a second interconnects may each include a bump and an under-bump metallization.
  • FIG. 5 is a general illustration of a method of forming a semiconductor package according to various embodiments.
  • the method may include, in 502, forming a carrier (or carrier wafer) by forming a redistribution layer including a first metallization layer.
  • the method may also include, in 504, forming or providing a chip structure including a second metallization layer.
  • the method may further include, in 506, forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer when the carrier (or carrier wafer) and the chip structure are bonded to each other.
  • the magnetic stack, the first metallization layer and the second metallization layer may form an inductor.
  • the semiconductor package may be formed such that part of the inductor is formed in the carrier wafer or carrier, and part of the inductor is formed in the chip structure.
  • the redistribution layer of the carrier or carrier wafer may be formed on or over a substrate.
  • the method may include forming the redistribution layer on or over a substrate.
  • the redistribution layer of the carrier or carrier wafer may include the first metallization layer.
  • the method may also include providing or forming a chip structure including a semiconductor chip and a redistribution layer in contact with the semiconductor chip.
  • the redistribution layer of the chip structure may include the second metallization layer.
  • the magnetic stack may include one or more magnetic layers.
  • the magnetic stack may be a laminated magnetic stack.
  • the magnetic stack may include or consist of a single magnetic layer.
  • the carrier wafer or carrier may include the magnetic stack.
  • the chip structure may include the magnetic stack.
  • the carrier wafer or carrier may include a first portion of the magnetic stack.
  • the chip structure may include a second portion of the magnetic stack.
  • the first metallization layer may be thicker than the second metallization layer.
  • the first metallization layer may have a thickness of any value more than 10 mih.
  • the second metallization layer may have a thickness of any value less than 10 / m.
  • the second metallization layer may be thicker than the first metallization layer.
  • the second metallization layer may have a thickness of any value more than 10 mth.
  • the first metallization layer may have a thickness of any value less than 10 /nn.
  • the first metallization layer may have a thickness of any value more than 10 mth.
  • the second metallization layer may have a thickness of any value more than 10 mth.
  • the method may include forming a plurality of first metal vias and a plurality of second metal vias connecting the first metallization layer and the second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
  • the method may include forming a plurality of first interconnects and a plurality of second interconnects connecting the first metallization layer and the second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first interconnects, and the plurality of second interconnects.
  • a first interconnect and a second interconnects may each include a bump and an under-bump metallization.
  • Various embodiments may relate to wafer-to-wafer (W2W) processing, chip-to-wafer (C2W) processing, or chip-to-chip (C2C) processing.
  • W2W wafer-to-wafer
  • C2W chip-to-wafer
  • C2C chip-to-chip
  • the carrier may be a chip or a wafer.
  • the chip structure may include a semiconductor chip and a redistribution layer.
  • the chip structure may be a part of a wafer.
  • FIG. 6 is a schematic of an inductor included in a semiconductor package according to various embodiments.
  • the first metallization or metal layer 608 may be formed or arranged in the carrier (inductor wafer or substrate), while the second metallization or metal layer 610 may be formed or arranged in the molded chip structure (CMOS chip (after BEOL)).
  • the magnetic stack or layer may be formed or arranged in carrier or the molded chip structure.
  • FIG. 7A is a schematic of a semiconductor package 700a according to various embodiments.
  • the semiconductor package 700a may include a carrier.
  • the carrier may include a redistribution layer 702 including a first metallization layer 708.
  • the redistribution layer 702 may provide fan-out connections.
  • the redistribution layer 702 may further include one or more additional metallization layers.
  • the redistribution layer 702 may also include one or more dielectric layers supporting the metallization layers. Each of the dielectric layers may be in contact with a metallization layer.
  • the semiconductor package 700a may further include a molded chip structure 704 bonded to the carrier, i.e. the redistribution layer 702.
  • the molded chip structure 704 may include a semiconductor chip 704a, i.e. an application specific integrated circuit (ASIC) chip such as a PMIC chip, including a second metallization layer 710.
  • the semiconductor chip 704a may include a further redistribution layer 712 including the second metallization layer 710.
  • the molded chip structure 704 may additionally include an encapsulation layer 704b in contact with the semiconductor chip 704a.
  • the semiconductor package 700 i.e. the redistribution layer 712 of the molded chip structure 704, may further include a magnetic stack 706 between the first metallization layer 708 and the second metallization layer 710.
  • the magnetic stack 706, the first metallization layer 708, and the second metallization layer 710 may form an inductor.
  • the molded chip structure 704 may be formed by bonding the semiconductor chip 704a to the carrier, followed by depositing a mold compound to form the encapsulation layer 704b.
  • the redistribution layer 702 of the carrier may include electrically conductive pads 714a, external contact pads 714b, and one or more interconnects 714c electrically connecting the conductive pads 714a and the external contact pads 714b.
  • the carrier wafer may further include solder bumps 716 electrically connected to the external contact pads 714b.
  • the solder bumps 716 may form a ball grid array (BGA).
  • FIG. 7B is a schematic of a semiconductor package 700b according to various other embodiments.
  • the magnetic stack 706 may be part of the carrier 702 together with metallization layer 708.
  • the metallization layer 710 may still be part of the molded chip structure 704.
  • FIG. 7B also shows that the electrically conductive pads 718a may be included in the redistribution layer 702 of the carrier. Bumps 720a may connect the electrically conductive pads 718a with the metallization layer 710. The electrically conductive pads 718a may also be in electrical connection with the metallization layer 708.
  • the package 700b may be similar to the package 700a shown in FIG. 7A except for the arrangement of the magnetic stack 706 and the electrically conductive pads 718a.
  • the metallization layers 708, 710 may not be processed in the same wafer twice, thereby reducing the stress on the wafers and providing ease of wafer processing.
  • the use of the metal layers may lower the overall dc-resistance, thereby improving the quality factor (Q) of the inductor.
  • FIG. 7C is a schematic of a semiconductor package 700c according to yet various other embodiments.
  • FIG. 7C shows that the metallization layer 710 may be thicker than the metallization layer 708.
  • the magnetic stack 706 may be included in the molded chip structure 704 with the metallization layer 710, while the metallization layer 708 may be included in the carrier.
  • the package 700c may be similar to the package 700a shown in FIG. 7A except for the relative thicknesses of the metallization layers 708, 710.
  • FIG. 7F is a schematic of a semiconductor package 700f according to yet various other embodiments.
  • FIG. 7F shows that the metallization layers 708, 710 may be substantially of equal thicknesses.
  • the magnetic stack 706 may be included in the carrier 702 with the metallization layer 708, while the metallization layer 710 may be included in the molded chip structure 704.
  • the package 700f may be similar to the package 700b shown in FIG. 7B except for the relative thicknesses of the metallization layers 708, 710.
  • FIG. 7G is a schematic of a semiconductor package 700g according to yet various other embodiments.
  • FIG. 7G discloses a first magnetic stack or layer 706a in the carrier 702, and a second magnetic stack or layer 706b in the molded chip structure 704.
  • Electrically conductive pads 718a may be in electrical connection with metallization layer 708 in the carrier 702, while electrically conductive pads 718c may be in electrical connection with metallization layer 710 in the molded chip structure 704.
  • the electrically conductive pads 718a may be connected to electrically conductive pads 718c via bumps 720a.
  • Bumps 720b may electrically connect conductive pads 718b in the molded chip structure 704 to electrically conductive pads 714a in the carrier.
  • Package 700g may differ from packages 700e, 700f by the split magnetic stacks or layers 706a, b and the arrangements of the electrically conductive pads 718a,c.
  • FIG. 7H is a schematic of a semiconductor package 700h according to yet various other embodiments.
  • the semiconductor package 700h may be similar to the semiconductor package 700g but with thicker metallization layers 708, 710.
  • Both the semiconductor package 700g shown in FIG. 7G and the semiconductor package 700h shown in FIG. 7H have a first magnetic stack or layer 706a in the carrier, and a second magnetic stack or layer 706b in the molded chip structure 704.
  • the total thickness of the two magnetic stacks or layers 706a, 706b may provide a higher inductance for a given number of turns, thus improving inductance density.
  • the use of thick magnetic layers or stacks may result in lower dc-resistance, thus improving the quality factor of the inductor.
  • FIG. 8 shows some embodiments of the semiconductor package.
  • the location of the magnetic stack or layer and the location of the thick metallization layer may differ amongst the various embodiments.
  • FIG. 10 is a table comparing the conventional scheme and the proposed scheme according to various embodiments.
  • FIG. 11 A illustrates a method of forming a semiconductor package according to various embodiments.
  • Step 1 shows a silicon oxide (S1O2) layer formed on a silicon (Si) wafer.
  • Step 2 shows a redistribution layer (RDL) formed on the silicon oxide layer.
  • the redistribution layer may include a portion of the inductor, i.e. the first metallization layer required for the inductor.
  • Step 3 shows the forming of a magnetic stack over the first metallization layer, thereby forming a carrier.
  • Step 4 shows a chip structure with a redistribution layer (RDL) including the second metallization required for the inductor.
  • the chip structure may include a PMIC chip.
  • the magnetic stack is formed as part of the carrier.
  • the magnetic stack may be part of the chip structure.
  • a first magnetic stack may be formed as part of the carrier, and a second magnetic stack may be formed as part of the chip structure.
  • FIG. 12B illustrates a method of forming a semiconductor package according to various embodiments.
  • a silicon oxide layer may be formed over the active area (PMIC).
  • a redistribution layer RDL
  • the redistribution layer may include a first metallization layer.
  • a magnetic layer/stack and vias may be formed over the first metallization layer.
  • a chip/wafer with a second metallization layer may be provided over the magnetic layer/stack and vias so that the first metallization layer, the second metallization layer, the thin magnetic layer/stack and the vias form an inductor.
  • the vias may connect the first metallization layer and the second metallization layer.
  • the conventional inductors realized on silicon are more suitable for communication systems, filters, tank circuits and other RFIC circuits and are generally without a magnetic core.
  • Conventional structures with thin-film magnetic layers are either based on post CMOS process or are implemented on a separate wafer in a stand-alone manner and assembled to the PMIC. Both these approaches may have the limitation of processing thicker copper twice on the same wafer. With limited copper thickness, the resulting dc-resistance may be large (low Q), which makes them unattractive for power applications.
  • various embodiments may relate to a split structure so as to enable the use of thicker copper layers, thereby reducing the dc-resistance of the inductor and improving the quality factor (Q). Processing of such a structure can easily be achieved in the standard CMOS flow and may be appealing for the integrated voltage regulators where a PMIC is tightly integrated with the required inductor.
  • Various embodiments may relate to a method of forming a semiconductor package.
  • the method may include forming a carrier including a first metallization layer.
  • the method may also include forming a molded chip structure including a second metallization layer.
  • the method may further include forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer.
  • the magnetic stack, the first metallization layer and the second metallization layer may form an inductor.

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Abstract

Various embodiments may provide a semiconductor package. The semiconductor package may include a carrier. The carrier may include a redistribution layer including a first metallization layer. The semiconductor package may further include a chip structure bonded to the carrier. The chip structure may include a second metallization layer. The semiconductor package may further include a magnetic stack between the first metallization layer and the second metallization layer. The magnetic stack, the first metallization layer and the second metallization layer form an inductor.

Description

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of priority of Singapore application No. 10201810384P filed November 21, 2018, the contents of it being hereby incorporated by reference in its entirety for all purposes.
TECHNICAL FIELD
[0002] Various aspects of this disclosure relate to a semiconductor package. Various aspects of this disclose relate to a method of forming a semiconductor package.
BACKGROUND
[0003] The real-estate printed circuit board (PCB) area of a traditional direct current/direct current (DC/DC) converter is dominated by the input capacitor and the output filters which include an inductor and a capacitor. The size of these passive elements is determined by the switching frequency of the converter. The converter can be switched faster so as to reduce the size of these passive elements. However, the size of these components is still large to be integrated on silicon using a standard complementary metal oxide semiconductor (CMOS) process. In such a process, an inductor is realized using back-end of the line (BEOL) metal layers. Various shaped inductors, e.g. spiral, toroidal, etc. may be realized in this manner. It would require a large number of turns to realize the required inductance required for power management applications. Due to the large number of turns, the dc-resistance is large, which degrades the quality factor of such an inductor.
[0004] One way to reduce the number of turns of such an inductor is by using a magnetic core (similar to commercially available wire-wound inductors). In a CMOS process, the core may be realized through magnetic thin-films. The use of a magnetic core increases the resulting inductance per unit length of wire, and a higher inductance can be realized with smaller series resistance. Nickel-ferrite (NiFe) and cobalt-zirconium-tantalite (CZT) may be good potential candidates as the magnetic material.
[0005] Thin-film based inductors are typically used for monolithic integration. In such an inductor structure, a magnetic core (including magnetic thin film) is used in a toroid like inductor structure.
[0006] FIG. 1A is a schematic showing an inductor with a core of a magnetic thin film. Two BEOL metal layers are used to realize the required turns of the inductor as shown in FIG. 1A.
[0007] FIG. IB is a schematic showing that the core may be a single layer or may include stacked laminated layers. The layers are separated using thin laminating material.
[0008] The inductance of the structure may depend upon the width of the magnetic core and the number of the turns around the core. The dc-resistance of the inductor shown in FIG. 1A depends upon the number of turns and the thickness of the two metal layers used to form the turns. As the thickness of the metal trace is rather limited, the structure suffers from high dc-resistance; thereby resulting in high ohmic loss and poor efficiency. Theoretically, while keeping all the other parameters same, doubling the thickness of the metal traces would reduce the dc-resistance by a factor of half and so on. FIG. 1C illustrates the variation of inductance (L) and resistance (R) of a thin film inductor with wire thickness. The overall efficiency of a DC/DC converter depends on the losses of the system.
[0009] However, processing the thick metal layers twice (i.e. forming the lower metal layer and upper metal layer) on the same substrate faces challenges, such as wafer warpage, de-lamination, etc. and hence is avoided for reliable integration.
SUMMARY
[0010] Various embodiments may provide a semiconductor package. The semiconductor package may include a carrier. The carrier may include a redistribution layer including a first metallization layer. The semiconductor package may further include a chip structure bonded to the carrier. The chip structure may include a second metallization layer. The semiconductor package may further include a magnetic stack between the first metallization layer and the second metallization layer. The magnetic stack, the first metallization layer and the second metallization layer form an inductor.
[0011] Various embodiments may provide a method of forming a semiconductor package. The method may include forming a carrier by forming a redistribution layer including a first metallization layer. The method may also include forming a chip structure including a second metallization layer. The method may further include forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer when the carrier and the chip structure are bonded to each other. The magnetic stack, the first metallization layer and the second metallization layer may form an inductor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:
FIG. 1 A is a schematic showing an inductor with a core of a magnetic thin film.
FIG. IB is a schematic showing that the core may be a single layer or may include stacked laminated layers.
FIG. 1C illustrates the variation of inductance (L) and resistance (R) of a thin film inductor with wire thickness.
FIG. 2 shows some inductor structures based on thin-film magnetic layers.
FIG. 3A is a schematic showing a package containing a power management integrated circuit (PMIC) chip and an inductor including two metal layers and a magnetic core.
FIG. 3B is another schematic showing the package shown in FIG. 3A.
FIG. 4 is a general illustration of a semiconductor package 400 according to various embodiments. FIG. 5 is a general illustration of a method of forming a semiconductor package according to various embodiments.
FIG. 6 is a schematic of an inductor included in a semiconductor package according to various embodiments.
FIG. 7A is a schematic of a semiconductor package according to various embodiments. FIG. 7B is a schematic of a semiconductor package according to various other embodiments.
FIG. 7C is a schematic of a semiconductor package according to yet various other embodiments. FIG. 7D is a schematic of a semiconductor package according to yet various other embodiments. FIG. 7E is a schematic of a semiconductor package according to yet various other embodiments. FIG. 7F is a schematic of a semiconductor package according to yet various other embodiments. FIG. 7G is a schematic of a semiconductor package according to yet various other embodiments. FIG. 7H is a schematic of a semiconductor package according to yet various other embodiments. FIG. 8 shows some embodiments of the semiconductor package.
FIG. 9 shows different views of a semiconductor package according to various embodiments. FIG. 10 is a table comparing the conventional scheme and the proposed scheme according to various embodiments.
FIG. 11A illustrates a method of forming a semiconductor package according to various embodiments.
FIG. 11B illustrates a method of forming a semiconductor package according to various embodiments.
FIG. 12A illustrates a method in which two redistribution layers (RDLs) are formed over a substrate.
FIG. 12B illustrates a method of forming a semiconductor package according to various embodiments.
FIG. 12C illustrates a method of forming a semiconductor package according to other various embodiments.
DETAILED DESCRIPTION
[0013] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
[0014] Embodiments described in the context of one of the methods or semiconductor packages is analogously valid for the other methods or semiconductor packages. Similarly, embodiments described in the context of a method are analogously valid for a semiconductor package, and vice versa.
[0015] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.
[0016] The word "over" used with regards to a deposited material formed“over” a side or surface, may be used herein to mean that the deposited material may be formed "directly on”, e.g. in direct contact with, the implied side or surface. The word "over" used with regards to a deposited material formed“over” a side or surface, may also be used herein to mean that the deposited material may be formed "indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. In other words, a first layer“over” a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.
[0017] In the context of various embodiments, the articles“a”,“an” and“the” as used with regard to a feature or element include a reference to one or more of the features or elements.
[0018] In the context of various embodiments, the term“about” or“approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.
[0019] As used herein, the term“and/or” includes any and all combinations of one or more of the associated listed items.
[0020] A conventional way of realizing the inductors involves using BEOL metal layers in a CMOS process. Such inductors are mostly used in radio frequency integrated circuits (RFIC) and the required inductance is of the order of 1 ~ 10 nH. Since the inductors are mostly used for small signals in low-noise amplifiers, oscillators, filters, matching networks etc., the de-resistance is less of a concern. Hence, air-core inductors, without a magnetic layer, are typically used. Various shaped inductors have been designed and optimized for this purpose, some of the shapes being circular spiral, square spiral, and octagonal spiral. Due to large number of turns being used to realize the inductor; the dc-resistance is high. As a result, such inductors are not suitable for power applications in which a low dc-resistance is preferred.
[0021] A magnetic layer has been used to improve the inductance and for reducing the number of turns for the given inductance. A toroidal inductor in a post CMOS process is shown in FIG. 2. It uses a cobalt- zirconium-tantalite (CZT) based magnetic layer sandwiched between two copper layers. Such an inductor is implemented on single wafer using 5pm thick copper (Cu) coils for redistribution layer (RDL) in BEOL process. The reported inductor has limitations in achieving high quality factor (Q) with the best quality factor reported to be less than 10. This is due to the limited copper thickness which can be achieved in such a process.
[0022] The conventional inductor designs are either implemented without magnetic layer, which results in a smaller inductor density, or are implemented using magnetic core and would suffer from limitations in the thickness of metal which can be processed to realize the inductor. Thicker metal layers are needed to improve the quality of the inductors; however, processing the thick metal twice on a same substrate has challenges of wafer warpage, de-lamination, etc. and hence is avoided for reliable integration. Various embodiments may relate to a structure that make use of magnetic core for better inductor density and which uses a split structure which gives extra design freedom to increase the metal thickness. Thicker metal traces may result in smaller dc- resistance in the inductor thereby improving the quality factor of the inductor.
[0023] In order to appreciate the structure, it is important to understand the assembly flow and processes involved. A conventional structure such as a power management integrated circuit (PMIC) may be designed using a standard CMOS process and the inductor may fabricated on the same wafer, with the inductor realized using two or more copper traces and a magnetic stack core. FIG. 3A is a schematic showing a package containing a power management integrated circuit (PMIC) chip and an inductor including two metal layers and a magnetic core. For packaging or assembly process, a supporting wafer is used which contains the re-distribution layer (RDL) for routing the required input-output (IO) ports from the PMIC to the designated pin in the package of choice (say ball grid array (BGA) in this example). [0024] As discussed earlier, the inductor includes two metal layers and a magnetic layer. The dc-resistance of such an inductor may depend on the thickness of these metal or RDL layers on the inductor wafer/ substrate. The dc-resistance may be reduced by making these metal lines thicker. However, it is challenging to process thick metal/RDL lines twice on the same wafer. The thickness of the metal/RDL lines is limited, e.g. cannot be more than 20 /zm. The stress induced during the processing of first thick metal results in wafer warpage. It may also result in de lamination or peeling effects, which inhibits or increases the difficulties of subsequent processing to complete the inductor structure.
[0025] As such, the inductor can be realized using thinner copper layers, e.g. using the back end of the line in the CMOS process. In such an approach, as the thickness of the metal trace is rather limited, the structure suffers from high dc-resistance; thereby resulting in high ohmic loss and poor conversion efficiency in end applications. Various embodiments may relate to an approach which improves the dc-resistance of the inductor by overcoming the limitations of copper thickness.
[0026] FIG. 3B is another schematic showing the package shown in FIG. 3A. In order to overcome the challenges in processing the thick metal/RDL twice on the same wafer, the inductor structure may be split. In various embodiments, one of the two thick metal layer/RDL may be fabricated on one wafer, and the remaining one thick metal layer/RDL may be fabricated on the other wafer. In other words, the first thick RDL is formed or processed on the PMIC wafer, whereas the second thick RDL is formed or processed on the inductor wafer/substrate. The magnetic layer may be formed or processed on either of these two wafers. After the flip-chip assembly process, the structure integrity may be established and the required inductor may be realized. Various embodiments may relate to a package in which the RDLl, the RDL2 and/or the magnetic layer indicated in FIG. 3B may be relocated.
[0027] Various embodiments may relate to a structure which is fabricated using existing assembly flow, realizes thick metal with low dc-resistance, and improves the overall quality factor (Q) of the inductor.
[0028] FIG. 4 is a general illustration of a semiconductor package 400 according to various embodiments. The semiconductor package 400 may include a carrier or carrier wafer 402 including a redistribution layer including a first metallization layer. The semiconductor package 400 may further include a chip structure 404 (e.g. CMOS chip after BEOL) bonded to the carrier or carrier wafer 402. The chip structure 404 may include a second metallization layer. The semiconductor package 400 may further include a magnetic stack 406 between the first metallization layer and the second metallization layer. The magnetic stack 406, the first metallization layer and the second metallization layer may form an inductor.
[0029] In other words, the package 400 may include an inductor having one part formed as part of the carrier 402, and another part formed as part of the chip structure 404. The carrier 402 may include a first metallization of the inductor, while the chip structure 404 may include a second metallization of the inductor. The magnetic stack 406 of the inductor may be part of the carrier 402 and/or part of the molded chip structure 404.
[0030] In various embodiments, the chip structure 402 may include a semiconductor chip, and a redistribution layer in contact with the semiconductor chip. The redistribution layer of the chip structure 402 may include the second metallization.
[0031] In various embodiments, the chip structure 402 may be a molded chip structure further including an encapsulation layer in contact with the semiconductor chip. In various embodiments, the encapsulation layer may include a suitable mold compound.
[0032] In various embodiments, the magnetic stack 406 may include one or more magnetic layers. The magnetic stack 406 may be a laminated magnetic stack. In various other embodiments, the magnetic stack 406 may include or consist of a single magnetic layer. The magnetic layer or layers may include a magnetic material such as nickel-ferrite (NiFe) or cobalt-zirconium-tantalite (CZT). The magnetic layer or layers may include any other suitable magnetic material.
[0033] As highlighted above, in various embodiments, the carrier wafer or carrier 402 may include the magnetic stack 406. The redistribution layer of the carrier wafer or carrier 402 may include the magnetic stack.
[0034] In various other embodiments, the chip structure 404 may include the magnetic stack 406. The redistribution layer of the chip structure 404 may include the magnetic stack.
[0035] In yet various other embodiments, the carrier wafer or carrier 402, e.g. the redistribution layer of the carrier wafer or carrier 402, may include a first portion of the magnetic stack 406. The chip structure, the redistribution layer of the carrier wafer or carrier 402, may include a second portion of the magnetic stack 406. [0036] In various embodiments, the first metallization layer may be thicker than the second metallization layer. For instance, the first metallization layer may have a thickness of any value more than 10 mhi, while the second metallization layer may have a thickness of any value less than 10 mih, e.g. 5 mhi or 7 mih.
[0037] In various other embodiments, the second metallization layer may be thicker than the first metallization layer. For instance, the second metallization layer may have a thickness of any value more than 10 mhi, while the first metallization layer may have a thickness of any value less than 10 mih, e.g. 5 mhi or 7 mih.
[0038] In yet various other embodiments, a thickness of the first metallization layer may be substantially equal to a thickness of the second metallization layer. The thickness of the first metallization layer and the thickness of the second metallization layer may each be of a value more than 10 mpi.
[0039] In various embodiments, the first metallization layer may have a thickness of any value more than 10 mhi. The second metallization layer may have a thickness of any value more than 10 mih.
[0040] The first metallization layer and/or the second metallization layer may include a suitable metal such as copper, aluminum, gold, tungsten, titanium, silver, or tin. Alternatively, the first metallization layer and/or the second metallization layer may include a suitable alloy, such as an alloy of copper, aluminum, gold, tungsten, titanium, silver, or tin.
[0041 ] In various embodiments, the semiconductor package 400 may include a plurality of first metal vias. The semiconductor package 400 may also include a plurality of second metal vias. The plurality of first metal vias and the plurality of second metal vias may connect the first metallization layer and the second metallization layer so that the magnetic stack 406 is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
[0042] In various embodiments, the semiconductor package 400 may include a plurality of first interconnects and a plurality of second interconnects. The plurality of first interconnects and the plurality of second interconnects may connect the first metallization layer and the second metallization layer so that the magnetic stack 406 is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first interconnects, and the plurality of second interconnects. A first interconnect and a second interconnects may each include a bump and an under-bump metallization.
[0043] FIG. 5 is a general illustration of a method of forming a semiconductor package according to various embodiments. The method may include, in 502, forming a carrier (or carrier wafer) by forming a redistribution layer including a first metallization layer. The method may also include, in 504, forming or providing a chip structure including a second metallization layer. The method may further include, in 506, forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer when the carrier (or carrier wafer) and the chip structure are bonded to each other. The magnetic stack, the first metallization layer and the second metallization layer may form an inductor.
[0044] In other words, the semiconductor package may be formed such that part of the inductor is formed in the carrier wafer or carrier, and part of the inductor is formed in the chip structure.
[0045] In various embodiments, the redistribution layer of the carrier or carrier wafer may be formed on or over a substrate. In various embodiments, the method may include forming the redistribution layer on or over a substrate. The redistribution layer of the carrier or carrier wafer may include the first metallization layer. The method may also include providing or forming a chip structure including a semiconductor chip and a redistribution layer in contact with the semiconductor chip. The redistribution layer of the chip structure may include the second metallization layer.
[0046] In various embodiments, the magnetic stack may include one or more magnetic layers. The magnetic stack may be a laminated magnetic stack. In various other embodiments, the magnetic stack may include or consist of a single magnetic layer.
[0047] In various embodiments, the carrier wafer or carrier may include the magnetic stack. In various other embodiments, the chip structure may include the magnetic stack.
[0048] In yet various embodiments, the carrier wafer or carrier may include a first portion of the magnetic stack. The chip structure may include a second portion of the magnetic stack.
[0049] In various embodiments, the first metallization layer may be thicker than the second metallization layer. The first metallization layer may have a thickness of any value more than 10 mih. The second metallization layer may have a thickness of any value less than 10 / m. [0050] In various other embodiments, the second metallization layer may be thicker than the first metallization layer. The second metallization layer may have a thickness of any value more than 10 mth. The first metallization layer may have a thickness of any value less than 10 /nn.
[0051] In yet various other embodiments, a thickness of the first metallization layer may be substantially equal to a thickness of the second metallization layer.
[0052] In various embodiments, the first metallization layer may have a thickness of any value more than 10 mth. In various embodiments, the second metallization layer may have a thickness of any value more than 10 mth.
[0053] In various embodiments, the method may include forming a plurality of first metal vias and a plurality of second metal vias connecting the first metallization layer and the second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
[0054] In various embodiments, the method may include forming a plurality of first interconnects and a plurality of second interconnects connecting the first metallization layer and the second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first interconnects, and the plurality of second interconnects. A first interconnect and a second interconnects may each include a bump and an under-bump metallization.
[0055] Various embodiments may relate to wafer-to-wafer (W2W) processing, chip-to-wafer (C2W) processing, or chip-to-chip (C2C) processing.
[0056] In various embodiments, the carrier may be a chip or a wafer. In various embodiments, the chip structure may include a semiconductor chip and a redistribution layer. In various embodiments, the chip structure may be a part of a wafer.
[0057] FIG. 6 is a schematic of an inductor included in a semiconductor package according to various embodiments. The first metallization or metal layer 608 may be formed or arranged in the carrier (inductor wafer or substrate), while the second metallization or metal layer 610 may be formed or arranged in the molded chip structure (CMOS chip (after BEOL)). The magnetic stack or layer may be formed or arranged in carrier or the molded chip structure. [0058] FIG. 7A is a schematic of a semiconductor package 700a according to various embodiments. The semiconductor package 700a may include a carrier. The carrier may include a redistribution layer 702 including a first metallization layer 708. The redistribution layer 702 may provide fan-out connections. The redistribution layer 702 may further include one or more additional metallization layers. The redistribution layer 702 may also include one or more dielectric layers supporting the metallization layers. Each of the dielectric layers may be in contact with a metallization layer. The semiconductor package 700a may further include a molded chip structure 704 bonded to the carrier, i.e. the redistribution layer 702. The molded chip structure 704 may include a semiconductor chip 704a, i.e. an application specific integrated circuit (ASIC) chip such as a PMIC chip, including a second metallization layer 710. The semiconductor chip 704a may include a further redistribution layer 712 including the second metallization layer 710.
[0059] The molded chip structure 704 may additionally include an encapsulation layer 704b in contact with the semiconductor chip 704a. The semiconductor package 700, i.e. the redistribution layer 712 of the molded chip structure 704, may further include a magnetic stack 706 between the first metallization layer 708 and the second metallization layer 710. The magnetic stack 706, the first metallization layer 708, and the second metallization layer 710 may form an inductor.
[0060] The molded chip structure 704 may be formed by bonding the semiconductor chip 704a to the carrier, followed by depositing a mold compound to form the encapsulation layer 704b.
[0061] The redistribution layer 702 of the carrier may include electrically conductive pads 714a, external contact pads 714b, and one or more interconnects 714c electrically connecting the conductive pads 714a and the external contact pads 714b. The carrier wafer may further include solder bumps 716 electrically connected to the external contact pads 714b. The solder bumps 716 may form a ball grid array (BGA).
[0062] The further redistribution layer 712 may also include electrically conductive pads 718a, 718b. The molded chip structure 704 may also include bumps 720a connecting electrically conductive pads 718a to the first metallization layer 708. The conductive pads 718a may be connected to the second metallization layer 710. As such, the first metallization layer 708 may be in electrical connection with the second metallization layer 710. The molded chip structure 704 may further include bumps 720b connecting electrically conductive pads 718b to the electrically conductive pads 714a of redistribution layer 702. [0063 ] As highlighted above, one of the layers 710 for the inductor may be realized in the PMIC chip structure 704 after the BEOL metallization process. This layer 710 may also be a part of the BEOL. The magnetic stack 706 may also be formed or deposited in the same wafer 704. The second metallization layer 710 may be a thick one or may be of normal thickness. However, the first metallization layer 708 may be realized in the carrier 702.
[0064] FIG. 7B is a schematic of a semiconductor package 700b according to various other embodiments. The magnetic stack 706 may be part of the carrier 702 together with metallization layer 708. The metallization layer 710 may still be part of the molded chip structure 704.
[0065] FIG. 7B also shows that the electrically conductive pads 718a may be included in the redistribution layer 702 of the carrier. Bumps 720a may connect the electrically conductive pads 718a with the metallization layer 710. The electrically conductive pads 718a may also be in electrical connection with the metallization layer 708.
[0066] The package 700b may be similar to the package 700a shown in FIG. 7A except for the arrangement of the magnetic stack 706 and the electrically conductive pads 718a.
[0067] The metallization layers 708, 710 may not be processed in the same wafer twice, thereby reducing the stress on the wafers and providing ease of wafer processing. The use of the metal layers may lower the overall dc-resistance, thereby improving the quality factor (Q) of the inductor.
[0068] FIG. 7C is a schematic of a semiconductor package 700c according to yet various other embodiments. FIG. 7C shows that the metallization layer 710 may be thicker than the metallization layer 708. The magnetic stack 706 may be included in the molded chip structure 704 with the metallization layer 710, while the metallization layer 708 may be included in the carrier. The package 700c may be similar to the package 700a shown in FIG. 7A except for the relative thicknesses of the metallization layers 708, 710.
[0069] FIG. 7D is a schematic of a semiconductor package 700d according to yet various other embodiments. FIG. 7D shows that the metallization layer 710 may be thicker than the metallization layer 708. The magnetic stack 706 may be included in the carrier with the metallization layer 708, while the metallization layer 710 may be included in the molded chip structure 704. The package 700d may be similar to the package 700b shown in FIG. 7B except for the relative thicknesses of the metallization layers 708, 710. [0070] As shown in FIGS. 7C-D, the metallization layer 710 in the molded chip structure 704 may be thicker than the metallization layer 708 included in the carrier. The magnetic stack 706 may be in the molded chip structure 704, or in the carrier.
[0071] FIG. 7E is a schematic of a semiconductor package 700e according to yet various other embodiments. FIG. 7E shows that the metallization layers 708, 710 may be substantially of equal thicknesses. The magnetic stack 706 may be included in the molded chip structure 704 with the metallization layer 710, while the metallization layer 708 may be included in the carrier 702. The package 700e may be similar to the package 700a shown in FIG. 7A except for the relative thicknesses of the metallization layers 708, 710.
[0072] FIG. 7F is a schematic of a semiconductor package 700f according to yet various other embodiments. FIG. 7F shows that the metallization layers 708, 710 may be substantially of equal thicknesses. The magnetic stack 706 may be included in the carrier 702 with the metallization layer 708, while the metallization layer 710 may be included in the molded chip structure 704. The package 700f may be similar to the package 700b shown in FIG. 7B except for the relative thicknesses of the metallization layers 708, 710.
[0073] It may be possible to process two thick metal layers 708, 710 independently in the molded chip structure 704 containing the PMIC 704a and in the carrier. The magnetic layer 706 may either be in the molded chip structure 704 or in the carrier. As noticed from FIGS. 7E-F, both the metal layers 708, 710 may be thick. Consequently, the resulting dc-resistance may be very much lower, thereby having better quality factor as compared to the inductor realized using the metal layers with standard thickness.
[0074] FIG. 7G is a schematic of a semiconductor package 700g according to yet various other embodiments. FIG. 7G discloses a first magnetic stack or layer 706a in the carrier 702, and a second magnetic stack or layer 706b in the molded chip structure 704. Electrically conductive pads 718a may be in electrical connection with metallization layer 708 in the carrier 702, while electrically conductive pads 718c may be in electrical connection with metallization layer 710 in the molded chip structure 704. The electrically conductive pads 718a may be connected to electrically conductive pads 718c via bumps 720a. Bumps 720b may electrically connect conductive pads 718b in the molded chip structure 704 to electrically conductive pads 714a in the carrier. Package 700g may differ from packages 700e, 700f by the split magnetic stacks or layers 706a, b and the arrangements of the electrically conductive pads 718a,c.
[0075] FIG. 7H is a schematic of a semiconductor package 700h according to yet various other embodiments. The semiconductor package 700h may be similar to the semiconductor package 700g but with thicker metallization layers 708, 710.
[0076] Both the semiconductor package 700g shown in FIG. 7G and the semiconductor package 700h shown in FIG. 7H have a first magnetic stack or layer 706a in the carrier, and a second magnetic stack or layer 706b in the molded chip structure 704. By having two magnetic stacks or layers 706a, 706b, the total thickness of the two magnetic stacks or layers 706a, 706b may provide a higher inductance for a given number of turns, thus improving inductance density. In addition, the use of thick magnetic layers or stacks may result in lower dc-resistance, thus improving the quality factor of the inductor.
[0077] FIG. 8 shows some embodiments of the semiconductor package. The location of the magnetic stack or layer and the location of the thick metallization layer may differ amongst the various embodiments.
[0078] FIG. 9 shows different views of a semiconductor package 900 according to various embodiments. The semiconductor package 900 may include a carrier, such as a bottom die 902. The bottom die 902 may include a first metallization layer 908. The semiconductor package 900 may further include a top die 904. The top die 904 may include a second metallization layer 910. The semiconductor package 900 may further include a magnetic stack 906 between the first metallization layer 908 and the second metallization layer 910. The magnetic stack 906, the first metallization layer 908 and the second metallization layer 910 may form an inductor. The top die 904 may be flip-chipped onto the bottom die 902.
[0079] In various embodiments, the magnetic stack 906 may be included in the top die 904, similar to package 400a shown in FIG. 4A.
[0080] FIG. 10 is a table comparing the conventional scheme and the proposed scheme according to various embodiments.
[0081] FIG. 11 A illustrates a method of forming a semiconductor package according to various embodiments. Step 1 shows a silicon oxide (S1O2) layer formed on a silicon (Si) wafer. Step 2 shows a redistribution layer (RDL) formed on the silicon oxide layer. The redistribution layer may include a portion of the inductor, i.e. the first metallization layer required for the inductor. Step 3 shows the forming of a magnetic stack over the first metallization layer, thereby forming a carrier. Step 4 shows a chip structure with a redistribution layer (RDL) including the second metallization required for the inductor. The chip structure may include a PMIC chip. Step 5 shows bonding of the chip structure such that the magnetic stack is between the first metallization of the carrier and the second metallization of the chip structure. The method may also include depositing of a mold compound to be in contact with the PMIC chip. In addition to the PMIC chip, other components such as a load and a capacitor (C) may also be bonded to the carrier. The mold compound may also be in contact with the other components. In other words, the mold compound may form an encapsulation layer covering the PMIC chip as well as the other components. In Step 6, the silicon wafer may be removed by back grinding, and etching. Solder balls may be attached in Step 7. As shown in FIG. 11 A, the first metallization is thicker than the second metallization.
[0082] FIG. 1 IB illustrates a method of forming a semiconductor package according to various embodiments. Step 1 shows a silicon oxide (S1O2) layer formed on a silicon (Si) wafer. Step 2 shows a redistribution layer (RDL) formed on the silicon oxide layer. The redistribution layer may include a portion of the inductor, i.e. the first metallization layer required for the inductor. Step 3 shows the forming of a magnetic stack over the first metallization layer, thereby forming a carrier. Step 4 shows a chip structure with a redistribution layer (RDL) including the second metallization required for the inductor. The chip structure may include a PMIC chip. Step 5 shows bonding of the chip structure such that the magnetic stack is between the first metallization of the carrier and the second metallization of the chip structure. The method may also include depositing of a mold compound to be in contact with the PMIC chip. In addition to the PMIC chip, other components such as a load and a capacitor (C) may also be bonded to the carrier. The mold compound may also be in contact with the other components. In other words, the mold compound may form an encapsulation layer covering the PMIC chip as well as the other components. In Step 6, the silicon wafer may be removed by back grinding, and etching. Solder balls may be attached in Step 7. The method illustrated in FIG. 11B is similar to FIG. 11 A, except that the second metallization is thicker than the first metallization.
[0083] For both FIGS. 11 A-B, the magnetic stack is formed as part of the carrier. However, in various embodiments, the magnetic stack may be part of the chip structure. In various other embodiments, a first magnetic stack may be formed as part of the carrier, and a second magnetic stack may be formed as part of the chip structure.
[0084] FIG. 12A illustrates a method in which two redistribution layers (RDLs) are formed over a substrate. As highlighted in FIG. 12 A, the method may limit the thicknesses of the metallization layers.
[0085] FIG. 12B illustrates a method of forming a semiconductor package according to various embodiments. In step 1, a silicon oxide layer may be formed over the active area (PMIC). In step 2, a redistribution layer (RDL) may be formed on the silicon oxide layer. The redistribution layer may include a first metallization layer. In step 3, a magnetic layer/stack and vias may be formed over the first metallization layer. In step 4, a chip/wafer with a second metallization layer may be provided over the magnetic layer/stack and vias so that the first metallization layer, the second metallization layer, the thin magnetic layer/stack and the vias form an inductor. The vias may connect the first metallization layer and the second metallization layer.
[0086] FIG. 12C illustrates a method of forming a semiconductor package according to other various embodiments. In step 1, a silicon oxide layer may be formed over the active area (PMIC). In step 2, a redistribution layer (RDL) may be formed on the silicon oxide layer. The redistribution layer may include a first metallization layer. In step 3, a magnetic layer/stack and vias may be formed on a chip/wafer with a second metallization layer. In step 4, the chip/wafer may be bonded or provided over the redistribution layer such that the first metallization layer, the second metallization layer, the thin magnetic layer/stack and the vias form an inductor. The vias may connect the first metallization layer and the second metallization layer.
[0087] The conventional inductors realized on silicon are more suitable for communication systems, filters, tank circuits and other RFIC circuits and are generally without a magnetic core. Conventional structures with thin-film magnetic layers are either based on post CMOS process or are implemented on a separate wafer in a stand-alone manner and assembled to the PMIC. Both these approaches may have the limitation of processing thicker copper twice on the same wafer. With limited copper thickness, the resulting dc-resistance may be large (low Q), which makes them unattractive for power applications. To this end, various embodiments may relate to a split structure so as to enable the use of thicker copper layers, thereby reducing the dc-resistance of the inductor and improving the quality factor (Q). Processing of such a structure can easily be achieved in the standard CMOS flow and may be appealing for the integrated voltage regulators where a PMIC is tightly integrated with the required inductor.
[0088] Various embodiments may relate to a semiconductor package including a carrier. The carrier may include a first metallization layer. The semiconductor package may further include a molded chip structure bonded to the carrier. The molded chip structure may include a second metallization layer. The semiconductor package may further include a magnetic stack between the first metallization layer and the second metallization layer. The magnetic stack, the first metallization layer and the second metallization layer may form an inductor.
[0089] Various embodiments may relate to a method of forming a semiconductor package. The method may include forming a carrier including a first metallization layer. The method may also include forming a molded chip structure including a second metallization layer. The method may further include forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer. The magnetic stack, the first metallization layer and the second metallization layer may form an inductor.
[0090] Various embodiments may relate to a technique for realizing the inductor using two RDL lines in different wafers. The two different wafers may be integrated together to realize the inductor. The magnetic layer or stack may be formed on either wafer.
[0091] Various embodiments may be attractive for reducing the dc-resistance in conventional thin- film magnetic inductors realized using BEOL. The resulting inductors may have better quality factor and may improve overall conversion efficiency.
[0092] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

Claims
1. A method of forming a semiconductor package, the method comprising:
forming a carrier by forming a redistribution layer comprising a first metallization layer;
forming a chip structure comprising a second metallization layer; and forming a magnetic stack so that the magnetic stack is between the first metallization layer and the second metallization layer when the carrier and the chip structure are bonded to each other;
wherein the magnetic stack, the first metallization layer and the second metallization layer form an inductor.
2. The method according to claim 1,
wherein the magnetic stack comprises one or more magnetic layers.
3. The method according to claim 1,
wherein the magnetic stack is a laminated magnetic stack.
4. The method according to claim 1,
wherein the carrier comprises the magnetic stack.
5. The method according to claim 1,
wherein the chip structure comprises the magnetic stack.
6. The method according to claim 1 ,
wherein the carrier comprises a first portion of the magnetic stack; and wherein the chip structure comprises a second portion of the magnetic stack.
7. The method according to claim 1, wherein the first metallization layer is thicker than the second metallization layer.
8. The method according to claim 7,
wherein the first metallization layer has a thickness of any value more than 10 mih; and
wherein the second metallization layer has a thickness of any value less than 10 mhi.
9. The method according to claim 1,
wherein the second metallization layer is thicker than the first metallization layer.
10. The method according to claim 9,
wherein the second metallization layer has a thickness of any value more than 10 mpi; and
wherein the first metallization layer has a thickness of any value less than 10 mhi.
11. The method according to claim 1 ,
wherein a thickness of the first metallization layer is substantially equal to a thickness of the second metallization layer.
12. The method according to claim 1,
wherein the first metallization layer has a thickness of any value more than 10 mhi; and
wherein the second metallization layer has a thickness of any value more than 10 mih.
13. The method according to claim 1, further comprising:
forming a plurality of first metal vias and a plurality of second metal vias connecting the first metallization layer and the second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
14. A semiconductor package comprising:
a carrier comprising a redistribution layer comprising a first metallization layer; a chip structure bonded to the carrier, the chip structure comprising a second metallization layer; and
a magnetic stack between the first metallization layer and the second metallization layer;
wherein the magnetic stack, the first metallization layer and the second metallization layer form an inductor.
15. The semiconductor package according to claim 14,
wherein the magnetic stack comprises one or more magnetic layers.
16. The semiconductor package according to claim 14,
wherein the magnetic stack is a laminated magnetic stack.
17. The semiconductor package according to claim 14,
wherein the carrier comprises the magnetic stack.
18. The semiconductor package according to claim 14,
wherein the chip structure comprises the magnetic stack.
19. The semiconductor package according to claim 14,
wherein the carrier comprises a first portion of the magnetic stack; and wherein the chip structure comprises a second portion of the magnetic stack.
20. The semiconductor package according to claim 14, further comprising:
a plurality of first metal vias; and a plurality of second metal vias;
wherein the plurality of first metal vias and the plurality of second metal vias connect the first metallization layer and die second metallization layer so that the magnetic stack is within a region surrounded by the first metallization layer, the second metallization layer, the plurality of first metal vias, and the plurality of second metal vias.
PCT/SG2019/050554 2018-11-21 2019-11-11 Semiconductor package and method of forming the same WO2020106214A1 (en)

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