WO2020106213A1

WO2020106213A1 - A system and method for charge balancing an h-bridge stimulator

Info

Publication number: WO2020106213A1
Application number: PCT/SG2019/050551
Authority: WO
Inventors: Yong-Joon Jeon
Original assignee: Agency For Science, Technology And Research
Priority date: 2018-11-19
Filing date: 2019-11-11
Publication date: 2020-05-28

Abstract

This document describes a system and method for balancing charge across a pair of stimulators at the stimulator-tissue interface in an H-bridge stimulator circuit. In particular, the system described herein causes a path of low-resistance to be selectively formed between the stimulators using existing switches in the H-bridge circuit.

Description

A SYSTEM AND METHOD FOR CHARGE BALANCING AN H-BRIDGE STIMULATOR

Field of the Invention

This invention relates to a system and method for balancing charge across a pair of stimulators at the stimulator-tissue interface in an H-bridge stimulator circuit. In particular, the invention relates to a system that causes a path of low-resistance to be selectively formed between the stimulators using existing switches in the H-bridge circuit.

Summary of the Prior Art

Functional electrical stimulation is a technique for artificially generating muscular movements by applying low-energy electrical pulses to the affected area. This technique may be used to benefit those who have lost hearing, vision, or muscular functions. Typically, such stimulations may be applied using commercial stimulators that specifically target the affected area such as cortical stimulators, retinal implant stimulators, spinal cord stimulators and any other similar biomedical devices.

Commercial functional electrical stimulators usually employ charge balanced biphasic stimulation techniques to stimulate the targeted tissue and these techniques require that the charge stored in the electrode-tissue interface be removed in order to ensure that the efficacy of the stimulators will not be degraded. To do so, these stimulators usually adopt passive charge balancing techniques to form an electrical shorting path between each pair of electrodes in the stimulator circuit to remove any charges that may be stored at the respective electrode-tissue interfaces during the stimulation process.

In order to form the electrical shorting path between the electrodes, those skilled in the art have proposed that an additional switch be provided between each pair of electrodes in the H-bridge stimulator circuit. This is so that when this switch is turned on, the electrodes may be electrically shorted together so that charges stored at the electrode-tissue interface may dissipate. For this switch to work as described above, the ON” resistance of this additional switch must be much less than the resistance at the electrode-tissue interface. As such, if the resistance at the electrode-tissue interface is taken to be 1 kQ, this means that in order for the ON resistance of the switch to be one tenth of the resistance at the electrode tissue interface, the channel width of the transistor used to make this switch would have to be much wider than the channel widths of the other switches in the H-bridge circuit. For example, if a 0.18um high-voltage CMOS process were utilized for the switches in the H- bridge circuit, in order for the required ON resistance values to be achieved by the additional switch, the switch would have to use a NMOS transistor having a channel width around 250um. This increase in channel width is detrimental as it would lead to a drastic increase in the overall size of the stimulator as every electrode pair would require such an additional switch to be added rendering such a solution impractical.

Further, when an additional switch is used during the charge balancing phase, there is the possibility that unintentional charging or discharging may occur at the electrodes due to parasitic capacitances in the circuit as the electrodes are directly connected to the ground and power supplies during this phase.

For the above reasons, those skilled in the art are constantly striving to come up with a system and method for balancing charge across the electrodes at an electrode-tissue interface in a H-bridge circuit so that the charge stored there may be discharged in an efficient, effective and practical manner.

Summary of the Invention

The above and other problems are solved and an advance in the art is made by systems and methods provided by embodiments in accordance with the invention.

A first advantage of embodiments of systems and methods in accordance with the invention is that additional switches do not need to be added to existing H-bridge stimulator circuits. This allows the chip area occupied by the original H-bridge circuit to remain the same.

A second advantage of embodiments of systems and methods in accordance with the invention is that when the path of low-resistance is formed between each pair of electrodes, the path itself is isolated from power lines and external power elements.

A third advantage of embodiments of systems and methods in accordance with the invention is that the path of low-resistance is formed between each pair of electrodes using existing switches in the H-bridge stimulation circuit.

The above advantages are provided by embodiments of a system in accordance with the invention operating in the following manner.

According to a first aspect of the invention, a charge balancing system is disclosed, the system comprising: a H-bridge circuit comprising at least two pairs of switching elements, wherein a first electrode is provided at a first end of the at least two pairs of switching elements and a second electrode is provided at a second end of the at least two pairs of switching elements, the first and second electrodes being configured to be connectable to a tissue for receiving stimulation; a switchable biasing circuit configured to provide a biasing voltage to a node common to switching elements of one of the at least two pairs of switching elements to enable the switching elements coupled to the node to be turned on, whereby an electrical shorting path is formed by turning off the switching elements not coupled to the node, turning on the switching elements coupled to the node and by disabling a current source coupled to the node, the electrical shorting path comprising the pair of switching elements that are turned on and the first and second electrodes, wherein charges on the first and second electrodes are balanced through the electrical shorting path.

With reference to the first aspect, the at least two pairs of switching elements comprise a pair of P-type Metal Oxide Semiconductor (PMOS) switches and a pair of N-type Metal Oxide Semiconductor (NMOS) switches.

With reference to the first aspect, the two pairs of switching elements comprise two pairs of P-type Metal Oxide Semiconductor (PMOS) switches.

With reference to the first aspect, the at least two pairs of switching elements comprise two pairs of N-type Metal Oxide Semiconductor (NMOS) switches.

With reference to the first aspect, the switchable biasing circuit comprises: a Field Effect Transistor (FET) configured as a switch; and a voltage source, whereby a constant voltage is provided by the voltage source through the FET when the FET is switched on.

With reference to the first aspect, the switchable biasing circuit comprises: a PMOS configured as a source follower that is controlled by an inverter coupled to the PMOS’s gate, whereby the PMOS configured as a source follower provides a constant voltage to the node when the PMOS configured as a source follower is turned on.

With reference to the first aspect, the system further comprises an inrush current resistor provided between the node and the biasing circuit.

According to a second aspect of the invention, a method for balancing charges at a first and second electrode in a H-bridge circuit is disclosed, the circuit having at least two pairs of switching elements, wherein the first electrode is provided at a first end of the at least two pairs of switching elements and the second electrode is provided at a second end of the at least two pairs of switching elements. The method comprises the step of providing, using a switchable biasing circuit, a biasing voltage to a node coupled between switching elements of one of the at least two pairs of switching elements to enable the switching elements coupled to the node to be turned on; forming an electrical shorting path by turning off the switching elements not coupled to the node, turning on the switching elements coupled to the node and by disabling a current source coupled to the node, the electrical shorting path comprising the pair of switching elements that are turned on and the first and second electrodes, wherein charges on the first and second electrodes are balanced through the electrical shorting path.

With reference to the second aspect, the at least two pairs of switching elements comprise a pair of P-type Metal Oxide Semiconductor (PMOS) switches and a pair of N-type Metal Oxide Semiconductor (NMOS) switches.

With reference to the second aspect, the at least two pairs of switching elements comprise two pairs of P-type Metal Oxide Semiconductor (PMOS) switches.

With reference to the second aspect, the at least two pairs of switching elements comprise two pairs of N-type Metal Oxide Semiconductor (NMOS) switches.

With reference to the second aspect, the step of providing the biasing voltage to the node comprises the step of providing a constant voltage from a voltage source to the node through a Field Effect Transistor (FET) configured as a switch when the FET is switched on.

With reference to the second aspect, the step of providing the biasing voltage to the node comprises the step of providing a constant voltage from a voltage source to the node through a PMOS configured as a source follower, the PMOS being controlled by an inverter coupled to the PMOS’s gate, when the PMOS configured as a source follower is turned on.

With reference to the second aspect, the method further comprises the step of providing an inrush current resistor between the node and the biasing circuit.

Brief Description of the Drawings

The above advantages and features in accordance with this invention are described in the following detailed description and are shown in the following drawings:

Figure 1 illustrating a system representative of an H-bridge stimulation circuit with a switchable biasing circuit provided at the source terminals of the N-type Metal-Oxide- Semiconductor (NMOS) switches in accordance with embodiments of the invention;

Figure 2 illustrating a switchable biasing circuit in accordance with embodiments of the invention; Figure 3 illustrating a system representative of an H-bridge stimulation circuit with a switchable biasing circuit provided at the source terminals of the P-type Metal-Oxide- Semiconductor (PMOS) switches in accordance with embodiments of the invention;

Figure 4 illustrating a switchable biasing circuit in accordance with embodiments of the invention;

Figure 5 illustrating a circuit comprising two NMOS switches connected in tandem with a switchable biasing circuit provided at the source terminals of the NMOS switches in accordance with embodiments of the invention;

Figure 6 illustrating plots representative of the resistance of the NMOS switches when the switches are switched ON over varying drain-source voltages whereby the different plots represent the various tail bias voltages, V_B|As that are provided to the circuit illustrated in Figure 5;

Figure 7 illustrating plots representative of the current flowing through the tail bias circuit illustrated in Figure 5 over varying drain-source voltages whereby the different plots represent the various switchable biasing voltages, V_B|As that are provided to the circuit;

Figure 8 illustrating simulated current and voltage waveforms of biphasic stimulation done using a standard H-bridge stimulation circuit (that does not have a switchable biasing circuit) with and without charge balancing; and

Figure 9 illustrating simulated current and voltage waveforms of biphasic stimulation done using an H-bridge stimulation circuit (having a switchable biasing circuit) in accordance with embodiments of the invention, the plots showing the simulated results with and without charge balancing.

Detailed Description

The H-bridge circuit has at least two pairs of switching elements whereby a first electrode is provided at a first end of the two pairs of switching elements and a second electrode is provided at a second end of the two pairs of switching elements. In operation, the two electrodes would be connected to a tissue that is to be stimulated. The system also includes a switchable biasing circuit that is configured to provide a biasing voltage to a node common to switching elements of one of the pair of switching elements in the H-bridge circuit and the biasing circuit is configured such that it ensures that the switching elements coupled to the node are biased appropriately when the H-bridge circuit is in a charge balancing mode. This ensures that a low-resistance path is able to be formed between the two electrodes during the charge balancing mode to allow the charge stored between the two electrodes to be balanced appropriately.

Figure 1 illustrates a system representative of an extended H-bridge stimulation circuit with a switchable biasing circuit in accordance with embodiments of the invention. In this embodiment of the invention, H-bridge stimulation circuit 101 comprises two stimulation channels, that is stimulation channel pair comprising channel CHO and CH1 , whereby the two stimulation channels are made up of two pairs of switching elements: switching element pair 105 and switching element pair 1 10; as well as switchable biasing circuit 150. Switching element pair 105 comprises two P-type Metal-Oxide-Semiconductor (PMOS) switches, SWP_Q and SWPi while switching element pair 1 10 comprises two N-type Metal-Oxide- Semiconductor (NMOS) switches SWN₀ and SWNi. A switching element may comprise, but is not limited to, a Field Effect Transistor (FET) that is configured to operate as a switch or any other semiconductor devices that may operate as a switch.

Additionally, an electrode ElecO is provided at one end of switching element pairs 105 and 1 10 while another electrode Eled is provided at the other end of switching element pairs 105 and 1 10 as illustrated in Figure 1. Tissue that is to be stimulated by H-bridge circuit 101 is then to be provided between electrodes ElecO and Eled .

In this embodiment of the invention, switchable biasing circuit 150 is configured to provide a biasing voltage to a common node 120 of switching element pair 1 10, i.e. to provide a biasing voltage to source terminals of NMOS switches SWN₀ and SWN_{1 ;} when the charges between electrodes ElecO and Eled are to be balanced. During normal operation of H-bridge circuit 101 , switchable biasing circuit 150 will be switched off so that it will not affect the normal operation of the switches in the H-bridge circuit. Further, H-bridge circuit 101 is also biased by a current source 1 15 that is provided at the source terminals of the NMOS switches SWN₀ and SWNi and a biasing voltage VDDH that is provided at the source terminals of the PMOS switches SWP₀ and SWP^

One skilled in the art will recognize that H-bridge stimulation circuit 101 as described above may be extended to have as many stimulation channel pairs as required. To achieve this, multiples of switching element pairs 105 and 1 10 may be daisy-chained together to produce the extended H-bridge circuit. The detailed workings of a H-bridge circuit will be omitted for brevity in this description as the operation of H-bridge circuits are well known to those skilled in the art.

The charge balancing process will take place when the tissue is not being stimulated and during this process, current source 1 15 will be turned off. The balancing of the charges between these two electrodes may be done by switching the PMOS switches SWP₀ and S\NP^ off while switching the NMOS switches SWN₀ and SWISh on. In order to ensure that the NMOS switches SWN₀ and SWNi are able to switch on properly, switchable biasing circuit 150 is configured to provide a biasing voltage to the source terminals of NMOS switches SWN₀ and SW^.

It should be noted that if a biasing voltage is not provided to the source terminals of NMOS switches SWN₀ and SW^ when the PMOS switches SWP₀ and SWP-i and current source 1 15 are turned off, switches SWN₀ and SWNi will not be able to turn on properly. This is because when the PMOS switches and current source are turned off, the voltage at the source terminals of SWN₀ and SWNi become undefined and is treated as a floating voltage. As a result, the voltage at the source terminals of switches SWN₀ and SWNi become vulnerable to coupling and leakage currents from the other switches in the H-bridge circuit. In particular, when switches SWP₀ and SWPi and current source 1 15 are switched off, these elements are treated as resistors with extremely large resistance values. Hence, when the large resistances of these elements are combined with the voltage VDDH at the power rails, this in turn causes the voltage at the source terminals of switches SWN₀ and SWNi to indirectly increase.

However, when biasing circuit 150 provides a fixed biasing voltage to common node 120, i.e. to the source terminals of the NMOS switches SWN₀ and SWN_{1 ;} this allows these switches to turn on normally even though the PMOS switches SWP₀ and SWPi and the current source 1 15 are turned off. Further, biasing circuit 150 also acts an isolator that isolates electrodes ElecO, Eled and the ground line thereby preventing unintentional discharges or charges from junction parasitic capacitances.

Hence, as the NMOS switches SWN₀ and SWNi are able to turn on properly due to the use of biasing circuit 150, a low-resistance path 160 is formed between electrodes ElecO and Eled through switches SWN₀ and SWNi thereby allowing any stored charge at the electrode-tissue interface to dissipate. Figures 2(a) and (b) illustrate exemplary circuits of switchable biasing circuit 150. One skilled in the art will recognize that switchable biasing circuit 150 may comprise other types of biasing circuits that may be configured to selectively provide a biasing voltage to a node without departing from this invention. The exemplary biasing circuit illustrated in Figure 2(a) comprises a NMOS switch that is configured to provide a voltage V_SRC to the V_BIAS node (or to the common node 120) when the NMOS switch is switched on and the circuit illustrated in Figure 2(b) comprises a similar configuration whereby the NMOS switch is replaced with a PMOS switch that is controlled by a logic-NOT gate. The biasing circuit illustrated in Figure 2(b) is also known as a source follower circuit that is driven by an inverter logic gate whereby the source follower provides a constant output voltage when the switch used in the source follower circuit is switched on.

In embodiments of the invention, the voltage provided by biasing circuit 150 to common node 120 should be similar to the voltage level at the common node 120 when the H-bridge circuit is in its normal mode of operation, i.e. when current source 1 15 is switched on and when the biasing circuit is turned off. In addition to the above, an inrush current resistor may also be connected between the output of biasing circuit 150 and the common node 120 to reduce the initial current surge which may occur whenever the biasing circuit 150 is switched on.

One skilled in the art will recognize that switching element pair 105 and 1 10 may comprise of only NMOS or PMOS switching elements (instead of a PMOS pair and a NMOS pair) provided that the current source 1 15, biasing circuit 150 and power rail V _DDH are all configured accordingly.

Figure 3 illustrates another embodiment of the extended H-bridge stimulation circuit with a switchable biasing circuit in accordance with embodiments of the invention. In this embodiment of the invention, H-bridge stimulation circuit 301 comprises two stimulation channels, that is stimulation channel pair comprising channel CH2 and CH3, whereby the two stimulation channels are made up of two pairs of switching elements: switching element pair 305 and switching element pair 310; as well as switchable biasing circuit 350. Switching element pair 305 comprises two P-type Metal-Oxide-Semiconductor (PMOS) switches, SWP₂ and SWP₃ while switching element pair 310 comprises two N-type Metal-Oxide- Semiconductor (NMOS) switches SWN₂ and SWN₃. An electrode Elec2 is provided at one end of switching element pairs 305 and 310 while another electrode Elec3 is provided at the other end of switching element pairs 305 and 310 as illustrated in Figure 3. Tissue that is to be stimulated by H-bridge circuit 301 is then to be provided between electrodes Elec2 and Elec3.

In this embodiment of the invention, switchable biasing circuit 350 is configured to provide a biasing voltage to a common node 320 of switching element pair 305, i.e. to provide a biasing voltage to source terminals of PMOS switches SWP₂ and SWP₃, when the charges between electrodes Elec2 and Elec3 are to be balanced. During normal operation of H-bridge circuit 301 , switchable biasing circuit 350 will be switched off so that it will not affect the normal operation of the switches in the H-bridge circuit. Further, H-bridge circuit 301 is also biased by a current source 315 that is provided at the source terminals of the PMOS switches SWP₂ and SWP₃ and ground plane is provided at the source terminals of the NMOS switches.

One skilled in the art will recognize that H-bridge stimulation circuit 301 as described above may be extended to have as many stimulation channel pairs as required. To achieve this, multiples of switching element pairs 305 and 310 may be provided to produce the extended H-bridge circuit. The detailed workings of a H-bridge circuit will be omitted for brevity in this description as the operation of H-bridge circuits are well known to those skilled in the art.

When the tissue is not being stimulated, current source 315 will be turned off. The balancing of the charges between these two electrodes may be done by switching the MOS switches SWP₀ and SWP-i on while switching the NMOS switches SWN₀ and SW^ off. In order to ensure that the PMOS switches SWP₂ and SWP₃ are able to switch on properly, switchable biasing circuit 350 is configured to provide a biasing voltage to the source terminals of PMOS switches SWP₂ and SWP₃.

As described above in relation to the previous embodiment of the invention (i.e. in relation to Figure 1 ), when a biasing voltage is not provided to the source terminals of PMOS switches SWP₂ and SWP₃ when the NMOS switches SWN₂ and SWN₃ and current source 315 are turned off, the PMOS switches will not turn on properly.

However, when a fixed biasing voltage is provided to common node 320, i.e. to the source terminals of the PMOS switches, this allows these switches to turn on normally even though the NMOS switches and the current source 315 are turned off. Further, biasing circuit 350 also acts an isolator that isolates electrodes Elec2, Elec3 from the ground line thereby preventing unintentional discharges or charges from junction parasitic capacitances. Hence, as the PMOS switches SWP₂ and SWP₃ are able to turn on properly due to the use of biasing circuit 350, a low-resistance path 360 is formed between electrodes Elec3 and Elec4 through PMOS switches SWP₂ and SWP₃ thereby allowing any stored charge at the electrode-tissue interface to dissipate.

Figures 4(a) and (b) illustrate exemplary circuits of switchable biasing circuit 350. One skilled in the art will recognize that switchable biasing circuit 350 may comprise other types of biasing circuits that may be configured to selectively provide a biasing voltage to a node without departing from this invention. The exemplary biasing circuit illustrated in Figure 4(a) comprises a PMOS switch that is configured to provide a voltage V_SRC to the V_BIAS node (or to the common node 320) when the PMOS switch is switched on and the circuit illustrated in Figure 4(b) comprises a configuration configured to perform a similar function.

In embodiments of the invention, the voltage provided by biasing circuit 350 to common node 320 should be similar to the voltage level at the common node 320 when the H-bridge circuit is in its normal mode of operation, i.e. when current source 315 is switched on and when the biasing circuit is turned off. In addition to the above, an inrush current resistor may also be connected between the output of biasing circuit 350 and the common node 320 to reduce the initial current surge which may occur whenever the biasing circuit 350 is switched on.

One skilled in the art will recognize that switching element pair 305 and 310 may comprise of only PMOS or NMOS switching elements (instead of a PMOS pair and a NMOS pair) provided that the current source 315, biasing circuit 350 and power rail V_DDH are all configured accordingly.

Simulation

Simulations were carried out based on the circuit illustrated in Figure 5 to determine how the ON resistance values, RON.NMOS of the NMOS switches SWN₀ and SW^ would be affected when the biasing voltage applied to common node 520 is varied between 0.5 and 2 Volts. In particular, circuit 500 as illustrated in Figure 5 includes a pair of NMOS switches that are connected in tandem such that the source terminals of these switches are connected to current source 1 15 and biasing circuit 150 while the drain terminals of these switches are connected to a voltage source, V_DS. For the simulation of circuit 500, the current source 1 15 was switched off and the NMOS switches SWN₀ and SW^ were switched on. The biasing voltage V_BIAS provided to node 520 was then varied between 0.5 and 2.0 Volts. The ON resistance value, RON.NMOS, of a NMOS switch was then plotted when the voltage source, V_Ds, was varied between -5 and 5 Volts. The resulting plot 600 is illustrated in Figure 6.

From plots 610, 615 and 620 which were generated when the biasing voltage was at 0.5 Volts, 1 .0 Volts and 1 .5 Volts respectively, it can be seen that the ON resistance value, Fto_M.NMos was less than 1000W when the voltage source V_Ds was between -1 and 1 Volts. The plots also show that if the biasing voltage is higher than 1 .5 Volts, e.g. plot 605 which was generated when the biasing voltage was 2 Volts, the NMOS switches would not be able to attain an ON resistance value RON.NMOS low enough for passive charge balancing to occur. Therefore, biasing circuit 150 has to be configured to provide a suitably low biasing voltage to the common node in order to ensure that the NMOS switches are able to attain the desired low ON resistance values.

Figure 7 illustrates the biasing current, I BIAS, as the voltage source V_DS was varied between -5 and 5 Volts for varying values of biasing voltage V_BIAS- The plots in plot 700 were generated when the current source 1 15 was switched off and the NMOS switches SWN₀ and SW^ were switched on.

From plots 705-720, it can be seen that the biasing current I_BI_AS was observed to be less than 15 pA even though the voltage source V_DS was set to be as high as 5 Volts. As the biasing current is low, this implies that biasing circuit 150 will have high output impedance values when in use. This is advantageous as it causes the electrode-tissue interfaces to be effectively isolated from power rails and external voltage sources during the passive charge balancing process.

In order to determine the effect of the selective biasing circuit on the H-bridge stimulation circuit, a single biphasic stimulation process was simulated using the H-bridge stimulation circuit illustrated in Figure 1 . This simulation assumed that the electrode-tissue interface may be represented by a model comprising a resistor R_F that is connected in parallel with a capacitor C_Di_, and that these two parallel components are connected in series with a resistor R_s. For this simulation, it was assumed that resistance R_s = 2.5kOhm, resistance R_F = 1 MOhm and C_Di_ = 200nF. The pulse widths (T_W|DTH) of both cathodic and anodic pulses were set to 80us and the spacing between two consecutive biphasic stimuli (T _BSTM.SPC) were set to 10ms and the stimulation current was set as I_STIM = 6.2mA.

The simulated results of the stimulation current I_SHM, and stimulation voltage V_SHM are illustrated in Figure 8 for the single biphasic stimulation process. In particular, plot 805 illustrates the stimulation current I_SHM, plot 810 illustrates the stimulation voltage V_SHM when passive charge balancing is disabled, and plot 815 illustrates the stimulation voltage V_SHM when passive charge balancing is enabled. It should be noted that the charge balancing process typically takes place in between the biphasic stimulation phases.

The results show that regardless whether the passive charge balancing process is applied to H-bridge stimulation circuit, the stimulation voltage V_SHM plots of 810 and 815 remain roughly the same. In particular, the simulated plots 810 and 815 show that the stimulation voltage V_SHM were 25.8mV and 23.9mV for plots 810 and 815 respectively after the biphasic stimulation was completed. This occurred as the NMOS switches in the circuit did not switch on during the passive charge balancing process due to the floating voltage at the source terminals of the NMOS switches.

In contrast, when the single biphasic stimulation process was simulated using the same H-bridge stimulation circuit described above, the results obtained were significantly different. Figure 9 shows the simulated results of the stimulation current l_s™, and stimulation voltage V_STIM for the single biphasic stimulation process when a biasing circuit is used to provide a biasing voltage to a common node of the NMOS switches, i.e. the biasing voltage is provided to the source terminals of the NMOS switches. Plot 805 illustrates the stimulation current l_s™, plot 810 illustrates the stimulation voltage V_s™ when passive charge balancing is disabled, and plot 815 illustrates the stimulation voltage V_s™ when passive charge balancing is enabled (with a biasing voltage applied to the source terminals of the NMOS switches). The results show that when the passive charge balancing function is enabled in this simulation, a stimulated voltage V_s™ of 4.2uV is obtained after the biphasic stimulation has ended. Conversely, when the passive charge balancing process is disabled, a stimulation voltage V_s™ of 25.9mV is obtained after the biphasic stimulation has ended. This shows that when the biasing voltage is applied to the common node of the NMOS switches, the NMOS switches are able to switch on properly during the phase balancing process. As a result, stored charges at the electrode-tissue interface were able to balance when a path of low electrical-resistance was formed between the electrodes and through the NMOS switches that were switched on.

The above is a description of embodiments of a system and method in accordance with the present invention as set forth in the following claims. It is envisioned that others may and will design alternatives that fall within the scope of the following claims.

Claims

IB CLAIMS:

1. A charge balancing system comprising:

a H-bridge circuit comprising at least two pairs of switching elements, wherein a first electrode is provided at a first end of the at least two pairs of switching elements and a second electrode is provided at a second end of the at least two pairs of switching elements, the first and second electrodes being configured to be connectable to a tissue for receiving stimulation;

a switchable biasing circuit configured to provide a biasing voltage to a node common to switching elements of one of the at least two pairs of switching elements to enable the switching elements coupled to the node to be turned on,

whereby an electrical shorting path is formed by turning off the switching elements not coupled to the node, turning on the switching elements coupled to the node and by disabling a current source coupled to the node, the electrical shorting path comprising the pair of switching elements that are turned on and the first and second electrodes,

wherein charges on the first and second electrodes are balanced through the electrical shorting path.

2. The system according to claim 1 wherein the at least two pairs of switching elements comprise a pair of P-type Metal Oxide Semiconductor (PMOS) switches and a pair of N- type Metal Oxide Semiconductor (NMOS) switches.

3. The system according to claim 1 wherein the at least two pairs of switching elements comprise two pairs of P-type Metal Oxide Semiconductor (PMOS) switches.

4. The system according to claim 1 wherein the at least two pairs of switching elements comprise two pairs of N-type Metal Oxide Semiconductor (NMOS) switches.

5. The system according to claim 1 wherein the switchable biasing circuit comprises:

a Field Effect Transistor (FET) configured as a switch; and

a voltage source, whereby a constant voltage is provided by the voltage source through the FET when the FET is switched on.

6. The system according to claim 1 wherein the switchable biasing circuit comprises: a PMOS configured as a source follower that is controlled by an inverter coupled to the PMOS’s gate, whereby the PMOS configured as a source follower provides a constant voltage to the node when the PMOS configured as a source follower is turned on.

7. The system according to claim 1 further comprising:

an inrush current resistor provided between the node and the biasing circuit.

8. A method for balancing charges at a first and second electrode in a H-bridge circuit, the circuit having at least two pairs of switching elements, wherein the first electrode is provided at a first end of the at least two pairs of switching elements and the second electrode is provided at a second end of the at least two pairs of switching elements, the method comprising:

providing, using a switchable biasing circuit, a biasing voltage to a node common to switching elements of one of the at least two pairs of switching elements to enable the switching elements coupled to the node to be turned on;

forming an electrical shorting path by turning off the switching elements not coupled to the node, turning on the switching elements coupled to the node and by disabling a current source coupled to the node, the electrical shorting path comprising the pair of switching elements that are turned on and the first and second electrodes,

9. The method according to claim 8 wherein the at least two pairs of switching elements comprise a pair of P-type Metal Oxide Semiconductor (PMOS) switches and a pair of N- type Metal Oxide Semiconductor (NMOS) switches.

10. The method according to claim 8 wherein the at least two pairs of switching elements comprise two pairs of P-type Metal Oxide Semiconductor (PMOS) switches.

1 1 . The method according to claim 8 wherein the at least two pairs of switching elements comprise two pairs of N-type Metal Oxide Semiconductor (NMOS) switches.

12. The method according to claim 8 wherein the providing the biasing voltage to the node comprises the step of: providing a constant voltage from a voltage source to the node through a Field Effect Transistor (FET) configured as a switch when the FET is switched on.

13. The method according to claim 8 wherein the providing the biasing voltage to the node comprises the step of:

providing a constant voltage from a voltage source to the node through a PMOS configured as a source follower, the PMOS being controlled by an inverter coupled to the PMOS’s gate, when the PMOS configured as a source follower is turned on.

14. The method according to claim 8 further comprising:

providing an inrush current resistor between the node and the biasing circuit.