WO2020102212A1

WO2020102212A1 - Plating for thermal management

Info

Publication number: WO2020102212A1
Application number: PCT/US2019/060951
Authority: WO
Inventors: Nazila Dadvand; Christopher Daniel Manack; Salvatore Frank Pavone
Original assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Current assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Priority date: 2018-11-16
Filing date: 2019-11-12
Publication date: 2020-05-22
Anticipated expiration: 2021-05-16
Also published as: US20200365483A1; US10734304B2; US12068221B2; US20200161210A1; CN112889133A

Abstract

Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer (108). The process also includes forming a seed copper layer on the diffusion barrier layer (108). The process also includes forming a copper layer on the seed copper layer (112). The process also includes immersion plating a silver layer on the copper layer (118).

Description

PLATING FOR THERMAL MANAGEMENT

[0001] This disclosure relates generally to thermal management, and, in particular, examples to plating for thermal management.

BACKGROUND

[0002] In electronic packaging, thermal management is an important aspect of packaging design and it considers the issues associated with degradation of a device at high temperatures. Thermal management is becoming more important with the continuous trends for compact and more highly integrated systems having smaller features and higher currents. Conduction is one of the methods of heat transfer from a package or device in which the heat is transferred through a solid medium. The selection of materials used for the device and the substrate influence the ability of the device to conduct the generated heat away.

[0003] [0004] To rapidly transfer heat, heat-sinks such as copper, aluminum, or copper and aluminum alloys can be used. Copper is a better electrical and thermal conductor than aluminum. However, copper oxidizes. The formation of oxide on copper reduces its thermal conductivity. In addition, long term storage of the device after backside electroplating with copper can reduce the plated copper thickness due to corrosion. Copper oxide also has weak adhesion to copper. If the copper oxide separates, it can expose the copper underneath the oxide to air and form an additional oxide layer. Applying a thin layer of tin on copper protects the copper surface from corrosion and allows long storage of the device prior to installation. However, there are disadvantages related to the use of tin. Immersion tin chemistry contains a thiourea which is carcinogenic. Tin plating can create whiskers that present contamination and shorting problems. Tin does not work well with multiple reflow/assembly processes. Tin can aggressively attack solder masks. Tin forms an intermetallic with copper over time that results in the loss of pure tin, which results in degradation of solder performance. The first reflow exposure will dramatically reduce the pure tin thickness and the resulting deposit stress could result in tin whiskers. This is a naturally occurring characteristic of tin in direct contact with copper.

SUMMARY

[0004] In accordance with an example, a process includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

[0005] BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a process flow diagram of an example process.

[0007] FIGS. 2A-K (collectively“FIG. 2”) are schematic diagrams of the process of FIG. 1.

[0008] FIG. 3 is a process flow diagram of an example process.

[0009] FIGS. 4A-K (collectively“FIG. 4”) are schematic diagrams of the process of FIG. 3.

[0010] FIG. 5 is a process flow diagram of an example process.

[0011] FIGS. 6A-L (collectively“FIG. 6”) are schematic diagrams of the process of FIG. 5.

[0012] FIGS. 7A-J are perspective diagrams of an example process.

[0013] FIG. 8 is a chemical diagram of a compound for an example process.

[0014] FIG. 9 is another chemical diagram of the compound of FIG. 8.

[0015] FIGS. 10A-F (collectively“FIG. 10”) are schematic diagrams of example structures using a backside copper contact.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0016] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are not necessarily drawn to scale.

[0017] The term“coupled” may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are“coupled.” [0018] The term“on” may include structures that have intervening components between a first component and the component that the first component is“on.” The terms“encapsulated and encapsulation” are used. As used herein, a semiconductor die can be encapsulated with mold compound by covering at least portions of the semiconductor die and a substrate, such as a lead frame, the semiconductor die is mounted to, with mold compound. There can be portions of the substrate or the semiconductor die, such as external terminals that are formed from portions of the lead frame, that are not covered with the mold compound and yet the package is still described as“encapsulated” and is described as being formed by“encapsulation”, even when some portions are not covered with mold compound.

[0019] FIG. 1 is a process flow diagram of an example process 100 illustrated in FIGS. 2A-K. Step 102 is providing a semiconductor wafer 202 (FIG. 2A) having active components (not shown) and contacts, as shown in FIG. 2A as pillars including titanium-tungsten layer (TiW) 204, seed copper layer 206 and plated copper layer 208. A“semiconductor wafer” is a thin, usually circular slice of semiconductor material such as silicon, gallium arsenide, silicon germanium, III-V and 11-IV compound semiconductor materials. A“seed layer” is a layer deposited to promote preferential growth of a subsequent layer. In this case, copper seed layer 206 provides the nucleation sites for formation of copper layer 208 by, for example, electroless plating. Step 104 is covering the active side of the semiconductor wafer (i.e., the side with active devices and contact pillars) with a protective polymer 210 (FIG. 2B), such as CONDOX, which is commercially available from DISCO Corporation of Japan. The “active side” of a semiconductor wafer is the side where active components such as transistors and diodes are formed.

[0020] Step 106 is thinning semiconductor wafer 202 as shown in FIG. 2C. The thinned semiconductor wafer 202 is 150m thick, for example. In FIG. 2C, the assembly is inverted so that the backside is up. The“backside” is the opposite side of the semiconductor wafer from the active side. Step 108 is depositing a titanium-tungsten (TIW) layer 212 (FIG. 2D) as a diffusion barrier layer using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or another suitable deposition process to a thickness of 50 to 600 nm. A“diffusion barrier layer” is a layer to prevent intermixing of materials. In this case, TiW layer 212 prevents migration of copper into semiconductor wafer 202. Copper seed layer 214 is formed on TiW layer 212 using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or other suitable deposition process to a thickness of 50 to 600 nm.

[0021] Step 110 is forming a patterned layer such as photolithographic layer 216 (FIG. 2E) over the interstices or“streets” between dies when the semiconductor wafer is subsequently diced. A semiconductor wafer is“diced” when it is cut into singulated semiconductor devices or “dies.” The singulated devices may be integrated circuits or individual active components. Step 112 is forming a conductive layer, such as copper layer 218 (FIG. 2F) on the exposed portions of copper seed layer 214 to a thickness of 50 to 600 nm. Copper layer 218 is formed using a plating process such as electroless plating or electrolytic plating.

[0022] Step 114 is removing photolithographic layer 216 as shown in FIG. 2G. Step 116 is etching copper seed layer 214 and TiW layer 212 using copper layer 218 as a mask as shown in FIG. 2H. These layers are etched chemically using appropriate etchant such as mixture of sulfuric acid and ferric chloride for etching copper seed and hydrogen peroxide for etching TiW. Step 118 is forming a silver layer 220 on copper layer 218 as shown in FIG. 21. Silver layer 220 is formed using immersion plating to a thickness of 1m, for example. Immersion plating of silver uses a dissolved salt of silver, such as silver cyanides, silver nitrates and others (See, Torok, et al. “Nanoscale characterization of thin immersion silver coatings on copper substrates,” Cornell University Library arXiv: 1502.01579 [cond-mat.mtrl-sci] (5 February 2015) (available at the uniform resource locator (URL):https://arxiv.org/abs/1502.01579). which is hereby incorporated herein by reference). In addition, the immersion solution can contain chemicals to set pH levels and organic solderability preservatives. Example organic solderability preservatives are discussed in Cole et al., U.S. Patent No. 5,858,074 issued January 12, 1999, which is hereby incorporated herein by reference. The use of organic solderability preservatives improves solder contacts to silver layer 220, as well as improving other types of connections to silver layer 220, such as silver paste. Step 120 dices the semiconductor wafer 202 into individual dies as shown in FIG. 2J. Step 122 removes the polymer 210 to provide the structure in FIG 2K, which is ready for packaging. For example, each die may be encapsulated in an encapsulant such as mold compound except for contacts to the pillars and the surface of silver layer 220. In an example configuration, the surface of layer 220 is soldered to a contact to provide rapid thermal transmission from the die, through copper layer 218 and silver layer 220. Thus, the high thermal conductivity of copper and silver provides good thermal management without the cost of gold plating or the complications tin plating (carcinogenic immersion solution, tin whiskers, intermetallic compound formation and others).

[0023] FIG. 3 is a flow diagram of an example process 300 illustrated in FIGS. 4A-K. Step 302 is forming active devices and contacts in a semiconductor wafer 402 (FIG. 4A). In this example, the contacts are pillars that include TiW layer 404, seed copper layer 406 and plated copper layer 408. Step 304 forms a layer of CONDOX 410 by, for example, a spin-on process to cover the active side of semiconductor wafer 402 (FIG. 4B). Step 306 thins the semiconductor wafer 402 (FIG. 4C) using the TAIKO process. DISCO Corporation of Japan developed the TAIKO process, which thins the semiconductor wafer except for a 3mm rim around the periphery of the semiconductor wafer. The 3mm rim provides stiffness to the entire semiconductor wafer to avoid problems such as die warpage.

[0024] Step 308 is depositing a diffusion barrier layer such as TiW layer 412 on the backside of semiconductor wafer 402 (FIG. 4D) using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or another suitable deposition process to a thickness of 50 to 600 nm. A seed copper layer 414 is then formed on TiW layer 412 using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or another suitable deposition process to a thickness of 50 to 600 nm. Step 310 forms a patterned layer such as photoresist layer 416 on seed copper layer 414 (FIG. 4E). The openings in photoresist layer in this example are less than the area of each die in semiconductor wafer 402. Thus, the photoresist layer covers the area between dies.

[0025] Step 312 is forming conductive layers such as copper layers 418 on the exposed portions of seed copper layer 414 (FIG. 4F) using, for example, electroless or electrolytic plating. Step 314 is forming silver layer 420 on the surface of copper layer 418 (FIG. 4G) using, for example, immersion plating with silver nitrate to a thickness of 1 m, for example. Other salts of silver may be used in other examples. In addition, the immersion solution may include organic solderability preservatives. Step 316 is removing photoresist layer 416 as shown in FIG. 4H.

[0026] Step 318 etches seed copper layer 414 and TiW layer 412 using copper layer 418 and silver layer 420 (FIG. 41) as an etch mask. These layers are etched chemically using appropriate etchant such as mixture of sulfuric acid and ferric chloride for etching copper seed and hydrogen peroxide for etching TiW. Step 320 is dicing semiconductor wafer 402 (FIG. 4J). As noted above, the conductive stack including TiW layer 412, seed copper layer 414, copper layer 418 and silver layer 420 are not in the regions between dies or“streets.” Step 322 is removing CONDOX 410 as shown in FIG. 4K.

[0027] FIG. 5 is a flow diagram of an example process 500 illustrated in FIGS. 6A-L. Step 502 is forming active devices in a semiconductor wafer 602 (FIG. 6A). Step 504 is thinning the backside of semiconductor wafer 602 (FIG. 6B). The backside is the opposite side to the active side, i.e. the side where the active devices are formed. In this example, semiconductor wafer 602 is thinned using the TAIKO process to a thickness of 150m, for example. Step 506 is forming a TiW layer 604 on the active side of semiconductor wafer 602 and a TiW layer 608 on the backside of semiconductor wafer 602. TiW layers 604 and 608 may be formed separately or simultaneously using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or other suitable deposition process to a thickness of 50 to 600 nm. Seed copper layer 606 is formed on TiW layer 604 and seed copper layer 610 is formed on TiW layer 608, either simultaneously or separately, using sputtering, physical vapor deposition (PVD) or chemical vapor deposition (CVD) or another suitable deposition process to a thickness of 50 to 600 nm (FIG. 6C). Step 508 is forming photoresist layer on seed copper layer 606 and seed copper layer 610 as shown in FIG. 6D using, for example, a spin-on process.

[0028] Step 510 is patterning photoresist 612 to provide a patterned layer as shown in FIG. 6E. On the active side of semiconductor wafer 602 over seed copper layer 606, the openings in patterned photoresist correspond to contact points on the semiconductor wafer for contact to the active devices. Step 512 is forming conductive layers such as copper layers 614 and 616 on the exposed portions of seed copper layer 606 and seed copper layer 610 using sputtering, CVD, PVD or another suitable process to a thickness of 50 to 600 nm as shown in FIG. 6F. Step 514 is removing photoresist layer 612 as shown in FIG. 6G. Step 516 is removing the portions of TiW layer 604, seed copper layer 606, TiW layer 608 and seed copper layer 610 that are not covered by copper layers 614 and 616 using, for example, etching chemically using appropriate etchant such as mixture of sulfuric acid and ferric chloride for etching copper seed and hydrogen peroxide for etching TiW as shown in FIG. 6H.

[0029] Step 518 is forming a protective polymer layer 620, such as CONDOX, on the active side of semiconductor wafer 602 (FIG. 61). Step 520 is forming silver layer 622 on copper layer 614 using immersion plating with an organic solderability preservative to a thickness of 1m, for example (FIG. 6J). Step 522 is removing polymer 620 (FIG. 6K). Step 524 is dicing semiconductor wafer 602 as shown in FIG. 6L.

[0030] FIGS. 7A-J are perspective diagrams of an example process like process 100 (FIG. 1). FIG. 7A shows the active side of semiconductor wafer 702. Multiple copper bumps on the active side of semiconductor wafer 702 include TiW layer 704, seed copper layer 706 and copper layer 708. Each of these bumps will provide electrical contact to the active circuitry in a particular die on the semiconductor wafer. FIG. 7B shows formation of an adhesive layer 710, such as CONDOX, on the active side of semiconductor wafer 702. In FIG. 7C, semiconductor wafer 702 is inverted from the view of FIGS. 7A and B. The backside of semiconductor wafer 702 is thinned to a thickness of 150m in this example. TiW layer 712 is deposited on the backside of semiconductor wafer 702 to a thickness of 50 to 600 nm, for example, using sputtering, PVD, CVD or another suitable method. FIG. 7D shows copper seed layer 714, which is deposited to a thickness of 50 to 600 nm, for example, using sputtering, PVD, CVD or another suitable method. [0031] FIG. 7E shows photoresist layer 716, which is spun onto copper seed layer 714. As shown in FIG. 7F, photoresistor layer 716 is patterned to provide a patterned layer including an opening for each die of semiconductor wafer 702. FIG. 7G shows conductive layers such as copper layers 718, which are plated onto the exposed portions of copper seed layer 714 using electroless or electrolytic plating to a thickness of 50 to 600 nm, for example. In an additional example, silver is plated to the surface of copper layers 718 using immersion plating to a thickness of 1m, for example. FIG. 7H shows the resulting structure after the removal of photoresist layer 716. FIG. 71 shows the removal of the portions of copper seed layer 714 and TiW layer 712 by using chemical etchants and using copper layers 718 as an etch mask. FIG. 7J shows semiconductor wafer 702 diced into separate dies. The singulated dies are then encapsulated using an encapsulant such as mold compound, except to leave copper layers 718 and the bumps on the active side exposed. In one example, the solder balls cover the exposed portion of the bumps to provide a ball grid array.

[0032] FIG. 8 is a chemical diagram of one trimethoxysilane radical from (3- mercaptopropyl)trimethoxysilane. The sulfanyl (mercapto) radical (HS) binds the trimethoxysilane radicals to the propyl organic chain as shown in FIG. 9. When dipped in a solution including (3 -mercaptopropyl)trimethoxy silane, the sulfanyl radical mediates the bonding of the trimethoxysilane radical to the surface of the metal, such as copper or silver (as shown in FIG. 9). In one example, the solution includes 97% by volume methanol and 3% by volume (3-mercaptopropyl)trimethoxysilane. The trimethoxysilane radicals provide protection to the surface of the metal and mediates binding of conductive epoxies to the metal. The use of (3-mercaptopropyl)trimethoxysilane mitigates delamination issues between the metal and the conductive epoxies and can eliminate delamination issues. Examples of chemicals that may be substituted for (3-mercaptopropyl)trimethoxysilane are (3-Mercaptopropyl)triethoxysilane, which provides tri ethoxy silane radicals, and (3-Mercaptopropyl)methyldimethoxysilane, which provides methyldimethoxysilane radicals.

[0033] FIGS. 10A-F show examples of semiconductor devices using a backside copper contact. FIG. 10A shows a simple mounting of a semiconductor die 1002 having contacts 1004 and backside copper 1006. Backside copper 1006 may or may not include a silver layer formed by immersion. Backside copper 1006 is mounted to copper substrate 1010 using a conductive paste such as silver paste 1008. By preparing backside copper 1006 with (3- mercaptopropyl)trimethoxysilane as described hereinabove, the bond between backside copper 1006 and silver paste 1008 is improved. Also, the use of backside copper 1006 provides good conduction of heat away from semiconductor die 1002 through backside copper 1006, silver paste 1008 and copper substrate 1010, thus enhancing transfer of heat away from semiconductor die 1002.

[0034] FIG. 10B shows another example configuration. As with the structure of FIG. 10 A, semiconductor die 1002 has contacts 1004 and backside copper 1006. Backside copper 1006 may or may not include a silver layer formed by immersion. Backside copper 1006 is mounted to copper substrate 1010 using silver paste 1008. Preparing backside copper 1006 with (3- mercaptopropyl)trimethoxysilane as described hereinabove improves the bond between backside copper 1006 and silver paste 1008. Also, the use of backside copper 1006 provides good conduction of heat away from semiconductor die 1002 through backside copper 1006, silver paste 1008 and copper substrate 1010, thus enhancing transfer of heat away from semiconductor die 1002. In addition to the structure of FIG. 10A, the structure of FIG. 10B includes an active side copper substrate 1012 and encapsulation structure 1014.

[0035] FIG. IOC shows another example configuration. As with the structure of FIG. 10B, semiconductor die 1002 has contacts 1004 and backside copper 1006. In addition, the structure of FIG. IOC includes active side copper substrate 1012 Backside copper 1006 may or may not include a silver layer formed by immersion. Backside copper 1006 is mounted to copper substrate 1010 using silver paste 1008. Preparing backside copper 1006 with (3- mercaptopropyl)trimethoxy silane improves the bond between backside copper 1006 and silver paste 1008. Also, the use of backside copper 1006 provides good conduction of heat away from semiconductor die 1002 through backside copper 1006, silver paste 1008 and copper substrate 1010, thus enhancing transfer of heat away from semiconductor die 1002. In the structure of FIG. IOC, encapsulation structure 1014 is and encapsulant such as mold compound. As shown in FIG. 10D, using patterned etching, openings 1016 are formed in copper substrate 1010 and active side copper substrate 1012. As shown in FIG. 10E, openings 1016 are used as a mask to etch encapsulation structure 1014 and silver paste 1008 to expose contacts 1004 and backside copper 1006. In FIG. 10F, a suitable deposition technique like sputtering forms copper layers 1018 and 1020 on the active side and back side, respectively. Copper layers 1018 and 1020 are then patterned to provide appropriate connections to contacts 1004 and backside copper 1006. [0036] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

CLAIMS What is claimed is:

1. A process comprising:

forming a diffusion barrier layer on a backside of a semiconductor wafer; forming a seed copper layer on the diffusion barrier layer; forming a copper layer on the seed copper layer; and immersion plating a silver layer on the copper layer.

2. The process of claim 1 in which the diffusion barrier layer is a titanium-tungsten layer.

3. The process of claim 1 in which the backside is opposite an active side and active components are formed in the active side.

4. The process of claim 3 further comprising forming a polymer layer on the active side of the semiconductor wafer.

5. The process of claim 1 in which the immersion plating is in an immersion solution that includes an organic solderability preservative.

6. The process of claim 1 in which the forming a seed copper layer is sputtering the seed copper layer.

7. The process of claim 1 in which the forming a copper layer is plating the copper layer.

8. The process of claim 1 further including: patterning the copper layer, the seed copper layer and the diffusion barrier layer; and dicing the semiconductor wafer.

9. A semiconductor device comprising: a diffusion barrier layer on a backside of a semiconductor die; a seed copper layer on the diffusion barrier layer; a copper layer on the seed copper layer; a silver layer formed by immersion plating on the copper layer; and an encapsulant encapsulating the semiconductor die except for the silver layer.

10. The semiconductor device of claim 9 in which the diffusion barrier layer is a titanium- tungsten layer.

11. The semiconductor device of claim 9 in which the backside is opposite an active side, active components are formed in the active side, and further comprising at least one lead coupled to the active components having a contact not encapsulated by the encapsulant.

12. The semiconductor device of claim 9 in which the immersion plating is in an immersion solution that includes an organic solderability preservative.

13. The semiconductor device of claim 9 in which the seed copper layer is formed by sputtering the seed copper layer.

14. The semiconductor device of claim 9 in which the copper layer is formed by plating the copper layer.

15. The semiconductor device of claim 9 in which the encapsulant is mold compound.

16. The semiconductor device of claim 9 in which the encapsulant is an encapsulation structure.

17. A process comprising: forming a conductive layer on a die; immersing the conductive layer in a solution in (3-mercapto)R, where R is selected from a group of trimethoxysilane, triethoxysilane and methyldimethoxysilane; and adhering a conductive paste to the conductive layer.

18. The process of claim 17 in which the conductive layer is a silver layer.

19. The process of claim 17 in which the conductive paste is silver paste.

20. The process of claim 17 in which the solution is 97% by volume methanol and 3% by volume (3 -mercapto)trimethoxy silane.