WO2020095984A1

WO2020095984A1 - Systems and methods for performing binary arithmetic coding in video coding

Info

Publication number: WO2020095984A1
Application number: PCT/JP2019/043637
Authority: WO
Inventors: Frank Bossen
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2018-11-07
Filing date: 2019-11-07
Publication date: 2020-05-14

Abstract

According to an aspect of an invention, a method comprises determining an initial probability state of bin of a syntax element and entropy encoding the bin of the syntax element using the determined initial probability state.

Description

SYSTEMS AND METHODS FOR PERFORMING BINARY ARITHMETIC CODING IN VIDEO CODING

This disclosure relates to video coding and more particularly to techniques for performing binary arithmetic coding.

Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, laptop or desktop computers, tablet computers, digital recording devices, digital media players, video gaming devices, cellular telephones, including so-called smartphones, medical imaging devices, and the like. Digital video may be coded according to a video coding standard. Video coding standards define the format of a compliant bitstream. A compliant bitstream is data structure that may be received and decoded by a video decoding device to generate reconstructed video data. Video coding standards may incorporate video compression techniques. Examples of video coding standards include ISO/IEC MPEG-4 Visual and ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC) and High-Efficiency Video Coding (HEVC). HEVC is described in High Efficiency Video Coding (HEVC), Rec. ITU-T H.265, December 2016, which is incorporated by reference, and referred to herein as ITU-T H.265. Extensions and improvements for ITU-T H.265 are currently being considered for the development of next generation video coding standards. For example, the ITU-T Video Coding Experts Group (VCEG) and ISO/IEC (Moving Picture Experts Group (MPEG) (collectively referred to as the Joint Video Exploration Team (JVET)) are working to standardized video coding technology with a compression capability that significantly exceeds that of the current HEVC standard. The Joint Exploration Model 7 (JEM 7), Algorithm Description of Joint Exploration Test Model 7 (JEM 7), ISO/IEC JTC1/SC29/WG11 Document: JVET-G1001, July 2017, Torino, IT, which is incorporated by reference herein, describes the coding features that were under coordinated test model study by the JVET as potentially enhancing video coding technology beyond the capabilities of ITU-T H.265. It should be noted that the coding features of JEM 7 are implemented in JEM reference software. As used herein, the term JEM may collectively refer to algorithms included in JEM 7 and implementations of JEM reference software. Further, in response to a “Joint Call for Proposals on Video Compression with Capabilities beyond HEVC,” jointly issued by VCEG and MPEG, multiple descriptions of video coding tools were proposed by various groups at the 10^th Meeting of ISO/IEC JTC1/SC29/WG11 16-20 April 2018, San Diego, CA. From the multiple descriptions of video coding tools, a resulting initial draft text of a video coding specification is described in “Versatile Video Coding (Draft 1),” 10^th Meeting of ISO/IEC JTC1/SC29/WG11 16-20 April 2018, San Diego, CA, document JVET-J1001-v2, which is incorporated by reference herein, and referred to as JVET-J1001. This current development of the a next generation video coding standard by the VCEG and MPEG is referred to as the Versatile Video Coding (VVC) project. “Versatile Video Coding (Draft 4),” 13th Meeting of ISO/IEC JTC1/SC29/WG11 9-18 January 2019, Marrakech, MA, document JVET-M1001-v1, which is incorporated by reference herein, and referred to as JVET-M1001, represents the current iteration of the draft text of a video coding specification corresponding to the VVC project.

Video compression techniques enable data requirements for storing and transmitting video data to be reduced. Video compression techniques may reduce data requirements by exploiting the inherent redundancies in a video sequence. Video compression techniques may sub-divide a video sequence into successively smaller portions (i.e., groups of pictures within a video sequence, a picture within a group of pictures, regions within a picture, sub-regions within regions, etc.). Intra prediction coding techniques (e.g., spatial prediction techniques within a picture) and inter prediction techniques (i.e., inter-picture techniques (temporal)) may be used to generate difference values between a unit of video data to be coded and a reference unit of video data. The difference values may be referred to as residual data. Residual data may be coded as quantized transform coefficients. Syntax elements may relate residual data and a reference coding unit (e.g., intra-prediction mode indices, and motion information). Residual data and syntax elements may be entropy coded. Entropy encoded residual data and syntax elements may be included in data structures forming a compliant bitstream.

In one example, a method comprises determining an initial probability state of bin of a syntax element and entropy encoding the bin of the syntax element using the determined initial probability state.

In one example, a device comprises one or more processors configured to determine an initial probability state of a bin of a syntax element and entropy decode the bin of the syntax element using the determined initial probability state.

FIG. 1 is a conceptual diagram illustrating an example of a group of pictures coded according to a quad tree multi-tree partitioning in accordance with one or more techniques of this disclosure. FIG. 2A is conceptual diagram illustrating example of coding a block of video data in accordance with one or more techniques of this disclosure. FIG. 2B is conceptual diagram illustrating example of coding a block of video data in accordance with one or more techniques of this disclosure. FIG. 3 is a block diagram illustrating an example of a system that may be configured to encode and decode video data according to one or more techniques of this disclosure. FIG. 4 is a block diagram illustrating an example of a video encoder that may be configured to encode video data according to one or more techniques of this disclosure. FIG. 5 is a block diagram illustrating an example of a entropy encoder that may be configured to encode video data according to one or more techniques of this disclosure. FIG. 6 is a block diagram illustrating an example of a video decoder that may be configured to decode video data according to one or more techniques of this disclosure. FIG. 7 is a block diagram illustrating an example of a entropy decoder that may be configured to encode video data according to one or more techniques of this disclosure. FIG. 8 is a conceptual diagram illustrating an example of a group of pictures coded according to a quad tree binary tree partitioning in accordance with one or more techniques of this disclosure.

In general, this disclosure describes various techniques for coding video data. In particular, this disclosure describes techniques for performing binary arithmetic coding. It should be noted that although techniques of this disclosure are described with respect to ITU-T H.264, ITU-T H.265, JEM, and JVET-M1001 the techniques of this disclosure are generally applicable to video coding. For example, the coding techniques described herein may be incorporated into video coding systems, (including video coding systems based on future video coding standards) including video block structures, intra prediction techniques, inter prediction techniques, transform techniques, filtering techniques, and/or entropy coding techniques other than those included in ITU-T H.265, JEM, and JVET-M1001. Thus, reference to ITU-T H.264, ITU-T H.265, JEM, and/or JVET-M1001 is for descriptive purposes and should not be construed to limit the scope of the techniques described herein. Further, it should be noted that incorporation by reference of documents herein is for descriptive purposes and should not be construed to limit or create ambiguity with respect to terms used herein. For example, in the case where an incorporated reference provides a different definition of a term than another incorporated reference and/or as the term is used herein, the term should be interpreted in a manner that broadly includes each respective definition and/or in a manner that includes each of the particular definitions in the alternative.

In one example, a device comprises one or more processors configured to determine an initial probability state of a bin of a syntax element and entropy encode the bin of the syntax element using the determined initial probability state.

In one example, a non-transitory computer-readable storage medium comprises instructions stored thereon that, when executed, cause one or more processors of a device to determine an initial probability state of a bin of a syntax element and entropy encode the bin of the syntax element using the determined initial probability state.

In one example, an apparatus comprises means for determining an initial probability state of a bin of a syntax element and means for entropy encoding the bin of the syntax element using the determined initial probability state.

In one example, a method comprises determining an initial probability state of a bin of a syntax element and entropy decoding the bin of the syntax element using the determined initial probability state.

In one example, a non-transitory computer-readable storage medium comprises instructions stored thereon that, when executed, cause one or more processors of a device to determine an initial probability state of a bin of a syntax element and entropy decode the bin of the syntax element using the determined initial probability state.

In one example, an apparatus comprises means for determining an initial probability state of a bin of a syntax element and means for entropy decoding the bin of the syntax element using the determined initial probability state.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

Video content typically includes video sequences comprised of a series of frames (or pictures). A series of frames may also be referred to as a group of pictures (GOP). Each video frame or picture may include a plurality of slices or tiles, where a slice or tile includes a plurality of video blocks. As used herein, the term video block may generally refer to an area of a picture or may more specifically refer to the largest array of sample values that may be predictively coded, sub-divisions thereof, and/or corresponding structures. Further, the term current video block may refer to an area of a picture being encoded or decoded. A video block may be defined as an array of sample values that may be predictively coded. It should be noted that in some cases pixel values may be described as including sample values for respective components of video data, which may also be referred to as color components, (e.g., luma (Y) and chroma (Cb and Cr) components or red, green, and blue components). It should be noted that in some cases, the terms pixel value and sample value are used interchangeably. Video blocks may be ordered within a picture according to a scan pattern (e.g., a raster scan). A video encoder may perform predictive encoding on video blocks and sub-divisions thereof. Video blocks and sub-divisions thereof may be referred to as nodes.

A video sampling format, which may also be referred to as a chroma format, may define the number of chroma samples included in a CU with respect to the number of luma samples included in a CU. For example, for the 4:2:0 sampling format, the sampling rate for the luma component is twice that of the chroma components for both the horizontal and vertical directions. As a result, for a CU formatted according to the 4:2:0 format, the width and height of an array of samples for the luma component are twice that of each array of samples for the chroma components. As described above, a CU is typically defined according to the number of horizontal and vertical luma samples. For a CU formatted according to the 4:2:2 format, the width of an array of samples for the luma component is twice that of the width of an array of samples for each chroma component, but the height of the array of samples for the luma component is equal to the height of an array of samples for each chroma component. Further, for a CU formatted according to the 4:4:4 format, an array of samples for the luma component has the same width and height as an array of samples for each chroma component.

ITU-T H.264 specifies a macroblock including 16x16 luma samples. That is, in ITU-T H.264, a picture is segmented into macroblocks. ITU-T H.265 specifies an analogous Coding Tree Unit (CTU) structure (which may be referred to as a largest coding unit (LCU)). In ITU-T H.265, pictures are segmented into CTUs. In ITU-T H.265, for a picture, a CTU size may be set as including 16x16, 32x32, or 64x64 luma samples. In ITU-T H.265, a CTU is composed of respective Coding Tree Blocks (CTB) for each component of video data (e.g., luma (Y) and chroma (Cb and Cr). It should be noted that video having one luma component and the two corresponding chroma components may be described as having two channels, i.e., a luma channel and a chroma channel. Further, in ITU-T H.265, a CTU may be partitioned according to a quadtree (QT) partitioning structure, which results in the CTBs of the CTU being partitioned into Coding Blocks (CB). That is, in ITU-T H.265, a CTU may be partitioned into quadtree leaf nodes. According to ITU-T H.265, one luma CB together with two corresponding chroma CBs and associated syntax elements are referred to as a coding unit (CU). In ITU-T H.265, a minimum allowed size of a CB may be signaled. In ITU-T H.265, the smallest minimum allowed size of a luma CB is 8x8 luma samples. In ITU-T H.265, the decision to code a picture area using intra prediction or inter prediction is made at the CU level.

In ITU-T H.265, a CU is associated with a prediction unit (PU) structure having its root at the CU. In ITU-T H.265, PU structures allow luma and chroma CBs to be split for purposes of generating corresponding reference samples. That is, in ITU-T H.265, luma and chroma CBs may be split into respective luma and chroma prediction blocks (PBs), where a PB includes a block of sample values for which the same prediction is applied. In ITU-T H.265, a CB may be partitioned into 1, 2, or 4 PBs. ITU-T H.265 supports PB sizes from 64x64 samples down to 4x4 samples. In ITU-T H.265, square PBs are supported for intra prediction, where a CB may form the PB or the CB may be split into four square PBs (i.e., intra prediction PB types include MxM or M/2xM/2, where M is the height and width of the square CB). In ITU-T H.265, in addition to the square PBs, rectangular PBs are supported for inter prediction, where a CB may by halved vertically or horizontally to form PBs (i.e., inter prediction PB types include MxM, M/2xM/2, M/2xM, or MxM/2). Further, it should be noted that in ITU-T H.265, for inter prediction, four asymmetric PB partitions are supported, where the CB is partitioned into two PBs at one quarter of the height (at the top or the bottom) or width (at the left or the right) of the CB (i.e., asymmetric partitions include M/4xM left, M/4xM right, MxM/4 top, and MxM/4 bottom). Intra prediction data (e.g., intra prediction mode syntax elements) or inter prediction data (e.g., motion data syntax elements) corresponding to a PB is used to produce reference and/or predicted sample values for the PB.

JEM specifies a CTU having a maximum size of 256x256 luma samples. JEM specifies a quadtree plus binary tree (QTBT) block structure. In JEM, the QTBT structure enables quadtree leaf nodes to be further partitioned by a binary tree (BT) structure. That is, in JEM, the binary tree structure enables quadtree leaf nodes to be recursively divided vertically or horizontally. FIG. 8 illustrates an example of a CTU (e.g., a CTU having a size of 256x256 luma samples) being partitioned into quadtree leaf nodes and quadtree leaf nodes being further partitioned according to a binary tree. That is, in FIG. 8 dashed lines indicate additional binary tree partitions in a quadtree. Thus, the binary tree structure in JEM enables square and rectangular leaf nodes, where each leaf node includes a CB. As illustrated in FIG. 8, a picture included in a GOP may include slices, where each slice includes a sequence of CTUs and each CTU may be partitioned according to a QTBT structure. FIG. 8 illustrates an example of QTBT partitioning for one CTU included in a slice. In JEM, CBs are used for prediction without any further partitioning. That is, in JEM, a CB may be a block of sample values on which the same prediction is applied. Thus, a JEM QTBT leaf node may be analogous a PB in ITU-T H.265.

As described above, each video frame or picture may divided into one or more regions. For example, according to ITU-T H.265, each video frame or picture may be partitioned to include one or more slices and further partitioned to include one or more tiles, where each slice includes a sequence of CTUs (e.g., in raster scan order) and where a tile is a sequence of CTUs corresponding to a rectangular area of a picture. It should be noted that a slice, in ITU-T H.265, is a sequence of one or more slice segments starting with an independent slice segment and containing all subsequent dependent slice segments (if any) that precede the next independent slice segment (if any) within the same access unit. A slice segment, like a slice, is a sequence of CTUs. Thus, in some cases, the terms slice and slice segment may be used interchangeably to indicate a sequence of CTUs. Further, it should be noted that in ITU-T H.265, a tile may consist of CTUs contained in more than one slice and a slice may consist of CTUs contained in more than one tile. However, ITU-T H.265 provides that one or both of the following conditions shall be fulfilled: (1) All CTUs in a slice belong to the same tile; and (2) All CTUs in a tile belong to the same slice. With respect to JVET-M1001, slices are required to consist of an integer number of complete tiles instead of only being required to consist of an integer number of complete CTUs. As such, a slice including a set of CTUs which do not form a rectangular region of a picture may or may not be supported in some video coding techniques. Further, a slice that is required to consist of an integer number of complete tiles is referred to as a tile group. The techniques described herein may applicable to slices, tiles, and/or tile groups. FIG. 1 is a conceptual diagram illustrating an example of a group of pictures including tile groups. In the example illustrated in FIG. 1, Pic₃is illustrated as including two tile groups (i.e., Tile Group₁ and Tile Group₂). It should be noted that in some cases, Tile Group₁ and Tile Group₂ may be classified as slices and/or tiles.

JEM specifies a CTU having a maximum size of 256x256 luma samples. JEM specifies a quadtree plus binary tree (QTBT) block structure. In JEM, the QTBT structure enables quadtree leaf nodes to be further partitioned by a binary tree (BT) structure. That is, in JEM, the binary tree structure enables quadtree leaf nodes to be recursively divided vertically or horizontally. In JVET-M1001, CTUs are partitioned according a quadtree plus multi-type tree (QTMT) structure. The QTMT in JVET-M1001 is similar to the QTBT in JEM. However, in JVET-M1001, in addition to indicating binary splits, the multi-type tree may indicate so-called ternary (or triple tree (TT)) splits. A ternary split divides a block vertically or horizontally into three blocks. In the case of a vertical TT split, a block is divided at one quarter of its width from the left edge and at one quarter its width from the right edge and in the case of a horizontal TT split a block is at one quarter of its height from the top edge and at one quarter of its height from the bottom edge. Referring again to FIG. 1, FIG. 1 illustrates an example of a CTU being partitioned into quadtree leaf nodes and quadtree leaf nodes being further partitioned according to a BT split or a TT split. That is, in FIG. 1 dashed lines indicate additional binary and ternary splits in a quadtree.

For intra prediction coding, an intra prediction mode may specify the location of reference samples within a picture. In ITU-T H.265, defined possible intra prediction modes include a planar (i.e., surface fitting) prediction mode (predMode: 0), a DC (i.e., flat overall averaging) prediction mode (predMode: 1), and 33 angular prediction modes (predMode: 2-34). In JEM, defined possible intra-prediction modes include a planar prediction mode (predMode: 0), a DC prediction mode (predMode: 1), and 65 angular prediction modes (predMode: 2-66). It should be noted that planar and DC prediction modes may be referred to as non-directional prediction modes and that angular prediction modes may be referred to as directional prediction modes. It should be noted that the techniques described herein may be generally applicable regardless of the number of defined possible prediction modes.

For inter prediction coding, a motion vector (MV) identifies reference samples in a picture other than the picture of a video block to be coded and thereby exploits temporal redundancy in video. For example, a current video block may be predicted from reference block(s) located in previously coded frame(s) and a motion vector may be used to indicate the location of the reference block. A motion vector and associated data may describe, for example, a horizontal component of the motion vector, a vertical component of the motion vector, a resolution for the motion vector (e.g., one-quarter pixel precision, one-half pixel precision, one-pixel precision, two-pixel precision, four-pixel precision), a prediction direction and/or a reference picture index value. Further, a coding standard, such as, for example ITU-T H.265, may support motion vector prediction. Motion vector prediction enables a motion vector to be specified using motion vectors of neighboring blocks. Examples of motion vector prediction include advanced motion vector prediction (AMVP), temporal motion vector prediction (TMVP), so-called “merge” mode, and “skip” and “direct” motion inference. Additional examples of motion vector prediction include advanced temporal motion vector prediction (ATMVP) and Spatial-temporal motion vector prediction (STMVP).

As described above, intra prediction data or inter prediction data is used to produce reference sample values for a block of sample values. The difference between sample values included in a current PB, or another type of picture area structure, and associated reference samples (e.g., those generated using a prediction) may be referred to as residual data. Residual data may include respective arrays of difference values corresponding to each component of video data. Residual data may be in the pixel domain. A transform, such as, a discrete cosine transform (DCT), a discrete sine transform (DST), an integer transform, a wavelet transform, or a conceptually similar transform, may be applied to an array of difference values to generate transform coefficients. In some cases, a transform process may include rotation, and/or performance of one or more one dimensional transforms. It should be noted that in ITU-T H.265 and JVET-M1001, a CU is associated with a transform unit (TU) structure having its root at the CU level. That is, in ITU-T H.265, an array of difference values may be partitioned for purposes of generating transform coefficients (e.g., four 8x8 transforms may be applied to a 16x16 array of residual values). For each component of video data, such sub-divisions of difference values may be referred to as Transform Blocks (TBs). It should be noted that in some cases, a core transform and a subsequent secondary transforms may be applied (in the video encoder) to generate transform coefficients. It should be noted that in ITU-T H.265, TBs are not necessarily aligned with PBs. Further, it should be noted that in ITU-T H.265, TBs may have the following sizes 4x4, 8x8, 16x16, and 32x32. It should be noted that in JEM, residual values corresponding to a CB are used to generate transform coefficients without further partitioning. That is, in JEM a QTBT leaf node may be analogous to both a PB and a TB in ITU-T H.265. It should be noted that in JEM, a core transform and a subsequent secondary transforms may be applied (in the video encoder) to generate transform coefficients. For a video decoder, the order of transforms is reversed. Further, in JEM, whether a secondary transform is applied to generate transform coefficients may be dependent on a prediction mode.

A quantization process may be performed on transform coefficients or residual sample values directly, e.g., in the case of palette coding quantization. Quantization approximates transform coefficients by amplitudes restricted to a set of specified values. Quantization essentially scales transform coefficients in order to vary the amount of data required to represent a group of transform coefficients. Quantization may include division of transform coefficients (or resulting values of addition of an offset value to transform coefficients) by a quantization scaling factor and any associated rounding functions (e.g., rounding to the nearest integer). Quantized transform coefficients may be referred to as coefficient level values. Inverse quantization (or “dequantization”) may include multiplication of coefficient level values by the quantization scaling factor, and any reciprocal rounding or offset addition operations. It should be noted that as used herein the term quantization process in some instances may refer to division by a scaling factor to generate level values and multiplication by a scaling factor to recover transform coefficients in some instances. That is, a quantization process may refer to quantization in some cases and inverse quantization in some cases. Further, it should be noted that although in some of the examples below quantization processes are described with respect to arithmetic operations associated with decimal notation, such descriptions are for illustrative purposes and should not be construed as limiting. For example, the techniques described herein may be implemented in a device using binary operations and the like. For example, multiplication and division operations described herein may be implemented using bit shifting operations and the like.

With respect to the equations used herein, the following arithmetic operators may be used:

Further, the following logical operators may be used:

Further, the following relational operators may be used:

Further, the following bit-wise operators may be used:

Further, the following assignment operators may be used:

Further, the following defined mathematical functions may be used:

FIGS. 2A-2B are conceptual diagrams illustrating examples of coding a block of video data. As illustrated in FIG. 2A, a current block of video data (e.g., a CB corresponding to a video component) is encoded by generating a residual by subtracting a set of prediction values from the current block of video data, performing a transformation on the residual, and quantizing the transform coefficients to generate level values. As illustrated in FIG. 2B, the current block of video data is decoded by performing inverse quantization on level values, performing an inverse transform, and adding a set of prediction values to the resulting residual. It should be noted that in the examples in FIGS. 2A-2B, the sample values of the reconstructed block differs from the sample values of the current video block that is encoded. In this manner, coding may said to be lossy. However, the difference in sample values may be considered acceptable or imperceptible to a viewer of the reconstructed video.

Further, as illustrated in FIGS. 2A-2B, coefficient level values are generated using an array of scaling factors. In ITU-T H.265, an array of scaling factors is generated by selecting a scaling matrix and multiplying each entry in the scaling matrix by a quantization scaling factor. In ITU-T H.265, a scaling matrix is selected based in part on a prediction mode and a color component, where scaling matrices of the following sizes are defined: 4x4, 8x8, 16x16, and 32x32. It should be noted that in some examples, a scaling matrix may provide the same value for each entry (i.e., all coefficients are scaled according to a single value). In ITU-T H.265, the value of a quantization scaling factor, may be determined by a quantization parameter, QP. In ITU-T H.265, for a bit-depth of 8-bits, the QP can take 52 values from 0 to 51 and a change of 1 for QP generally corresponds to a change in the value of the quantization scaling factor by approximately 12%. Further, in ITU-T H.265, a QP value for a set of transform coefficients may be derived using a predictive quantization parameter value (which may be referred to as a predictive QP value or a QP predictive value) and an optionally signaled quantization parameter delta value (which may be referred to as a QP delta value or a delta QP value). In ITU-T H.265, a quantization parameter may be updated for each CU and a respective quantization parameter may be derived for each of the luma and chroma channels.

Referring again to FIG. 2A, quantized transform coefficients are coded into a bitstream. Quantized transform coefficients and syntax elements (e.g., syntax elements indicating a coding structure for a video block) may be entropy coded according to an entropy coding technique. An entropy coding process includes coding values of syntax elements using lossless data compression algorithms. Examples of entropy coding techniques include content adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), probability interval partitioning entropy coding (PIPE), and the like. Entropy encoded quantized transform coefficients and corresponding entropy encoded syntax elements may form a compliant bitstream that can be used to reproduce video data at a video decoder. An entropy coding process, for example, CABAC, may include performing a binarization on syntax elements. Binarization refers to the process of converting a value of a syntax element into a series of one or more bits. These bits may be referred to as “bins.” Binarization may include one or a combination of the following coding techniques: fixed length coding, unary coding, truncated unary coding, truncated Rice coding, Golomb coding, k-th order exponential Golomb coding, and Golomb-Rice coding. For example, binarization may include representing the integer value of 5 for a syntax element as 00000101 using an 8-bit fixed length binarization technique or representing the integer value of 5 as 11110 using a unary coding binarization technique. As used herein each of the terms fixed length coding, unary coding, truncated unary coding, truncated Rice coding, Golomb coding, k-th order exponential Golomb coding, and Golomb-Rice coding may refer to general implementations of these techniques and/or more specific implementations of these coding techniques. For example, a Golomb-Rice coding implementation may be specifically defined according to a video coding standard, for example, ITU-T H.265.

In the example of CABAC in ITU-T H.265, for a particular bin, a context index provides an 8-bit variable, initValue. initValue is used to determine an initial most probable state (MPS) value for the bin (i.e., an MPS for a bin is one of 0 or 1) and a probability value of the bin being the least probably state (LPS). For example, a context index may indicate, at an initial state, that the MPS of a bin is 0 and the probability of the bin being 1 is 0.3. It should be noted that a context index may be selected based on values of previously coded syntax elements. For example, values of syntax elements associated with neighboring video blocks may be used to determine a context index.

In particular, ITU-T H.265 provides where initValue is used in the initialization of variables pStateIdx and valMps, where pStateIdx indicates a probability value and valMps indicates an LPS. In particular, initial values of pStateIdx and valMps are derived based on values of initValue as follows:

It should be noted that in ITU-T H.265, a variable initType, which may have values of 0, 1, or 2, is determined based on slice type (i.e., whether a slice is a I slice, a P slice, or a B slice ) and a CABAC initialization flag which is signaled in the picture parameter set (PPS). initType essentially determines a subset of possible context index value for a bin. For example, an initType value of 0 may indicates a context index is one of 0, 1, or 2, an initType value of 1 may indicate a context index is one of 3, 4, or 5, and initType value of 2 may indicate a context index is one of 6, 7, or 8. It should be noted that for a bin, difference context values do not necessary correspond to unique values of initValue.

In a manner similar to ITU-T H.265, JVET-M1001 uses an 8-bit variable, initValue to determine an initial most probable state (MPS) value for the bin and a probability value of the bin being the least probably state (LPS).

Binary arithmetic coding codes a series of 0’s and 1’s based on the principle of recursive interval subdivision. Essentially, for a binary string (b₁,...,b_N), for an interval having an initial width (range) R₀, for (b₁,...,b_N), R₀ is recursively divided as follows:

As illustrated above, R_i is determined based on whether the observed value of b_i is the MPS or LPS. For example, for b₁ if R₀ is 512, the LPS is 0, and pLPS₁*R₀ is 158, if b₁ is observed to be 1, R₁ = 354 and if b₁ is observed to be 0, R₁ = 158. As described above, in ITU-T H.265, a context index provides an MPS value for a bin and a probability value of the bin being the LPS, where the probability value of the bin being the LPS (i.e., pLPS) is indicated by one of 64 probability states. In particular, in ITU-T H.265, pStateIdx, is indexed such that, pStateIdx = 0 corresponds to a maximum LPS probability value, and decreasing LPS probabilities are indexed to higher values of pStateIdx. Further, in ITU-T H.265, R₀is 512 which can be represented by 9-bits. However, R_i is quantized to a set {Q1,...,Q4} such that all possible values of pLPS_i*R_i-1are pre-computed and indexed according to a 64x4 look-up table.

During encoding, after an interval for R_i is determined, i.e., based on pLPS_i and the observed value of b_i, a renormalization process occurs. A renormalization process essentially determines whether bits are output (e.g., written to a bitstream) based on the value of R_i. Essentially, in renormalization, if R_i falls below a threshold value, and R_i is doubled and a bit value may be output. For example, in encoder side renormalization process described in ITU-T H.265, a determination is made if R_i is less than 256. If R_i is not less than 256, no bits are written to the bitstream and R_i+1is computed for b_i+1, using R_i. If R_i is less than 256, a 0-bit, a 1-bit, or no bit is conditionally written to the bitstream based on the lower end of the sub-interval, and R_i is doubled, and R_i+1is computed for b_i+1(i.e., based on the doubled value of R_i). A binary decoder receiving the output bits (i.e., the arithmetic code) recovers the binary string (b₁,...,b_N) by performing the same interval sub-division at each b_i as an encoder and by comparing subsets of the arithmetic code to R_i values.

In ITU-T H.265, the observed value of a bin is used to update the context index. ITU-T H.265 provides the following with respect to updating the context index based on the determined value of the bin:

Thus, in ITU-T H.265, if the bin value is determined to be equal to the MPS, the LPS probability value is decreased. If the bin value is determined to be equal to the LPS, the LPS probability value is increased and further, if the current probability state pLPS is 0.5 (i.e., pStateIdx equals 0), a LPS inversion occurs (i.e., the previous LPS value becomes the MPS). It should be noted, that according to ITU-T H.265, some syntax elements are entropy coded using arithmetic coding according to equal probability states, such coding may be referred to as bypass coding. In JVET-M1001 binary arithmetic coding is performed in a similar manner as ITU-T H.265.

Further, in one example, for each context variable, two variables pStateL and pStateH may be initialized as follows, where the variables pStateL and pStateH correspond to probability states presented at a low and a high precision, respectively.

Further, in one example, for each context variable, two variables pStateL and pStateH may be initialized as follows:

With respect to pStateL and pStateH the arithmetic decoding process for a binary decision may be as follows:

With respect to pStateL and pStateH the state update process may be as follows:

Tables 3-24 illustrate the tile group data syntax as currently expressed in JVET-M1001. It should be noted that as currently expressed in JVET-M1001 may refer to as currently being described in JVET-M1001 and/or as currently being implemented in the corresponding reference software. Further, it should be noted that with respect to Tables 3-24, the descriptor ae(v) refers to a context-adaptive arithmetic entropy-coded syntax element. Further, for each syntax element in Tables 3-24, a binarization is provided.

Tables 3A etc. illustrate the slice data syntax as currently expressed in JVET-L1001. It should be noted that as currently expressed in JVET-L1001 may refer to as currently being described in JVET-L1001 and/or as currently being implemented in the corresponding reference software. Further, it should be noted that with respect to Tables 3A etc., the descriptor ae(v) refers to a context-adaptive arithmetic entropy-coded syntax element. Further, for each syntax element in Tables 3A etc. , a binarization is provided.

FL refers to a fixed-length binarization with cMax as an input. An FL binarization is constructed by using the fixedLength bit unsigned integer bin string of the symbol value symbolVal, where fixedLength = Ceil( Log2( cMax + 1 ) ). The indexing of bins for the FL binarization is such that the binIdx = 0 relates to the most significant bit with increasing values of binIdx towards the least significant bit.

TR refers to a Truncated Rice binarization process with cMax and cRiceParam as an inputs. A TR binarization A TR bin string is a concatenation of a prefix bin string and, when present, a suffix bin string. For the derivation of the prefix bin string, the following applies:

TB refers to a Truncated Binary (TB) binarization with value synVal and cMax as inputs. The bin string of the TB binarization process of a syntax element synVal is specified as follows:

EGk refers to a k-th order Exp-Golomb (EGk) binarization. The bin string of the EGk binarization process for each value symbolVal is specified as follows, where each call of the function put( X ), with X being equal to 0 or 1, adds the binary value X at the end of the bin string:

In Tables 3-24, if Specified is provided as the binarization for a syntax element, the binarization is provided with the semantics of the syntax element below.

Table 3 illustrates the coding tree unit syntax in JVET-M1001 and Table 3 illustrates the dual tree implicit quadtree split syntax in JVET-M1001.

In Tables 3A etc. , if Specified is provided as the binarization for a syntax element, the binarization is provided with the semantics of the syntax element below.

Table 3A illustrates the coding tree unit syntax in JVET-L1001 and Table 4A illustrates the dual tree implicit quadtree split syntax in JVET-L1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 3.

Table 5 illustrates the sample adaptive offset syntax in JVET-M1001.

Table 5A illustrates the sample adaptive offset syntax in JVET-L1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 5.

Table 7A illustrates the coding quadtree syntax in JVET-L1001.

JVET-L1001 provides the following definitions for the respective syntax elements illustrated in Table 7A

Table 8 illustrates the Coding tree syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 8.

Table 8A illustrates the multi type tree syntax in JVET-L1001.

JVET-L1001 provides the following definitions for the respective syntax elements illustrated in Table 8A.

Table 10 illustrates the coding unit syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 10.

Table 10A illustrates the coding unit syntax in JVET-L1001.

JVET-L1001 provides the following definitions for the respective syntax elements illustrated in Table 10A.

Table 17 illustrates the PCM sample syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 17.

Table 18 illustrates the merge data syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 18.

Table 21 illustrates the motion vector difference syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 21.

Table 22 illustrates the transform tree syntax in JVET-M1001 and Table 23 illustrates the transform unit syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 23.

JVET-L1001 provides the following definitions for the respective syntax elements illustrated in Table 23A.

Table 24 illustrates the residual coding syntax in JVET-M1001.

JVET-M1001 provides the following definitions for the respective syntax elements illustrated in Table 24.

Table 24A illustrates the residual coding syntax in JVET-L1001.

JVET-L1001 provides the following definitions for the respective syntax elements illustrated in Table 24A.

As described above, JVET-M1001 uses an 8-bit variable, initValue to determine an initial most probable state (MPS) value for the bin and a probability value of the bin being the least probably state (LPS). With respect to the each of the syntax elements described above with respect to Tables 2-24, Table 26 provides for each bin of the respective syntax element (indicated by binIdx) whether the bin is: bypass coded (i.e., arithmetic code according to equal probability states); or specifies a ctxInc value for the bin. The ctxInc is used in conjunction with Table 28 and a respective tables to determine an initValue for a bin. It should be noted that in Table 26 when more than one value is provided ctxInc in Table 26, the assignment process is further specified.

As described above, JVET-L1001 uses an 8-bit variable, initValue to determine an initial most probable state (MPS) value for the bin and a probability value of the bin being the least probably state (LPS). With respect to the each of the syntax elements described above with respect to Tables 3A etc., Table 26A provides for each bin of the respective syntax element (indicated by binIdx) whether the bin is: bypass coded (i.e., arithmetic code according to equal probability states); or specifies a ctxInc value for the bin. The ctxInc is used in conjunction with Table 28A and respective Tables 24C-63C to determine an initValue for a bin. It should be noted that in Table 26A when more than one value is provided ctxInc in Table 26A, the assignment process is further specified.

With respect to alf_ctb_flag in Table 19, the derivation of ctxInc may be as provided “Specification draft for Adaptive Loop Filter,” 11th Meeting of ISO/IEC JTC1/SC29/WG11 10-18 July 2018, Ljubljana, SI, document JVET-K0564-v1, which is provided in Table 26B.

With respect to alf_ctb_flag, split_qt_flag, split_cu_flag, cu_skip_flag, amvr_flag, merge_subblock_flag, merge_triangle_flag, and inter_affine_flag the derivation of ctxInc may be as follows:

With respect to merge_affine_flag, inter_affine_flag, and amvr_mode in Table 19, the derivation of ctxInc may be as provided in Table 27B.

With respect to last_sig_coeff_x_prefix and last_sig_coeff_y_prefix in Table 26, the derivation of ctxInc may be as follows:

With respect to tu_cbf_luma in Table 26, the derivation of ctxInc may be as follows:

With respect to coded_sub_block_flag in Table 26, the derivation of ctxInc may be as follows:

With respect to sig_coeff_flag, par_level_flag, abs_level_gt1_flag, and abs_level_gt3_flag in Table 26, the derivation of ctxInc may be based on the variables locNumSig and locSumAbsPass1 which may be derived as follows:

With respect to sig_coeff_flag, par_level_flag, rem_abs_gt1_flag, and rem_abs_gt2_flag, in Table 26A, the derivation of ctxInc may be as provided in “CE7: Transform coefficient coding with reduced number of regular-coded bins (tests 7.1.3a, 7.1.3b),” 12th Meeting of ISO/IEC JTC1/SC29/WG11 3-12 October 2018, Macao, CN, document JVET-L0274-v4, which for the sake of brevity is not repeated herein.

With respect to mts_idx, in Table 26A, the derivation of ctxInc may be as follows:

With respect to sig_coeff_flag in Table 26, the derivation of ctxInc may be as follows:

With respect to par_level_flag, abs_level_gt1_flag, and abs_level_gt3_flag in Table 26, the derivation of ctxInc may be as follows:

As provided above, for each non-bypass bin in Table 26, a ctxInc value is specified. Table 28 provides a ctxIdxOffest value for each ctxInc specified in Table 26. Where the ctxIdxOffset value is the lowest value specified in an entry for an initType. The derivation of initType depends on the value of the cabac_init_flag syntax element and initType is derived as follows:

As provided above, for each non-bypass bin in Table 26A, a ctxInc value is specified. Table 28A provides a ctxIdxOffest value for each ctxInc specified in Table 26A. Where the ctxIdxOffset value is the lowest value specified in an entry for an initType. The derivation of initType depends on the value of the cabac_init_flag syntax element and initType is derived as follows:

For each for each non-bypass bin in Table 26, the sum of ctxInc derived from Table 26 and ctxIdxOffset derived from Table 28 provide an entry in one of respective at which an initValue is provided.

For each for each non-bypass bin in Table 26A, the sum of ctxInc derived from Table 26A and ctxIdxOffest derived from Table 28A provided an entry in one of respective tables 24C-63C at which a initValue is provided.

With respect to the context coded bins, Tables 24C-63C provide the value of initValue specified in JVET-L1001 for each context index.

The values of initValue specified in JVET-L1001 for syntax element may be less than ideal.

With respect to the context coded bins, the value of initValue specified in JVET-M1001 for each context index may be less than ideal or yet to be defined.

FIG. 3 is a block diagram illustrating an example of a system that may be configured to code (i.e., encode and/or decode) video data according to one or more techniques of this disclosure. System 100 represents an example of a system that may perform video coding using partitioning techniques described according to one or more techniques of this disclosure. As illustrated in FIG. 3, system 100 includes source device 102, communications medium 110, and destination device 120. In the example illustrated in FIG. 3, source device 102 may include any device configured to encode video data and transmit encoded video data to communications medium 110. Destination device 120 may include any device configured to receive encoded video data via communications medium 110 and to decode encoded video data. Source device 102 and/or destination device 120 may include computing devices equipped for wired and/or wireless communications and may include set top boxes, digital video recorders, televisions, desktop, laptop, or tablet computers, gaming consoles, mobile devices, including, for example, “smart” phones, cellular telephones, personal gaming devices, and medical imagining devices.

Communications medium 110 may include any combination of wireless and wired communication media, and/or storage devices. Communications medium 110 may include coaxial cables, fiber optic cables, twisted pair cables, wireless transmitters and receivers, routers, switches, repeaters, base stations, or any other equipment that may be useful to facilitate communications between various devices and sites. Communications medium 110 may include one or more networks. For example, communications medium 110 may include a network configured to enable access to the World Wide Web, for example, the Internet. A network may operate according to a combination of one or more telecommunication protocols. Telecommunications protocols may include proprietary aspects and/or may include standardized telecommunication protocols. Examples of standardized telecommunications protocols include Digital Video Broadcasting (DVB) standards, Advanced Television Systems Committee (ATSC) standards, Integrated Services Digital Broadcasting (ISDB) standards, Data Over Cable Service Interface Specification (DOCSIS) standards, Global System Mobile Communications (GSM) standards, code division multiple access (CDMA) standards, 3rd Generation Partnership Project (3GPP) standards, European Telecommunications Standards Institute (ETSI) standards, Internet Protocol (IP) standards, Wireless Application Protocol (WAP) standards, and Institute of Electrical and Electronics Engineers (IEEE) standards.

Storage devices may include any type of device or storage medium capable of storing data. A storage medium may include a tangible or non-transitory computer-readable media. A computer readable medium may include optical discs, flash memory, magnetic memory, or any other suitable digital storage media. In some examples, a memory device or portions thereof may be described as non-volatile memory and in other examples portions of memory devices may be described as volatile memory. Examples of volatile memories may include random access memories (RAM), dynamic random access memories (DRAM), and static random access memories (SRAM). Examples of non-volatile memories may include magnetic hard discs, optical discs, floppy discs, flash memories, or forms of electrically programmable memories (EPROM) or electrically erasable and programmable (EEPROM) memories. Storage device(s) may include memory cards (e.g., a Secure Digital (SD) memory card), internal/external hard disk drives, and/or internal/external solid state drives. Data may be stored on a storage device according to a defined file format.

Referring again to FIG. 3, source device 102 includes video source 104, video encoder 106, and interface 108. Video source 104 may include any device configured to capture and/or store video data. For example, video source 104 may include a video camera and a storage device operably coupled thereto. Video encoder 106 may include any device configured to receive video data and generate a compliant bitstream representing the video data. A compliant bitstream may refer to a bitstream that a video decoder can receive and reproduce video data therefrom. Aspects of a compliant bitstream may be defined according to a video coding standard. When generating a compliant bitstream video encoder 106 may compress video data. Compression may be lossy (discernible or indiscernible) or lossless. Interface 108 may include any device configured to receive a compliant video bitstream and transmit and/or store the compliant video bitstream to a communications medium. Interface 108 may include a network interface card, such as an Ethernet card, and may include an optical transceiver, a radio frequency transceiver, or any other type of device that can send and/or receive information. Further, interface 108 may include a computer system interface that may enable a compliant video bitstream to be stored on a storage device. For example, interface 108 may include a chipset supporting Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe) bus protocols, proprietary bus protocols, Universal Serial Bus (USB) protocols, I²C, or any other logical and physical structure that may be used to interconnect peer devices.

Referring again to FIG. 3, destination device 120 includes interface 122, video decoder 124, and display 126. Interface 122 may include any device configured to receive a compliant video bitstream from a communications medium. Interface 108 may include a network interface card, such as an Ethernet card, and may include an optical transceiver, a radio frequency transceiver, or any other type of device that can receive and/or send information. Further, interface 122 may include a computer system interface enabling a compliant video bitstream to be retrieved from a storage device. For example, interface 122 may include a chipset supporting PCI and PCIe bus protocols, proprietary bus protocols, USB protocols, I²C, or any other logical and physical structure that may be used to interconnect peer devices. Video decoder 124 may include any device configured to receive a compliant bitstream and/or acceptable variations thereof and reproduce video data therefrom. Display 126 may include any device configured to display video data. Display 126 may comprise one of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display. Display 126 may include a High Definition display or an Ultra High Definition display. It should be noted that although in the example illustrated in FIG. 3, video decoder 124 is described as outputting data to display 126, video decoder 124 may be configured to output video data to various types of devices and/or sub-components thereof. For example, video decoder 124 may be configured to output video data to any communication medium, as described herein.

FIG. 4 is a block diagram illustrating an example of video encoder 200 that may implement the techniques for encoding video data described herein. It should be noted that although example video encoder 200 is illustrated as having distinct functional blocks, such an illustration is for descriptive purposes and does not limit video encoder 200 and/or sub-components thereof to a particular hardware or software architecture. Functions of video encoder 200 may be realized using any combination of hardware, firmware, and/or software implementations. In one example, video encoder 200 may be configured to encode video data according to the techniques described herein. Video encoder 200 may perform intra prediction coding and inter prediction coding of picture areas, and, as such, may be referred to as a hybrid video encoder. In the example illustrated in FIG. 4, video encoder 200 receives source video blocks. In some examples, source video blocks may include areas of picture that has been divided according to a coding structure. For example, source video data may include macroblocks, CTUs, CBs, sub-divisions thereof, and/or another equivalent coding unit. In some examples, video encoder 200 may be configured to perform additional sub-divisions of source video blocks. It should be noted that some techniques described herein may be generally applicable to video coding, regardless of how source video data is partitioned prior to and/or during encoding. In the example illustrated in FIG. 4, video encoder 200 includes summer 202, transform coefficient generator 204, coefficient quantization unit 206, inverse quantization/transform processing unit 208, summer 210, intra prediction processing unit 212, inter prediction processing unit 214, filter unit 216, and entropy encoding unit 218.

As illustrated in FIG. 4, video encoder 200 receives source video blocks and outputs a bitstream. Video encoder 200 may generate residual data by subtracting a predictive video block from a source video block. Summer 202 represents a component configured to perform this subtraction operation. In one example, the subtraction of video blocks occurs in the pixel domain. Transform coefficient generator 204 applies a transform, such as a discrete cosine transform (DCT), a discrete sine transform (DST), or a conceptually similar transform, to the residual block or sub-divisions thereof (e.g., four 8x8 transforms may be applied to a 16x16 array of residual values) to produce a set of residual transform coefficients. Transform coefficient generator 204 may be configured to perform any and all combinations of the transforms included in the family of discrete trigonometric transforms. As described above, in ITU-T H.265, TBs are restricted to the following sizes 4x4, 8x8, 16x16, and 32x32. In one example, transform coefficient generator 204 may be configured to perform transformations according to arrays having sizes of 4x4, 8x8, 16x16, and 32x32. In one example, transform coefficient generator 204 may be further configured to perform transformations according to arrays having other dimensions. In particular, in some cases, it may be useful to perform transformations on rectangular arrays of difference values. In one example, transform coefficient generator 204 may be configured to perform transformations according to the following sizes of arrays: 2x2, 2x4N, 4Mx2, and/or 4Mx4N. In one example, a 2-dimensional (2D) MxN inverse transform may be implemented as 1-dimensional (1D) M-point inverse transform followed by a 1D N-point inverse transform. In one example, a 2D inverse transform may be implemented as a 1D N-point vertical transform followed by a 1D N-point horizontal transform. In one example, a 2D inverse transform may be implemented as a 1D N-point horizontal transform followed by a 1D N-point vertical transform. Transform coefficient generator 204 may output transform coefficients to coefficient quantization unit 206.

Coefficient quantization unit 206 may be configured to perform quantization of the transform coefficients. As described above, the degree of quantization may be modified by adjusting a quantization parameter. Coefficient quantization unit 206 may be further configured to determine quantization parameters and output QP data (e.g., data used to determine a quantization group size and/or delta QP values) that may be used by a video decoder to reconstruct a quantization parameter to perform inverse quantization during video decoding. It should be noted that in other examples, one or more additional or alternative parameters may be used to determine a level of quantization (e.g., scaling factors). The techniques described herein may be generally applicable to determining a level of quantization for transform coefficients corresponding to a component of video data based on a level of quantization for transform coefficients corresponding another component of video data.

Referring again to FIG. 4, quantized transform coefficients are output to inverse quantization/transform processing unit 208. Inverse quantization/transform processing unit 208 may be configured to apply an inverse quantization and an inverse transformation to generate reconstructed residual data. As illustrated in FIG. 4, at summer 210, reconstructed residual data may be added to a predictive video block. In this manner, an encoded video block may be reconstructed and the resulting reconstructed video block may be used to evaluate the encoding quality for a given prediction, transformation, and/or quantization. Video encoder 200 may be configured to perform multiple coding passes (e.g., perform encoding while varying one or more of a prediction, transformation parameters, and quantization parameters). The rate-distortion of a bitstream or other system parameters may be optimized based on evaluation of reconstructed video blocks. Further, reconstructed video blocks may be stored and used as reference for predicting subsequent blocks.

As described above, a video block may be coded using an intra prediction. Intra prediction processing unit 212 may be configured to select an intra prediction mode for a video block to be coded. Intra prediction processing unit 212 may be configured to evaluate a frame and/or an area thereof and determine an intra prediction mode to use to encode a current block. As illustrated in FIG. 4, intra prediction processing unit 212 outputs intra prediction data (e.g., syntax elements) to entropy encoding unit 218 and transform coefficient generator 204. As described above, a transform performed on residual data may be mode dependent. As described above, possible intra prediction modes may include planar prediction modes, DC prediction modes, and angular prediction modes. Further, in some examples, a prediction for a chroma component may be inferred from an intra prediction for a luma prediction mode. Inter prediction processing unit 214 may be configured to perform inter prediction coding for a current video block. Inter prediction processing unit 214 may be configured to receive source video blocks and calculate a motion vector for PUs of a video block. A motion vector may indicate the displacement of a PU (or similar coding structure) of a video block within a current video frame relative to a predictive block within a reference frame. Inter prediction coding may use one or more reference pictures. Further, motion prediction may be uni-predictive (use one motion vector) or bi-predictive (use two motion vectors). Inter prediction processing unit 214 may be configured to select a predictive block by calculating a pixel difference determined by, for example, sum of absolute difference (SAD), sum of square difference (SSD), or other difference metrics. As described above, a motion vector may be determined and specified according to motion vector prediction. Inter prediction processing unit 214 may be configured to perform motion vector prediction, as described above. Inter prediction processing unit 214 may be configured to generate a predictive block using the motion prediction data. For example, inter prediction processing unit 214 may locate a predictive video block within a frame buffer (not shown in FIG. 4). It should be noted that inter prediction processing unit 214 may further be configured to apply one or more interpolation filters to a reconstructed residual block to calculate sub-integer pixel values for use in motion estimation. Inter prediction processing unit 214 may output motion prediction data for a calculated motion vector to entropy encoding unit 218. As illustrated in FIG. 4, inter prediction processing unit 214 may receive reconstructed video block via filter unit 216. Filter unit 216 may be configured to perform deblocking and/or Sample Adaptive Offset (SAO) filtering. Deblocking refers to the process of smoothing the boundaries of reconstructed video blocks (e.g., make boundaries less perceptible to a viewer). SAO filtering is a non-linear amplitude mapping that may be used to improve reconstruction by adding an offset to reconstructed video data.

Referring again to FIG. 4, entropy encoding unit 218 receives quantized transform coefficients and predictive syntax data (i.e., intra prediction data, motion prediction data, QP data, etc.). It should be noted that in some examples, coefficient quantization unit 206 may perform a scan of a matrix including quantized transform coefficients before the coefficients are output to entropy encoding unit 218. In other examples, entropy encoding unit 218 may perform a scan. Entropy encoding unit 218 may be configured to perform entropy encoding according to one or more of the techniques described herein. Entropy encoding unit 218 may be configured to output a compliant bitstream, i.e., a bitstream that a video decoder can receive and reproduce video data therefrom.

FIG. 5 is a block diagram illustrating an example of an entropy encoder that may be configured to encode values of syntax elements according to one or more techniques of this disclosure. Entropy encoding unit 300 may include a context adaptive entropy encoding unit, e.g., a CABAC encoder. As illustrated in FIG. 5, entropy encoder 300 includes binarization unit 302, binary arithmetic encoding unit 304, and context modeling unit 310. Entropy encoding unit 300 may receive one or more syntax elements values and output a compliant bitstream. As described above, binarization includes representing a value of syntax element in to a bin string. Binarization unit 302 may be configured to receive a value for a syntax element and produce a bin string according to one or more binarization techniques. Binarization unit 302 may use, for example, any one or combination of the following techniques to produce a bin string: fixed length coding, unary coding, truncated unary coding, truncated Rice coding, Golomb coding, exponential Golomb coding, and Golomb-Rice coding.

As described above, binary arithmetic encoding codes a series of 0’s and 1’s based on the principle of recursive interval subdivision, where for a received binary string (b₁,...,b_N), an interval R₀ is recursively divided based on the estimated probability of b_i being the LPS, and bits are written to a bitstream according to a renormalization process. As further described above, the estimated probability of b_i being the LPS is based on a context index. Binary arithmetic encoding unit 304 is configured to receive a bin string from binarization unit 302 and a context index corresponding to a bin from context modeling unit 306, and perform binary arithmetic encoding on the bin string. That is, binary arithmetic encoding unit 304 is configured to write bits to a bitstream according to a renormalization process and further indicate an observed value of a bin such that a context model may be updated. The context models may be defined according to a video coding standard, such as for example, ITU-T H.265. The context models may be stored in a memory. For example, context modeling unit 306 may store a series of indexed tables and/or utilize mapping functions to determine a context model for a particular bin. It should be noted that the functions of binary coding are not limited to particular function blocks and the example of binary arithmetic encoding unit 304 and context modeling unit 306 in the example FIG. 5 should not be construed as limiting.

As described above, the values of initValue specified in JVET-M1001 for syntax elements may be less than ideal. According to the techniques herein, in one example, the values of initValue for respective syntax element may be as provided in Tables 29-87 and Tables 29A-87A. It should be noted that in Tables 29-87, initValues correspond to the example initialization of variables pStateL and pStateH as provided above in paragraphs and in Tables 29A-87A initValues correspond to the example initialization of variables pStateL and pStateH as provided above in paragraphs.

As described above, the values of initValue specified in JVET-L1001 for syntax elements may be less than ideal. According to the techniques herein, in one example, the values of initValue for respective syntax element may be as provided in Tables 64B-103B.

In this manner, video encoder 200 represents an example of a device configured to determine an initial probability state of bin of a syntax element and entropy encode the bin of the syntax element using the determined initial probability state.

FIG. 6 is a block diagram illustrating an example of a video decoder that may be configured to decode video data according to one or more techniques of this disclosure. In one example, video decoder 400 may be configured to reconstruct video data based on one or more of the techniques described above. That is, video decoder 400 may operate in a reciprocal manner to video encoder 200 described above. Video decoder 400 may be configured to perform intra prediction decoding and inter prediction decoding and, as such, may be referred to as a hybrid decoder. In the example illustrated in FIG. 6 video decoder 400 includes an entropy decoding unit 402, inverse quantization unit 404, inverse transformation processing unit 406, intra prediction processing unit 408, inter prediction processing unit 410, summer 412, filter unit 414, and reference buffer 416. Video decoder 400 may be configured to decode video data in a manner consistent with a video encoding system, which may implement one or more aspects of a video coding standard. It should be noted that although example video decoder 400 is illustrated as having distinct functional blocks, such an illustration is for descriptive purposes and does not limit video decoder 400 and/or sub-components thereof to a particular hardware or software architecture. Functions of video decoder 400 may be realized using any combination of hardware, firmware, and/or software implementations.

As illustrated in FIG. 6, entropy decoding unit 402 receives an entropy encoded bitstream. Entropy decoding unit 402 may be configured to decode quantized syntax elements and quantized coefficients from the bitstream according to a process reciprocal to an entropy encoding process. Entropy decoding unit 402 may be configured to perform entropy decoding according any of the entropy coding techniques described above. Entropy decoding unit 402 may parse an encoded bitstream in a manner consistent with a video coding standard. Video decoder 400 may be configured to parse an encoded bitstream where the encoded bitstream is generated based on the techniques described above.

FIG. 7 is a block diagram illustrating an example entropy decoding unit that may implement one or more of the techniques described in this disclosure. Entropy decoding unit 500 receives an entropy encoded bitstream and decodes syntax elements from the bitstream. As illustrated in FIG. 7, entropy decoding unit 500 includes a binary arithmetic decoding module 502, a context modeling unit 504 and a binarization unit 506. Entropy decoding unit 500 may perform reciprocal functions to entropy encoding unit 300 described above with respect to FIG. 5.

As shown in FIG. 7, context modeling unit 508 and a binarization unit 506 receive a request for a syntax element value. Context modeling unit 504 determines a context index for the syntax element. Further, context modeling unit 504 updates a context index based on the determination made by binary arithmetic decoding module 502, for example, according to the probability estimate techniques described above. Binary arithmetic decoding module 502 receives n bits from the bitstream, i.e., the arithmetic code, and outputs a sequence of parsed bins based on the arithmetic code and the calculated sub-intervals. Binarization unit 506 determines possible valid binarization values for a syntax element and uses a bin matching function to determine if a series parsed bin values corresponds to a valid value for the syntax element. When a series bin values corresponds to a valid value for the syntax element, the value of the syntax element is output. That is, entropy decoding unit 500 is configured to determine the value of a bin based on the current sub-interval and bits from the bitstream, where the current sub-interval is determined based on techniques described herein, for example, probability estimation techniques described herein.

In this manner, video decoder 400 represents an example of a device configured to determine an initial probability state of bin of a syntax element and entropy decode the bin of the syntax element using the determined initial probability state.

Referring again to FIG. 6, inverse quantization unit 404 receives quantized transform coefficients (i.e., level values) and quantization parameter data from entropy decoding unit 402. Quantization parameter data may include any and all combinations of delta QP values and/or quantization group size values and the like described above. Video decoder 400 and/or inverse quantization unit 404 may be configured to determine QP values used for inverse quantization based on values signaled by a video encoder and/or through video properties and/or coding parameters. That is, inverse quantization unit 404 may operate in a reciprocal manner to coefficient quantization unit 206 described above. For example, inverse quantization unit 404 may be configured to infer predetermined values), allowed quantization group sizes, and the like, according to the techniques described above. Inverse quantization unit 404 may be configured to apply an inverse quantization. Inverse transform processing unit 406 may be configured to perform an inverse transformation to generate reconstructed residual data. The techniques respectively performed by inverse quantization unit 404 and inverse transform processing unit 406 may be similar to techniques performed by inverse quantization/transform processing unit 208 described above. Inverse transform processing unit 406 may be configured to apply an inverse DCT, an inverse DST, an inverse integer transform, Non-Separable Secondary Transform (NSST), or a conceptually similar inverse transform processes to the transform coefficients in order to produce residual blocks in the pixel domain. Further, as described above, whether a particular transform (or type of particular transform) is performed may be dependent on an intra prediction mode. As illustrated in FIG. 6, reconstructed residual data may be provided to summer 412. Summer 412 may add reconstructed residual data to a predictive video block and generate reconstructed video data. A predictive video block may be determined according to a predictive video technique (i.e., intra prediction and inter frame prediction).

Intra prediction processing unit 408 may be configured to receive intra prediction syntax elements and retrieve a predictive video block from reference buffer 416. Reference buffer 416 may include a memory device configured to store one or more frames of video data. Intra prediction syntax elements may identify an intra prediction mode, such as the intra prediction modes described above. In one example, intra prediction processing unit 308 may reconstruct a video block using according to one or more of the intra prediction coding techniques described herein. Inter prediction processing unit 410 may receive inter prediction syntax elements and generate motion vectors to identify a prediction block in one or more reference frames stored in reference buffer 416. Inter prediction processing unit 410 may produce motion compensated blocks, possibly performing interpolation based on interpolation filters. Identifiers for interpolation filters to be used for motion estimation with sub-pixel precision may be included in the syntax elements. Inter prediction processing unit 410 may use interpolation filters to calculate interpolated values for sub-integer pixels of a reference block. Filter unit 414 may be configured to perform filtering on reconstructed video data. For example, filter unit 414 may be configured to perform deblocking and/or SAO filtering, as described above with respect to filter unit 216. Further, it should be noted that in some examples, filter unit 414 may be configured to perform proprietary discretionary filter (e.g., visual enhancements). As illustrated in FIG. 6, a reconstructed video block may be output by video decoder 400.

In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

Moreover, each functional block or various features of the base station device and the terminal device used in each of the aforementioned embodiments may be implemented or executed by a circuitry, which is typically an integrated circuit or a plurality of integrated circuits. The circuitry designed to execute the functions described in the present specification may comprise a general-purpose processor, a digital signal processor (DSP), an application specific or general application integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic, or a discrete hardware component, or a combination thereof. The general-purpose processor may be a microprocessor, or alternatively, the processor may be a conventional processor, a controller, a microcontroller or a state machine. The general-purpose processor or each circuit described above may be configured by a digital circuit or may be configured by an analogue circuit. Further, when a technology of making into an integrated circuit superseding integrated circuits at the present time appears due to advancement of a semiconductor technology, the integrated circuit by this technology is also able to be used.

Various examples have been described. These and other examples are within the scope of the following claims.

<Cross Reference>
This Nonprovisional application claims priority under 35 U.S.C. § 119 on provisional Application No. 62/757,054 on November 7, 2018, No. 62/757,669 on November 8, 2018, No. 62/790,763 on January 10, 2019, No. 62/803,239 on February 8, 2019, No. 62/815,980 on March 8, 2019, No. 62/803,734 on November 2, 2019 the entire contents of which are hereby incorporated by reference.

WHAT IS CLAIMED IS:

Claims

A method of entropy encoding, the method comprising:
determining an initial probability state of a bin of a syntax element; and
entropy encoding the bin of the syntax element using the determined initial probability state.
A method of entropy decoding, the method comprising:
determining an initial probability state of a bin of a syntax element; and
entropy decoding the bin of the syntax element using the determined initial probability state.
The method of any of claims 1 or 2 where an initial probability state of a bin of a syntax element includes one of the initial probability states specified herein.
The method of any of claims 1 or 2 where determining an initial probability state of a bin of a syntax element includes determining the initial probability state based on one of the tables specified herein.
A device for coding video data, the device comprising one or more processors configured to perform any and all combinations of the steps of claims 1-4.
The device of claim 5, wherein the device includes a video encoder.
The device of claim 5, wherein the device includes a video decoder.
A system comprising:
the device of claim 6; and
the device of claim 7.
An apparatus for coding video data, the apparatus comprising means for performing any and all combinations of the steps of claims 1-4.
A non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed, cause one or more processors of a device for coding video data to perform any and all combinations of the steps of claims 1-4.