WO2020093476A1

WO2020093476A1 - Data driving circuit and liquid crystal display

Info

Publication number: WO2020093476A1
Application number: PCT/CN2018/117755
Authority: WO
Inventors: 吴苗发; 胡雪; 乔红玉; 王天娇
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2018-11-06
Filing date: 2018-11-27
Publication date: 2020-05-14
Also published as: CN109410854A

Abstract

A data driving circuit, comprising: a data driving unit (10) comprising an analog buffer (12) and a multiplier (11), two output ends of the analog buffer (12) being connected to two input ends of the multiplier (11) respectively; a first switch unit (20), one end of which is connected to one common node of the analog buffer (12) and the multiplier (11), and the other end thereof is grounded; and a second switch unit (30), one end of which is connected to the other node of the analog buffer (12) and the multiplier (11), and the other end thereof is grounded.

Description

Data driving circuit and liquid crystal display

Technical field

The present application relates to the field of liquid crystal display, in particular to a data driving circuit and a liquid crystal display.

Background technique

In the prior art, the analog buffer module in the data driver chip converts the low-load-capacity voltage converted and output by the DAC into a high-load-capacity analog voltage, and the analog data signal is transferred to the output multiplexer after the driving capacity is improved In the device; the liquid crystal requires AC voltage drive, so the polarity of the pixel voltage is positive and negative alternating with respect to the Vcom potential. In heavy load mode, the data drive voltage rises from V2 to the positive polarity voltage V1 at the first TP falling edge, and falls to the negative polarity V2 at the next TP falling edge, and the data drive voltage rises to high voltage V1 from the TP falling edge The rise time is shorter, the power consumption is larger, and the same is true when the voltage drops, so the Source IC temperature is higher, and there is a risk of burning the IC.

Therefore, the existing technology has defects and needs to be improved urgently.

technical problem

The purpose of the present application is to provide a data driving circuit and a liquid crystal display, which have the effect of reducing the temperature of the data driving chip under a heavy load screen.

Technical solution

An embodiment of the present application provides a data driving circuit, including:

A driving unit, the driving unit is used for accessing a data driving signal, which includes an analog buffer and a multiplier, and two output terminals of the analog buffer are respectively connected to two input terminals of the multiplier;

A first switching unit, one end of the first switching unit is connected to a common node of the analog buffer and the multiplier, and the other end of the first switching unit is grounded through a first storage capacitor;

A second switching unit, one end of the second switching unit is connected to the analog buffer and another common node of the multiplier, and the other end of the second switching unit is grounded through a second storage capacitor;

Between the rising and falling edges of the Nth high level of the data driving signal, the output voltage of the analog buffer first rises from the first preset voltage to the second preset voltage, and then after the falling edge arrives Rise from the second preset voltage to the third preset voltage;

Between the rising edge and the falling edge of the N + 1 high level of the data driving signal, the voltage of the output terminal of the analog buffer first drops from the third preset voltage to the second preset voltage, and then on the falling edge After the arrival, the second preset voltage drops to the first preset voltage, where N is an odd number;

Both the first switch unit and the second switch unit are field effect transistors.

In the data driving circuit described in this application, during the Nth high level and the N + 1th high level, the output terminal voltage of the analog buffer is maintained at the third preset voltage.

In the data driving circuit described in this application, at the rising edge of the Nth high level, the first switching unit is turned on, and the first storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second The preset voltage, the first switching unit is turned off at the falling edge of the Nth high level, the output terminal voltage of the analog buffer rises to the third preset voltage, at the rising edge of the N + 1th high level , The first switching unit is turned on, and the output terminal voltage of the analog buffer simultaneously charges the first storage capacitor;

At the rising edge of the Nth high level, the second switching unit is opened, and the second storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second preset voltage, at the Nth high level When the falling edge of the second switch unit is closed, the output voltage of the analog buffer rises to a third preset voltage, and at the rising edge of the N + 1 high level, the second switch unit is opened and the analog buffer The voltage at the output terminal of the converter simultaneously charges the second storage capacitor.

In the data driving circuit described in this application, the driving unit further includes a shift register, a second buffer, a level shifter, and a D \ A converter;

The shift register, the second buffer, the level shifter, the D \ A converter, and the analog buffer are connected in sequence.

In the data driving circuit described in this application, the second buffer is a line buffer.

In the data driving circuit described in this application, both the first switch unit and the second switch unit are NMOS transistors.

In the data driving circuit described in the present application, the data driving circuit further includes a sub-control chip, and the sub-control chip is connected to the control terminals of the first switch unit and the second switch unit.

An embodiment of the present application further provides a data driving circuit, including:

In the second switching unit, one end of the second switching unit is connected to the analog buffer and another common node of the multiplier, and the other end of the second switching unit is grounded through a second storage capacitor.

In the data driving circuit described in this application, between the rising and falling edges of the Nth high level of the data driving signal, the voltage at the output end of the analog buffer first rises from the first preset voltage to the second A preset voltage, and then rises from the second preset voltage to the third preset voltage after the falling edge comes;

Between the rising edge and the falling edge of the N + 1 high level of the data driving signal, the voltage of the output terminal of the analog buffer first drops from the third preset voltage to the second preset voltage, and then on the falling edge After the arrival, the second preset voltage drops to the first preset voltage, where N is an odd number.

In the data driving circuit described in this application, both the first switching unit and the second switching unit are field effect transistors.

The data driving circuit described in the present application further includes a sub-control chip connected to the control terminals of the first switch unit and the second switch unit.

An embodiment of the present application further provides a liquid crystal display, which includes a data driving circuit, and the data driving circuit includes:

In the liquid crystal display described in this application, between the rising edge and the falling edge of the Nth high level of the data driving signal, the voltage at the output end of the analog buffer first rises from the first preset voltage to the second Set voltage, and then rise from the second preset voltage to the third preset voltage after the falling edge comes;

In the liquid crystal display of the present application, during the Nth high level and the N + 1th high level, the output terminal voltage of the analog buffer is maintained at the third preset voltage.

In the liquid crystal display of the present application, at the rising edge of the Nth high level, the first switching unit is opened, and the first storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second pre- Set the voltage, the first switch unit is turned off at the falling edge of the Nth high level, the output terminal voltage of the analog buffer rises to the third preset voltage, and at the rising edge of the N + 1th high level, The first switch unit is turned on, and the voltage at the output end of the analog buffer simultaneously charges the first storage capacitor;

Beneficial effect

The present application improves the data voltage utilization rate through the charging and discharging of the first storage capacitor and the second storage capacitor, and reduces the temperature of the data driving chip under the heavy load screen.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments or the technical solutions in the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the application For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without paying any creative labor.

FIG. 1 is a schematic structural diagram of a data driving circuit in an embodiment of the present application.

FIG. 2 is a driving timing diagram of the data driving circuit in the embodiment of the present application.

Embodiments of the invention

The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary, and are only used to explain the present application, and cannot be construed as limiting the present application.

In the description of this application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back, "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise" etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it cannot be understood as a limitation to this application. In addition, the terms “first” and “second” are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise specifically limited.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or integrally connected; may be mechanical, electrical, or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediary, may be the connection between two elements or the interaction of two elements relationship. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

In this application, unless otherwise clearly specified and defined, the first feature "above" or "below" the second feature may include the direct contact of the first and second features, or may include the first and second features Contact not directly but through another feature between them. Moreover, the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature is "below", "below" and "below" the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.

The following disclosure provides many different implementations or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit this application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.

Please refer to FIG. 1, which is a schematic structural diagram of a data driving circuit in an embodiment of the present application, which is used in a liquid crystal display. The data driving circuit includes: a driving unit 10, a first switching unit 20, and a second switching unit 40. The first storage capacitor 30 and the second storage capacitor 50.

Wherein, the driving unit is used to access the data driving signal, which includes a shift register 16, a second buffer 15, a level shifter 14, a D \ A converter 13, an analog buffer 12, and a multiplier 11, the simulation The two output terminals of the buffer 12 are respectively connected to the two input terminals of the multiplier 11. The shift register, the second buffer, the level shifter, the D \ A converter, and the analog buffer are connected in sequence. In the data driving circuit described in this application, the second buffer is a line buffer. One end of the first switch unit 20 is connected to the analog buffer 12 and a common node of the multiplier 11, the other end of the first switch unit 20 is grounded through a first storage capacitor 30; One end is connected to the analog buffer 12 and another common node of the multiplier 11, and the other end of the second switch unit 40 is grounded through a second storage capacitor 50.

Wherein, the first switch unit 20 and the second switch unit 40 are both field effect transistors. Both the first switch unit 20 and the second switch unit 40 are NMOS transistors.

In some embodiments, the data driving circuit further includes a sub-control chip, and the sub-control chip is connected to the control terminals of the first switch unit and the second switch unit. The sub-control chip is used to control the on and off of the first switch unit and the second switch unit.

Please also refer to FIG. 2. During operation, between the rising and falling edges of the Nth high level of the data driving signal, the output voltage of the analog buffer first rises from the first preset voltage to the second preset Voltage, and then rises from the second preset voltage to the third preset voltage after the falling edge comes; between the rising and falling edges of the N + 1 high level of the data driving signal, the analog buffer The voltage at the output terminal first drops from the third preset voltage to the second preset voltage, and then falls from the second preset voltage to the first preset voltage after the falling edge comes, where N is an odd number. During the Nth high level and the N + 1th high level, the output voltage of the analog buffer is maintained at the third preset voltage.

Specifically, at the rising edge of the Nth high level, the first switch unit 20 is opened, and the first storage capacitor 30 is discharged so that the output terminal voltage of the analog buffer first climbs to the second preset voltage. The first switch unit is turned off at the falling edge of the Nth high level, and the output terminal voltage of the analog buffer 12 rises to the third preset voltage. At the rising edge of the N + 1th high level, the first switch When the unit 20 is turned on, the output terminal voltage of the analog buffer 12 simultaneously charges the first storage capacitor 30; at the rising edge of the Nth high level, the second switching unit 40 is turned on, and the second storage capacitor 50 is discharged so that The output voltage of the analog buffer 12 first climbs to the second preset voltage, the second switch unit 40 is turned off when the Nth high level falls, and the output voltage of the analog buffer 12 rises to the third The preset voltage, at the rising edge of the N + 1 high level, the second switch unit is turned on, and the voltage at the output end of the analog buffer simultaneously charges the second storage capacitor.

The present application also provides a liquid crystal display, which includes the data driving circuit described above.

In the description of this specification, reference to the descriptions of the terms "one embodiment", "certain embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means the combination of The specific features, structures, materials, or characteristics described in the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expression of the above-mentioned terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In summary, although the present application has been disclosed as preferred embodiments above, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes without departing from the spirit and scope of the present application Such changes and retouching, so the scope of protection of this application shall be subject to the scope defined by the claims.

Claims

A data driving circuit, including:

A driving unit, the driving unit is used for accessing a data driving signal, which includes an analog buffer and a multiplier, and two output terminals of the analog buffer are respectively connected to two input terminals of the multiplier;

A first switching unit, one end of the first switching unit is connected to a common node of the analog buffer and the multiplier, and the other end of the first switching unit is grounded through a first storage capacitor;

A second switching unit, one end of the second switching unit is connected to the analog buffer and another common node of the multiplier, and the other end of the second switching unit is grounded through a second storage capacitor;

Between the rising and falling edges of the Nth high level of the data driving signal, the output voltage of the analog buffer first rises from the first preset voltage to the second preset voltage, and then after the falling edge arrives Rise from the second preset voltage to the third preset voltage;

Between the rising edge and the falling edge of the N + 1 high level of the data driving signal, the voltage of the output terminal of the analog buffer first drops from the third preset voltage to the second preset voltage, and then on the falling edge After the arrival, the second preset voltage drops to the first preset voltage, where N is an odd number;

Both the first switch unit and the second switch unit are field effect transistors.
The data driving circuit according to claim 1, wherein during the Nth high level and the N + 1th high level, the output terminal voltage of the analog buffer is maintained at a third preset voltage.
The data driving circuit according to claim 1, wherein at the rising edge of the Nth high level, the first switching unit is turned on, and the first storage capacitor discharges so that the output voltage of the analog buffer first climbs to The second preset voltage, the first switching unit is turned off at the falling edge of the Nth high level, the output terminal voltage of the analog buffer rises to the third preset voltage, and rises at the N + 1th high level At the same time, the first switching unit is turned on, and the output voltage of the analog buffer simultaneously charges the first storage capacitor;

At the rising edge of the Nth high level, the second switching unit is opened, and the second storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second preset voltage, at the Nth high level When the falling edge of the second switch unit is closed, the output voltage of the analog buffer rises to a third preset voltage, and at the rising edge of the N + 1 high level, the second switch unit is opened and the analog buffer The voltage at the output terminal of the converter simultaneously charges the second storage capacitor.
The data driving circuit according to claim 1, wherein the driving unit further includes a shift register, a second buffer, a level shifter, and a D \ A converter;

The shift register, the second buffer, the level shifter, the D \ A converter, and the analog buffer are connected in sequence.
The data driving circuit according to claim 4, wherein the second buffer is a line buffer.
The data driving circuit according to claim 5, wherein the first switching unit and the second switching unit are both NMOS transistors.
The data driving circuit according to claim 1, wherein the data driving circuit further comprises a sub-control chip, and the sub-control chip is connected to the control terminals of the first switch unit and the second switch unit.
A data driving circuit, including:

A driving unit, the driving unit is used for accessing a data driving signal, which includes an analog buffer and a multiplier, and two output terminals of the analog buffer are respectively connected to two input terminals of the multiplier;

A first switching unit, one end of the first switching unit is connected to a common node of the analog buffer and the multiplier, and the other end of the first switching unit is grounded through a first storage capacitor;

In the second switching unit, one end of the second switching unit is connected to the analog buffer and another common node of the multiplier, and the other end of the second switching unit is grounded through a second storage capacitor.
The data driving circuit according to claim 8, wherein between the rising edge and the falling edge of the Nth high level of the data driving signal, the voltage at the output end of the analog buffer first rises from the first preset voltage to A second preset voltage, and then rises from the second preset voltage to the third preset voltage after the falling edge comes;

Between the rising edge and the falling edge of the N + 1 high level of the data driving signal, the voltage of the output terminal of the analog buffer first drops from the third preset voltage to the second preset voltage, and then on the falling edge After the arrival, the second preset voltage drops to the first preset voltage, where N is an odd number.
The data driving circuit according to claim 9, wherein during the Nth high level and the N + 1th high level, the output terminal voltage of the analog buffer is maintained at a third preset voltage.
The data driving circuit according to claim 9, wherein at the rising edge of the Nth high level, the first switch unit is turned on, and the first storage capacitor discharges so that the output terminal voltage of the analog buffer first climbs to The second preset voltage, the first switching unit is turned off at the falling edge of the Nth high level, the output terminal voltage of the analog buffer rises to the third preset voltage, and rises at the N + 1th high level At the same time, the first switching unit is turned on, and the output voltage of the analog buffer simultaneously charges the first storage capacitor;

At the rising edge of the Nth high level, the second switching unit is opened, and the second storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second preset voltage, at the Nth high level When the falling edge of the second switch unit is closed, the output voltage of the analog buffer rises to a third preset voltage, and at the rising edge of the N + 1 high level, the second switch unit is opened and the analog buffer The voltage at the output terminal of the converter simultaneously charges the second storage capacitor.
The data driving circuit according to claim 8, wherein the driving unit further includes a shift register, a second buffer, a level shifter, and a D \ A converter;

The shift register, the second buffer, the level shifter, the D \ A converter, and the analog buffer are connected in sequence.
The data driving circuit according to claim 12, wherein the second buffer is a line buffer.
The data driving circuit according to claim 8, wherein the first switching unit and the second switching unit are both field effect transistors.
The data driving circuit according to claim 13, wherein the first switching unit and the second switching unit are both NMOS transistors.
The data driving circuit according to claim 8, wherein the data driving circuit further comprises a sub-control chip, and the sub-control chip is connected to the control terminals of the first switch unit and the second switch unit.
A liquid crystal display includes a data driving circuit, and the data driving circuit includes:

A driving unit, the driving unit is used for accessing a data driving signal, which includes an analog buffer and a multiplier, and two output terminals of the analog buffer are respectively connected to two input terminals of the multiplier;

A first switching unit, one end of the first switching unit is connected to a common node of the analog buffer and the multiplier, and the other end of the first switching unit is grounded through a first storage capacitor;

In the second switching unit, one end of the second switching unit is connected to the analog buffer and another common node of the multiplier, and the other end of the second switching unit is grounded through a second storage capacitor.
The liquid crystal display of claim 17, wherein between the rising edge and the falling edge of the Nth high level of the data driving signal, the voltage at the output terminal of the analog buffer first rises from the first preset voltage to the Two preset voltages, and then rise from the second preset voltage to the third preset voltage after the falling edge comes;

Between the rising edge and the falling edge of the N + 1 high level of the data driving signal, the voltage of the output terminal of the analog buffer first drops from the third preset voltage to the second preset voltage, and then on the falling edge After the arrival, the second preset voltage drops to the first preset voltage, where N is an odd number.
18. The liquid crystal display of claim 18, wherein during the Nth high level and the N + 1th high level, the output voltage of the analog buffer is maintained at a third preset voltage.
The liquid crystal display of claim 18, wherein at the rising edge of the Nth high level, the first switching unit is turned on, and the first storage capacitor discharges so that the output voltage of the analog buffer first climbs to the Two preset voltages, the first switch unit is turned off at the falling edge of the Nth high level, the output terminal voltage of the analog buffer rises to the third preset voltage, at the rising edge of the N + 1th high level When the first switch unit is turned on, the output voltage of the analog buffer simultaneously charges the first storage capacitor;

At the rising edge of the Nth high level, the second switching unit is opened, and the second storage capacitor discharges so that the output voltage of the analog buffer first climbs to the second preset voltage, at the Nth high level When the falling edge of the second switch unit is closed, the output voltage of the analog buffer rises to a third preset voltage, and at the rising edge of the N + 1 high level, the second switch unit is opened and the analog buffer The voltage at the output terminal of the converter simultaneously charges the second storage capacitor.