WO2020087931A1 - 一种数据备份方法、装置及系统 - Google Patents

一种数据备份方法、装置及系统 Download PDF

Info

Publication number
WO2020087931A1
WO2020087931A1 PCT/CN2019/090758 CN2019090758W WO2020087931A1 WO 2020087931 A1 WO2020087931 A1 WO 2020087931A1 CN 2019090758 W CN2019090758 W CN 2019090758W WO 2020087931 A1 WO2020087931 A1 WO 2020087931A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
controller
write instruction
storage device
stored
Prior art date
Application number
PCT/CN2019/090758
Other languages
English (en)
French (fr)
Inventor
吉辛维克多
周智
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2020087931A1 publication Critical patent/WO2020087931A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1456—Hardware arrangements for backup

Definitions

  • This application relates to the storage field, and in particular, to a data backup method, device, and system.
  • Serial ATA Advanced Host Control Interface / Advanced Host Controller Interface Serial ATA Advanced Host Controller Interface, AHCI
  • Non-volatile high-speed transmission bus non-volatile memory express, NVMe
  • NVMe is a kind of interface that allows the host (host) and non-volatile storage (non-volatile memory, NVM) subsystem communication
  • NVM non-volatile memory
  • This interface for communication between subsystems (including controllers and storage media) is attached to the Peripheral Component Interconnect Express (PCIe) interface in the form of a register interface, optimized for enterprise and consumer solid-state storage It has the advantages of high performance and low access delay.
  • PCIe Peripheral Component Interconnect Express
  • one method of data backup is to provide two storage devices, one of which is a backup of the other storage device.
  • the host When the host performs a write operation, it triggers NVMe write instructions to the two storage devices respectively. After acquiring the NVMe write instructions, the two storage devices respectively obtain data from the host and write the data to be stored into their respective storage media.
  • This application discloses a data backup method, device and system.
  • the first storage device obtains the data to be stored from the host side, it will actively push the data message to the second storage device, and the second storage device no longer needs to obtain the data to be stored from the host.
  • the present application discloses a data backup system.
  • the system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the host is used to trigger a first write instruction to the first controller and a second write instruction to the second controller, wherein the first write instruction carries an association identifier, and the association identifier is used to associate the data to be stored and the second write instruction .
  • the first controller is used to obtain the first write instruction and the data to be stored, store the data to be stored in the storage medium of the first storage device according to the first write instruction, and send a data message to the second controller, the data message includes The data to be stored and the associated identifier.
  • the second controller is used to obtain the second write instruction and the data message, associate the second write instruction and the data to be stored according to the association identifier carried in the data message, and store the data to be stored in the second storage device according to the second write instruction Storage media.
  • the backup system may be a backup system based on a non-volatile high-speed transmission bus (non-volatile memory express, NVMe), and the first write instruction and / or the second write instruction may be a submission queue entry (submission queue) based on NVMe entry, SQE).
  • the host triggering the first write instruction may be writing the first write instruction to a submission queue (SQ) associated with the first controller, and notifying the first controller through a doorbell mechanism.
  • the host triggering the second write instruction may be that the host writes the second write instruction to the SQ associated with the second controller, and notifies the second controller through the doorbell mechanism.
  • the host may also directly send the first write instruction to the first controller, and send the second write instruction to the second controller.
  • the first controller After acquiring the data to be stored, the first controller actively sends the stored data to the second controller, and carries in the data packet an association identifier associating the data to be stored with the second write instruction, and the second write instruction receives the data message After that, the second write instruction and the data to be stored are associated according to the association identifier, and the data to be stored is written to the storage medium of the second storage device according to the second write instruction, thereby completing the backup operation of the data to be stored.
  • the second controller no longer needs to obtain the data to be stored from the host. Compared with the prior art where the first controller and the second controller respectively obtain the data to be stored from the host, the host is interconnected with the first storage device and the second storage device The data traffic of the upstream port of the switching network is halved.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the first controller may write the data to be stored to the second controller in the form of a PCIe message, and the PCIe address indicated by the association identifier is an entry to write the data to be stored.
  • the second controller may determine the second write instruction associated with the data to be stored according to the address of the PCIe message.
  • the second controller includes an internal memory, and the second controller stores the data to be stored in the second storage Before the storage medium of the device, it is also used to store the data to be stored in the storage space of the internal memory, and record the mapping relationship between the storage space and the associated identification.
  • the present invention does not limit the order in which the second controller obtains the second write instruction and the data to be stored.
  • the second controller can cache the data to be stored in its own internal memory and record the storage The mapping relationship between the storage space where data is stored and the associated identification.
  • the second controller is further configured to determine the storage location of the second write instruction according to the association identifier, the second The controller is used for acquiring the second write instruction according to the storage location of the second write instruction.
  • the host and the second controller maintain the correspondence between the association identifier and the slot of the sending queue.
  • the host triggers the first write instruction and the second write instruction, the host writes the second write instruction into the SQ slot corresponding to the association identifier
  • the second controller may determine the SQ slot stored in the second write instruction according to the association identifier, and obtain the second write instruction from the SQ slot.
  • the association identifier includes a partial field of the second write instruction, and the second controller is configured to The partial field of the instruction acquires the second write instruction.
  • the association identifier may be indication information of the second write instruction.
  • the second controller may query the second write instruction according to the association identifier.
  • the second controller is further used to trigger a completion message, and the completion message is used to instruct the second controller To complete the storage operation of the data to be stored, the host is also used to obtain a completion message.
  • the completion message may be a completion queue entry (CQE), which is used to instruct the second controller to complete the write operation indicated by the second write instruction.
  • CQE completion queue entry
  • the trigger completion message of the second controller may specifically be that after the second controller completes the write operation, the CQE is written into a completion queue (CQ), and the host is notified by an interrupt.
  • the present invention provides a data backup method.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a first control And a storage medium.
  • the second storage device includes a second controller and a storage medium.
  • the method includes: the host triggers a first write instruction, the first write instruction carries an association identifier, and the association identifier is used to associate the second write instruction with the data to be stored
  • the first write instruction is used to instruct the first controller to store the data to be stored in the storage medium of the first storage device, and instructs the first controller to send a data message to the second controller, the data message contains the data to be stored and Association identifier;
  • the host triggers a second write instruction, which is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.
  • the method further includes: the host obtains a completion message triggered by the second controller, and the completion message is used to instruct the second controller to complete the storage of the data to be stored operating.
  • the data message is a PCIe message
  • the association identifier includes a PCIe address field of the second controller.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE.
  • the second aspect is the host-side method implementation corresponding to the system of the first aspect.
  • the description in the first aspect or any possible implementation of the first aspect corresponds to the second aspect or any possible implementation of the second aspect The method will not be repeated here.
  • the present application provides a readable medium, including an execution instruction, when the processor of the computing device executes the execution instruction, the computing device executes the second aspect above or any possible implementation of the second aspect above The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor performs the execution of the memory storage Instructions to cause the computing device to perform the method in the above second aspect or any possible implementation manner of the above second aspect.
  • the present application discloses a data backup method.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a first control And a storage medium.
  • the second storage device includes a second controller and a storage medium.
  • the method includes: the first controller obtains a first write instruction triggered by the host and data to be stored.
  • the first write instruction carries an association identifier.
  • the association identifier is used for To associate the data to be stored with a second write instruction, the second write instruction is triggered by the host, and is used to instruct the second controller to write the data to be stored into the storage medium of the second storage device; the first controller according to the first write instruction Store the data to be stored in the storage medium of the first storage device; the first controller sends a data message to the second controller, and the data message includes the data to be stored and the association identifier.
  • the data message is a PCIe message
  • the association identifier includes a PCIe address field of the second controller.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE.
  • the fifth aspect is the method implementation of the first controller side corresponding to the system of the first aspect.
  • the description in the first aspect or any possible implementation manner of the first aspect corresponds to the fifth aspect or any one of the fifth aspects.
  • the possible implementation manners will not be repeated here.
  • the present application provides a readable medium, including an execution instruction, and when the processor of the computing device executes the execution instruction, the computing device performs the above fifth aspect or any possible implementation of the above fifth aspect The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor executes the memory storage Instructions to cause the computing device to perform the method in the above fifth aspect or any possible implementation manner of the above fifth aspect.
  • the present application discloses a data backup method.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device, and the first storage device includes the first control.
  • a storage medium includes a second controller and a storage medium.
  • the method includes: the second controller obtains a write instruction triggered by the host.
  • the write instruction is used to instruct the second controller to write the data to be stored in the first The storage medium of the second storage device; the second controller receives the data message sent by the first controller, the data message contains the data to be stored and the association identifier, and the association identifier is used to associate the write instruction and the data to be stored; The write instruction stores the data to be stored in the storage medium of the second storage device.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the second controller includes an internal memory, and the second controller stores the data to be stored in the second storage Before the storage medium of the device, the method further includes: the second controller stores the data to be stored in the storage space of the internal memory, and records the mapping relationship between the storage space and the associated identifier.
  • the method further includes: the second controller determines the storage location of the write instruction according to the association identifier; second The obtaining the write instruction by the controller includes: the second controller obtains the write instruction according to the storage location of the write instruction.
  • the association identifier includes a partial field of the write instruction; the second controller acquiring the write instruction includes: second The controller obtains the write instruction according to some fields of the write instruction.
  • the method further includes: a second controller triggers a completion message, and the completion message is used to indicate the second The controller completes the storage operation of the data to be stored.
  • the write instruction is NVMe-based SQE.
  • the eighth aspect is the method implementation of the second controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the eighth aspect or any one of the eighth aspect The possible implementation manners will not be repeated here.
  • the present application provides a readable medium, including an execution instruction, and when the processor of the computing device executes the execution instruction, the computing device performs the above eighth aspect or any possible implementation of the above eighth aspect The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor performs memory storage Instructions to cause the computing device to perform the method in the above eighth aspect or any possible implementation manner of the above eighth aspect.
  • the present application discloses a data backup device.
  • the data backup system includes a first storage device, a second storage device, and a data backup device.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes The first controller and the storage medium
  • the second storage device includes the second controller and the storage medium
  • the data backup device includes: a processing unit for triggering the first write instruction, the first write instruction carries an association identifier, and the association identifier is used for association A second write instruction and data to be stored;
  • the first write instruction is used to instruct the first controller to store the data to be stored in the storage medium of the first storage device, and instructs the first controller to send a data message to the second controller,
  • the data message contains the data to be stored and the associated identifier;
  • the processing unit is also used to trigger a second write instruction, and the second write instruction is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.
  • the backup device further includes an acquiring unit, configured to acquire a completion message triggered by the second controller, and the completion message is used to instruct the second controller Complete the storage operation of the data to be stored.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address of the second controller Field.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE .
  • the eleventh aspect is the implementation of the device on the host side corresponding to the system of the first aspect.
  • the description in the first aspect or any possible implementation manner of the first aspect corresponds to either the eleventh aspect or the eleventh aspect.
  • the possible implementation manners will not be repeated here.
  • the present application discloses a data backup device.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device, and the first storage device includes data backup.
  • the second storage device includes a controller and a storage medium.
  • the data backup device includes: a processing unit for acquiring a first write instruction triggered by the host and data to be stored.
  • the first write instruction carries an association identifier, and the association identifier It is used to associate the data to be stored with the second write instruction, which is triggered by the host, and is used to instruct the controller to write the data to be stored into the storage medium of the second storage device, and according to the first write instruction
  • the stored data is stored in the storage medium of the first storage device; the sending unit is used to send a data message to the controller, and the data message includes the data to be stored and the association identifier.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the controller.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE .
  • the twelfth aspect is the device implementation of the first controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the twelfth aspect or the twelfth aspect. Any possible implementation manner will not be repeated here.
  • the present application discloses a data backup device.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a controller And a storage medium
  • the second storage device includes a data backup device and a storage medium
  • the data backup device includes: an acquisition unit for acquiring a write instruction triggered by the host, the write instruction is used to instruct the data backup device to write the data to be stored to the second The storage medium of the storage device, and receives the data message sent by the controller, the data message contains the data to be stored and the associated identifier, the associated identifier is used to associate the write instruction and the data to be stored; the processing unit is used to store the data according to the write instruction The data is stored in the storage medium of the second storage device.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the data backup device.
  • the data backup device further includes an internal memory, and the processing unit stores the data to be stored in the second Before the storage medium of the storage device, it is also used to store the data to be stored in the storage space of the internal memory, and record the mapping relationship between the storage space and the associated identification.
  • the acquiring unit is further used to determine the storage location of the write instruction according to the association identifier, and according to the write The storage location of the instruction gets the write instruction.
  • the association identifier includes a partial field of the write instruction; the obtaining unit is further used for Part of the field to get the write instruction.
  • the processing unit is further used to trigger a completion message, and the completion message is used to instruct the data backup device Complete the storage operation of the data to be stored.
  • the write instruction is a SQE based on NVMe.
  • the thirteenth aspect is the device implementation of the second controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the thirteenth aspect or the thirteenth aspect. Any possible implementation manner will not be repeated here.
  • the host triggers the first write instruction to the first controller and triggers the second write instruction to the second controller.
  • the first write instruction triggered by the host to the first controller carries an association identifier that associates the second write instruction and the data to be stored.
  • the first controller actively sends a data message to the second controller, where the data message carries the data to be stored and the association identifier.
  • the second controller associates the second write instruction and the data to be stored according to the association identifier, and writes the data to be stored to the storage medium of the second storage device according to the second write instruction, thereby avoiding the second control
  • the data traffic of the upstream port of the switching network interconnected by the host and the first storage device and the second storage device is the same as when no data backup is performed, thereby improving the overall performance of the system.
  • FIG. 1 is a schematic diagram of a logical structure of an NVMe system according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a data backup method based on NVMe
  • FIG. 3 is a schematic flowchart of a data backup method according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a hardware structure of a host according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a hardware structure of a controller according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a hardware structure of a controller according to an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a data backup method according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an entrance organization structure according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a PCIe address structure according to an embodiment of the invention.
  • FIG. 10 is a schematic diagram of a data storage structure according to an embodiment of the invention.
  • FIG. 11 is a schematic diagram of a logical structure of a data backup device according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a logical structure of a data backup device according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a logical structure of a data backup device according to an embodiment of the application.
  • the embodiments of the present invention use the terms first and second, etc., to distinguish objects, such as the first write instruction and the second write instruction, etc., but there is no logic or timing dependency between each "first” and “second” relationship.
  • a "data message” refers to a message carrying load data and an association identifier sent by the first storage device to the second storage device.
  • the load data is data to be stored or part of the data to be stored.
  • the first storage device may use one data packet to send the data to be stored to the second storage device, or it may split the data to be stored into multiple data packets and send To the second storage device, this embodiment of the present invention does not limit this.
  • the embodiment of the present invention collectively refers to the load data in the data packet as the data to be stored.
  • the term push means that the first storage device actively sends a data message to the second storage device.
  • the entry is an address space opened by the second storage device to the first storage device
  • the entry address may specifically be a PCIe address
  • the data message may be a PCIe write message.
  • the entrance may be an address space opened by the controller of the second storage device to the controller of the first storage device, and the controller of the first storage device may push the controller to the controller of the second storage device according to the address space to be stored data.
  • the association identifier carried in the data packet is used to associate the data to be stored and the write instruction.
  • the association identifier may include the entry address or a part of the entry address field.
  • the first storage device may push a data message to the second storage device through the entry, and the data message may carry the entry address.
  • the second storage device After receiving the data message, the second storage device identifies the entry address, and can allocate the corresponding storage space for the entry in the local internal memory, and caches the load data carried in the data message to the storage space instead of storing the load
  • the data is stored in the storage space indicated by the entry address.
  • the internal memory may be specifically the private memory space of the controller.
  • the storage device includes a controller and a storage medium, and the storage controller is hereinafter referred to as a controller.
  • the execution subject of the storage device is generally a controller.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the main body that the first storage device interacts with the outside world is the first controller
  • the main body that the second storage device interacts with the outside world is the second controller.
  • the embodiment of the present invention does not distinguish between the storage device and the controller when interacting with the outside world.
  • the specific implementation of the command triggered by the host may be SQE.
  • the host is interconnected with the first storage device and the second storage device through a switching network.
  • the upstream port of the switching network refers to the port interconnecting the switching network and the host.
  • the upstream traffic of the switching network refers to the data traffic interacting with the host.
  • the term host refers to a subject that can interact with the storage device and store data in the storage device.
  • the host can be a physical computer, virtual machine or network card.
  • the embodiment of the present invention does not limit the specific implementation form of the host.
  • FIG. 1 is an architecture diagram of a data backup system 100 according to an embodiment of the present invention.
  • the system 100 includes a host 101, a switching network 102, a first storage device 103, and a second storage device 105.
  • the first storage device 103 includes a first controller 104 and a storage medium
  • the second storage device 105 includes a second controller 106 and a storage medium.
  • the second storage device 105 is a backup of the first storage device 103 (that is, part or all of the data of the first storage device 103 will be backed up to the second storage device 105).
  • the storage medium is generally a non-volatile storage medium for permanently storing data.
  • the storage medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, an optical disk), or a semiconductor medium (for example, Flash), etc.
  • the embodiments of the present invention do not limit the specific implementation form of the storage medium.
  • the storage medium may further include a remote memory separate from the controller, for example, a storage medium interconnected with the controller through a network.
  • the switching network 102 may be used to refer to: any manner or interconnection protocol for interconnecting the host 101, the first storage device 103, and the second storage device 105.
  • the switching network 102 may be a PCIe bus, where the PCIe bus may include a PCIe switch, and the PCIe switch is interconnected with the host 101.
  • the switching network 102 may also be an internal interconnect bus of computer equipment, the Internet, an intranet, a local area network (LAN), a wide area network (wide area network, WAN), a storage area network (storage area network, SAN), etc. , Or any combination of the above networks.
  • the embodiment of the present invention does not limit the specific implementation form of the switching network 102.
  • the host 101 when performing data storage, the host 101 needs to trigger the same write instruction to the first storage device 103 and the second storage device 105 respectively.
  • the write instruction is SQE
  • the host 101 writes the SQE to the transmission queue associated with the first storage device 103, and notifies the first controller 104 of the new SQE through the doorbell mechanism.
  • the first controller 104 After receiving the doorbell notification, the first controller 104 goes to the sending queue to obtain the corresponding SQE, where the PRP or SGL field of the SQE carries the address information of the data to be stored.
  • the first controller 104 reads the data to be stored from the host 101 side according to the address information carried in the SQE, and then stores the data to be stored in the storage medium of the first storage device 103. Similarly, the host 101 writes the same read instruction to the transmission queue associated with the second storage device 105, and notifies the second controller 106 of the new SQE through the command mechanism. After acquiring the SQE, the second controller 106 still needs to go to the host 101 side to read the data to be stored according to the address information carried by the SQE, and then write the data to be stored into the storage medium of the second storage device 105 and trigger the host 101 Complete the message. Based on the above process, the same data needs to be read twice from the host side, and the upstream data traffic of the switching network 102 is twice that without backup.
  • the uplink data traffic refers to the data traffic interacting with the host 101.
  • the host 101 triggers the first write instruction and the second write instruction to the first storage device 103 and the second storage device 105 respectively when data needs to be stored, wherein the first write The instruction carries an association identifier, and the association identifier is used to associate the data to be stored and the second write instruction.
  • the first controller 104 After acquiring the first write instruction and the data to be stored, the first controller 104 writes the data to be stored into the storage medium of the first storage device 103, and actively pushes the data message to the second controller 106, which is carried in the data message The data to be stored and the associated identifier.
  • the second controller 106 After acquiring the second write instruction and the data message, the second controller 106 associates the second write instruction and the data to be stored according to the association identifier, and writes the data to be stored into the storage of the second storage device 105 according to the second write instruction Media and trigger a completion message to the host 101.
  • the first storage device 103 actively pushes the data message containing the data to be stored and the associated identifier to the second storage device 105, thereby avoiding the step of the second storage device 105 reading the message from the host 101 side, thereby The upstream port of the switching network 102 interconnecting the first storage device 103, the second storage device 105 and the host 101 is reduced, and the overall performance of the system is improved.
  • FIG. 4 is a schematic structural diagram of a host 400 according to an embodiment of the present application.
  • the host 400 includes a processor 401 connected to the system memory 402.
  • the processor 301 may be a central processing unit (CPU), an image processor (graphics processing unit, GPU), a field programmable gate array (Field Programmable Gate Array, FPGA), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or a digital Signal processor (digital signal processor, DSP) and other calculation logic or any combination of the above calculation logic.
  • the processor 301 may be a single-core processor or a multi-core processor.
  • the processor 401 may further include backup logic 410, and the backup logic 410 may be a specific hardware circuit or a firmware module integrated in the processor 401. If the backup logic 410 is a specific hardware circuit, the backup logic 410 executes the method of the embodiment of the present application, and if the backup logic 410 is a firmware module, the processor 410 executes the firmware code in the backup logic 410 to implement the technology of the embodiment of the present application Program.
  • the backup logic 410 includes: (1) logic (circuit / firmware code) for triggering the first write instruction, the first write instruction carries an association identifier, and the association identifier is used to associate the second write instruction and the data to be stored, the first The write instruction is used to instruct the first storage device to store the data to be stored in the storage medium of the first storage device, and instructs the first storage device to send a data message to the second storage device, where the data message includes the data to be stored and the association identifier; (2) Logic (circuit / firmware code) for triggering the code of the second write instruction, which is used to instruct the second storage medium to store the data to be stored in the storage medium of the second storage device.
  • the bus 409 is used to transfer information between the components of the host 400.
  • the bus 409 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 409 is also connected with an input / output interface 405 and a communication interface 403.
  • the input / output interface 405 is connected with an input / output device for receiving input information and outputting operation results.
  • the input / output device can be a mouse, keyboard, monitor, or optical drive.
  • the communication interface 403 is used to implement communication with other devices or networks.
  • the communication interface 403 may be interconnected with other devices or networks in a wired or wireless manner.
  • the host 400 may be interconnected with the switching network through the communication interface 403 and connected to the controller through the switching network.
  • the system memory 402 may include some software, for example, an operating system 408 (for example, Darwin, RTXC, LINUX, UNIX, OS, X, WINDOWS, or embedded operating system (for example, Vxworks)), an application program 407, and a backup module 406.
  • an operating system 408 for example, Darwin, RTXC, LINUX, UNIX, OS, X, WINDOWS, or embedded operating system (for example, Vxworks)
  • an application program 407 for example, Vxworks
  • the processor 401 executes the backup module 406 to implement the technical solution of the embodiment of the present application.
  • the backup module 406 includes: (1) a code for triggering the first, the first write instruction carries an association identifier, the association identifier is used to associate the second write instruction and the data to be stored, and the first write instruction is used to instruct the first storage
  • the device stores the data to be stored in the storage medium of the first storage device, and instructs the first storage device to send a data message to the second storage device, the data message contains the data to be stored and the association identifier; (2) is used to trigger the second The code of the write instruction.
  • the second write instruction is used to instruct the second storage medium to store the data to be stored in the storage medium of the second storage device.
  • FIG. 4 is merely an example of a host 400.
  • the host 400 may include more or fewer components than those shown in FIG. 4, or have different component configurations.
  • various components shown in FIG. 4 may be implemented by hardware, software, or a combination of hardware and software.
  • FIG. 5 is a schematic structural diagram of a controller 500 according to an embodiment of the present application.
  • the controller 500 includes a processor 501 connected to the system memory 502.
  • the processor 401 may be computational logic such as CPU, GPU, FPGA, ASIC, or DSP, or any combination of the above.
  • the processor 401 may be a single-core processor or a multi-core processor.
  • the processor 501 may further include backup logic 505, and the backup logic 505 may be a specific hardware circuit or a firmware module integrated in the processor 501. If the backup logic 505 is a specific hardware circuit, the backup logic 505 executes the method of the embodiment of the present application, and if the backup logic 505 is a firmware module, the processor 501 executes the firmware code in the backup logic 505 to implement the technology of the embodiment of the present application Program.
  • the backup logic 505 includes: (1) logic (circuit / firmware code) for acquiring the first write instruction triggered by the host and the data to be stored, the first write instruction carries an association identifier, and the association identifier is used to associate the data to be stored with the first Two write instructions; (2) logic (circuit / firmware code) for storing data to be stored in the storage medium of the first storage device according to the first write instruction; (3) for sending data messages to the second storage device Logic (circuit / firmware code), the data message contains the data to be stored and the associated identification.
  • logic circuit / firmware code
  • the bus 507 is used to transfer information between the components of the controller 500.
  • the bus 507 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 507 may also be connected with a communication interface 503.
  • the communication interface 503 is used to realize communication with other devices or networks.
  • the communication interface 503 may be interconnected with other devices or networks in a wired or wireless manner.
  • the controller 500 is interconnected with the switching network and the storage medium through the communication interface 503.
  • the system memory 502 may include some software, for example, an operating system 504 (such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)) and a backup module 506.
  • an operating system 504 such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)
  • the processor 501 executes the backup module 506 to implement the technical solution of the embodiment of the present application.
  • the backup module 506 includes: (1) a code for acquiring a first write instruction triggered by the host and data to be stored, the first write instruction carrying an association identifier, and the association identifier is used to associate the data to be stored and the second write instruction; (2 ) Code for storing the data to be stored in the storage medium of the first storage device according to the first write instruction; (3) Code for sending a data message to the second storage device, the data message containing the data to be stored and Association ID.
  • FIG. 5 is only an example of a controller 500, and the controller 500 may include more or fewer components than those shown in FIG. 5, or have different component configurations. Meanwhile, various components shown in FIG. 5 may be implemented by hardware, software, or a combination of hardware and software.
  • FIG. 6 is a schematic structural diagram of a controller 600 according to an embodiment of the present application.
  • the controller 600 includes a processor 601 connected to the system memory 602.
  • the processor 401 may be computational logic such as CPU, GPU, FPGA, ASIC, or DSP, or any combination of the above.
  • the processor 401 may be a single-core processor or a multi-core processor.
  • the processor 601 may further include a register, and the register may be opened to be accessed by controllers of other storage devices. More specifically, the register can be used as a PCIe address space to be opened to controllers of other storage devices for the controllers of other storage devices to access through the PCIe address.
  • the processor 601 may further include backup logic 605, and the backup logic 605 may be a specific hardware circuit or a firmware module integrated in the processor 601. If the backup logic 605 is a specific hardware circuit, the backup logic 605 executes the method of the embodiment of the present application, and if the backup logic 605 is a firmware module, the processor 601 executes the firmware code in the backup logic 605 to implement the technology of the embodiment of the present application Program.
  • the backup logic 605 includes: (1) logic (circuit / firmware code) for acquiring a write command triggered by the host; (2) logic (circuit / firmware code) for receiving a data message sent by the first storage device , The data packet contains the data to be stored and the association identifier, and the association identifier is used to associate the write instruction and the data to be stored; (3) the logic for storing the data to be stored in the storage medium of the second storage device according to the write instruction (Circuit / firmware code).
  • the bus 607 is used to transfer information between the components of the controller 600.
  • the bus 607 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 607 can also be connected with a communication interface 603.
  • the communication interface 603 is used to implement communication with other devices or networks.
  • the communication interface 603 may be interconnected with other devices or networks in a wired or wireless manner.
  • the controller 600 is interconnected with the host and the storage medium through the communication interface 603.
  • the controller 600 may also be connected to the network through the communication interface 603 and interconnected with the host or the storage medium through the network.
  • the system memory 602 may include some software, for example, an operating system 604 (such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)) and a backup module 606.
  • an operating system 604 such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)
  • the processor 601 executes the backup module 606 to implement the technical solution of the embodiment of the present application.
  • the backup module 606 includes: (1) a code for acquiring a write instruction triggered by the host; (2) a code for receiving a data message sent by the first storage device, the data message includes data to be stored and an association identifier, and the association identifier It is used to associate the write instruction and the data to be stored; (3) The code used to store the data to be stored in the storage medium of the second storage device according to the write instruction.
  • FIG. 6 is merely an example of a controller 600.
  • the controller 600 may include more or fewer components than those shown in FIG. 6, or have different component configurations. Meanwhile, various components shown in FIG. 6 may be implemented by hardware, software, or a combination of hardware and software.
  • an embodiment of the present invention provides a data backup method.
  • the data backup system includes a first storage device, a second storage device, and a host, where the first storage device is a backup of the second storage device, the first storage device includes a first controller and a storage medium, and the second storage device includes a second control And storage media.
  • the method 700 includes:
  • Step 701 The host triggers the first write instruction.
  • the first write instruction carries an association identifier, and the association identifier is used to associate the second write instruction with the data to be stored.
  • the first write instruction may specifically be NVMe-based SQE.
  • the first write instruction is SQE as an example for explanation. However, it should be understood that the embodiment of the present invention does not limit the specific implementation form of the first write instruction.
  • the process of triggering the first write instruction from the host can refer to the NMVe standard.
  • the host writes the SQE to the sending queue associated with the first controller, and notifies the first controller that a new SQE has entered the sending queue related to the first controller through the doorbell, so as to remind the first controller to read the SQE.
  • the host triggering the first write instruction may also be implemented in other forms.
  • the host may directly send the first write instruction to the first controller.
  • the invention does not limit the specific implementation form of the host triggering the first write instruction.
  • Step 702 The host triggers the second write instruction.
  • the second write instruction may be NVMe-based SQE.
  • the second write instruction is SQE as an example for explanation. However, it should be understood that the embodiment of the present invention does not limit the specific implementation form of the second write instruction.
  • the second write instruction may be specifically a write instruction, which is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.
  • the host triggering the second write instruction may be that the host writes the second write instruction to the sending queue associated with the second controller, and notifies the second controller that a new SQE has entered the second
  • the controller sends a queue to remind the second controller to read the SQE.
  • the second write command triggered by the host may also be implemented in other forms.
  • the host may directly send the second write instruction to the second controller.
  • the invention does not limit the specific implementation form of the host triggering the second write instruction.
  • Step 703 The first controller obtains the first write instruction.
  • the first controller may obtain the first write instruction from the send queue associated with the host. Specifically, the first controller receives the doorbell notification of the host, the doorbell is used to indicate that a new SQE arrives in the sending queue, and the first controller goes to the sending queue to obtain the SQE. The first controller may also directly receive the first write command sent by the host.
  • the embodiment of the present invention does not limit the specific implementation form of the first controller acquiring the first write instruction.
  • Step 704 The first controller obtains the data to be stored.
  • the format of the first write instruction may refer to the NVMe standard
  • the host may indicate the address information of the data to be stored through the PRP or SGL field of SQE in the first write instruction.
  • the first controller reads the data to be stored from the host side according to the address information.
  • the host may also directly send the data to be stored to the first controller, and the first controller directly receives the data to be stored from the host.
  • the embodiment of the present invention does not limit the specific implementation form of the first controller acquiring the data to be stored.
  • Step 705 The first controller stores the data to be stored in the storage medium of the first storage device according to the first write instruction.
  • Step 706 The first controller sends a data message to the second controller.
  • the data message contains the data to be stored and the association identifier.
  • the first controller may divide the data to be stored into multiple data packets and send the data to the second controller.
  • the first controller may actively push the data message to the second controller.
  • the association identifier carried in the data packet is used to associate the data to be stored and the second write instruction.
  • the embodiment of the present invention does not limit the specific implementation manner of the association identifier.
  • the association identifier may directly or indirectly indicate the second write instruction corresponding to the data to be stored carried in the data packet.
  • the data message may be a PCIe write operation message. More specifically, the data message may be a transaction layer packet, and the load data may be a load carried in a transaction layer packet (transaction layer packet, TLP) ( payload), the association identifier may be the PCIe address of the TLP or a partial field of the PCIe address.
  • TLP transaction layer packet
  • the second controller opens a part of its address space to the first controller. More specifically, the address space opened by the second controller to the first controller may serve as the PCIe address space of the second controller.
  • the first controller can access the PCIe address access.
  • the second controller may open a part of the PCIe address of the base address register to the first controller for access.
  • the base address register is used as an example for illustration, but it should be understood that the embodiment of the present invention does not limit the type and form of the address space that the second controller opens to the first controller for access.
  • the second controller may organize a part of the PCIe addresses of the base address register into the form of portals, and each entry occupies a part of the PCIe address space of the base address register.
  • the first controller may write a data message to the second controller through the portal.
  • the entry is the data entry for the PCIe write operation from the first controller to the second controller. In the following description, the function of the entry will be described in more detail.
  • the data message pushed by the first controller to the second controller may be a PCIe message.
  • the first controller writes the data to be stored associated with the second write instruction to the second through the entry
  • the address segment of the PCIe message indicates the entry corresponding to the write operation, that is, the entry address is a PCIe address or a partial field of the PCIe address in the data message.
  • the association identifier may be an entry address or a partial field of the entry address.
  • the second controller is also used to determine the storage address of the second write instruction according to the association identifier, and obtain the second write instruction according to the storage address of the second write instruction.
  • the address for storing the second write instruction may be the address of the slot in the commit queue where the second write instruction is stored.
  • the host and the second controller maintain the correspondence between the entry and the slot in the sending queue.
  • the host stores the second write instruction in the slot of the sending queue corresponding to the entry indicated by the association identifier, and carries the association identifier in the first write instruction.
  • the first controller sends a data message to the second controller according to the association identifier, and the data message carries the association identifier.
  • the second controller determines the slot in the sending queue associated with the host to store the second address according to the association identifier, and obtains the second write instruction associated with the data to be stored from the slot.
  • the present invention does not limit the organization of entries in the PCIe address space, but only needs to ensure that each entry corresponds to a specific second write instruction during the data backup operation, and each entry is uniquely associated with a specific second write instruction.
  • a part of the PCIe address of the base address register of the second controller may be organized in the form of through holes (aperture), and each through hole contains multiple entries, that is, the entries may be organized in the form of an array, which is added through the array base address The port offset is addressed to the entrance, and this array is called a via.
  • Each entry is associated with a slot in the send queue.
  • Fig. 8 is a schematic diagram of the structure of the base address register. As shown in Fig. 8, each through hole is composed of a group of entries P0 to PN.
  • the PCIe address structure includes the base address of BAR, the via offset, and the entry offset.
  • the BAR and the through hole offset are used to uniquely determine the through hole
  • the entrance offset is used to indicate a specific entrance in the through hole.
  • the data to be stored is “pushed” by the first controller to the second controller through the PCIe BAR hole.
  • Push refers to the PCIe write transaction initiated by the first controller.
  • the entries may also be arbitrarily distributed in the PCIe address space, and arbitrarily distributed entries in the PCIe space are called arbitrary "data entries”.
  • the association identifier is an entry address or a partial field of the entry address.
  • the host and the second controller maintain the correspondence between the entry and the slot in the SQ, and the SQ slot corresponds to the entry in a one-to-one relationship.
  • the host triggers the first write instruction and the second write instruction through the correspondence between the entry and the SQ slot.
  • the second controller may obtain the corresponding second write instruction according to the association identifier in the data packet.
  • the SQ slot storing the second write instruction is used to associate the entry with the second write instruction, and the second write instruction corresponding to the entry is determined through the SQ slot.
  • the association identifier may also be indication information of the second write instruction.
  • the association identifier may further include a partial field of the second write instruction, and the second controller obtains the second write instruction according to the association identifier.
  • the second write instruction may be SQE, and the indication information associated with the SQE is used to uniquely determine an SQE.
  • the SQE indication information is carried in the data message, so that the association between the SQE and the data to be stored is directly realized, rather than the indirect association through the SQ slot.
  • the associated identifier may consist of "queue ID + CID". If the CID of each SQE is unique, the association identifier may be the CID carried by the corresponding SQE. In other implementations, the association identifier may also be part of the CID.
  • the association identifier may also be specified using a specifically defined SGL type or SGL subtype or other fields in the SQE, as long as the second controller can uniquely determine the second write instruction according to the association identifier, this embodiment of the present invention does not Limit the specific implementation of the association ID.
  • Step 707 The second controller obtains the second write instruction.
  • the second controller may obtain the second write instruction from the sending queue associated with the host. More specifically, the second controller receives the doorbell notification of the host, the doorbell is used to indicate that a new SQE arrives in the sending queue corresponding to the second controller, and after receiving the doorbell of the host, the controller goes to the sending queue to obtain the The second write instruction.
  • the second controller may also directly receive the second write command sent by the host.
  • the embodiment of the present invention does not limit the specific implementation form of the second controller acquiring the second write instruction.
  • the format of the second write instruction may refer to the NVMe standard, but in the embodiment of the present invention, the data to be stored and the second write instruction are associated through the association identifier, and the data to be stored is actively pushed to the second by the first controller Controller.
  • the second write instruction no longer requires the second controller to actively acquire the data to be stored through the PCIe read operation, so the second write instruction does not need to carry the address information of the data to be stored through the SGL field or the PRP field.
  • the SGL domain or PRP domain of the second write instruction may not carry other information, and the processing method of the SGL domain or PRP domain by the second controller may be "ignore", that is, the SGL or PRP.
  • the association identifier may be an entry address or a partial field of the entry address.
  • the second controller maintains the correspondence between the entry and the slot in the sending queue. After receiving the data message, the second controller is also used to determine the storage address of the second write instruction according to the association identifier, and obtain the second write instruction according to the storage address of the second write instruction.
  • the association identifier may also be indication information of the second write instruction.
  • the association identifier may also include some fields of the second write instruction.
  • the second controller may also look up the second write instruction indicated by the association identifier in the sending queue according to the association identifier.
  • Step 708 The second controller obtains the data to be stored.
  • the data message carries the data to be stored.
  • the address information carried in the data message indicates an entry of the second controller.
  • the entry of the second controller is used to receive the data message and is an entry for the first controller to send the data message to the second controller.
  • the storage space for the data to be stored may be the internal memory of the second controller, instead of storing the data to be stored in the storage space indicated by the entry address.
  • the second controller After receiving the data message, the second controller parses the data message to obtain the address of the data message, obtains the association identifier, and recognizes that the association identifier is the address information of the entrance that the second controller wants the first controller to open.
  • the address stores the data to be stored in the data message into its own internal memory.
  • the second controller may allocate a specific storage block in its own internal memory for each entry to store the data to be stored received by the entry.
  • the second controller may establish a mapping relationship between the storage block and the entry.
  • the internal memory used by the second controller to store data can no longer be accessed by the outside world through PCIe addressing, nor is it also used as a command memory buffer.
  • the embodiment of the present invention does not limit the specific implementation of the storage block used to store the data to be stored the way.
  • the first controller may use multiple data packets to send the data to be stored.
  • the second controller may use the root data structure to organize the data received from the portal.
  • the data message may specifically be a PCIe write message, and the first controller writes the data to be written to the second controller through the PCIe write operation.
  • the second controller can organize the data into a root data structure to facilitate data management.
  • the second controller after receiving the data message, decodes the address of the data message and identifies the associated identifier, identifies the entry and root data structure according to the associated identifier, and allocates free memory blocks for data from the memory storage , And save the data to the allocated memory block, and attach the memory block to the root data structure.
  • the second controller first stores the data in its own internal memory, and when certain conditions are met, stores the data stored in its own internal memory to the storage medium of the second storage device.
  • the satisfying condition here may be that the second controller obtains the second write instruction, or the amount of data is accumulated to the extent that the second NMVe controller can perform a write operation on the storage medium.
  • the internal memory of the second controller may be the private memory of the controller.
  • the embodiment of the present invention does not limit the order in which the second controller acquires the data message and the second write instruction.
  • the second controller may first receive the data message pushed by the first controller, and determine the second write instruction according to the association identifier.
  • the second controller may also obtain the second write instruction first, and then obtain the corresponding data to be stored according to the second write instruction.
  • the second controller may determine the association identifier according to the second write instruction, and then determine the corresponding entry according to the association identifier, and obtain the stored load data from the storage space allocated to the entry according to the association identifier.
  • the embodiment of the present invention does not limit the sequence of the data to be stored corresponding to the second write instruction and the second write instruction itself to the second controller.
  • the second controller may maintain a one-to-one correspondence between the SQ slot and the entry.
  • the entry corresponding to the second write instruction may be determined according to the maintained correspondence. If the second controller detects that no data has arrived at the corresponding entry, the second controller suspends the second write instruction and waits for data to arrive. Until the second controller detects that data has arrived at the corresponding entry, it can perform the write operation of the data to be stored.
  • the second controller detects that the second write instruction corresponding to the data has not reached the second controller or the corresponding SQ slot according to the association identifier carried in the data packet . Then the second controller can attach the data to the root data structure and wait for the relevant second write instruction to arrive until the corresponding second write instruction reaches the second controller or the addressable SQ slot of the second controller. The controller obtains the second write instruction, and stores the data to be stored in the storage medium of the second storage device according to the second write instruction.
  • Step 709 The second controller stores the data to be stored in the storage medium of the second storage device.
  • the first controller may send the data to be stored through multiple data packets, and the second controller receives the data to be stored pushed by the first controller and the second controller to the second storage device through the portal.
  • Storage media write operations can be performed in parallel. If the data to be stored currently received through the portal is completed, that is, the data currently received through the portal has been completely written to the storage medium of the second storage device, but the system needs more data to complete the backup operation, the second controller hangs Start the second write command and wait for data to arrive.
  • Step 710 The second controller triggers the completion message.
  • the completion message is used to instruct the second controller to complete the storage operation of the data to be stored.
  • the completion message may be a trigger completion queue entry (CQE).
  • CQE is used to instruct the second controller to complete the write operation indicated by the second write instruction.
  • the trigger completion message of the second controller may specifically be that after the second controller completes the write operation, the CQE is written into a completion queue (CQ), and the host is notified by an interrupt.
  • the host triggers the first write instruction to the first controller and triggers the second write instruction to the second controller.
  • the first write instruction triggered by the host to the first controller carries an association identifier that associates the second write instruction and the data to be stored.
  • the first controller actively sends a data message to the second controller, where the data message carries the data to be stored and the association identifier.
  • the second controller associates the second write instruction and the data to be stored according to the association identifier, and writes the data to be stored to the storage medium of the second storage device according to the second write instruction, thereby avoiding the second control
  • the data traffic of the upstream port of the switching network interconnected by the host and the first storage device and the second storage device is the same as when no data backup is performed, thereby improving the overall performance of the system.
  • FIG. 11 is a schematic diagram of a logical structure of a data backup device 1100 according to an embodiment of the invention.
  • the data backup system includes a first storage device, a second storage device, and a data backup device 1100.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes the first controller and the storage medium, and the second storage device includes the first Two controllers and storage media, as shown in FIG. 11, the data backup device 1100 includes a processing unit 1101 and an acquisition unit 1102, where,
  • the processing unit 1101 is used to trigger a first write instruction, the first write instruction carries an association identifier, and the association identifier is used to associate the second write instruction with the data to be stored; the first write instruction is used to instruct the first controller to store the data to be stored Into the storage medium of the first storage device and instruct the first controller to send a data message to the second controller, where the data message contains the data to be stored and the association identifier.
  • the processing unit 1101 is also used to trigger a second write instruction, and the second write instruction is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.
  • the backup device 1100 further includes an obtaining unit 1102, configured to obtain a completion message triggered by the second controller, where the completion message is used to instruct the second controller to complete the storage operation of the data to be stored.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE.
  • the processing unit 1101 and the obtaining unit 1102 may be implemented by the backup logic 410 in the processor 401 in FIG. 4 or by the processor 401 in FIG. 4 and the backup module 406 in the system memory 402 achieve.
  • the embodiments of the present application are the embodiments of the host device corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, which will not be repeated here.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a data backup device 1200 and a storage medium, and the second storage device includes a controller and storage. medium.
  • the backup device 1200 includes a processing unit 1201 and a sending unit 1202, where,
  • the processing unit 1201 is used to obtain a first write instruction triggered by the host and the data to be stored.
  • the first write instruction carries an association identifier, and the association identifier is used to associate the data to be stored with the second write instruction.
  • the second write instruction is triggered by the host and used Yu instructs the controller to write the data to be stored in the storage medium of the second storage device, and stores the data to be stored in the storage medium of the first storage device according to the first write instruction.
  • the sending unit 1202 is used to send a data message to the controller.
  • the data message includes the data to be stored and the association identifier.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the controller.
  • the association identifier includes a partial field of the second write instruction.
  • the first write instruction and / or the second write instruction are NVMe-based SQE.
  • the processing unit 1201 and the sending unit 1202 may be implemented by the backup logic 505 in the processor 501 in FIG. 5 or by the processor 501 in FIG. 5 and the backup module 506 in the system memory 502 achieve.
  • the embodiments of the present application are the device embodiments of the first controller corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, which will not be repeated here.
  • the data backup system includes a first storage device, a second storage device, and a host.
  • the second storage device is a backup of the first storage device.
  • the first storage device includes a controller and a storage medium
  • the second storage device includes a data backup device 1300 and storage. medium.
  • the backup device 1300 includes an acquisition unit 1301 and a processing unit 1302, where,
  • the obtaining unit 1301 is used to obtain a write instruction triggered by the host.
  • the write instruction is used to instruct the data backup device to write the data to be stored into the storage medium of the second storage device, and receive a data message sent by the controller.
  • the associated identifier is used to associate the write instruction and the data to be stored.
  • the processing unit 1302 is configured to store the data to be stored in the storage medium of the second storage device according to the write instruction.
  • the data message is a PCIe message
  • the association identifier includes a PCIe address field of the data backup device 1301.
  • the data backup device 1300 further includes an internal memory. Before the processing unit 1302 stores the data to be stored in the storage medium of the second storage device, it is also used to store the data to be stored in the storage space of the internal memory and record the storage space The mapping relationship with the associated identification.
  • the obtaining unit 1301 is further configured to determine the storage location of the write instruction according to the association identifier, and obtain the write instruction according to the storage location of the write instruction.
  • the association identifier includes a partial field of the write instruction
  • the obtaining unit 1301 is further configured to obtain the write instruction according to the partial field of the write instruction.
  • processing unit 1302 is also used to trigger a completion message, and the completion message is used to instruct the data backup device 1300 to complete the storage operation of the data to be stored.
  • the write instruction is NVMe-based SQE.
  • the obtaining unit 1301 and the processing unit 1302 may be specifically implemented by the backup logic 605 in the processor 601 in FIG. 6 or may be implemented by the processor 601 in FIG. 6 and the backup module 606 in the system memory 602 to fulfill.
  • the embodiments of the present application are the device embodiments of the second controller corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, and are not repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

一种数据备份方法，装置和系统。该系统包括第一存储装置（103），第二存储装置（105）和主机（101）。第一存储装置（103）包含第一控制器（104）和存储介质，第二存储装置（105）包含第二控制器（106）和存储介质。主机（101）向第一控制器（104）触发第一写指令，并向第二控制器（106）触发第二写指令，其中，第一写指令携带关联标识，该关联标识用于关联待存储数据和第二写指令。第一控制器（104）获取第一写指令和待存储数据，根据第一写指令将待存储数据存入第一存储装置（103）的存储介质，并向第二控制器（106）发送数据报文，该数据报文包含待存储数据和该关联标识。第二控制器（106）获取第二写指令和数据报文，根据数据报文中携带的关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据存入第二存储装置（105）的存储介质。

Description

一种数据备份方法、装置及系统 技术领域
本申请涉及存储领域，尤其涉及一种数据备份的方法、装置和系统。
背景技术
随着存储技术的发展，尤其是在使用闪存(Flash)作为存储介质的固态硬盘(solid state drive，SSD)中，传统的机械硬盘设计的串行高级技术附件(serial advanced technology attachment，SATA)接口与串行ATA高级主控接口/高级主机控制器接口(Serial ATA Advanced Host Controller Interface,AHCI)标准已经无法满足存储设备的要求，成为限制存储设备处理能力的一大瓶颈。非易失性高速传输总线(non-volatile memory express，NVMe)应运而生，NVMe是一种允许主机(host)和非易失性存储(non-volatile memory，NVM)子系统通信的接口，NVM子系统(包括控制器和存储介质)通信的该接口以寄存器接口的方式附加到高速外围部件互连总线(Peripheral Component Interconnect express，PCIe)接口之上，为企业级和消费级固态存储做了优化具有性能高、访问时延低的优势。
现有技术中，一种数据备份的方式是设置两个存储装置，其中一个存储装置是另外一个存储装置的备份。主机在进行写操作时，分别向两个存储装置触发NVMe写指令，两个存储装置获取NVMe写指令后，分别从主机处获取数据，并将待存储数据写入各自的存储介质。
发明内容
本申请公开了一种数据备份方法、装置和系统。在进行数据存储的过程中，第一存储装置从主机侧获取到待存储数据后，会主动向第二存储装置推送数据报文，第二存储装置不再需要从主机获取待存储数据。
第一方面，本申请公开了一种数据备份系统，该系统包括第一存储装置，第二存储装置和主机。其中，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质。主机用于向第一控制器触发第一写指令，并向第二控制器触发第二写指令，其中，第一写指令携带关联标识，该关联标识用于关联待存储数据和第二写指令。第一控制器用于获取第一写指令和待存储数据，根据第一写指令将待存储数据存入第一存储装置的存储介质，并向第二控制器发送数据报文，该数据报文包含待存储数据和该关联标识。第二控制器用于获取第二写指令和数据报文，根据数据报文中携带的关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据存入第二存储装置的存储介质。
其中，该备份系统可以为基于非易失性高速传输总线(non-volatile memory express，NVMe)的备份系统，第一写指令和/或第二写指令可以为基于NVMe的提交队列条目(submission queue entry，SQE)。主机触发第一写指令可以为将第一写指令写入与第一控制器关联的提交队列(submission queue，SQ)，并通过门铃机制通知第一控制器。 同理，主机触发第二写指令可以为主机将第二写指令写入与第二控制器关联的SQ，并通过门铃机制通知第二控制器。主机也可以直接将第一写指令发送至第一控制器，并将第二写指令发送至第二控制器。第一控制器获取到待存储数据后主动向第二控制器发送该存储数据，并在数据报文中携带关联待存储数据和第二写指令的关联标识，第二写指令接收到数据报文后，根据关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据写入第二存储装置的存储介质，从而完成待存储数据的备份操作。第二控制器不再需要从主机获取待存储数据，与现有技术中第一控制器和第二控制器分别取主机获取待存储数据相比，主机与第一存储装置和第二存储装置互联的交换网络的上行端口的数据流量减半。
根据第一方面，在第一方面的第一种可能的实现方式中，该数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。第一控制器可以通过PCIe报文的形式向第二控制器写入待存储数据，关联标识指示的PCIe地址是写入待存储数据的入口。第二控制器可以根据PCIe报文的地址确定与该待存储数据关联的第二写指令。
根据第一方面或第一方面第一种可能的实现方式，在第一方面第二种可能的实现方式中，第二控制器包含内部存储器，第二控制器将待存储数据存入第二存储装置的存储介质之前，还用于将待存储数据存入内部存储器的存储空间，并记录存储空间与关联标识之间的映射关系。本发明不限定第二控制器获取第二写指令和待存储数据的顺序，第二控制器可以首先接收到数据报文后，并将待存储数据缓存在自己的内部存储器中，并记录存储待存储数据的存储空间与关联标识的映射关系。
根据第一方面或第一方面以上任意种可能的实现方式，在第一方面第三种可能的实现方式中，第二控制器还用于根据关联标识确定第二写指令的存储位置，第二控制器用于根据第二写指令的存储位置获取第二写指令。主机和第二控制器维护有关联标识与发送队列的槽位之间的对应关系，主机在触发第一写指令和第二写指令的时候，将第二写指令存入关联标识对应的SQ槽位中，第二控制器获取到关联标识后，可以根据关联标识确定第二写指令存储的SQ槽位，并从该SQ槽位中获取第二写指令。
根据第一方面或第一方面以上任一种可能的实现方式，在第一方面第四种可能的实现方式中，关联标识包含第二写指令的部分字段，第二控制器用于根据第二写指令的部分字段获取第二写指令。关联标识可以为第二写指令的指示信息，第二控制器获取到关联标识后，可以根据该关联标识查询第二写指令。
根据第一方面或第一方面以上任一种可能的实现方式，在第一方面第五种可能的实现方式中，第二控制器还用于触发完成消息，完成消息用于指示第二控制器完成对待存储数据的存储操作，主机还用于获取完成消息。
完成消息可以为触发完成队列条目(completion queue entry，CQE)，CQE用于指示第二控制器完成第二写指令指示的写操作。第二控制器触发完成消息可以具体为第二控制器完成写操作后，将CQE写入完成队列(completion queue，CQ)，并通过中断通知主机。
第二方面，本发明提供了一种数据备份方法，数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质，该方法包括：主机触发第一 写指令，第一写指令携带关联标识，关联标识用于关联第二写指令和待存储数据；第一写指令用于指示第一控制器将待存储数据存入第一存储装置的存储介质，并指示第一控制器向第二控制器发送数据报文，数据报文包含待存储数据和关联标识；主机触发第二写指令，第二写指令用于指示第二控制器将待存储数据存入第二存储装置的存储介质。
根据第二方面，在第二方面的第一种可能的实现方式中，该方法还包括：主机获取第二控制器触发的完成消息，完成消息用于指示第二控制器完成对待存储数据的存储操作。
根据第二方面或第二方面第一种可能的实现方式，在第二方面第二种可能的实现方式中，该数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。
根据第二方面或第二方面第一种可能的实现方式，在第二方面第三种可能的实现方式中，关联标识包含第二写指令的部分字段。
根据第二方面或第二方面以上任一种可能的实现方式，在第二方面第四种可能的实现方式中，第一写指令和/或第二写指令为基于NVMe的SQE。
第二方面为第一方面系统对应的主机侧的方法实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第二方面或第二方面任一种可能的实现方式，在此不再赘述。
第三方面，本申请提供了一种可读介质，包括执行指令，当计算设备的处理器执行该执行指令时，该计算设备执行以上第二方面或以上第二方面的任一种可能的实现方式中的方法。
第四方面，本申请提供了一种计算设备，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当计算设备运行时，处理器执行存储器存储的执行指令，以使计算设备执行以上第二方面或以上第二方面的任一种可能的实现方式中的方法。
第五方面，本申请公开了一种数据备份方法，数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质，该方法包括：第一控制器获取主机触发的第一写指令和待存储数据，第一写指令携带关联标识，关联标识用于关联待存储数据和第二写指令，该第二写指令由主机触发，用于指示第二控制器将待存储数据写入第二存储装置的存储介质；第一控制器根据第一写指令将待存储数据存入第一存储装置的存储介质；第一控制器向第二控制器发送数据报文，数据报文包含待存储数据和关联标识。
根据第五方面，在第五方面的第一种可能的实现方式中，该数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。
根据第五方面，在第五方面第二种可能的实现方式中，关联标识包含第二写指令的部分字段。
根据第五方面或第五方面以上任一种可能的实现方式，在第五方面第三种可能的实现方式中，第一写指令和/或第二写指令为基于NVMe的SQE。
第五方面为第一方面系统对应的第一控制器侧的方法实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第五方面或第五方面任一种可能的实现方 式，在此不再赘述。
第六方面，本申请提供了一种可读介质，包括执行指令，当计算设备的处理器执行该执行指令时，该计算设备执行以上第五方面或以上第五方面的任一种可能的实现方式中的方法。
第七方面，本申请提供了一种计算设备，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当计算设备运行时，处理器执行存储器存储的执行指令，以使计算设备执行以上第五方面或以上第五方面的任一种可能的实现方式中的方法。
第八方面，本申请公开了一种数据备份方法，数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质，该方法包括：第二控制器获取主机触发的写指令，该写指令用于指示第二控制器将待存储数据写入第二存储装置的存储介质；第二控制器接收第一控制器发送的数据报文，数据报文包含待存储数据和关联标识，关联标识用于关联写指令和待存储数据；第二控制器根据写指令将待存储数据存入第二存储装置的存储介质。
根据第八方面，在第八方面的第一种可能的实现方式中，数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。
根据第八方面或第八方面第一种可能的实现方式，在第八方面第二种可能的实现方式中，第二控制器包含内部存储器，第二控制器将待存储数据存入第二存储装置的存储介质之前，该方法还包括：第二控制器将待存储数据存入内部存储器的存储空间，并记录存储空间与关联标识之间的映射关系。
根据第八方面或第八方面以上任意种可能的实现方式，在第八方面第三种可能的实现方式中，该方法还包括：第二控制器根据关联标识确定写指令的存储位置；第二控制器获取写指令包括：第二控制器根据写指令的存储位置获取写指令。
根据第八方面或第八方面以上任一种可能的实现方式，在第八方面第四种可能的实现方式中，关联标识包含写指令的部分字段；第二控制器获取写指令包括：第二控制器根据写指令的部分字段获取写指令。
根据第八方面或第八方面以上任一种可能的实现方式，在第八方面第五种可能的实现方式中，该方法还包括：第二控制器触发完成消息，完成消息用于指示第二控制器完成对待存储数据的存储操作。
根据第八方面或第八方面以上任一种可能的实现方式，在第八方面第六种可能的实现方式中，该写指令为基于NVMe的SQE。
第八方面为第一方面系统对应的第二控制器侧的方法实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第八方面或第八方面任一种可能的实现方式，在此不再赘述。
第九方面，本申请提供了一种可读介质，包括执行指令，当计算设备的处理器执行该执行指令时，该计算设备执行以上第八方面或以上第八方面的任一种可能的实现方式中的方法。
第十方面，本申请提供了一种计算设备，包括：处理器、存储器和总线；存储器用 于存储执行指令，处理器与存储器通过总线连接，当计算设备运行时，处理器执行存储器存储的执行指令，以使计算设备执行以上第八方面或以上第八方面的任一种可能的实现方式中的方法。
第十一方面，本申请公开了一种数据备份装置，数据备份系统包括第一存储装置，第二存储装置和数据备份装置，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质，数据备份装置包括：处理单元，用于触发第一写指令，第一写指令携带关联标识，关联标识用于关联第二写指令和待存储数据；第一写指令用于指示第一控制器将待存储数据存入第一存储装置的存储介质，并指示第一控制器向第二控制器发送数据报文，数据报文包含待存储数据和关联标识；处理单元还用于触发第二写指令，第二写指令用于指示第二控制器将待存储数据存入第二存储装置的存储介质。
根据第十一方面，在第十一方面的第一种可能的实现方式中，该备份装置还包括获取单元，用于获取第二控制器触发的完成消息，完成消息用于指示第二控制器完成对待存储数据的存储操作。
根据第十一方面或第十一方面第一种可能的实现方式，在第十一方面第二种可能的实现方式中，数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。
根据第十一方面或第十一方面第一种可能的实现方式，在第十一方面第三种可能的实现方式中，关联标识包含第二写指令的部分字段。
根据第十一方面或第十一方面以上任一种可能的实现方式，在第十一方面第四种可能的实现方式中，该第一写指令和/或第二写指令为基于NVMe的SQE。
第十一方面为第一方面系统对应的主机侧的装置实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第十一方面或第十一方面任一种可能的实现方式，在此不再赘述。
第十二方面，本申请公开了一种数据备份装置，数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含数据备份装置和存储介质，第二存储装置包含控制器和存储介质，该数据备份装置包括：处理单元，用于获取主机触发的第一写指令和待存储数据，第一写指令携带关联标识，关联标识用于关联待存储数据和第二写指令，该第二写指令由主机触发，用于指示控制器将待存储数据写入所述第二存储装置的存储介质，并根据第一写指令将待存储数据存入第一存储装置的存储介质；发送单元，用于向控制器发送数据报文，数据报文包含待存储数据和关联标识。
根据第十二方面，在第十二方面的第一种可能的实现方式中，数据报文为PCIe报文，关联标识包含控制器的PCIe地址字段。
根据第十二方面，在第十二方面第二种可能的实现方式中，关联标识包含第二写指令的部分字段。
根据第十二方面或第十二方面以上任一种可能的实现方式，在第十二方面第三种可能的实现方式中，该第一写指令和/或第二写指令为基于NVMe的SQE。
第十二方面为第一方面系统对应的第一控制器侧的装置实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第十二方面或第十二方面任一种可能的 实现方式，在此不再赘述。
第十三方面，本申请公开了一种数据备份装置，数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含控制器和存储介质，第二存储装置包含数据备份装置和存储介质，数据备份装置包括：获取单元，用于获取主机触发的写指令，该写指令用于指示数据备份装置将待存储数据写入第二存储装置的存储介质，并接收控制器发送的数据报文，数据报文包含待存储数据和关联标识，关联标识用于关联写指令和待存储数据；处理单元，用于根据写指令将待存储数据存入第二存储装置的存储介质。
根据第十三方面，在第十三方面的第一种可能的实现方式中，数据报文为PCIe报文，关联标识包含数据备份装置的PCIe地址字段。
根据第十三方面或第十三方面第一种可能的实现方式，在第十三方面第二种可能的实现方式中，数据备份装置还包含内部存储器，处理单元将待存储数据存入第二存储装置的存储介质之前，还用于将待存储数据存入内部存储器的存储空间，并记录存储空间与关联标识之间的映射关系。
根据第十三方面或第十三方面以上任意种可能的实现方式，在第十三方面第三种可能的实现方式中，获取单元还用于根据关联标识确定写指令的存储位置，并根据写指令的存储位置获取写指令。
根据第十三方面或第十三方面以上任一种可能的实现方式，在第十三方面第四种可能的实现方式中，关联标识包含写指令的部分字段；获取单元还用于根据写指令的部分字段获取该写指令。
根据第十三方面或第十三方面以上任一种可能的实现方式，在第十三方面第五种可能的实现方式中，处理单元还用于触发完成消息，完成消息用于指示数据备份装置完成对待存储数据的存储操作。
根据第十三方面或第十三方面以上任一种可能的实现方式，在第十三方面第六种可能的实现方式中，该写指令为基于NVMe的SQE。
第十三方面为第一方面系统对应的第二控制器侧的装置实现方式，第一方面或第一方面任一种可能的实现方式中的描述对应适用于第十三方面或第十三方面任一种可能的实现方式，在此不再赘述。
根据本发明实施例公开的技术方案，主机向第一控制器触发第一写指令，并向第二控制器触发第二写指令。其中，主机向第一控制器触发的第一写指令中携带有关联第二写指令和待存储数据的关联标识。第一控制器获取到待存储数据后，主动向第二控制器发送数据报文，数据报文中携带待存储数据和该关联标识。第二控制器获取到数据报文后，根据关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据写入第二存储装置的存储介质，从而避免了第二控制器从主机获取待存储数据的流程。主机与第一存储装置和第二存储装置互联的交换网络的上行端口的数据流量与不进行数据备份时一样，从而提升了系统的总体性能。
附图说明
图1为依据本申请一实施例的NVMe系统的逻辑结构示意图；
图2为一种基于NVMe的数据备份方法的流程示意图；
图3为依据本申请一实施例的数据备份方法的流程示意图；
图4为依据本申请一实施例的主机的硬件结构示意图；
图5为依据本申请一实施例的控制器的硬件结构示意图；
图6为依据本申请一实施例的控制器的硬件结构示意图；
图7为依据本申请一实施例的数据备份方法的流程示意图；
图8为依据本发明一实施例的入口组织结构示意图；
图9为依据本发明一实施例的PCIe地址结构示意图；
图10为依据本发明一实施例的数据存储结构示意图；
图11为依据本申请一实施例的数据备份装置的逻辑结构示意图；
图12为依据本申请一实施例的数据备份装置的逻辑结构示意图；
图13为依据本申请一实施例的数据备份装置的逻辑结构示意图。
具体实施方式
下面将结合附图，对本发明实施例进行描述。
本发明实施例采用术语第一和第二等来区分各个对象，例如第一写指令和第二写指令等，但各个“第一”和“第二”之间不具有逻辑或时序上的依赖关系。
在本发明实施例中，“数据报文”是指第一存储装置向第二存储装置发送的携带载荷数据和关联标识的报文。其中，载荷数据为待存储数据或待存储数据的部分数据。在本发明实施例中，根据待存储数据的大小，第一存储装置可以使用一个数据报文将待存储数据发送至第二存储装置，也可以将待存储数据拆分成多个数据报文发送至第二存储装置，本发明实施例对此不进行限定。在以下描述中，本发明实施例将数据报文中的载荷数据统称为待存储数据。
在本发明实施例中，推送(push)一词是指第一存储装置向第二存储装置主动发送数据报文。
在本发明实施例中，入口为第二存储装置向第一存储装置开放的地址空间，入口地址可以具体为PCIe地址，数据报文可以为PCIe写报文。更具体的，入口可以为第二存储装置的控制器向第一存储装置的控制器开放的地址空间，第一存储装置的控制器可以根据该地址空间向第二存储装置的控制器推送待存储数据。
在本发明实施例中，数据报文中携带的关联标识用于关联待存储数据和写指令。关联标识可以包含入口地址或者入口地址的部分字段。
在本发明实施例中，第一存储装置可以通过入口向第二存储装置推送数据报文，数据报文中可以携带该入口地址。第二存储装置接收到数据报文后，识别入口地址，可以在本地的内部存储器中为该入口分配对应的存储空间，并将数据报文携带的载荷数据缓存至该存储空间，而不是将载荷数据存入入口地址指示的存储空间。内部存储器可以具体为控制器的私有内存空间。
在本发明实施例中，存储装置包含控制器和存储介质，存储控制器以下简称控制器。存储装置的执行主体一般是控制器。例如，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质。第一存储装置与外界交互的主体是第一控制 器，第二存储装置与外界的交互主体是第二控制器。在以下描述中，在于外界交互时，本发明实施例不对存储装置和控制器进行区分。
在本发明实施例中，主机触发的指令的具体实现方式可以为SQE。
在本发明实施例中，主机通过交换网络与第一存储装置和第二存储装置互联。交换网络的上行端口是指交换网络与主机互联的端口。交换网络的上行流量是指与主机之间交互的数据流量。
在本发明实施例中，主机一词是指可以与存储装置进行交互，并向存储装置存储数据的主体。主机可以是一个实体计算机，虚拟机或者网卡等。本发明实施例不限定主机的具体实现形式。
图1为依据本发明一实施例的数据备份系统100的架构图，如图1所示，系统100包含主机101，交换网络102,第一存储装置103和第二存储装置105。其中，第一存储装置103包含第一控制器104和存储介质，第二存储装置105包含第二控制器106和存储介质。第二存储装置105为第一存储装置103的备份(也就是说第一存储装置103的部分数据或者全部数据会被备份到第二存储装置105中)。
在本发明实施例中，存储介质一般为非易失存储介质，用于永久存储数据。存储介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如光盘)、或者半导体介质(例如闪存(Flash)等，本发明实施例不限定存储介质的具体实现形式。在一些实施例中，存储介质还可能进一步包括与控制器分离的远程存储器，例如通过网络与控制器互联的存储介质。
在本发明实施例中，交换网络102可以用于指代：主机101、第一存储装置103以及第二存储装置105互联的任意方式或互联协议等。例如，交换网络102可以为PCIe总线，其中PCIe总线可以包含PCIe交换机，该PCIe交换机与主机101互联。交换网络102还可以为计算机设备内部互联总线，因特网，内联网(intranet)，局域网(local area network，LAN)，广域网络(wide area network，WAN)，存储区域网络(storage area network，SAN)等，或者以上网络的任意组合。本发明实施例不限定交换网络102的具体实现形式。
如图2所示，在传统备份方法中，主机101在进行数据存储时，需要向第一存储装置103和第二存储装置105分别触发相同的写指令。具体的，该写指令为SQE，主机101向与第一存储装置103关联的发送队列中写入该SQE，并通过门铃机制通知第一控制器104有新的SQE。第一控制器104接收到门铃通知后，去发送队列获取对应的SQE，其中，SQE的PRP或SGL字段携带有待存储数据的地址信息。第一控制器104根据SQE中携带的地址信息从主机101侧读取待存储数据，然后将待存储数据存入第一存储装置103存储介质。同理，主机101将相同的读指令写入与第二存储装置105关联的发送队列，并通过命令机制通知第二控制器106有新的SQE。第二控制器106获取到该SQE后，仍需根据SQE携带的地址信息去主机101侧读取待存储数据，然后将待存储数据写入第二存储装置105的存储介质，并向主机101触发完成消息。基于以上流程，需要从主机侧读取两次相同的数据，交换网络102的上行数据流量是没有备份时的两倍。其中，上行数据流量是指与主机101交互的数据流量。
在本发明实施例中，如图3所示，主机101在需要存储数据的时候，分别向第一存 储装置103和第二存储装置105触发第一写指令和第二写指令，其中第一写指令中携带关联标识，该关联标识用于关联待存储数据和第二写指令。第一控制器104获取到第一写指令和待存储数据后，将待存储数据写入第一存储装置103的存储介质，并主动向第二控制器106推送数据报文，数据报文中携带待存储数据和该关联标识。第二控制器106获取到第二写指令和该数据报文后，根据关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据写入第二存储装置105的存储介质，并向主机101触发完成消息。本发明实施例通过第一存储装置103主动向第二存储装置105推送包含待存储数据和关联标识的数据报文，从而避免了第二存储装置105从主机101侧读取报文的步骤，从而减少了第一存储装置103，第二存储装置105与主机101互联的交换网络102的上行端口的流量，提升了系统的总体性能。
图4为依据本申请一实施例的主机400的结构示意图。
如图4所示，主机400包括处理器401，处理器401与系统内存402连接。处理器301可以为中央处理器(CPU)，图像处理器(graphics processing unit，GPU),现场可编程门阵列(Field Programmable Gate Array，FPGA)，专用集成电路(Application Specific Integrated Circuit，ASIC)或数字信号处理器(digital signal processor，DSP)等计算逻辑或以上任意计算逻辑的组合。处理器301可以为单核处理器或多核处理器。
在本申请的一个实施例中，处理器401还可以包括备份逻辑410，备份逻辑410可以为具体的硬件电路或集成在处理器401中的固件模块。如果备份逻辑410为具体的硬件电路，则备份逻辑410执行本申请实施例的方法，如果备份逻辑410为固件模块，则处理器410执行备份逻辑410中的固件代码来实现本申请实施例的技术方案。备份逻辑410包括：(1)用于触发第一写指令的逻辑(电路/固件代码)，第一写指令携带关联标识，该关联标识用于关联第二写指令和待存储数据，该第一写指令用于指示第一存储装置将待存储数据存入第一存储装置的存储介质，并指示第一存储装置向第二存储装置发送数据报文，数据报文包含待存储数据和关联标识；(2)用于触发第二写指令的代码的逻辑(电路/固件代码)，该第二写指令用于指示第二存储介质将待存储数据存入第二存储装置的存储介质。
总线409用于在主机400的各部件之间传递信息，总线409可以使用有线的连接方式或采用无线的连接方式，本申请并不对此进行限定。总线409还连接有输入/输出接口405和通信接口403。
输入/输出接口405连接有输入/输出设备，用于接收输入的信息，输出操作结果。输入/输出设备可以为鼠标、键盘、显示器、或者光驱等。
通信接口403用来实现与其他设备或网络之间的通信，通信接口403可以通过有线或者无线的形式与其他设备或网络互联。例如，主机400可以通过通信接口403与交换网络互联，并通过交换网络连接控制器。
本申请实施例的一些特征可以由处理器401执行系统内存402中的软件代码来完成/支持。系统内存402可以包括一些软件，例如，操作系统408(例如Darwin、RTXC、LINUX、UNIX、OS X、WINDOWS或嵌入式操作系统(例如Vxworks))，应用程序407，和备份模块406等。
在本申请的一个实施例中，处理器401执行备份模块406来实现本申请实施例的技术方案。备份模块406包括：(1)用于触发第一的代码，第一写指令携带关联标识，该关联标识用于关联第二写指令和待存储数据，该第一写指令用于指示第一存储装置将待存储数据存入第一存储装置的存储介质，并指示第一存储装置向第二存储装置发送数据报文，数据报文包含待存储数据和关联标识；(2)用于触发第二写指令的代码，该第二写指令用于指示第二存储介质将待存储数据存入第二存储装置的存储介质。
此外，图4仅仅是一个主机400的例子，主机400可能包含相比于图4展示的更多或者更少的组件，或者有不同的组件配置方式。同时，图4中展示的各种组件可以用硬件、软件或者硬件与软件的结合方式实施。
图5为依据本申请一实施例的控制器500的结构示意图。
如图5所示，控制器500包括处理器501，处理器501与系统内存502连接。处理器401可以CPU，GPU,FPGA，ASIC或DSP等计算逻辑或以上任意计算逻辑的组合。处理器401可以为单核处理器或多核处理器。
在本申请的一个实施例中，处理器501还可以包括备份逻辑505，备份逻辑505可以为具体的硬件电路或集成在处理器501中的固件模块。如果备份逻辑505为具体的硬件电路，则备份逻辑505执行本申请实施例的方法，如果备份逻辑505为固件模块，则处理器501执行备份逻辑505中的固件代码来实现本申请实施例的技术方案。备份逻辑505包括：(1)用于获取主机触发的第一写指令和待存储数据的逻辑(电路/固件代码)，该第一写指令携带关联标识，关联标识用于关联待存储数据和第二写指令；(2)用于根据第一写指令将待存储数据存入第一存储装置的存储介质的逻辑(电路/固件代码)；(3)用于向第二存储装置发送数据报文的逻辑(电路/固件代码)，该数据报文包含待存储数据和关联标识。
总线507用于在控制器500的各部件之间传递信息，总线507可以使用有线的连接方式或采用无线的连接方式，本申请并不对此进行限定。总线507还可以连接有通信接口503。
通信接口503用来实现与其他设备或网络之间的通信，通信接口503可以通过有线或者无线的形式与其他设备或网络互联。例如，控制器500通过通信接口503与交换网络和存储介质互联。
本申请实施例的一些特征可以由处理器501执行系统内存502中的软件代码来完成/支持。系统内存502可以包括一些软件，例如，操作系统504(例如Darwin、RTXC、LINUX、UNIX、OS X、WINDOWS、macOS或嵌入式操作系统(例如Vxworks))和备份模块506等。
在本申请的一个实施例中，处理器501执行备份模块506来实现本申请实施例的技术方案。备份模块506包括：(1)用于获取主机触发的第一写指令和待存储数据的代码，该第一写指令携带关联标识，关联标识用于关联待存储数据和第二写指令；(2)用于根据第一写指令将待存储数据存入第一存储装置的存储介质的代码；(3)用于向第二存储装置发送数据报文的代码，该数据报文包含待存储数据和关联标识。
此外，图5仅仅是一个控制器500的例子，控制器500可能包含相比于图5展示的更多或者更少的组件，或者有不同的组件配置方式。同时，图5中展示的各种组件可以用硬件、软件或者硬件与软件的结合方式实施。
图6为依据本申请一实施例的控制器600的结构示意图。
如图6所示，控制器600包括处理器601，处理器601与系统内存602连接。处理器401可以CPU，GPU,FPGA，ASIC或DSP等计算逻辑或以上任意计算逻辑的组合。处理器401可以为单核处理器或多核处理器。
在本发明实施例中，处理器601内部还可以包含寄存器，该寄存器可以开放给其他存储装置的控制器访问。更具体的，该寄存器可以作为PCIe地址空间开放给其他存储装置的控制器，供其他存储装置的控制器通过PCIe地址进行访问。
在本申请的一个实施例中，处理器601还可以包括备份逻辑605，备份逻辑605可以为具体的硬件电路或集成在处理器601中的固件模块。如果备份逻辑605为具体的硬件电路，则备份逻辑605执行本申请实施例的方法，如果备份逻辑605为固件模块，则处理器601执行备份逻辑605中的固件代码来实现本申请实施例的技术方案。备份逻辑605包括：(1)用于获取主机触发的写指令的逻辑(电路/固件代码)；(2)用于接收所述第一存储装置发送的数据报文的逻辑(电路/固件代码)，该数据报文包含待存储数据和关联标识，关联标识用于关联该写指令和待存储数据；(3)用于根据该写指令将待存储数据存储入第二存储装置的存储介质的逻辑(电路/固件代码)。
总线607用于在控制器600的各部件之间传递信息，总线607可以使用有线的连接方式或采用无线的连接方式，本申请并不对此进行限定。总线607还可以连接有通信接口603。
通信接口603用来实现与其他设备或网络之间的通信，通信接口603可以通过有线或者无线的形式与其他设备或网络互联。例如，控制器600通过通信接口603与主机和存储介质互联，控制器600也可以通过通信接口603连接网络，并通过网络与主机或存储介质互联。
本申请实施例的一些特征可以由处理器601执行系统内存602中的软件代码来完成/支持。系统内存602可以包括一些软件，例如，操作系统604(例如Darwin、RTXC、LINUX、UNIX、OS X、WINDOWS、macOS或嵌入式操作系统(例如Vxworks))和备份模块606等。
在本申请的一个实施例中，处理器601执行备份模块606来实现本申请实施例的技术方案。备份模块606包括：(1)用于获取主机触发的写指令的代码；(2)用于接收第一存储装置发送的数据报文的代码，数据报文包含待存储数据和关联标识，关联标识用于关联写指令和待存储数据；(3)用于根据写指令将待存储数据存入第二存储装置的存储介质的代码。
此外，图6仅仅是一个控制器600的例子，控制器600可能包含相比于图6展示的更多或者更少的组件，或者有不同的组件配置方式。同时，图6中展示的各种组件可以用硬件、软件或者硬件与软件的结合方式实施。
为了减少数据备份过程中对交换网络的上行端口的带宽的占用，本发明实施例提供了一种数据备份方法。数据备份系统包括第一存储装置，第二存储装置和主机，其中第一存储装置是第二存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质。如图7所示，方法700包括：
步骤701：主机触发第一写指令。
其中，第一写指令携带关联标识，该关联标识用于关联第二写指令和待存储数据。
在本发明实施例中，第一写指令可以具体为基于NVMe的SQE。在以下描述中，以第一写指令为SQE为例进行解释说明。但应理解，本发明实施例并不限定第一写指令的具体实现形式。
在本发明实施例中，主机向触发第一写指令的流程可以参照NMVe标准。主机将SQE写入与第一控制器关联的发送队列，并通过门铃通知第一控制器有新的SQE进了与第一控制器相关的发送队列，以便提醒第一控制器读取SQE。
在本发明实施例中，主机触发第一写指令也可以为其他实现形式。例如，主机可以将第一写指令直接发送至第一控制器。本发明不限定主机触发第一写指令的具体实现形式。
步骤702：主机触发第二写指令。
同理，第二写指令可以为基于NVMe的SQE。在以下描述中，以第二写指令为SQE为例进行解释说明。但应理解，本发明实施例不限定第二写指令的具体实现形式。
在本发明实施例中，第二写指令可以具体为写指令，用于指示第二控制器将待存储数据存入第二存储装置的存储介质。
在本发明实施例中，主机触发第二写指令可以为主机将第二写指令写入与第二控制器关联的发送队列，并通过门铃通知第二控制器有新的SQE进入了与第二控制器相关的发送队列，以便提醒第二控制器读取SQE。主机触发第二写指令也可以为其他实现形式。例如，主机可以将第二写指令直接发送至第二控制器。本发明不限定主机触发第二写指令的具体实现形式。
步骤703：第一控制器获取第一写指令。
在本发明实施例中，第一控制器可以从与主机关联的发送队列里获取第一写指令。具体的，第一控制器接收到主机的门铃通知，该门铃用于指示有新的SQE到达发送队列，第一控制器去发送队列中获取该SQE。第一控制器也可以直接接收主机发送的第一写指令。本发明实施例不限定第一控制器获取第一写指令的具体实现形式。
步骤704：第一控制器获取待存储数据。
本发明实施例中，第一写指令的格式可以参照NVMe标准，主机可以在第一写指令中通过SQE的PRP或SGL字段指示待存储数据的地址信息。第一控制器根据该地址信息从主机侧读取待存储数据。
在本发明实施例中，主机也可以直接向第一控制器发送待存储数据，第一控制器从主机直接接收待存储数据。本发明实施例不限定第一控制器获取待存储数据的具体实现形式。
步骤705：第一控制器根据第一写指令将待存储数据存入第一存储装置的存储介质。
步骤706：第一控制器向第二控制器发送数据报文。
其中，该数据报文中包含待存储数据和该关联标识。在具体实现过程中，因为数据报文携带的载荷数据的大小受限，第一控制器可以将待存储数据分为多个数据报文发送至第二控制器。
在本发明实施例中，第一控制器可以主动向第二控制器推送该数据报文。其中，数据报文携带的关联标识用于关联待存储数据和第二写指令。本发明实施例不限定关联标识的具体实现方式，关联标识可以直接或间接的指示数据报文中携带的待存储数据对应 的第二写指令。
在本发明实施例中，数据报文可以为PCIe写操作报文，更具体的，数据报文可以是事务层包，载荷数据可以为传输层包(transaction layer packet，TLP)中携带的负荷(payload)，该关联标识可以为TLP的PCIe地址或者PCIe地址的部分字段。
在本发明实施例中，第二控制器将其一部分地址空间开放给第一控制器。更具体的，第二控制器给第一控制器开放的地址空间可以作为第二控制器的PCIe地址空间。第一控制器可以访问该PCIe地址访问。例如，第二控制器可以将基地址寄存器的一部分PCIe地址开放给第一控制器访问。
在以下描述中，以基地址寄存器举例说明，但应理解本发明实施例不限定第二控制器开放给第一控制器访问的地址空间的种类和形式。
在本发明实施例中，第二控制器可以将一部分基地址寄存器的PCIe地址组织成入口(portal)的形式，每一个入口占据该基地址寄存器的一部分PCIe地址空间。第一控制器可以通过入口向第二控制器写入数据报文。入口即第一控制器向第二控制器进行PCIe写操作的数据入口，在下面的描述中，会对入口的功能进行更详细的描述。
在本发明实施例中，第一控制器向第二控制器推送的数据报文可以为PCIe报文，第一控制器通过将与第二写指令关联的待存储数据通过入口写入到第二控制器，PCIe报文的地址段指示该写操作对应的入口，即入口地址为数据报文中PCIe地址或者PCIe地址的部分字段。
在本发明实施例中，关联标识可以为入口地址或者入口地址的部分字段。第二控制器接收到数据报文后，还用于根据关联标识确定第二写指令的存储地址，并根据第二写指令的存储地址获取第二写指令。存储第二写指令的地址可以为提交队列中存储第二写指令的槽位地址。
在本发明实施例中，主机和第二控制器维护有入口与发送队列中槽位的对应关系。主机在触发第一写指令和第二写指令的时候，将第二写指令存入关联标识指示的入口对应的发送队列的槽位，并在第一写指令中携带该关联标识。第一控制器根据该关联标识向第二控制器发送数据报文，数据报文中携带该关联标识。第二控制器获取到数据报文后，根据关联标识确定与主机关联的发送队列中存储第二地址的槽位，并从该槽位中获取待存储数据关联的第二写指令。
本发明不限定PCIe地址空间里的入口的组织方式，只需要保证在数据备份操作的过程中，每个入口和具体的第二写指令唯一对应，每个入口唯一地关联到具体的第二写指令。例如，可以将第二控制器的基地址寄存器的一部分PCIe地址组织成通孔(aperture)的形式，每一个通孔中包含多个入口，即入口可以组织成数组的形式，通过数组基地址加入口偏移量寻址到入口，这个数组称为通孔。每一个入口关联发送队列的一个槽位。图8为基地址寄存器的结构示意图，如图8所示，每个通孔由一组入口P 0～P N组成。
图9为依据本发明一实施例的PCIe数据报文中的PCIe地址结构。如图9所示，PCIe地址结构中包含BAR的基地址、通孔偏移量以及入口偏移量。其中，BAR和通孔偏移量用于唯一的确定通孔，入口偏移量用于指示该通孔中具体的入口。在本发明实施例中，待存储数据由第一控制器通过PCIe BAR空间的通孔“推送”到第二控制器。“推送”指的是第一控制器发起的PCIe写事务。
在本发明实施例中，入口还可以任意分布在PCIe地址空间，在PCIe空间中任意分布的入口称为任意的“数据入口”。
在本发明实施例中，关联标识为入口地址或者入口地址的部分字段。主机和第二控制器维护有入口与SQ中槽位的对应关系，SQ槽位与入口一一对应。主机通过入口与SQ槽位的对应关系触发第一写指令和第二写指令。第二控制器根据SQ槽位与入口的对应关系，可以根据数据报文中的关联标识获取到对应的第二写指令。本发明实施例使用存储第二写指令的SQ槽位将入口与第二写指令关联起来，通过SQ槽位确定入口对应的第二写指令。
在本发明实施例的其他实现方式中，关联标识还可以为第二写指令的指示信息。例如，关联标识还可以包含第二写指令的部分字段，第二控制器根据关联标识获取第二写指令。具体的，第二写指令可以为SQE，关联标识为SQE的指示信息，用于唯一的确定一个SQE。
在本发明实施例中，通过在数据报文中携带SQE的指示信息，从而直接实现SQE与待存储数据的关联，而不是通过SQ槽位实现间接的关联。例如，如果一个SQ中的每个SQE有各自独特的命令标识CID，则关联标识可以由“队列ID+CID”组成。如果每个SQE的CID都是唯一的，则关联标识可以为对应SQE携带的CID。在其他实现方式中，关联标识还可以为CID的一部分。在本发明实施例中，关联标识还可以使用特别定义的SGL类型或者SGL子类型或者SQE中其他字段指定，只要第二控制器可以根据关联标识唯一的确定第二写指令，本发明实施例不限定关联标识的具体实现方式。
步骤707：第二控制器获取第二写指令。
本发明实施例中，第二控制器可以从与主机关联的发送队列里获取该第二写指令。更具体的，第二控制器接收到主机的门铃通知，该门铃用于指示有新的SQE到达第二控制器所对应的发送队列，控制器在接收到主机的门铃后，去发送队列获取该第二写指令。第二控制器也可以直接接收主机发送的第二写指令。本发明实施例不限定第二控制器获取第二写指令的具体实现形式。
本发明实施例中，第二写指令的格式可以参照NVMe标准，但本发明实施例通过关联标识关联了待存储数据和第二写指令，且待存储数据由第一控制器主动推送至第二控制器。第二写指令不再需要第二控制器主动通过PCIe读操作去获取待存储数据，所以第二写指令中不需要再通过SGL域或者PRP域携带待存储数据的地址信息。在具体实现中，第二写指令的SGL域或者PRP域中可以不携带其他信息，第二控制器对SGL域或者PRP域的处理方法可以为“忽略”，即本发明实施例可以省略SGL或者PRP。
在本发明实施例中，关联标识可以为入口地址或者入口地址的部分字段。第二控制器维护有入口与发送队列中槽位的对应关系。第二控制器接收到数据报文后，还用于根据关联标识确定第二写指令的存储地址，并根据第二写指令的存储地址获取第二写指令。
在本发明实施例中，关联标识还可以为第二写指令的指示信息。例如，关联标识还可以包含第二写指令的部分字段。第二控制器还可以根据该关联标识在发送队列中查找该关联标识指示的第二写指令。
步骤708：第二控制器获取待存储数据。
在本发明实施例中，数据报文中携带待存储数据。数据报文中携带的地址信息指示 第二控制器的一个入口，第二控制器的入口用于接收数据报文，是第一控制器向第二控制器发送数据报文的入口。第二控制器接收到数据报文后，用于待存储数据的存储空间可以是第二控制器的内部存储器，而不是将待存储数据存入入口地址指示的存储空间。
第二控制器接收到数据报文后，解析数据报文获得数据报文的地址，获得关联标识，并识别出关联标识是第二控制器想第一控制器开放的入口的地址信息，第二地址将数据报文中的待存储数据存入自己的内部存储器。具体的，第二控制器可以为每个入口在自己的内部存储器中分配具体的存储块，用于存储该入口接收到的待存储数据。为了便于数据管理和查询，第二控制器可以建立存储块与入口的映射关系。第二控制器用于存储数据的内部存储器可以不再通过PCIe寻址的方式供外界访问，不是也不作为命令内存缓冲区，本发明实施例不限定用于存储待存储数据的存储块的具体实现方式。
可选的，第一控制器可以使用多个数据报文对待存储数据进行发送。第二控制器可以使用根数据结构对从入口接收的数据进行组织。如图10所示，数据报文可以具体为PCIe写报文，第一控制器通过PCIe写操作将待写入数据写入第二控制器。第二控制器接收到数据报文后，可以将数据组织成根数据结构，以方便数据的管理。
在本发明实施例中，第二控制器接收到数据报文后，解码数据报文的地址并识别关联标识，根据关联标识识别入口和根数据结构，从内存存储器中为数据分配空闲的内存块，并将数据保存至分配的内存块，将内存块附到根数据结构。第二控制器首先将数据存储在自己的内部存储器中，在满足一定的条件时，将自己的内部存储器中存储的数据存储至第二存储装置的存储介质。此处的满足条件可以为第二控制器获取到第二写指令，或者数据量积累到第二NMVe控制器可以对存储介质进行一次写操作的程度。其中，第二控制器的内部存储器可以为控制器的私有内存。
本发明实施例不限定第二控制器获取数据报文和第二写指令的顺序，第二控制器可以先接收到第一控制器推送的数据报文，并根据关联标识确定第二写指令。第二控制器也可以先获取第二写指令，再根据第二写指令获取对应的待存储数据。例如，第二控制器可以根据第二写指令确定该关联标识，然后根据关联标识确定对应的入口，并根据关联标识从为该入口分配的存储空间中获取存储的载荷数据。
本发明实施例不限定与第二写指令对应的待存储数据和第二写指令本身的到达第二控制器的顺序。
第二控制器可以维护有SQ槽位与入口的一一对应关系，当从一个槽位中获取到第二写指令后，可以根据维护的对应关系确定该第二写指令对应的入口。如果第二控制器检测到对应的入口还没有数据到达，则第二控制器挂起第二写指令，等待数据到来。直至第二控制器检测到对应的入口有数据到达，便可以执行对待存储数据的写操作。
如果一部分数据先于第二写指令到达第二控制器，第二控制器根据数据报文中携带的关联标识检测到数据对应的第二写指令还没有到达第二控制器或者对应的SQ槽位。则第二控制器可以将数据附到根数据结构，等待相关的第二写指令到来，直至对应的第二写指令到达第二控制器或者第二控制器可寻址的SQ槽位，第二控制器获取该第二写指令，并根据第二写指令将待存储数据存入第二存储装置的存储介质。
步骤709：第二控制器将待存储数据存入第二存储装置的存储介质。
在本发明实施例中，第一控制器可以通过多个数据报文发送待存储数据，第二控制 器通过入口接收第一控制器推送的待存储数据和第二控制器向第二存储装置的存储介质的写操作可以并行执行。如果当前通过入口接收的待存储数据处理完成，即当前通过入口接收到的数据已经完全写入第二存储装置的存储介质，但系统需要更多的数据来完成备份操作，第二控制器则挂起第二写指令等待数据到来。
步骤710：第二控制器触发完成消息。
第二控制器完成对待存储数据的存储操作后，会触发完成消息。该完成消息用于指示第二控制器完成对待存储数据的存储操作。
在本发明实施例中，完成消息可以为触发完成队列条目(completion queue entry，CQE)，CQE用于指示第二控制器完成第二写指令指示的写操作。第二控制器触发完成消息可以具体为第二控制器完成写操作后，将CQE写入完成队列(completion queue，CQ)，并通过中断通知主机。
根据本发明实施例公开的技术方案，主机向第一控制器触发第一写指令，并向第二控制器触发第二写指令。其中，主机向第一控制器触发的第一写指令中携带有关联第二写指令和待存储数据的关联标识。第一控制器获取到待存储数据后，主动向第二控制器发送数据报文，数据报文中携带待存储数据和该关联标识。第二控制器获取到数据报文后，根据关联标识关联第二写指令和待存储数据，并根据第二写指令将待存储数据写入第二存储装置的存储介质，从而避免了第二控制器从主机获取待存储数据的流程。主机与第一存储装置和第二存储装置互联的交换网络的上行端口的数据流量与不进行数据备份时一样，从而提升了系统的总体性能。
图11为依据本发明一实施例的一种数据备份装置1100的逻辑结构示意图。数据备份系统包括第一存储装置，第二存储装置和数据备份装置1100，第二存储装置为第一存储装置的备份，第一存储装置包含第一控制器和存储介质，第二存储装置包含第二控制器和存储介质，如图11所示，数据备份装置1100包括处理单元1101和获取单元1102，其中，
处理单元1101用于触发第一写指令，第一写指令携带关联标识，该关联标识用于关联第二写指令和待存储数据；第一写指令用于指示第一控制器将待存储数据存入第一存储装置的存储介质，并指示第一控制器向第二控制器发送数据报文，数据报文包含待存储数据和关联标识。处理单元1101还用于触发第二写指令，第二写指令用于指示第二控制器将待存储数据存入第二存储装置的存储介质。
可选的，备份装置1100还包括获取单元1102，用于获取第二控制器触发的完成消息，该完成消息用于指示第二控制器完成对待存储数据的存储操作。
可选的，数据报文为PCIe报文，关联标识包含第二控制器的PCIe地址字段。
可选的，关联标识包含第二写指令的部分字段。
可选的，该第一写指令和/或第二写指令为基于NVMe的SQE。
在本申请实施例中，处理单元1101和获取单元1102可以由图4中的处理器401中的备份逻辑410来实现，或者由图4中的处理器401和系统内存402中的备份模块406来实现。
本申请实施例为以上实施例对应的主机的装置实施例，以上实施例部分的特征描述适用于本申请实施例，在此不再赘述。
图12为依据本发明一实施例的一种备份装置1200的逻辑结构示意图。数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含数据备份装置1200和存储介质，第二存储装置包含控制器和存储介质。如图12所示，备份装置1200包括处理单元1201和发送单元1202，其中，
处理单元1201用于获取主机触发的第一写指令和待存储数据，第一写指令携带关联标识，关联标识用于关联待存储数据和第二写指令，该第二写指令由主机触发，用于指示控制器将待存储数据写入所述第二存储装置的存储介质，并根据第一写指令将待存储数据存入第一存储装置的存储介质。
发送单元1202用于向控制器发送数据报文，数据报文包含待存储数据和关联标识。
可选的，数据报文为PCIe报文，关联标识包含该控制器的PCIe地址字段。
可选的，关联标识包含第二写指令的部分字段。
可选的，该第一写指令和/或第二写指令为基于NVMe的SQE。
在本申请实施例中，处理单元1201和发送单元1202可以由图5中的处理器501中的备份逻辑505来实现，或者由图5中的处理器501和系统内存502中的备份模块506来实现。
本申请实施例为以上实施例对应的第一控制器的装置实施例，以上实施例部分的特征描述适用于本申请实施例，在此不再赘述。
图13为依据本发明一实施例的一种备份装置1300的逻辑结构示意图。数据备份系统包括第一存储装置，第二存储装置和主机，第二存储装置为第一存储装置的备份，第一存储装置包含控制器和存储介质，第二存储装置包含数据备份装置1300和存储介质。如图13所示，备份装置1300包括获取单元1301和处理单元1302，其中，
获取单元1301用于获取主机触发的写指令，该写指令用于指示数据备份装置将待存储数据写入第二存储装置的存储介质，并接收控制器发送的数据报文，数据报文包含待存储数据和关联标识，关联标识用于关联写指令和待存储数据。
处理单元1302用于根据写指令将待存储数据存入第二存储装置的存储介质。
可选的，数据报文为PCIe报文，关联标识包含数据备份装置1301的PCIe地址字段。
可选的，数据备份装置1300还包含内部存储器，处理单元1302将待存储数据存入第二存储装置的存储介质之前，还用于将待存储数据存入内部存储器的存储空间，并记录存储空间与关联标识之间的映射关系。
可选的，获取单元1301还用于根据关联标识确定写指令的存储位置，并根据写指令的存储位置获取写指令。
可选的，关联标识包含写指令的部分字段，获取单元1301还用于根据写指令的部分字段获取该写指令。
可选的，处理单元1302还用于触发完成消息，完成消息用于指示数据备份装置1300完成对待存储数据的存储操作。
可选的，该写指令为基于NVMe的SQE。
在本申请实施例中，获取单元1301和处理单元1302可以具体由图6中的处理器601中的备份逻辑605来实现，或者由图6中的处理器601和系统内存602中的备份模块606 来实现。
本申请实施例为以上实施例对应的第二控制器的装置实施例，以上实施例部分的特征描述适用于本申请实施例，在此不再赘述。
以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者替换其中部分技术特征；而这些修改或者替换，并不使相应技术方案脱离权利要求的保护范围。

Claims (32)

  1. 一种数据备份系统，其特征在于，所述系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含第一控制器和存储介质，所述第二存储装置包含第二控制器和存储介质；
    所述主机用于触发第一写指令和第二写指令，所述第一写指令携带关联标识，所述关联标识用于关联待存储数据和所述第二写指令；
    所述第一控制器用于获取所述第一写指令和所述待存储数据，根据所述第一写指令将所述待存储数据存入所述第一存储装置的存储介质，并向所述第二控制器发送数据报文，所述数据报文包含所述待存储数据和所述关联标识；
    所述第二控制器用于获取所述第二写指令和所述数据报文，并根据所述第二写指令将所述待存储数据存入所述第二存储装置的存储介质。
  2. 根据权利要求1所述的系统，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述第二控制器的PCIe地址字段。
  3. 根据权利要求1或2所述的系统，其特征在于，所述第二控制器包含内部存储器，所述第二控制器将所述待存储数据存入所述第二存储装置的存储介质之前，还用于将所述待存储数据存入所述内部存储器的存储空间，并记录所述存储空间与所述关联标识之间的映射关系。
  4. 根据权利要求1-3任一项所述的系统，其特征在于，所述第二控制器还用于根据所述关联标识确定所述第二写指令的存储位置，所述第二控制器用于根据所述第二写指令的存储位置获取所述第二写指令。
  5. 根据权利要求1-3任一项所述的系统，其特征在于，所述关联标识包含所述第二写指令的部分字段，所述第二控制器用于根据所述第二写指令的部分字段获取所述第二写指令。
  6. 根据权利要求1-5任一项所述的系统，其特征在于，所述第一写指令和/或所述第二写指令为基于非易失性高速传输总线NVMe的提交队列条目SQE。
  7. 一种数据备份方法，其特征在于，数据备份系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含第一控制器和存储介质，所述第二存储装置包含第二控制器和存储介质，所述方法包括：
    所述主机触发第一写指令，所述第一写指令携带关联标识，所述关联标识用于关联第二写指令和待存储数据；所述第一写指令用于指示所述第一控制器将所述待存储数据存入所述第一存储装置的存储介质，并指示所述第一控制器向第二控制器发送数据报文，所述数据报文包含所述待存储数据和所述关联标识；
    所述主机触发第二写指令，所述第二写指令用于指示所述第二控制器将所述待存储数据存入所述第二存储装置的存储介质。
  8. 根据权利要求7所述的方法，其特征在于，所述第一写指令和/或所述第二写指令为基于非易失性高速传输总线NVMe的提交队列条目SQE。
  9. 根据权利要求7或8所述的方法，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述第二控制器的PCIe地址字段。
  10. 根据权利要求7或8所述的方法，其特征在于，所述关联标识包含所述第二写指令的部分字段。
  11. 一种数据备份方法，其特征在于，数据备份系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含第一控制器和存储介质，所述第二存储装置包含第二控制器和存储介质，所述方法包括：
    所述第一控制器获取所述主机触发的第一写指令和待存储数据，所述第一写指令携带关联标识，所述关联标识用于关联所述待存储数据和第二写指令，所述第二写指令由所述主机触发，用于指示所述第二控制器将所述待存储数据写入所述第二存储装置的存储介质；
    所述第一控制器根据所述第一写指令将所述待存储数据存入所述第一存储装置的存储介质；
    所述第一控制器向所述第二控制器发送数据报文，所述数据报文包含所述待存储数据和所述关联标识。
  12. 根据权利要求11所述的方法，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述第二控制器的PCIe地址字段。
  13. 根据权利要求11所述的方法，其特征在于，所述关联标识包含所述第二写指令的部分字段。
  14. 一种数据备份方法，其特征在于，数据备份系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含第一控制器和存储介质，所述第二存储装置包含第二控制器和存储介质，所述方法包括：
    所述第二控制器获取所述主机触发的写指令，所述写指令用于指示所述第二控制器将待存储数据写入所述第二存储装置的存储介质；
    所述第二控制器接收所述第一控制器发送的数据报文，所述数据报文包含所述待存储数据和关联标识，所述关联标识用于关联所述写指令和所述待存储数据；
    所述第二控制器根据所述写指令将所述待存储数据存入所述第二存储装置的存储介质。
  15. 根据权利要求14所述的方法，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述第二控制器的PCIe地址字段。
  16. 根据权利要求14或15所述的方法，其特征在于，所述第二控制器包含内部存储器，所述第二控制器将所述待存储数据存入所述第二存储装置的存储介质之前，所述方法还包括：
    所述第二控制器将所述待存储数据存入所述内部存储器的存储空间，并记录所述存储空间与所述关联标识之间的映射关系。
  17. 根据权利要求14-16任一项所述的方法，其特征在于，所述方法还包括：
    所述第二控制器根据所述关联标识确定所述写指令的存储位置；
    所述第二控制器获取所述写指令包括：所述第二控制器根据所述写指令的存储位置获取所述写指令。
  18. 根据权利要求14-16任一项所述的方法，其特征在于，所述关联标识包含所述写指令的部分字段；
    所述第二控制器获取所述写指令包括：所述第二控制器根据所述写指令的部分字段获取所述写指令。
  19. 根据权利要求14-18任一项所述的方法，其特征在于，所述写指令为基于非易失性高速传输总线NVMe的提交队列条目SQE。
  20. 一种数据备份装置，其特征在于，数据备份系统包括第一存储装置，第二存储装置和所述数据备份装置，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含第一控制器和存储介质，所述第二存储装置包含第二控制器和存储介质，所述数据备份装置包括：
    处理单元，用于触发第一写指令，所述第一写指令携带关联标识，所述关联标识用于关联第二写指令和待存储数据；所述第一写指令用于指示所述第一控制器将所述待存储数据存入所述第一存储装置的存储介质，并指示所述第一控制器向第二控制器发送数据报文，所述数据报文包含所述待存储数据和所述关联标识；
    所述处理单元还用于触发第二写指令，所述第二写指令用于指示所述第二控制器将所述待存储数据存入所述第二存储装置的存储介质。
  21. 根据权利要求20所述的数据备份装置，其特征在于，所述第一写指令和/或所述第二写指令为基于非易失性高速传输总线NVMe的提交队列条目SQE。
  22. 根据权利要求20或21所述的数据备份装置，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述第二控制器的PCIe地址字段。
  23. 根据权利要求20或21所述的数据备份装置，其特征在于，所述关联标识包含所述第二写指令的部分字段。
  24. 一种数据备份装置，其特征在于，数据备份系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含所述数据备份装置和存储介质，所述第二存储装置包含控制器和存储介质，所述数据备份装置包括：
    处理单元，用于获取所述主机触发的第一写指令和待存储数据，所述第一写指令携带关联标识，所述关联标识用于关联所述待存储数据和第二写指令，并根据所述第一写指令将所述待存储数据存入所述第一存储装置的存储介质，所述第二写指令由所述主机触发，用于指示所述控制器将所述待存储数据写入所述第二存储装置的存储介质；
    发送单元，用于向所述控制器发送数据报文，所述数据报文包含所述待存储数据和所述关联标识。
  25. 根据权利要求24所述的数据备份装置，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述控制器的PCIe地址字段。
  26. 根据权利要求24所述的数据备份装置，其特征在于，所述关联标识包含所述第二写指令的部分字段。
  27. 一种数据备份装置，其特征在于，数据备份系统包括第一存储装置，第二存储装置和主机，所述第二存储装置为所述第一存储装置的备份，所述第一存储装置包含控制器和存储介质，所述第二存储装置包含所述数据备份装置和存储介质，所述数据备份装置包括：
    获取单元，用于获取所述主机触发的写指令，并接收所述控制器发送的数据报文，所述数据报文包含待存储数据和关联标识，所述关联标识用于关联所述写指令和所述待存储数据，所述写指令用于指示所述数据备份装置将所述待存储数据写入所述第二存储装置的存储介质；
    处理单元，用于根据所述写指令将所述待存储数据存入所述第二存储装置的存储介质。
  28. 根据权利要求27所述的数据备份装置，其特征在于，所述数据报文为PCIe报文，所述关联标识包含所述数据备份装置的PCIe地址字段。
  29. 根据权利要求27或28所述的数据备份装置，其特征在于，所述数据备份装置还包含内部存储器，所述处理单元将所述待存储数据存入所述第二存储装置的存储介质之前，还用于将所述待存储数据存入所述内部存储器的存储空间，并记录所述存储空间与所述关联标识之间的映射关系。
  30. 根据权利要求27-29任一项所述的装置，其特征在于，所述获取单元还用于根据所述关联标识确定所述写指令的存储位置，并根据所述写指令的存储位置获取所述写指令。
  31. 根据权利要求27-29任一项所述的装置，其特征在于，所述关联标识包含所述写指令的部分字段；
    所述获取单元还用于根据所述写指令的部分字段获取所述写指令。
  32. 根据权利要求27-31任一项所述的装置，其特征在于，所述写指令为基于非易失性高速传输总线NVMe的提交队列条目SQE。
PCT/CN2019/090758 2018-10-31 2019-06-11 一种数据备份方法、装置及系统 WO2020087931A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811285163.3 2018-10-31
CN201811285163.3A CN109614264B (zh) 2018-10-31 2018-10-31 一种数据备份方法、装置及系统

Publications (1)

Publication Number Publication Date
WO2020087931A1 true WO2020087931A1 (zh) 2020-05-07

Family

ID=66002876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/090758 WO2020087931A1 (zh) 2018-10-31 2019-06-11 一种数据备份方法、装置及系统

Country Status (2)

Country Link
CN (1) CN109614264B (zh)
WO (1) WO2020087931A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109614264B (zh) * 2018-10-31 2023-12-08 华为技术有限公司 一种数据备份方法、装置及系统
CN114095386B (zh) * 2020-07-01 2024-03-26 阿里巴巴集团控股有限公司 一种数据流统计方法、设备及存储介质
CN113360318B (zh) * 2021-04-22 2022-11-15 山东英信计算机技术有限公司 一种资料备份方法、系统、存储介质及设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140047058A1 (en) * 2012-08-09 2014-02-13 Spectra Logic Corporation Direct memory access of remote data
CN103645969A (zh) * 2013-12-13 2014-03-19 华为技术有限公司 数据复制方法及数据存储系统
CN106933502A (zh) * 2015-12-29 2017-07-07 伊姆西公司 用于同步数据块索引的方法和系统
CN109614264A (zh) * 2018-10-31 2019-04-12 华为技术有限公司 一种数据备份方法、装置及系统

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201101020A (en) * 2009-06-30 2011-01-01 Jmicron Technology Corp Data backup apparatus and data backup method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140047058A1 (en) * 2012-08-09 2014-02-13 Spectra Logic Corporation Direct memory access of remote data
CN103645969A (zh) * 2013-12-13 2014-03-19 华为技术有限公司 数据复制方法及数据存储系统
CN106933502A (zh) * 2015-12-29 2017-07-07 伊姆西公司 用于同步数据块索引的方法和系统
CN109614264A (zh) * 2018-10-31 2019-04-12 华为技术有限公司 一种数据备份方法、装置及系统

Also Published As

Publication number Publication date
CN109614264A (zh) 2019-04-12
CN109614264B (zh) 2023-12-08

Similar Documents

Publication Publication Date Title
US11960725B2 (en) NVMe controller memory manager providing CMB capability
EP2849076B1 (en) Dma transmission method and system
US8762789B2 (en) Processing diagnostic requests for direct block access storage devices
US9727503B2 (en) Storage system and server
US9395921B2 (en) Writing data using DMA by specifying a buffer address and a flash memory address
US10593380B1 (en) Performance monitoring for storage-class memory
US9092426B1 (en) Zero-copy direct memory access (DMA) network-attached storage (NAS) file system block writing
TWI436217B (zh) 用於以記憶體裝置及系統控制主機記憶體存取之方法
US11579803B2 (en) NVMe-based data writing method, apparatus, and system
US11467764B2 (en) NVMe-based data read method, apparatus, and system
US20150261720A1 (en) Accessing remote storage devices using a local bus protocol
WO2020087931A1 (zh) 一种数据备份方法、装置及系统
US10901624B1 (en) Dummy host command generation for supporting higher maximum data transfer sizes (MDTS)
WO2020087930A1 (zh) 一种数据保护方法、装置及系统
CN108153582B (zh) Io命令处理方法与介质接口控制器
WO2022126534A1 (zh) 数据处理方法及相关设备
US9652198B2 (en) FIFO buffer clean-up

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19879968

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19879968

Country of ref document: EP

Kind code of ref document: A1