WO2020087930A1 - Procédé et appareil de protection de données, et système - Google Patents

Procédé et appareil de protection de données, et système Download PDF

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Publication number
WO2020087930A1
WO2020087930A1 PCT/CN2019/090715 CN2019090715W WO2020087930A1 WO 2020087930 A1 WO2020087930 A1 WO 2020087930A1 CN 2019090715 W CN2019090715 W CN 2019090715W WO 2020087930 A1 WO2020087930 A1 WO 2020087930A1
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Prior art keywords
data
storage device
controller
instruction
association identifier
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PCT/CN2019/090715
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English (en)
Chinese (zh)
Inventor
吉辛维克多
周智
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华为技术有限公司
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Publication of WO2020087930A1 publication Critical patent/WO2020087930A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data

Definitions

  • This application relates to the storage field, and in particular, to a data protection method, device, and system.
  • Serial ATA Advanced Host Control Interface / Advanced Host Controller Interface Serial ATA Advanced Host Controller Interface, AHCI
  • Non-volatile high-speed transmission bus non-volatile memory express, NVMe
  • NVMe is a kind of interface that allows the host (Host) and non-volatile storage (non-volatile memory, NVM) subsystem to communicate
  • NVM This interface for communication between subsystems (including controllers and storage media) is attached to the Peripheral Component Interconnect Express (PCIe) interface in the form of a register interface, optimized for enterprise and consumer solid-state storage It has the advantages of high performance and low access delay.
  • PCIe Peripheral Component Interconnect Express
  • one method of data protection is to group multiple storage devices into a Redundant Array of Independent Disks (RAID).
  • RAID Redundant Array of Independent Disks
  • one storage device in the plurality of storage devices stores the parity result of the data belonging to the RAID stripe stored in other storage devices.
  • the host needs to read the old data that needs to be updated from the storage device that stores the updated data and update the parity from the storage device that updates the data when updating the parity result
  • the old parity check result is read from the check result storage device, and the old data, the new data and the old parity check result are XORed to obtain a new parity check result, and the new parity check is performed
  • the verification result is stored in a storage device for storing the parity result of the RAID stripe.
  • the present application discloses a data protection method, device and system.
  • the first storage device When the data needs to be updated, after the first storage device obtains new data from the host side, it will perform an XOR operation on the new data and the old data, and actively push the old data and the new data to the second storage device that stores the parity
  • the XOR result of the data after acquiring the XOR result of the old data and the new data, the second storage device directly performs an XOR operation on the XOR result of the old data and the new data and the old parity result, thereby obtaining Update the parity check result.
  • the present application discloses a data protection system.
  • the system includes a host, a first storage device, a second storage device, and at least one other storage device.
  • the first storage device, the second storage device, and at least one other storage device form a RAID of a redundant array of independent hard disks.
  • the first storage device stores first data
  • the second storage device stores second data
  • the at least one other storage device stores at least one third data
  • the first data and the at least one third data belong to the same One RAID stripe
  • the second data is the parity result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the host is used to trigger a first instruction to the first controller and a second instruction to the second controller.
  • the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction.
  • the first controller is used to obtain the first instruction and the fourth data. After obtaining the first instruction, the first data and the fourth data are XORed to obtain the fifth data, and the data message is sent to the second controller.
  • the message contains fifth data and an associated identifier, where the fourth data is updated data of the first data.
  • the second controller is used to obtain a second instruction and a data message, and perform an exclusive-OR operation on the fifth data and the second data according to the second instruction to obtain sixth data.
  • the first instruction and / or the second instruction may be a submission queue entry (SQE) based on NVMe.
  • the host triggering the first instruction may be writing the first instruction into a submission queue (SQ) associated with the first controller, and notifying the first controller through the doorbell mechanism.
  • the host triggering the second instruction may be that the host writes the second instruction to the SQ associated with the second controller, and notifies the second controller through the doorbell mechanism.
  • the host may also directly send the first instruction to the first controller, and send the second instruction to the second controller.
  • the first controller After acquiring the fourth data, the first controller performs an XOR operation on the first data and the fourth data to obtain fifth data, and actively sends the fifth data to the second controller, and carries the associated first data in the data packet. 5.
  • the second instruction After receiving the data message, the second instruction associates the second instruction and the fifth data according to the association identifier, and performs an exclusive-OR operation on the fifth data and the second data according to the second instruction to obtain a new parity result sixth data.
  • the host no longer needs to perform multiple read and write operations on the storage device, and the data traffic of the uplink port of the switching network interconnecting the host with the first storage device and the second storage device is greatly reduced.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the first controller may write fifth data to the second controller in the form of a PCIe message, and the PCIe address indicated by the association identifier is an entry for writing fifth data.
  • the second controller may determine the second instruction associated with the fifth data according to the address of the PCIe message.
  • the second controller includes an internal memory, and the second controller performs the fifth data and the second data Before the XOR operation, it is also used to store the fifth data in the storage space of the internal memory, and record the mapping relationship between the storage space and the associated identifier.
  • the present invention does not limit the order in which the second controller obtains the second instruction and the fifth data.
  • the second controller may first receive the data packet, and cache the fifth data in its own internal memory, and record the fifth data The mapping relationship between the storage space and the associated ID.
  • the second controller is further used to determine the storage location of the second instruction according to the association identifier, and the second control The device is used for acquiring the second instruction according to the storage location of the second instruction.
  • the host and the second controller maintain the correspondence between the association identifier and the slot of the sending queue.
  • the host stores the second instruction in the SQ slot corresponding to the association identifier.
  • the second controller may determine the SQ slot stored in the second instruction according to the association identifier, and obtain the second instruction from the SQ slot.
  • the association identifier includes a partial field of the second instruction, and the second controller is configured to Some fields get the second instruction.
  • the association identifier may be indication information of the second instruction.
  • the second controller may query the second instruction according to the association identifier.
  • the second controller is further used to trigger a completion message, and the completion message is used to instruct the second controller The XOR operation on the fifth data and the second data is completed.
  • the host is also used to obtain the completion message.
  • the completion message may be a completion queue entry (CQE), which is used to instruct the second controller to complete the write operation indicated by the second instruction.
  • CQE completion queue entry
  • the trigger completion message of the second controller may specifically be that after the second controller completes the write operation, the CQE is written into a completion queue (CQ), and the host is notified by an interrupt.
  • the present invention provides a data protection method.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the method includes: the host triggers the first instruction, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction; the first instruction is used to instruct the first controller to perform an XOR operation on the first data and the fourth data to obtain the first Five data, and instructs the first controller to send a data message to the second controller, the data message contains the fifth data and the associated identifier, wherein the fourth data is the updated data of the first data; the host triggers the second instruction, the second The instruction is used to instruct the second controller to XOR the fifth data and the second data to obtain the sixth data.
  • the method further includes: the host obtains a completion message triggered by the second controller, and the completion message is used to instruct the second controller to complete the fifth data and XOR operation of the second data.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the association identifier includes a partial field of the second instruction.
  • the first instruction and / or the second instruction are based on a non-volatile high-speed transmission bus NVMe
  • the submission queue entry SQE is based on a non-volatile high-speed transmission bus NVMe The submission queue entry SQE.
  • the present application provides a readable medium, including an execution instruction, when the processor of the computing device executes the execution instruction, the computing device executes the second aspect above or any possible implementation of the second aspect above The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor performs the execution of the memory storage Instructions to cause the computing device to perform the method in the above second aspect or any possible implementation manner of the above second aspect.
  • the present application discloses a data protection method.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium
  • the method includes: a first control
  • the first instruction and the fourth data triggered by the host are acquired by the controller, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction, and the fourth data is the updated data of the first data; after the first controller obtains the first instruction XOR the first data and the fourth data to obtain the fifth data; the first controller sends the data to the second controller Text, data packet contains a fifth data and associated identity.
  • the data message is a PCIe message
  • the association identifier includes a PCIe address field of the second controller.
  • the association identifier includes a partial field of the second instruction.
  • the present application provides a readable medium, including an execution instruction, and when the processor of the computing device executes the execution instruction, the computing device performs the above fifth aspect or any possible implementation of the above fifth aspect The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor performs the execution of the memory storage Instructions to cause the computing device to perform the method in the above fifth aspect or any possible implementation manner of the above fifth aspect.
  • the present application discloses a data protection method.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium
  • the method includes: a second control
  • the controller obtains the operation command triggered by the host
  • the second controller receives the data message sent by the first controller, the data message contains the fifth data and the association identifier, the fifth data is the XOR result of the first data and the fourth data,
  • the fourth data is the updated data of the first data, and the associated identifier is used to indicate the operation instruction; the second controller Five and second data to obtain a sixth exclusive OR data.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the second controller includes an internal memory, and the second controller performs the fifth data and the second data Before the XOR operation, the method further includes: the second controller stores the fifth data in the storage space of the internal memory, and records the mapping relationship between the storage space and the association identifier.
  • the method further includes: the second controller determines the storage location of the operation instruction according to the association identifier; second The controller acquiring the operation instruction includes: the second controller acquiring the operation instruction according to the storage location of the operation instruction.
  • the association identifier includes a partial field of the operation instruction; the second controller acquiring the operation instruction includes: second The controller obtains the operation instruction according to some fields of the operation instruction.
  • the method further includes: a second controller triggers a completion message, and the completion message is used to indicate the second The controller completes the XOR operation on the fifth data and the second data.
  • the first instruction and / or the second instruction are based on a non-volatile high-speed transmission bus NVMe
  • the submission queue entry SQE is based on a non-volatile high-speed transmission bus NVMe The submission queue entry SQE.
  • the eighth aspect is the method implementation of the second controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the eighth aspect or any one of the eighth aspect The possible implementation manners will not be repeated here.
  • the present application provides a readable medium, including an execution instruction, and when the processor of the computing device executes the execution instruction, the computing device performs the above eighth aspect or any possible implementation of the above eighth aspect The way in the way.
  • the present application provides a computing device, including: a processor, a memory, and a bus; the memory is used to store execution instructions, the processor and the memory are connected through the bus, and when the computing device is running, the processor performs memory storage execution Instructions to cause the computing device to perform the method in the above eighth aspect or any possible implementation manner of the above eighth aspect.
  • the present application discloses a data protection device.
  • the data protection system includes a data protection device, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first The first data is stored in the storage device, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, The second data is a parity result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium
  • the data protection device includes : Processing unit, used to trigger the first instruction, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction; the first instruction is used to instruct the first controller to perform an XOR operation on the first data and the fourth data Fifth data, and instructs the first controller to send a data message to the second controller, the data message contains fifth data Association identifier, where the fourth data is the updated data of the first data; the processing unit is also used to trigger a second instruction, and the second instruction is used to instruct the second controller to perform an exclusive OR operation on the fifth data and the second data to obtain the sixth data.
  • the backup device further includes an acquiring unit, configured to acquire a completion message triggered by the second controller, and the completion message is used to indicate the first The second controller completes the XOR operation on the fifth data and the second data.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address of the second controller Field.
  • the association identifier includes a partial field of the second instruction.
  • the first instruction and / or the second instruction are based on non-volatile high-speed The submission queue entry SQE of the transmission bus NVMe.
  • the eleventh aspect is the implementation of the device on the host side corresponding to the system of the first aspect.
  • the description in the first aspect or any possible implementation manner of the first aspect corresponds to either the eleventh aspect or the eleventh aspect.
  • the possible implementation manners will not be repeated here.
  • the present application discloses a data protection device.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a data protection device and a storage medium
  • the second storage device includes a controller and a storage medium.
  • the data protection device includes: a processing unit for To obtain the first instruction and the fourth data triggered by the host, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction, and after obtaining the first instruction, perform an XOR operation on the first data and the fourth data to obtain the first instruction.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the controller.
  • the association identifier includes a partial field of the second instruction.
  • the twelfth aspect is the device implementation of the first controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the twelfth aspect or the twelfth aspect. Any possible implementation manner will not be repeated here.
  • the present application discloses a data protection device.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a controller and a storage medium
  • the second storage device includes a data protection device and a storage medium.
  • the data protection device includes: an acquisition unit for In order to obtain the operation command triggered by the host, and receive the data message sent by the controller, the data message contains the fifth data and the association identifier, the fifth data is the XOR result of the first data and the fourth data, and the fourth data is the Update data of a data, the associated identifier is used to indicate the operation instruction; the processing unit is used to follow the second instruction The fifth and second data to obtain a sixth exclusive OR data.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the data protection device.
  • the data protection device further includes an internal memory, and the processing unit pairs the fifth data and the second Before the XOR operation of the data, it is also used to store the fifth data in the storage space of the internal memory, and record the mapping relationship between the storage space and the associated identifier.
  • the acquiring unit is further used to determine the storage location of the operation instruction according to the association identifier, and according to the operation The instruction storage location obtains the operation instruction.
  • the association identifier includes a partial field of the operation instruction; the obtaining unit is used for Some fields get operation instructions.
  • the processing unit is further used to trigger a completion message, and the completion message is used to instruct the data protection device The XOR operation on the fifth data and the second data is completed.
  • the first instruction and / or the second instruction are based on non-volatile high-speed The submission queue entry SQE of the transmission bus NVMe.
  • the thirteenth aspect is the device implementation of the second controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the thirteenth aspect or the thirteenth aspect. Any possible implementation manner will not be repeated here.
  • the host triggers the first instruction to the first controller and triggers the second instruction to the second controller.
  • the first instruction triggered by the host to the first controller carries an association identifier indicating the second instruction.
  • the first controller After acquiring the fourth data of the new data, the first controller XORs the fourth data of the new data and the first data of the old data to obtain the fifth data, and actively sends a data message to the second controller, which is carried in the data message The fifth data and the associated identification.
  • the second controller After obtaining the data message, the second controller associates the second instruction and the fifth data according to the association identifier, and performs an exclusive OR operation on the fifth data and the old parity check result second data according to the second instruction to obtain a new parity The sixth data of the verification result.
  • the host is prevented from reading and writing the storage device multiple times during the data update process.
  • the data traffic of the upstream port of the switching network interconnecting the host with the first storage device and the second storage device is greatly reduced, thereby improving the overall performance of the system.
  • FIG. 1 is a schematic diagram of a logical structure of an NVMe system according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a data protection method based on NVMe
  • FIG. 3 is a schematic flowchart of a data protection method according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a hardware structure of a host according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a hardware structure of a controller according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a hardware structure of a controller according to an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a data protection method according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an entrance organization structure according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a PCIe address structure according to an embodiment of the invention.
  • FIG. 10 is a schematic diagram of a data storage structure according to an embodiment of the invention.
  • FIG. 11 is a schematic diagram of a logical structure of a data protection device according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a logical structure of a data protection device according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a logical structure of a data protection device according to an embodiment of the application.
  • first and second use the terms first and second to distinguish between various objects, such as the first instruction and the second instruction, etc., but there is no logical or timing dependency between the respective "first" and "second”.
  • a "data message” refers to a data message sent by a first storage device to a second storage device and carrying load data and an association identifier.
  • the term push means that the first storage device actively sends a data message to the second storage device.
  • the entry is an address space opened by the second storage device to the first storage device
  • the entry address may specifically be a PCIe address
  • the data message may be a PCIe write message.
  • the entry may be an address space opened by the controller of the second storage device to the controller of the first storage device, and the controller of the first storage device may push data to the controller of the second storage device according to the address space.
  • the first storage device may push a data message to the second storage device through the entry, and the data message may carry the entry address.
  • the second storage device After receiving the data message, the second storage device identifies the entry address, and can allocate the corresponding storage space for the entry in the local internal memory, and caches the load data carried in the data message to the storage space instead of storing the load
  • the data is stored in the storage space indicated by the entry address.
  • the internal memory may be specifically the private memory space of the controller.
  • the association identifier carried in the data packet is used to indicate the operation instruction.
  • the association identifier may include the entry address or a part of the entry address field.
  • the storage device includes a controller and a storage medium, and the storage controller is hereinafter referred to as a controller.
  • the execution subject of the storage device is generally a controller.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the main body that the first storage device interacts with the outside world is the first controller
  • the main body that the second storage device interacts with the outside world is the second controller.
  • the embodiment of the present invention does not distinguish between the storage device and the controller when interacting with the outside world.
  • the specific implementation of the command triggered by the host may be SQE.
  • the host is interconnected with the first storage device and the second storage device through a switching network.
  • the upstream port of the switching network refers to the port interconnecting the switching network and the host.
  • the upstream traffic of the switching network refers to the data traffic interacting with the host.
  • the term host refers to a subject that can interact with a storage device and store data to the storage device.
  • the host can be a physical computer, virtual machine or network card.
  • the embodiment of the present invention does not limit the specific implementation form of the host.
  • the system 100 includes a host 101, a switching network 102, a first storage device 103, a second storage device 105, and at least One other storage device 107.
  • the first storage device 103, the second storage device 105, and at least one other storage device 107 form a redundant array of independent hard disks RAID.
  • the first storage device 103 stores first data
  • the second storage device 105 stores second data
  • at least one other storage device 107 stores at least one third data
  • the second data is the parity result of the first data and at least one third data.
  • the first storage device 103 includes a first controller 104 and a storage medium
  • the second storage device 105 includes a second controller 106 and a storage medium.
  • the second storage device 105 is a backup of the first storage device 103.
  • a group of data having a RAID check relationship is distributed and stored in multiple storage devices, and the multiple storage devices belong to a RAID group.
  • the storage medium is generally a non-volatile storage medium for permanently storing data.
  • the storage medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, an optical disk), or a semiconductor medium (for example, Flash), etc.
  • the embodiments of the present invention do not limit the specific implementation form of the storage medium.
  • the storage medium may further include a remote memory separate from the controller, for example, a storage medium interconnected with the controller through a network.
  • the switching network 102 may be used to refer to any manner or interconnection protocol in which the host 101, the first storage device 103, and the second storage device 105 are interconnected.
  • the switching network 102 may be a PCIe bus, where the PCIe bus may include a PCIe switch, and the PCIe switch is interconnected with the host 101.
  • the switching network 102 may also be an internal interconnect bus of computer equipment, the Internet, an intranet, a local area network (LAN), a wide area network (wide area network, WAN), a storage area network (storage area network, SAN), etc. , Or any combination of the above networks.
  • the embodiment of the present invention does not limit the specific implementation form of the switching network 102.
  • the host 101 when the first data stored in the first storage device 103 needs to be updated, the host 101 also needs to update the second data of the parity result stored in the second storage device 105.
  • the data update process is that the host 101 first reads the first data dold from the first storage device 103, and then XORs the new data with the fourth data dnew to obtain the fifth data, and then reads the first data from the second storage device 105.
  • Two data Pold, and the fifth data of the XOR result of Pold and dold and dnew is XORed again to obtain a new parity result sixth data Pnew.
  • the host 101 then stores the new data dnew in the first storage device 103, and stores the new parity result Pnew in the second storage device 105.
  • the host 101 needs at least two read operations and two write operations.
  • the host 101 when the first data dold stored in the first storage device 103 needs to be updated, the host 101 writes the new data fourth data dnew to the first storage device 103 through a write operation.
  • the first storage device 103 XORs the first data dold and the fourth data dold to obtain fifth data, and then the first storage device 103 actively sends the fifth data to the second storage device 105, and the second storage device 105 transfers the fifth data
  • the data and the old parity check result second data Pold are XORed to obtain a new parity check result Pnew.
  • the host 101 when data needs to be updated, the host 101 needs to perform a write operation once.
  • the XOR operation of the old and new data is completed through the first storage device 103, and the fifth data of the XOR result of the old and new data is actively pushed to the second storage device 105, thereby avoiding the read and write operations of the host 101 to the storage device
  • the upstream port of the switching network 102 interconnecting the first storage device 103, the second storage device 105 and the host 101 is reduced, and the overall performance of the system is improved.
  • FIG. 4 is a schematic structural diagram of a host 400 according to an embodiment of the present application.
  • the data protection system includes a host 400, a first storage device, a second storage device, and at least one other storage device.
  • the first storage device, the second storage device, and at least one other storage device form a RAID of a redundant array of independent hard disks.
  • the first storage device stores first data
  • the second storage device stores second data
  • the at least one other storage device stores at least one third data.
  • the first data and at least one third data belong to the same RAID stripe
  • the first data, the second data, and the third data are all one stripe of the stripe.
  • the second data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium.
  • the host 400 includes a processor 401 connected to the system memory 402.
  • the processor 301 may be a central processing unit (CPU), an image processor (graphics processing unit, GPU), a field programmable gate array (Field Programmable Gate Array, FPGA), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or a digital Signal processor (digital signal processor, DSP) and other calculation logic or any combination of the above calculation logic.
  • the processor 301 may be a single-core processor or a multi-core processor.
  • the processor 401 may further include protection logic 410, and the protection logic 410 may be a specific hardware circuit or a firmware module integrated in the processor 401. If the protection logic 410 is a specific hardware circuit, the protection logic 410 executes the method of the embodiment of the present application, and if the protection logic 410 is a firmware module, the processor 410 executes the firmware code in the protection logic 410 to implement the technology of the embodiment of the present application Program.
  • the protection logic 410 includes: (1) logic (circuit / firmware code) for triggering the first instruction, the first instruction carries an association identifier, the association identifier is used to indicate the second instruction, and the first instruction is used to indicate the first control
  • the device performs an XOR operation on the first data and the fourth data to obtain fifth data, and instructs the first controller to send a data message to the second controller.
  • the data message includes the fifth data and the associated identifier, where the fourth data is Update data of the first data;
  • Logic (circuit / firmware code) of the code used to trigger the second instruction the second instruction is used to instruct the second controller to perform an exclusive OR operation on the fifth data and the second data
  • the sixth data includes: (1) logic (circuit / firmware code) for triggering the first instruction, the first instruction carries an association identifier, the association identifier is used to indicate the second instruction, and the first instruction is used to indicate the first control
  • the device performs an XOR operation on the first data and the fourth data to obtain fifth
  • the bus 409 is used to transfer information between the components of the host 400.
  • the bus 409 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 409 is also connected with an input / output interface 405 and a communication interface 403.
  • the input / output interface 405 is connected with an input / output device for receiving input information and outputting operation results.
  • the input / output device can be a mouse, keyboard, monitor, or optical drive.
  • the communication interface 403 is used to implement communication with other devices or networks.
  • the communication interface 403 may be interconnected with other devices or networks in a wired or wireless manner.
  • the host 400 may be interconnected with the switching network through the communication interface 403 and connected to the controller through the switching network.
  • the system memory 402 may include some software, for example, an operating system 408 (such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, or embedded operating system (such as Vxworks)), an application program 407, and a protection module 406.
  • an operating system 408 such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, or embedded operating system (such as Vxworks)
  • an application program 407 such as Vxworks
  • the processor 401 executes the protection module 406 to implement the technical solution of the embodiment of the present application.
  • the protection module 406 includes: (1) a code for triggering a first instruction.
  • the first instruction carries an association identifier, and the association identifier is used to indicate a second instruction, and the first instruction is used to instruct the first controller to
  • the fourth data performs an exclusive OR operation to obtain fifth data, and instructs the first controller to send a data message to the second controller.
  • the data message includes the fifth data and the associated identifier, where the fourth data is the update data of the first data (2)
  • a code for triggering a second instruction the second instruction is used to instruct the second controller to perform an exclusive OR operation on the fifth data and the second data to obtain sixth data.
  • FIG. 4 is merely an example of a host 400.
  • the host 400 may include more or fewer components than those shown in FIG. 4, or have different component configurations.
  • various components shown in FIG. 4 may be implemented by hardware, software, or a combination of hardware and software.
  • FIG. 5 is a schematic structural diagram of a controller 500 according to an embodiment of the present application.
  • the data protection system includes a host, a first storage device, a second storage device, and at least one other storage device.
  • the first storage device, the second storage device, and at least one other storage device form an independent hard disk redundancy Array RAID, where the first data is stored in the first storage device, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same One RAID stripe, the second data is a parity result of the first data and at least one third data,
  • the first storage device includes a first controller and a storage medium, and the second storage device includes a second controller and a storage medium.
  • the controller 500 includes a processor 501 connected to the system memory 502.
  • the processor 401 may be computational logic such as CPU, GPU, FPGA, ASIC, or DSP, or any combination of the above.
  • the processor 401 may be a single-core processor or a multi-core processor.
  • the processor 501 may further include protection logic 505, and the protection logic 505 may be a specific hardware circuit or a firmware module integrated in the processor 501. If the protection logic 505 is a specific hardware circuit, the protection logic 505 executes the method of the embodiment of the present application, and if the protection logic 505 is a firmware module, the processor 501 executes the firmware code in the protection logic 505 to implement the technology of the embodiment of the present application Program.
  • the protection logic 505 includes: (1) logic (circuit / firmware code) for acquiring the first instruction and the fourth data triggered by the host, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction, and the fourth data is Update data of the first data; (2) Logic (circuit / firmware code) used to XOR the first data and the fourth data after acquiring the first instruction; (3) Used to send 2.
  • the data message contains the fifth data and the associated identifier.
  • the bus 507 is used to transfer information between the components of the controller 500.
  • the bus 507 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 507 may also be connected with a communication interface 503.
  • the communication interface 503 is used to realize communication with other devices or networks.
  • the communication interface 503 may be interconnected with other devices or networks in a wired or wireless manner.
  • the controller 500 is interconnected with the switching network and the storage medium through the communication interface 503.
  • the system memory 502 may include some software, for example, an operating system 504 (such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)) and a protection module 506.
  • an operating system 504 such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)
  • the processor 501 executes a protection module 506 to implement the technical solution of the embodiment of the present application.
  • the protection module 506 includes: (1) a code for acquiring the first instruction and the fourth data triggered by the host, the first instruction carries an association identifier, the association identifier is used to indicate the second instruction, and the fourth data is the update of the first data Data; (2) a code for XORing the first data and the fourth data to obtain the fifth data after acquiring the first instruction; (3) a code for sending the data message to the second storage device, the The data message contains the fifth data and the associated identification.
  • FIG. 5 is only an example of a controller 500, and the controller 500 may include more or fewer components than those shown in FIG. 5, or have different component configurations. Meanwhile, various components shown in FIG. 5 may be implemented by hardware, software, or a combination of hardware and software.
  • FIG. 6 is a schematic structural diagram of a controller 600 according to an embodiment of the present application.
  • the data protection system includes a host, a first storage device, a second storage device, and at least one other storage device.
  • the first storage device, the second storage device, and at least one other storage device form an independent hard disk redundancy Array RAID, where the first data is stored in the first storage device, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to The same RAID stripe, the second data is the parity result of the first data and the at least one third data, the second data and the first data belong to the same RAID stripe, and the first storage device includes the first controller and The storage medium, the second storage device includes a second controller and a storage medium.
  • the controller 600 includes a processor 601 connected to the system memory 602.
  • the processor 401 may be computational logic such as CPU, GPU, FPGA, ASIC, or DSP, or any combination of the above.
  • the processor 401 may be a single-core processor or a multi-core processor.
  • the processor 601 may further include a register, and the register may be opened to be accessed by controllers of other storage devices. More specifically, the register can be used as a PCIe address space to be opened to controllers of other storage devices for the controllers of other storage devices to access through the PCIe address.
  • the processor 601 may further include protection logic 605, and the protection logic 605 may be a specific hardware circuit or a firmware module integrated in the processor 601. If the protection logic 605 is a specific hardware circuit, the protection logic 605 executes the method of the embodiment of the present application; if the protection logic 605 is a firmware module, the processor 601 executes the firmware code in the protection logic 605 to implement the technology of the embodiment of the present application Program.
  • the protection logic 605 includes: (1) logic (circuit / firmware code) for acquiring operation instructions triggered by the host; (2) logic (circuit / firmware code) for receiving data messages sent by the first storage device, data The message contains fifth data and an associated identifier.
  • the fifth data is the XOR result of the first data and the fourth data.
  • the fourth data is the updated data of the first data.
  • the associated identifier is used to indicate the operation instruction; (3)
  • the logic (circuit / firmware code) of the sixth data is obtained by XORing the fifth data and the second data according to the second instruction.
  • the bus 607 is used to transfer information between the components of the controller 600.
  • the bus 607 may use a wired connection or a wireless connection, which is not limited in this application.
  • the bus 607 can also be connected with a communication interface 603.
  • the communication interface 603 is used to implement communication with other devices or networks.
  • the communication interface 603 may be interconnected with other devices or networks in a wired or wireless manner.
  • the controller 600 is interconnected with the host and the storage medium through the communication interface 603.
  • the controller 600 may also be connected to the network through the communication interface 603 and interconnected with the host or the storage medium through the network.
  • the system memory 602 may include some software, for example, an operating system 604 (such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)) and a protection module 606.
  • an operating system 604 such as Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (such as Vxworks)
  • the processor 601 executes the protection module 606 to implement the technical solution of the embodiment of the present application.
  • the protection module 606 includes: (1) a code for acquiring an operation instruction triggered by a host; (2) a code for receiving a data message sent by the first storage device, the data message includes fifth data and an association identifier, and the fifth The data is the XOR result of the first data and the fourth data, the fourth data is the updated data of the first data, and the association mark is used to indicate the operation instruction; (3) is used to compare the fifth data and the second data according to the second instruction Perform the exclusive OR operation to get the code of the sixth data.
  • FIG. 6 is merely an example of a controller 600.
  • the controller 600 may include more or fewer components than those shown in FIG. 6, or have different component configurations. Meanwhile, various components shown in FIG. 6 may be implemented by hardware, software, or a combination of hardware and software.
  • inventions of the present invention provide a data protection method.
  • the method may be specifically a data protection method based on NVMe.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium
  • the second storage device includes a second controller and a storage medium. As shown in FIG. 7, the method 700 includes:
  • Step 701 The host triggers the first instruction.
  • the first command is generated by the host, the host sends the first command to the first controller; or the first command is generated by the host, the host adds the first command to the queue for the first controller to read, this implementation
  • the host adds the first command to the queue for the first controller to read
  • the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction.
  • the first instruction may specifically be NVMe-based SQE.
  • the first instruction is SQE as an example for explanation. However, it should be understood that the embodiment of the present invention does not limit the specific implementation form of the first instruction.
  • the process for the host to trigger the first instruction can refer to the NMVe standard.
  • the host writes the SQE to the sending queue associated with the first controller, and notifies the first controller of the new SQE through the doorbell.
  • the first command triggered by the host may also be implemented in other forms.
  • the host may directly send the first command to the first controller.
  • the invention does not limit the specific implementation form of the host triggering the first instruction.
  • Step 702 The host triggers the second instruction.
  • the second command is generated by the host, and the host sends the second command to the second controller; or the second command is generated by the host, the host adds the second command to the queue for the second controller to read, this implementation
  • the second command is generated by the host, the host adds the second command to the queue for the second controller to read, this implementation
  • the host adds the second command to the queue for the second controller to read
  • the second instruction may be NVMe-based SQE.
  • the second instruction is SQE as an example for explanation. However, it should be understood that the embodiment of the present invention does not limit the specific implementation form of the second instruction.
  • the host triggering the second instruction may be that the host writes the second instruction to the sending queue associated with the second controller, and notifies the second controller of the new SQE through the doorbell.
  • the second command triggered by the host may also be implemented in other forms. For example, the host may directly send the second command to the second controller.
  • the invention does not limit the specific implementation form of the host triggering the second instruction.
  • Step 703 The first controller obtains the first instruction.
  • the first controller may obtain the first instruction from the sending queue associated with the host. Specifically, the first controller receives the doorbell notification of the host, the doorbell is used to indicate that a new SQE arrives in the sending queue, and the first controller goes to the sending queue to obtain the SQE. The first controller may also directly receive the first command sent by the host.
  • the embodiment of the present invention does not limit the specific implementation form of the first controller acquiring the first instruction.
  • Step 704 The first controller obtains fourth data.
  • the fourth data is the updated data of the first data. That is, the fourth data will replace the first data in the first storage device.
  • the format of the first instruction may refer to the NVMe standard, and the host may indicate the address information of the fourth data through the PRP or SGL field of SQE in the first instruction.
  • the first controller reads the fourth data from the host side according to the address information.
  • the host may also directly send the fourth data to the first controller, and the first controller directly receives the fourth data from the host.
  • the embodiment of the present invention does not limit the specific implementation form of the first controller acquiring the fourth data.
  • the first controller After acquiring the fourth data, the first controller stores the fourth data in the storage medium of the first storage device.
  • Step 705 After acquiring the first instruction, the first controller performs an exclusive-OR operation on the first data and the fourth data to obtain fifth data.
  • the first data is old data dold stored in the first storage device
  • the fourth data is update data dnew of the first data
  • the second data is old parity stored in the second storage device
  • the verification result is Pold.
  • the calculation method of the new parity result Pnew is as follows:
  • the first controller first calculates the XOR result of the first data and the fourth data.
  • Step 706 The first controller sends a data message to the second controller.
  • the data packet contains the fifth data and the association identifier.
  • the first controller may divide the fifth data into multiple data packets and send the data to the second controller.
  • the first controller may actively push the data message to the second controller.
  • the association identifier carried in the data packet is used to associate the fifth data with the second instruction.
  • the embodiment of the present invention does not limit the specific implementation manner of the association identifier.
  • the association identifier may directly or indirectly indicate the second instruction corresponding to the fifth data carried in the data packet.
  • the data message may be a PCIe write operation message. More specifically, the data message may be a transaction layer packet (TLP), and the load data may be a payload carried in the TLP, and the association identifier It can be the PCIe address of the TLP or a partial field of the PCIe address.
  • TLP transaction layer packet
  • the load data may be a payload carried in the TLP
  • the association identifier It can be the PCIe address of the TLP or a partial field of the PCIe address.
  • the second controller opens a part of its address space to the first controller. More specifically, the address space opened by the second controller to the first controller may serve as the PCIe address space of the second controller.
  • the first controller can access the PCIe address access.
  • the second controller may open a part of the PCIe address of the base address register to the first controller for access.
  • the base address register is used as an example for illustration, but it should be understood that the embodiment of the present invention does not limit the type and form of the address space that the second controller opens to the first controller for access.
  • the second controller may organize a part of the PCIe addresses of the base address register into a portal, and each entry occupies a part of the PCIe address space of the base address register.
  • the first controller may write a data message to the second controller through the portal.
  • the entry is the data entry for the PCIe write operation from the first controller to the second controller. In the following description, the function of the entry will be described in more detail.
  • the data message pushed by the first controller to the second controller may be a PCIe message.
  • the first controller writes the fifth data associated with the second instruction to the second control through the entry
  • the address segment of the PCIe message indicates the entry corresponding to the write operation, that is, the entry address is a PCIe address or a partial field of the PCIe address in the data message.
  • the association identifier may be an entry address or a partial field of the entry address.
  • the second controller is also used to determine the storage address of the second instruction according to the association identifier, and obtain the second instruction according to the storage address of the second instruction.
  • the address for storing the second instruction may be the address of the slot in the commit queue where the second instruction is stored.
  • the host and the second controller maintain the correspondence between the entry and the slot in the sending queue.
  • the host stores the second command in the slot of the sending queue corresponding to the entry indicated by the association identifier, and carries the association identifier in the first instruction.
  • the first controller sends a data message to the second controller according to the association identifier, and the data message carries the association identifier.
  • the second controller determines the slot in the sending queue associated with the host to store the second address according to the association identifier, and obtains the second instruction associated with the fifth data from the slot.
  • the present invention does not limit the organization of entries in the PCIe address space, but only needs to ensure that each entry corresponds to a specific second instruction uniquely during the data protection operation, and each entry is uniquely associated with a specific second instruction.
  • a part of the PCIe address of the base address register of the second controller may be organized in the form of through holes (aperture), and each through hole contains multiple entries, that is, the entries may be organized in the form of an array, which is added through the array base address The port offset is addressed to the entrance, and this array is called a via.
  • Each entry is associated with a slot in the send queue.
  • Fig. 8 is a schematic diagram of the structure of the base address register. As shown in Fig. 8, each through hole is composed of a group of entries P0 to PN.
  • the PCIe address structure includes the base address of BAR, the via offset, and the entry offset. Among them, the BAR and the through hole offset are used to uniquely determine the through hole, and the entrance offset is used to indicate a specific entrance in the through hole.
  • the fifth data is "pushed" by the first controller to the second controller through the PCIe BAR hole.
  • “Push” refers to the PCIe write transaction initiated by the first controller.
  • the entries may also be arbitrarily distributed in the PCIe address space, and arbitrarily distributed entries in the PCIe space are called arbitrary "data entries”.
  • the association identifier is an entry address or a partial field of the entry address.
  • the host and the second controller maintain the correspondence between the entry and the slot in the SQ, and the SQ slot corresponds to the entry in a one-to-one relationship.
  • the host triggers the first instruction and the second instruction through the correspondence between the entry and the SQ slot.
  • the second controller may obtain the corresponding second instruction according to the association identifier in the data packet.
  • the SQ slot storing the second instruction is used to associate the entry with the second instruction, and the second instruction corresponding to the entry is determined by the SQ slot.
  • the association identifier may also be indication information of the second instruction.
  • the association identifier may further include a partial field of the second instruction, and the second controller obtains the second instruction according to the association identifier.
  • the second instruction may be SQE, and the indication information associated with the SQE is used to uniquely determine an SQE.
  • the SQE indication information is carried in the data message, so that the association between the SQE and the fifth data is directly realized, rather than the indirect association through the SQ slot.
  • the associated identifier may consist of "queue ID + CID”. If the CID of each SQE is unique, the association identifier may be the CID carried by the corresponding SQE. In other implementations, the association identifier may also be part of the CID.
  • the association identifier may also be specified using a specifically defined SGL type or SGL subtype or other fields in the SQE, as long as the second controller can uniquely determine the second instruction according to the association identifier, the embodiment of the present invention is not limited The specific implementation of the association identification.
  • the first instruction is used to instruct the first controller to perform the XOR operation on the first data and the fourth data, and instruct the first controller to change the XOR operation result of the first data and the fourth data.
  • Five data and the associated identifier are sent to the second controller.
  • Step 707 The second controller obtains the second instruction.
  • the second controller may obtain the second instruction from the sending queue associated with the host. More specifically, the second controller receives the doorbell notification of the host, the doorbell is used to indicate that a new SQE arrives in the sending queue, and after receiving the doorbell of the host, the controller goes to the sending queue to obtain the second instruction.
  • the second controller may also directly receive the second command sent by the host.
  • the embodiment of the present invention does not limit the specific implementation form of the second controller acquiring the second instruction.
  • the format of the second instruction may refer to the NVMe standard.
  • the second instruction is associated with the association identifier, and the fifth data is actively pushed to the second controller by the first controller.
  • the second command is no longer required.
  • the second controller actively takes the PCIe read operation to obtain data from the host, so the second command does not need to carry the address information of the data through the SGL field or the PRP field.
  • the SGL domain or PRP domain of the second instruction may not carry other information, and the processing method of the SGL domain or PRP domain by the second controller may be "ignore", that is, the SGL or PRP may be omitted in the embodiment of the present invention .
  • the association identifier may be an entry address or a partial field of the entry address.
  • the second controller maintains the correspondence between the entry and the slot in the sending queue. After receiving the data message, the second controller is also used to determine the storage address of the second instruction according to the association identifier, and obtain the second instruction according to the storage address of the second instruction.
  • the association identifier may also be indication information of the second instruction.
  • the association identifier may also include some fields of the second instruction.
  • the second controller may also search for the second instruction indicated by the association identifier in the sending queue according to the association identifier.
  • Step 708 The second controller obtains the data to be fifth.
  • the data message carries fifth data.
  • the address information carried in the data message indicates an entry of the second controller.
  • the entry of the second controller is used to receive the data message and is an entry for the first controller to send the data message to the second controller.
  • the storage space for the fifth data may be the internal memory of the second controller, instead of storing the fifth data in the storage space indicated by the entry address.
  • the second controller may allocate a specific storage block in its own internal memory for each entry to store the fifth data received by the entry.
  • the second controller may establish a mapping relationship between the storage block and the entry.
  • the internal memory used by the second controller to store data can no longer be accessed by the outside world through PCIe addressing, nor is it also used as a command memory buffer.
  • the embodiment of the present invention does not limit the specific implementation of the storage block for storing fifth data the way.
  • the first controller may use multiple data packets to send the fifth data.
  • the second controller may use the root data structure to organize the data received from the portal.
  • the data message may specifically be a PCIe write message, and the first controller writes the fifth data to the second controller through the PCIe write operation.
  • the second controller can organize the data into a root data structure to facilitate data management.
  • the second controller after receiving the data message, decodes the address of the data message and identifies the associated identifier, identifies the entry and root data structure according to the associated identifier, and allocates free memory blocks for data from the memory storage , And save the data to the allocated memory block, and attach the memory block to the root data structure.
  • the second controller first stores the data in its own internal memory. When certain conditions are met, the data stored in the internal memory is XORed with the second data or some fields of the second data. The satisfying condition here may be that the second controller obtains the second instruction, or the amount of data stored in the internal memory is accumulated to the extent that the second NMVe controller can perform an XOR operation on it.
  • the internal memory of the second controller may be the private memory of the controller.
  • the embodiment of the present invention does not limit the order in which the second controller acquires the data message and the second instruction.
  • the second controller may first receive the data message pushed by the first controller, and determine the second instruction according to the association identifier.
  • the second controller may also obtain the second instruction first, and then obtain the corresponding fifth data according to the second instruction.
  • the second controller may determine the association identifier according to the second instruction, and then determine the corresponding entry according to the association identifier, and obtain the stored load data from the storage space allocated to the entry according to the association identifier.
  • the embodiment of the present invention does not limit the order in which the fifth data corresponding to the second instruction and the second instruction itself arrive at the second controller.
  • the second controller may maintain a one-to-one correspondence between the SQ slot and the entry.
  • the entry corresponding to the second instruction may be determined according to the maintained correspondence. If the second controller detects that no data has arrived at the corresponding entry, the second controller suspends the second instruction and waits for the data to arrive. Until the second controller detects that data has arrived at the corresponding entry, it can perform an exclusive OR operation on the fifth data and the second data.
  • the second controller detects that the second instruction corresponding to the data has not reached the second controller or the corresponding SQ slot according to the association identifier carried in the data packet. Then the second controller can attach the data to the root data structure and wait for the relevant second instruction to arrive until the corresponding second instruction reaches the second controller or the addressable SQ slot of the second controller. Obtain the second instruction, and perform an exclusive OR operation on the fifth data and the second data according to the second instruction, thereby obtaining sixth data.
  • the second instruction is used to instruct the second controller to perform an XOR operation on the second data and the fifth data to obtain the latest parity check result of the stripe.
  • Step 709 The second controller performs an exclusive OR operation on the fifth data and the second data according to the second instruction to obtain sixth data.
  • the second instruction is used to instruct the second controller to perform an XOR operation on the second data and the fifth data to obtain the latest parity check result of the stripe.
  • the data is parity data of the fourth data and the at least one third data.
  • the sixth data is stored in the storage medium of the second storage device.
  • the first controller may send the fifth data through multiple data packets, and the second controller receives the data pushed by the first controller through the portal and the second controller combines the received data with the second XOR operations can be performed in parallel on some fields of the data. If the data processing currently received through the portal is completed, that is, the data currently received through the portal has been XORed with the corresponding field of the second data, but the system needs more data to complete the data protection, the second controller hangs The second instruction waits for data to arrive.
  • Step 710 The second controller triggers the completion message.
  • the completion message is used to instruct the second controller to complete the XOR operation on the fifth data and the second data.
  • the completion message may be a trigger queue entry (completion queue entry, CQE).
  • the trigger completion message of the second controller may specifically be that after the second controller completes the write operation, the CQE is written into a completion queue (CQ), and the host is notified by an interrupt.
  • the host triggers the first instruction to the first controller and triggers the second instruction to the second controller.
  • the first instruction triggered by the host to the first controller carries an association identifier indicating the second instruction.
  • the first controller After acquiring the fourth data of the new data, the first controller XORs the fourth data of the new data and the first data of the old data to obtain the fifth data, and actively sends a data message to the second controller, which is carried in the data message The fifth data and the associated identification.
  • the second controller After obtaining the data message, the second controller associates the second instruction and the fifth data according to the association identifier, and performs an exclusive OR operation on the fifth data and the old parity check result second data according to the second instruction to obtain a new parity The sixth data of the verification result.
  • the host is prevented from reading and writing the storage device multiple times during the data update process.
  • the data traffic of the upstream port of the switching network interconnecting the host with the first storage device and the second storage device is greatly reduced, thereby improving the overall performance of the system.
  • the data protection system includes a data protection device 1100, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first A storage device stores first data, a second storage device stores second data, at least one other storage device stores at least one third data, and the first data and at least one third data belong to the same RAID stripe
  • the second data is a parity check result of the first data and at least one third data.
  • the first storage device includes a first controller and a storage medium, and the second storage device includes a second controller and a storage medium.
  • the data protection device 1100 includes a processing unit 1101 and an acquisition unit 1102, where,
  • the processing unit 1101 is used to trigger a first instruction, the first instruction carries an association identifier, and the association identifier is used to indicate a second instruction; the first instruction is used to instruct the first controller to perform an XOR operation on the first data and the fourth data to obtain the first Five data, and instructs the first controller to send a data message to the second controller, where the data message contains the fifth data and the associated identifier, where the fourth data is the updated data of the first data.
  • the processing unit 1101 is further configured to trigger a second instruction, and the second instruction is used to instruct the second controller to perform an exclusive OR operation on the fifth data and the second data to obtain sixth data.
  • the backup device 1100 further includes an obtaining unit 1102, configured to obtain a completion message triggered by the second controller, and the completion message is used to instruct the second controller to complete the XOR operation on the fifth data and the second data.
  • an obtaining unit 1102 configured to obtain a completion message triggered by the second controller, and the completion message is used to instruct the second controller to complete the XOR operation on the fifth data and the second data.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the second controller.
  • the association identifier includes a partial field of the second instruction.
  • the processing unit 1101 and the obtaining unit 1102 may be implemented by the protection logic 410 in the processor 401 in FIG. 4 or may be implemented by the processor 401 in FIG. 4 and the protection module 406 in the system memory 402 achieve.
  • the embodiments of the present application are the embodiments of the host device corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, which will not be repeated here.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a data protection device 1200 and a storage medium
  • the second storage device includes a controller and a storage medium.
  • the backup device 1200 includes a processing unit 1201 and a sending unit 1202, where,
  • the processing unit 1201 is used to obtain the first instruction and the fourth data triggered by the host, the first instruction carries an association identifier, and the association identifier is used to indicate the second instruction, and after obtaining the first instruction, the first data and the fourth data are different Or the operation obtains the fifth data, wherein the fourth data is the updated data of the first data.
  • the sending unit 1202 is configured to send a data message to the controller.
  • the data message includes fifth data and an association identifier.
  • the data message is a PCIe message
  • the association identifier includes the PCIe address field of the controller.
  • the association identifier includes a partial field of the second instruction.
  • the processing unit 1201 and the sending unit 1202 may be implemented by the protection logic 505 in the processor 501 in FIG. 5 or by the processor 501 in FIG. 5 and the protection module 506 in the system memory 502 achieve.
  • the embodiments of the present application are the device embodiments of the first controller corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, which will not be repeated here.
  • the data protection system includes a host, a first storage device, a second storage device and at least one other storage device, the first storage device, the second storage device and at least one other storage device form a redundant array of independent hard disks RAID, the first storage device Where the first data is stored, the second data is stored in the second storage device, at least one third data is stored in at least one other storage device, the first data and the at least one third data belong to the same RAID stripe, the second The data is a parity check result of the first data and at least one third data.
  • the first storage device includes a controller and a storage medium
  • the second storage device includes a data protection device 1300 and a storage medium.
  • the backup device 1300 includes an acquisition unit 1301 and a processing unit 1302, where,
  • the obtaining unit 1301 is used to obtain an operation instruction triggered by the host, and receive a data message sent by the controller.
  • the data message includes fifth data and an association identifier.
  • the fifth data is the XOR result of the first data and the fourth data.
  • the fourth data is the updated data of the first data, and the associated identifier is used to indicate the operation instruction.
  • the processing unit 1302 is configured to perform an exclusive OR operation on the fifth data and the second data according to the second instruction to obtain sixth data.
  • the data message is a PCIe message
  • the association identifier includes a PCIe address field of the data protection device 1301.
  • the data protection device 1300 further includes an internal memory, and before the XOR operation is performed on the fifth data and the second data, the processing unit 1302 is also used to store the fifth data in the storage space of the internal memory, and record the storage space and The mapping relationship between association IDs.
  • the obtaining unit 1301 is further configured to determine the storage location of the operation instruction according to the association identifier, and obtain the operation instruction according to the storage location of the operation instruction.
  • the association identifier includes a partial field of the operation instruction
  • the obtaining unit 1301 is further configured to obtain the second instruction according to the partial field of the operation instruction.
  • processing unit 1302 is also used to trigger a completion message, and the completion message is used to instruct the data protection device 1300 to complete the XOR operation on the fifth data and the second data.
  • the acquiring unit 1301 and the processing unit 1302 may be specifically implemented by the protection logic 605 in the processor 601 in FIG. 6 or may be implemented by the processor 601 in FIG. 6 and the protection module 606 in the system memory 602 to fulfill.
  • the embodiments of the present application are the device embodiments of the second controller corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, and are not repeated here.

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Abstract

L'invention concerne un procédé et un appareil de protection de données, et un système. Le système comprend un hôte, un premier dispositif de stockage, un deuxième dispositif de stockage et au moins un autre dispositif de stockage, des premières données étant stockées dans le premier dispositif de stockage, des deuxièmes données étant stockées dans le deuxième dispositif de stockage, et les deuxièmes données étant un résultat de parité des premières données et d'au moins une troisième donnée. L'hôte est configuré pour déclencher une première instruction et une deuxième instruction, la première instruction portant un identifiant d'association pour indiquer la deuxième instruction. Le premier dispositif de stockage est configuré pour acquérir la première instruction et des quatrièmes données, pour effectuer une opération OU exclusif sur les premières données et les quatrièmes données après acquisition de la première instruction afin d'obtenir des cinquièmes données, et pour envoyer un message de données à un deuxième contrôleur, le message de données comprenant les cinquièmes données et l'identifiant d'association. Le deuxième dispositif de stockage est configuré pour acquérir la deuxième instruction et le message de données, et pour effectuer une opération OU exclusif sur les cinquièmes données et les deuxièmes données conformément à la deuxième instruction afin d'obtenir des sixièmes données.
PCT/CN2019/090715 2018-10-31 2019-06-11 Procédé et appareil de protection de données, et système WO2020087930A1 (fr)

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