WO2020087804A1

WO2020087804A1 - Display panel, display screen, and display terminal

Info

Publication number: WO2020087804A1
Application number: PCT/CN2019/075590
Authority: WO
Inventors: 谢峰; 楼均辉; 张治权; 赵永亮; 饶潞
Original assignee: 云谷（固安）科技有限公司
Priority date: 2018-10-31
Filing date: 2019-02-20
Publication date: 2020-05-07
Also published as: CN209071332U

Abstract

The present application provides a display panel, a display screen, and a display terminal. The display panel comprises a substrate and a spacer peg, and the spacer peg comprises a plurality of stacked spacer peg layers; forming a step between at least two adjacent spacer peg layers; in a direction perpendicular to the direction in which the spacer peg extends, the width of the bottom surface of the spacer peg layer which forms the step and is located on the upper layer is greater than the width of the top surface of the spacer peg layer which forms the step and is located on the lower layer.

Description

Display panel, display screen and display terminal

Technical field

The present application relates to the field of display technology, in particular to a display panel, a display screen and a display terminal.

Background technique

With the rapid development of electronic devices, users have higher and higher requirements on the screen ratio. Therefore, the comprehensive screen display of electronic devices has attracted more and more attention. Because electronic devices (such as mobile phones, tablet computers, etc.) need to integrate components such as front cameras, earpieces, and infrared sensing elements, it is usually necessary to slot (Notch) on the display of the electronic device to accommodate the camera, earpiece, and infrared sensing Components and other parts.

Summary of the invention

The present application provides a display panel, a display screen, and a display terminal, which can improve the display effect of full-screen display.

According to an aspect of the present application, a display panel is provided, including:

Substrate; and

The isolation column is arranged on the substrate;

Wherein, the isolation column includes stacked multiple isolation column layers; a step is formed between at least two adjacent isolation column layers; the step is formed in a width direction perpendicular to the extending direction of the isolation column And the width of the bottom surface of the isolation pillar layer located on the upper layer is greater than the width of the top surface of the isolation pillar layer located on the lower layer forming the step;

The extension direction of the isolation pillar is parallel to the extension direction of the substrate; the width direction is a direction parallel to the substrate and perpendicular to the extension direction of the isolation pillar; The dimension of the orthographic projection formed on the substrate in the width direction.

In the process of forming the cathode of the above display panel, it is difficult to form the cathode layer on the step formed by the isolation column layer, thereby effectively blocking the cathode layers of two adjacent rows or columns of subpixels, and avoiding the cathode layer and the light emitting layer on the isolation column The upper cathode layer is connected. Further, different voltages can be input to the cathodes separated from each other, so that different display brightness can be formed at corresponding positions of the display panel, so as to improve the cathode patterning effect and improve the display effect of the full-screen display.

Optionally, the isolation pillar layer includes a top surface away from the substrate and a bottom surface near the substrate; in the width direction, the width of the top surface of the isolation pillar layer is greater than or equal to the isolation pillar The width of the bottom surface of the layer.

Optionally, the isolation pillar layer includes a top surface away from the substrate and a bottom surface near the substrate; in the width direction, the width of the top surface of the isolation pillar layer is smaller than that of the isolation pillar layer The width of the bottom surface.

Therefore, at least a part of the surface of the side wall of the isolation pillar layer can be inclined toward the substrate, so that the cathode layer is not easily formed on the inclined side wall, thereby effectively blocking the cathodes of two adjacent rows or columns of sub-pixels.

Optionally, a cross-sectional shape of the isolation pillar layer perpendicular to the substrate and perpendicular to the extension direction of the isolation pillar is an inverted trapezoid. The inverted trapezoidal isolation column layer can further effectively block the cathodes of adjacent two rows or two columns of sub-pixels.

Optionally, materials of two adjacent isolation pillar layers forming the step are the same. For example, the isolation pillar layer is a negative photoresist layer.

Optionally, materials of two adjacent isolation pillar layers forming the step are different. For example, the isolation pillar layer on the upper layer forming the step is a photosensitive polyimide photoresist layer, and the isolation pillar layer on the lower layer forming the step is a silicon nitride layer.

On the one hand, since the materials of the two adjacent isolation pillar layers forming the steps are different, and the two have different etching rates, the steps can be etched in one etching process. On the other hand, inorganic materials can be selected to ensure that the entire separation column is non-conductive, so that it will not bring electromagnetic influence to the cathode formed on the separation column.

Optionally, the isolation pillar further includes at least one barrier layer, and the barrier layer is disposed below the isolation pillar layer that forms the step and is located below.

Optionally, an etching selection ratio of the barrier layer to the isolation pillar layer forming the step and in contact with the barrier layer is less than 1. Optionally, the barrier layer is a silicon oxide layer.

The barrier layer can block the etching, so that steps can be quickly formed between the isolation pillar layers. Due to the tip effect, pits will be formed on the lower surface of the isolation pillar layer located on the upper layer, which can further prevent the cathodes of adjacent two rows or two columns of sub-pixels from being connected to each other.

Optionally, the isolation pillar further includes at least one barrier layer, and the barrier layer is disposed between the two isolation pillar layers.

Optionally, the etching selection ratio of the barrier layer to any one of the two adjacent pillar layers adjacent thereto is less than 1.

Due to the blocking of the barrier layer, the isolation pillar layers on both sides of the barrier layer may form an inverted trapezoidal or positive trapezoidal shape, thereby further preventing the cathodes of adjacent two rows or two columns of subpixels from being connected to each other.

Optionally, the isolation pillar is provided with at least one spacing groove penetrating the isolation pillar in a direction perpendicular to the substrate, and the at least one spacing groove extends the isolation pillar in the extending direction of the isolation pillar Separated into at least two parts. Therefore, the cathode is blocked at the separation groove, and the cathodes of adjacent two rows or two columns of sub-pixels can be further blocked.

Optionally, the spacing groove has a first end near the substrate and a second end away from the substrate; in the width direction, the width of the second end of the spacing groove is smaller than the first The width of one end.

Optionally, the width of the second end of the spacing groove is 0.5 to 1 micrometer.

Since the width of the second end of the spacer is smaller than the width of the first end, the cathode material can be effectively prevented from entering the spacer when forming the cathode layer by sputtering. Even if the cathode material enters the spacer groove, the thickness of the cathode layer located at the spacer groove is smaller than the thickness of the cathode layer elsewhere, so the adhesion between the cathode layer and the sidewall of the spacer groove is reduced, thereby effectively improving the blocking phase The probability of the cathodes of sub-pixels adjacent to two rows or columns.

Optionally, the display panel includes a plurality of isolation pillars arranged in parallel on the substrate; the maximum width of the isolation pillars changes continuously or intermittently in the extending direction of the isolation pillars.

When external light passes through the isolation column, the positions of the diffraction fringes generated at different maximum width positions are different, so that the diffraction is not obvious, and the display effect of the full-screen display is improved.

Optionally, the isolation column is in the form of a strip; the strip-shaped isolation column and the isolation column whose maximum width changes continuously or intermittently are arranged alternately.

Optionally, the display panel is a PMOLED display panel, and the material transmittance of each film layer of the PMOLED display panel is greater than 90%. Therefore, the light transmittance of the display panel can be improved.

Optionally, the material of the conductive traces of the display panel is at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.

Optionally, the display panel further includes a plurality of first electrodes disposed between the substrate and the isolation column; the first electrodes extend in a wave shape in a direction parallel to the substrate; a plurality of The first electrodes extend in parallel in the same direction, and adjacent first electrodes have a pitch in the width direction; the width of the first electrode continuously changes in the extension direction of the first electrode or It changes intermittently, and the spacing between adjacent first electrodes changes continuously or intermittently.

Optionally, the display panel further includes a pixel definition layer disposed between the substrate and the isolation pillar, the pixel definition layer is formed with a plurality of pixel openings; the pixel openings are formed on the substrate Each side of the projection is a curve, and the sides are not parallel to each other.

Optionally, the orthographic projection of the pixel opening on the substrate is a circular unit or a plurality of mutually connected circular units; the circular unit is circular or elliptical.

According to another aspect of the present application, a display screen is provided, which includes at least one display area; the at least one display area includes a first display area, and a photosensitive device can be disposed below the first display area;

Wherein, the first display area is provided with the display panel described in any one of the above embodiments, and each display area in the at least one display area is used to display a picture, such as a dynamic or static picture.

Optionally, the at least one display area further includes a second display area; the display panel provided in the first display area is a PMOLED display panel, and an AMOLED display panel or an AMOLED-like display panel is provided in the second display area.

Optionally, the shape of the first display area is a rectangle, a circle, an ellipse, or a drop shape.

According to yet another aspect of the present application, a display terminal is provided, including:

Device body; and

A display screen, the display screen is provided on the device body;

Wherein, the display screen includes at least one display area; the at least one display area includes a first display area; the first display area is provided with the display panel described in any one of the above embodiments, the at least one display area Each display area in the area is used to display the picture;

Wherein, the device body is provided with a slotted area, the slotted area is located below the first display area, and a photosensitive device is provided in the slotted area.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. Those of ordinary skill in the art can obtain drawings of other embodiments according to these drawings without paying any creative labor.

1 is a schematic cross-sectional view of an isolation column according to an embodiment of the present application;

2 is a schematic cross-sectional view of an isolation column according to another embodiment of the present application;

3 is a schematic cross-sectional view of an isolation column according to yet another embodiment of the present application;

4 is a schematic cross-sectional view of an isolation column according to yet another embodiment of the present application;

5 is a schematic plan view of an isolation column according to an embodiment of the present application;

6 is a parallel schematic view of an isolation column according to another embodiment of the present application;

7 is a schematic diagram of a plan layout of a first electrode according to an embodiment of the present application;

8 is a schematic diagram of a projection of a pixel definition layer on a substrate according to an embodiment of the application;

9 is a schematic structural diagram of a display screen according to an embodiment of the present application;

10 is a schematic cross-sectional view of a display terminal according to an embodiment of the present application;

FIG. 11 is a schematic structural diagram of the device body of the display terminal shown in FIG. 10.

detailed description

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to related drawings. Some embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. The purpose of providing these embodiments is to be able to understand the disclosure of the application more thoroughly and comprehensively.

In describing the positional relationship, unless otherwise specified, when an element such as a layer, film, or substrate is described as being disposed "on" another film layer, the element may be directly disposed on the other film layer, or There may be one or more intermediate film layers. Further, when an element is described as being “under” another film layer, the element may be disposed directly under the other film layer, or one or more intermediate film layers may also be present. When a film layer is described as being disposed "between" two film layers, the film layer may be the only film layer disposed between the two film layers, or there may be one or more between the two film layers Interlayer.

Currently, a slotted area is usually formed by opening a hole on the screen to accommodate components such as a camera, an earpiece, an infrared sensor element, and the like. However, the slotted area cannot be used to display pictures. Therefore, none of these electronic devices can realize full-screen display in a true sense, that is, these electronic devices cannot display pictures in various areas of the entire screen, for example, cannot display pictures in the camera area.

According to the different driving methods, OLED (Organic Light-Emitting Diode) can be divided into PMOLED (Passive Matrix OLED, passive drive organic light emitting diode) and AMOLED (Active Matrix OLED, active drive organic light emitting diode). Taking PMOLED as an example, in the PMOLED display array, the electrodes of the same nature of the display cells in the same row are shared, and the electrodes of the same nature of the display cells in the same column are also shared. Specifically, the PMOLED display array forms a matrix with cathodes and anodes, and illuminates the sub-pixels in the display array in a scanning manner, where each sub-pixel operates in a short pulse mode and generates instant high-luminance light emission.

Because the PMOLED display panel does not have a TFT (Thin Film Transistor, thin film transistor) backplane and metal wiring, it has high light transmittance and can be used as a transparent display panel. A full-screen display can be achieved by setting a transparent display panel in the slotted area.

Generally, a PMOLED display panel needs to form a spacer between two adjacent rows and / or two columns of sub-pixels through a photolithography process to avoid short-circuiting between cathodes of two adjacent rows and / or two columns of sub-pixels. In the process of forming the cathode layer by sputtering, the cathode layer is also formed on the side wall of the separation column due to the irregular movement direction of metal atoms. The adhesion between the cathode layer on the side wall of the separation column and the side wall of the separation column is relatively good, and it is not easy to fall off, resulting in the connection of the cathode layer on the separation column and the cathode layer on the light emitting layer, which in turn leads to two adjacent rows and / or Or the cathode of the sub-pixel of the column is short-circuited. When forming other film layers by evaporation, due to the shadow effect of evaporation, the height of the isolation column needs to be the same as the height of the support layer used to support the mask plate (for example, 1.6 microns). Generally, photolithography technology is used to form the isolation pillars. However, due to the materials and equipment of the photolithography technology, the side walls of the isolation trapezoidal isolation pillars cannot be formed with a small angle of inclination, thus further increasing the separation of two adjacent rows and / or Or the difficulty of the cathodes of the two columns of sub-pixels is not conducive to achieving full-screen display.

The present application provides a display panel, a display screen, and a display terminal, which implement a full-screen display by setting a transparent display panel in a slotted area. The transparent display panel may be a PMOLED display panel.

FIG. 1 shows a schematic cross-sectional view of an isolation column in an embodiment of the present application. For ease of description, FIG. 1 only shows parts related to the embodiments of the present application.

An embodiment of the present application provides a display panel. The display panel includes a substrate 12 and an isolation column 14. The spacer 14 is provided on the substrate 12. In some embodiments, at least one other film layer may be disposed between the isolation pillar 14 and the substrate 12.

In the embodiment of the present application, the isolation pillar 14 includes a plurality of isolation pillar layers 142 stacked. A step 144 is formed between at least two adjacent isolation pillar layers 142. Each isolation pillar layer 142 has a bottom surface, a top surface opposite to the bottom surface, and a side wall connecting the top surface and the bottom surface. For two adjacent isolation pillar layers 142, the bottom surface of the isolation pillar layer 142 located on the upper layer (ie, away from the substrate 12) extends beyond the top surface of the isolation pillar layer 142 located on the lower layer (ie, close to the substrate 12), thereby being located on the upper layer A step 144 may be formed between the isolation pillar layer 142 and the isolation pillar layer 142 located below.

In the manufacturing process of the display panel, the film layers are layered layer by layer on, for example, a substrate, so the film layer formed later is considered to be located “above / upper” of the film layer formed previously. Accordingly, the film layer formed earlier is considered to be located "under / under" the film layer formed later. Therefore, when the film layer is described as "above / upper layer" or "below / lower layer" on another film layer, the up and down direction when laminating the film layers is used as a reference. Correspondingly, the aforementioned top surface of the isolation pillar layer 142 located at the lower layer refers to the surface of the isolation pillar layer 142 located at the lower side away from the substrate 12.

In the width direction perpendicular to the extending direction of the isolation pillar 14, the width of the bottom surface of the isolation pillar layer 142 on which the step 144 is formed and located on the upper layer is larger than the width of the top surface of the isolation pillar layer 142 on which the step 144 is formed and is located on the lower layer. The extending direction of the spacer 14 is parallel to the extending direction of the substrate 12, that is, the longitudinal direction of the spacer 14. The width direction is a direction parallel to the substrate 12 and perpendicular to the extending direction (longitudinal direction) of the spacer 14. The width of the spacer 14 is the dimension of the orthographic projection of the spacer 14 formed on the substrate 12 in the width direction.

The isolation column 14 is a three-dimensional structure, and its cross section in the direction perpendicular to the substrate 12 (ie, the longitudinal cross section) may have different widths at different height positions relative to the substrate 12. When the step 144 is formed and the width of the bottom surface of the isolation pillar layer 142 on the upper layer is larger than the width of the top surface of the separation column layer 142 on which the step 144 is formed, a step with an opening facing downward (ie, toward the substrate 12) 144.

In the process of forming a cathode from top to bottom sputtering, it is difficult to form a cathode layer on the side wall of the isolation pillar layer 142 forming the step 144, thereby effectively blocking the cathode layer of two adjacent rows or columns of sub-pixels, avoiding The cathodes of two adjacent rows or columns of sub-pixels are short-circuited. Further, different voltages can be input to the cathode layers separated from each other, so that different display brightness can be formed at corresponding positions of the display panel, so as to improve the cathode patterning effect and improve the display effect of the full-screen display.

Due to the different widths of the surfaces of the adjacent isolation pillar layers 142 contacting each other, a step 144 with an opening facing upward (that is, toward the direction away from the substrate 12) or an opening facing downward (that is, toward the substrate 12) may be formed.

For example, in an embodiment, when the width of the bottom surface of the isolation pillar layer 142 on which the step 144 is formed and located on the upper layer is smaller than the width of the top surface of the isolation pillar layer 142 on which the step 144 is located and is formed, the opening may be formed upward的步骤 144. The steps 144. However, in the actual manufacturing process, the cathode material can still be sputtered and formed on the side wall of the isolation pillar layer 142 forming the step 144 with the opening facing upward, so the cathodes of two adjacent rows or columns of sub-pixels cannot be well separated. Although it is possible to prevent the cathode material from sputtering on the sidewalls of the isolation pillar layer 142 by reducing the inclination angle of the sidewalls of the isolation pillar layer 142, the manufacturing process difficulty of forming the sidewalls of the isolation pillar layer 142 to form a smaller inclination angle is difficult Larger.

Therefore, the embodiment of forming the step 144 with the opening facing upward cannot block the cathodes of the adjacent two rows or two columns of sub-pixels, and the structure of the step 144 with the opening facing downward of the present application can preferably block the adjacent two rows or The cathodes of the two columns of sub-pixels.

In some embodiments of the present application, in the width direction of the isolation pillar 14, the width of the top surface of the isolation pillar layer 142 is greater than or equal to the width of the bottom surface of the isolation pillar layer 142. In other embodiments, in the width direction of the isolation pillar 14, the width of the top surface of the isolation pillar layer 142 is smaller than the width of the bottom surface of the isolation pillar layer 142.

In some embodiments, the width of the top surface of the isolation pillar layer 142 on which the step 144 is formed and located above is greater than the width of its bottom surface, and the width of the top surface of the isolation pillar layer 142 on which the step 144 is formed and located below is greater than the width of its bottom surface The width. The width of the top surface of the isolation pillar layer 142 is greater than the width of the bottom surface, so that the width of the isolation pillar layer 142 from top to bottom tends to become smaller, so that at least a portion of the side wall of the isolation pillar layer 142 faces the substrate 12 obliquely ( That is, the angle formed by at least part of the surface of the side wall of the isolation pillar layer 142 and the plane where the substrate 12 is located is less than 90 degrees). Since the cathode layer is not easily formed on the side wall of the isolation pillar layer 142 obliquely disposed facing the substrate 12, the isolation pillar 14 can effectively block the cathodes of two adjacent rows or columns of sub-pixels.

In some embodiments, the width of the top surface of the isolation pillar layer 142 forming the step 144 and located at the upper layer is smaller than the width of the bottom surface thereof, and the width of the top surface of the isolation pillar layer 142 forming the step 144 and located at the lower layer is smaller than the width of the bottom surface The width of the surface. As long as the step 144 is formed and the width of the bottom surface of the isolation pillar layer 142 on the upper layer is larger than the width of the top surface of the isolation column layer 142 on which the step 144 is formed, the step 144 with the opening facing downward can be formed. Therefore, in the process of forming the cathode, the cathodes of adjacent two rows or two columns of sub-pixels can still be effectively blocked.

In some embodiments, the cross-sectional shape of the isolation pillar layer perpendicular to the substrate and perpendicular to the extension direction of the isolation pillar is an inverted trapezoid (ie, the width of the top surface is greater than the width of the bottom surface). Further, the isolation pillar layer 142 forming the step 144 may have an inverted trapezoid shape. Adjacent two inverted trapezoidal isolation column layers 142 form a step 144 with the opening facing downward, which can effectively block the cathodes of two adjacent rows or columns of sub-pixels.

In the specific manufacturing process, a negative photoresist layer may be coated on the substrate 12 first, and then exposed and developed to form an inverted trapezoidal isolation pillar layer 142 located at the lower layer. Then, a negative photoresist layer of the same material is coated on the lower spacer column layer 142. Finally, the exposure range is increased compared to the first exposure, so that the negative photoresist layer in which the cross-linking reaction occurs is larger than the isolation pillar layer 142 located below it, so as to form a larger upper isolation pillar on the lower isolation pillar layer 142 Layer 142.

By forming the double inverted trapezoidal isolation column layer 142, the cathodes of adjacent two rows or two columns of sub-pixels can be further effectively blocked, and the manufacturing process is simpler and the cost is lower.

The combination of the plurality of isolation pillar layers 142 is not limited to this. For example, in some embodiments, the two adjacent isolation pillar layers 142 may be various combinations of positive trapezoidal shapes (top surface is smaller than the bottom surface), inverted trapezoidal, or rectangular shapes, as long as the openings that can block the cathode face downward Step 144 is sufficient.

In the extending direction of the isolation pillar 14, the contour of the side wall of the isolation pillar layer 142 may be linear or curved, which is not limited herein. For example, the contour of at least one side wall of the isolation pillar layer 142 has a non-linear shape. The non-linear shape includes at least one of a broken line segment, an arc, a semicircle, and a wave. The beneficial effects of different shapes of the spacer 14 will be described in more detail below.

In some embodiments of the present application, the materials of the two adjacent isolation pillar layers 142 forming the step 144 may be the same. In the actual manufacturing process, two photolithography processes are used. For example, by changing the exposure range of the two photolithography processes, an upper “large” and a “smaller” isolation pillar layer 142 can be formed to form the aforementioned step 144. The production process is simple and the production cost is low. In a specific embodiment, since the negative photoresist is easy to shape and has good insulation, the two upper and lower trapezoidal isolation column layers 142 can both use negative photoresist. For example, after the isolation pillar layer 142 at the lower layer is fabricated, the two exposure trapezoidal isolation pillar layers 142 can be formed by increasing the exposure range.

In other embodiments, the materials of the two adjacent isolation pillar layers 142 forming the step 144 may be different. For example, as shown in FIG. 2, the isolation pillar layer 142 on which the step 144 is formed and located above is a photosensitive polyimide photoresist layer, and the isolation pillar layer 142 on which the step 144 is formed and located below is a silicon nitride layer. On the one hand, since the materials of the two adjacent isolation pillar layers 142 forming the step 144 are different, and the two have different etching rates, the step 144 can be etched in one etching process. Specifically, due to the different etching speeds of two adjacent isolation pillar layers 142, when two adjacent isolation pillar layers 142 are etched in one etching process, the two adjacent isolation pillar layers 142 Different shapes are formed so that steps can be formed between the two. On the other hand, an inorganic material may be selected to ensure that the entire separation column 14 is not conductive, so that it will not bring electromagnetic influence to the cathode formed on the separation column 14 subsequently.

FIG. 2 shows a schematic cross-sectional view of an isolation column in another embodiment of the present application. For ease of description, FIG. 2 only shows parts related to the embodiments of the present application.

In some embodiments, the isolation pillar 14 may further include at least one barrier layer 18. The barrier layer 18 may be disposed below the isolation pillar layer 142 forming the step 144 and located below. The etching selection ratio of the barrier layer 18 to the isolation pillar layer 142 forming the step 144 and in contact with the barrier layer 18 is less than 1.

For example, in one embodiment, the barrier layer 18 is a silicon oxide layer, and the isolation pillar layer 142 is a silicon nitride layer. First, a silicon oxide layer (barrier layer 18) can be vapor-deposited on the substrate 12, and then the silicon oxide layer is etched, leaving only the required width. Next, a silicon nitride layer (isolation pillar layer 142) is vapor-deposited on the silicon oxide layer (barrier layer 18), and a photoresist layer is coated. The etching rate of the silicon oxide layer is smaller than that of the silicon nitride layer. At the beginning of the etching, due to the blocking of the silicon oxide layer, the etching rate of the upper portion of the silicon nitride layer (the portion away from the silicon oxide layer) is greater than the etching rate of the lower portion thereof, thereby forming a positive trapezoidal shape.

The aforementioned step 144 is formed between the silicon nitride layer (lower spacer column layer) and the photoresist layer (upper spacer column layer), which can effectively block the cathodes of two adjacent rows or columns of sub-pixels.

In some embodiments, the barrier layer 18 may be disposed between the two isolation pillar layers 142. The etching selection ratio of the barrier layer 18 to either of the two isolation pillar layers 142 adjacent thereto is less than one. Due to the blocking of the barrier layer 18, the etching rate of the lower part (the part far away from the barrier layer 18) of the isolation pillar layer 142 at the lower layer is higher than the etching rate of the upper part thereof, so that the upper "large" and the "small" inverted can be formed, for example Trapezoid. On the other hand, the upper part of the isolation pillar layer 142 (the part far away from the barrier layer 18) has an etching rate greater than that of the lower part, thereby forming a positive trapezoid such as "small" on the top and "large" on the bottom. Therefore, it is possible to further prevent the cathodes formed subsequently on the adjacent spacers 14 from being connected to each other.

Further, the isolation column layers 142 on both sides of the barrier layer 18 may be inorganic material layers to ensure that the isolation column 14 as a whole is not conductive, so as not to cause electromagnetic influence on the cathode formed on the isolation column 14 subsequently.

Further, the isolation pillar layers 142 on both sides of the barrier layer 18 may use the same material or different materials. In an embodiment, the isolation pillar layers 142 located on both sides of the barrier layer 18 use the same material, for example, silicon nitride may be used. On the one hand, the manufacturing cost can be saved; on the other hand, the shapes and sizes of the two etched isolation pillar layers 142 are relatively symmetrical, which can effectively avoid other adverse effects caused by the asymmetry of the shape and size.

FIG. 3 shows a schematic cross-sectional view of an isolation column in still another embodiment of the present application. FIG. 4 shows a schematic cross-sectional view of an isolation column in still another embodiment of the present application. For ease of description, FIGS. 3 and 4 only show parts related to the embodiments of the present application.

Due to the tip effect, pits as shown in FIG. 3 can be formed in the photoresist layer. The pit can further prevent the cathodes 30 of two adjacent rows or columns of sub-pixels from being connected to each other.

As shown in FIGS. 3 and 4, in some embodiments of the present application, the isolation column 24 is provided with at least one spacing groove 26 penetrating the isolation column 24 in a direction perpendicular to the substrate 22, the at least one spacing groove 26 is isolated The column 24 is divided into at least two parts in the extending direction of the column 24. Therefore, the cathode layer is blocked at the separation groove 26, thereby further blocking the cathodes 30 of adjacent two rows or two columns of sub-pixels.

Further, the spacing groove 26 has a first end (lower end) close to the substrate 22 and a second end (upper end) away from the substrate 22. In the width direction of the spacer 24, the width of the second end of the spacing groove 26 is smaller than the width of the first end of the spacing groove 26. Since the width of the second end of the spacer 26 is smaller than the width of the first end, the material of the cathode layer can be effectively prevented from entering the spacer 26 when the cathode layer is formed by sputtering. Even if the material of the cathode layer enters the spacer 26, the thickness of the cathode layer at the spacer 26 is smaller than the thickness of the cathode layer elsewhere, so the adhesion between the cathode layer and the sidewall of the spacer 26 is reduced, thereby The probability of blocking the cathode 30 of two adjacent rows or columns of sub-pixels is effectively improved.

In some embodiments, the width of the second end of the spacer 26 may be 0.5 μm to 1 μm, so that when the cathode layer is formed by sputtering, the probability of the cathode material entering the spacer 26 can be reduced to a lower level, thereby further The probability of blocking the cathode 30 of two adjacent rows or columns of sub-pixels is improved.

In some embodiments of the present application, the above display panel may be a transparent or transflective display panel. For example, in one embodiment, the display panel is a PMOLED (Passive Matrix OLED, passive organic electroluminescence diode, also called passive organic electroluminescence diode) display panel. The PMOLED display panel has no TFT backplane and metal wiring, so its light transmittance is high.

Further, it is also possible to make the display panel have higher light transmittance by using a film material with better light transmittance. For example, each film layer uses a material with a light transmittance greater than 90%, so that the light transmittance of the entire display panel can reach more than 70%. Further, each film layer uses a material with a light transmittance greater than 95%, which can further improve the light transmittance of the display panel, and even make the light transmittance of the entire display panel reach more than 80%.

Further, the conductive traces such as cathode 30 may be indium tin oxide (ITO), indium zinc oxide (IZO), silver-doped indium tin oxide (Ag + ITO) or silver-doped indium zinc oxide (Ag + IZO ) And other materials, the insulating layer can be made of silicon dioxide (SiO ₂ ), SiNx and aluminum oxide (Al ₂ O ₃ ), and the pixel definition layer can be made of highly transparent materials, thereby further improving the display panel ’s Transmittance.

Other technical means can also be used to increase the light transmittance of the display panel. The transparent or transflective display panel can display the picture normally when it is in the working state, and when the display panel is in the state of other functional requirements, external light can be irradiated through the display panel to the photosensitive device provided below the display panel, etc. .

When a photosensitive device such as a camera is placed below the display panel, the captured image often has serious blur problems, so the display effect of the full-screen display is poor. One of the reasons for this problem is that there are conductive traces in the display panel of the electronic device. When external light passes through these conductive traces, a diffraction effect is generated, which causes diffraction fringes, which in turn affects the normal operation of photosensitive devices such as cameras. For example, when the camera under the transparent display panel is working, the external light passing through the conductive traces of the display panel will produce a more obvious diffraction effect, resulting in distortion of the image taken by the camera. Diffraction is a physical phenomenon where light waves deviate from the original straight line when they encounter obstacles. Specifically, after passing through obstacles such as slits, small holes, or discs, light waves will deviate from the original straight line to varying degrees.

FIG. 5 shows a schematic plan view of an isolation column in an embodiment of the present application. FIG. 6 shows a schematic plan view of an isolation column in another embodiment of the present application. For ease of description, FIGS. 5 and 6 only show parts related to the embodiments of the present application.

As shown in FIGS. 5 and 6, in some embodiments of the present application, the display panel includes a plurality of isolation pillars 44. The maximum width of the spacer 44 changes continuously or discontinuously in the extending direction of the spacer 44. The isolation column 44 is a three-dimensional structure, and its cross section perpendicular to the substrate (ie, longitudinal section) may have different widths at different height positions relative to the substrate 12. Therefore, the maximum width of the above-mentioned spacer 44 is the maximum width of the spacer 14 in its longitudinal section.

When the external light passes through the isolation column, the isolation column acts as an obstacle to cause the diffraction effect of the light, and the position of its diffraction fringe is determined by the maximum width of each place. Therefore, it is only necessary to ensure that the isolation column 44 has a varying maximum width in its extending direction. The above-mentioned continuous change of the maximum width of the isolation column 44 means that the width at any two adjacent positions in the extending direction of the isolation column 44 is different. The discontinuous change of the maximum width of the isolation pillar 44 means that the width of two adjacent positions in the partial area in the extension direction of the isolation pillar 44 is the same, and the width of the two adjacent positions in the partial area is not the same.

Since the maximum width of the isolation column 44 continuously or intermittently changes in the extending direction of the isolation column 44, when external light passes through the isolation column 44, the positions of the diffraction fringes generated at different maximum width positions are different, so that The diffraction effect is not obvious, thereby improving the full-screen display effect of the display panel.

In some embodiments, the plurality of isolation pillars 44 of the display panel are arranged in parallel on the substrate. The maximum width of the spacer 44 is 5-100 microns. The minimum width of the spacer 44 depends on the manufacturing process. On the premise that the preparation process can be realized, the minimum width of the isolation pillar 44 may be less than or equal to 5 microns, or even smaller. The distance between two adjacent isolation columns 44 depends on the size design requirements of the cathodes 30 of two adjacent sub-pixels. By arranging a plurality of isolation pillars 44 in parallel on the substrate, the diffraction effect throughout the display panel can be uniformly improved, thereby improving the overall screen display effect of the display panel as a whole.

In some embodiments, the spacer 44 has a maximum width that varies periodically in its extending direction. That is, the maximum width change of the isolation column 44 is not an irregular change, but a regular periodic change, which can reduce the difficulty of the preparation process. In one embodiment, a width change period of the isolation pillar corresponds to a sub-pixel area. At least one side of the two sides of the edge region of the sub-pixel region on the top surface of the isolation column is non-linear. For example, in the embodiments shown in FIGS. 5 and 6, the non-linear shape may be at least one shape of a polyline, an arc, a semicircle, and a wave shape.

In some embodiments, the isolation column is strip-shaped, its top surface may be rectangular, and its longitudinal section may be inverted trapezoidal, that is, the maximum width of the isolation column may be constant in its extending direction.

In some embodiments, the display panel may include spacers of different shapes, such as strip-shaped spacers and spacers whose maximum width varies in the extending direction of the spacers. Separation columns of different shapes can be arranged alternately, so that the diffraction effect of the entire display panel is consistent everywhere, so that the entire display panel has a uniform display effect.

In some embodiments, the display panel further includes a first electrode and a pixel definition layer. The first electrode may be an anode. The pixel definition layer is formed on the first electrode, and a plurality of pixel openings are formed. For example, the pixel definition layer may cover at least a part of the edge of each first electrode to form a plurality of pixel openings, thereby exposing at least a part of each first electrode. The organic light emitting unit may be filled in the pixel opening. In some embodiments, the first electrode may be formed on the planarization layer, and the height of the planarization layer to the upper surface of the pixel definition layer is greater than the height of the planarization layer to the upper surface of the first electrode.

The first electrode may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), silver-doped indium tin oxide (Ag + ITO), or silver-doped indium zinc oxide (Ag + IZO), etc. Species.

The isolation column 14 may be formed on the pixel definition layer to isolate the cathodes of the adjacent two rows or columns of sub-pixels, and to define the cathode shape of the adjacent two rows or columns of sub-pixels.

FIG. 7 shows a schematic diagram of the plan layout of the first electrode in an embodiment of the present application. For ease of description, FIG. 7 only shows parts related to the embodiments of the present application.

As shown in FIG. 7, in some embodiments of the present application, the first electrode 61 extends in a wave shape in a direction parallel to the substrate. A plurality of first electrodes 61 extend in parallel in the same direction, and adjacent first electrodes 61 have a pitch in the width direction. The width of the first electrode 61 changes continuously or intermittently in the extending direction of the first electrode 61, and the pitch between adjacent first electrodes 61 changes continuously or intermittently.

Since the first electrode 61 has a wave shape, the width of the first electrode 61 varies continuously or intermittently in the extending direction of the first electrode 61. Continuously changing the width means that the width of the first electrode 61 at any two adjacent positions in its extending direction is different. The discontinuous change in width means that the width of the two adjacent positions in the partial area of the first electrode 61 in the extending direction is the same, and the width of the two adjacent positions in the partial area is not the same. For example, in some embodiments, the plurality of first electrodes 61 are regularly arranged on the substrate 62, therefore, the spacing between two adjacent first electrodes 61 is also present in a direction parallel to the extending direction of the first electrodes 61 Continuous change or intermittent change. In the extending direction of the first electrode 61, whether the width of the first electrode 61 changes continuously or intermittently may be a periodic change, and the length of a changing period in the extending direction of the first electrode 61 may correspond to one sub-pixel region.

Since the width of the first electrode 61 in its extending direction continuously changes or intermittently changes, the adjacent first electrodes 61 have a continuously changing pitch or an intermittently changing pitch. Therefore, at different width positions of the first electrode 61 and adjacent At different pitches of the first electrode 61, the positions of the generated diffraction fringes are different, and the derivative effects at different positions cancel each other, which can effectively reduce the diffraction effect, thereby ensuring that the image taken by the camera disposed below the transparent display panel High definition.

FIG. 8 shows a schematic diagram of the projection of the pixel definition layer on the substrate in an embodiment of the present application. For ease of description, the drawings only show parts related to the embodiments of the present application.

As shown in FIG. 8, in some embodiments of the present application, the pixel definition layer includes a plurality of pixel openings 75. Each side of the orthographic projection of the pixel opening 75 on the substrate 73 is a curve, and the sides are not parallel to each other.

Each side of the orthographic projection of the pixel opening 75 on the substrate 73 is not parallel to each other and each side is a curve, that is, the pixel opening 75 has a varying width in each direction and has different diffraction diffusion directions at the same position. During the diffraction process, the distribution of diffraction fringes is affected by the size of obstacles, such as the width of slits, the size of small holes, and so on. The positions of the diffraction fringes generated at the positions with the same width are consistent, so that a more obvious diffraction effect will occur. When external light passes through the pixel opening 75, diffraction stripes with different position distribution and diffusion directions can be generated at different width positions, so no significant diffraction effect will be generated, thereby ensuring that the photosensitive device provided under the display panel can normal work.

In some embodiments, the orthographic projection of the pixel opening 75 on the substrate 73 is a graphic unit or a plurality of graphic units communicating with each other. The graphic unit may be circular or elliptical. The graphic unit can also be composed of curves with different radii of curvature everywhere. The number of graphic units can be determined according to the shape of the corresponding sub-pixel. For example, the number of graphics units can be determined according to the aspect ratio of the sub-pixels. While determining the number of graphic units, it is necessary to take into account the aperture ratio of the sub-pixels. In some embodiments, the graphic unit may also be an axisymmetric graphic, thereby ensuring that each sub-pixel on the entire display panel has a uniform aperture ratio, so that the display panel has a uniform display effect.

The application also provides a display screen. 9 shows a schematic structural diagram of a display screen in an embodiment of the present application. For ease of description, FIG. 9 shows only parts related to the embodiments of the present application.

The display screen includes at least one display area. Each display area is used to display pictures, such as dynamic or static pictures. At least one display area includes a first display area 91. The first display area 91 is provided with a display panel as described in any of the foregoing embodiments. A photosensitive device 93 may be provided under the first display area 91.

Since the first display area 91 adopts the display panel in the foregoing embodiment, the cathodes 30 of two adjacent rows or columns of sub-pixels can be effectively blocked to prevent the cathode layer on the isolation column from being connected to the cathode layer on the light emitting layer. Further, different voltages can be input to the cathodes 30 that are separated from each other, so that different display brightnesses are formed at positions corresponding to the display panel, so as to improve the graphic effect of the cathodes 30 and improve the display effect of full-screen display. In addition, when the light passes through the first display area 91, no obvious diffraction effect is generated, thereby ensuring that the photosensitive device 93 located under the first display area 91 can work normally.

When the photosensitive device 93 located below the first display area 91 does not operate, the first display area 91 can normally perform dynamic or static picture display. When the photosensitive device 93 is in operation, the display screen of the first display area 91 changes as the display content of the overall display screen changes, such as displaying the image being shot. In another embodiment, when the photosensitive device 93 is working, the first display area 91 may also be in a non-display state, thereby further ensuring that the photosensitive device 93 can normally collect light through the display panel.

In some embodiments, the display screen further includes a second display area 92. The light transmittance of the first display area 91 is greater than the light transmittance of the second display area 92. In other embodiments, the light transmittances of the first display area 91 and the second display area 92 may also be the same, so that the entire display panel has a uniform light transmittance, and the display panel has a better display effect.

In some embodiments, the first display area 91 is provided with a PMOLED display panel, and the second display area 92 is provided with an AMOLED display panel or an AMOLED-like display panel, thereby forming a full screen composed of the PMOLED display panel and the AMOLED display panel.

The pixel circuit of the AMOLED-like display panel includes only one switching element (that is, driving TFT) without a capacitor structure. The other structure of the AMOLED-like display panel is the same as the AMOLED display panel.

AMOLED-like is a technology known to those skilled in the art, so its specific structure and principle will not be repeated here.

The present application also provides a display terminal 100. FIG. 10 shows a schematic structural diagram of a display terminal in an embodiment of the present application. For ease of description, FIG. 10 only shows parts related to the embodiments of the present application.

The display terminal 100 includes a device body 110 and a display screen 120. The display screen 120 is provided on the device body 110 and is electrically connected to the device body 110. The display screen 120 may use the display screen in any of the foregoing embodiments for displaying static or dynamic pictures.

FIG. 11 shows a schematic structural diagram of the device body 110 in an embodiment of the present application. For ease of description, FIG. 11 only shows parts related to the embodiments of the present application.

In this embodiment, the device body 110 may be provided with a slotted area 112 and a non-slotted area 114. The slotted area 112 is located below the first display area 91, and a photosensitive device 93 such as a camera and a light sensor may be provided in the slotted area 112. The display panel of the first display area 91 of the display screen 120 corresponds to the slotted area 112, so that the above-mentioned photosensitive device 93 can perform operations such as collecting external light through the first display area 91. Since the display panel of the first display area 91 can effectively improve the diffraction effect generated when external light passes through the first display area 91, the quality of the image captured by the camera located under the display panel can be effectively improved to avoid This causes distortion of the captured image, and also improves the accuracy and sensitivity of the light sensor to sense external light.

The above display terminal may be a mobile phone, a tablet computer, a notebook computer, an iPad and other electronic devices.

The technical features of the above embodiments can be arbitrarily combined. In order to simplify the description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the scope of this description.

The above examples only express several implementation manners of the present application, and their descriptions are more specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all fall within the protection scope of the present application. Therefore, the protection scope of the patent of this application shall be subject to the appended claims.

Claims

A display panel, including:

Substrate; and

The isolation column is arranged on the substrate;

Wherein, the isolation column includes a plurality of stacked isolation column layers; a step is formed between at least two adjacent isolation column layers; the step is formed in a width direction perpendicular to the extending direction of the isolation column And the width of the bottom surface of the isolation pillar layer located on the upper layer is greater than the width of the top surface of the isolation pillar layer located on the lower layer forming the step;

Wherein, the extension direction of the isolation pillar is parallel to the extension direction of the substrate; the width direction is a direction parallel to the substrate and perpendicular to the extension direction of the isolation pillar; the width is the isolation pillar The size of the orthographic projection formed on the substrate in the width direction.
The display panel according to claim 1, wherein the spacer column layer includes a top surface away from the substrate and a bottom surface close to the substrate; in the width direction, the top surface of the spacer column layer The width is greater than or equal to the width of the bottom surface of the isolation pillar layer.
The display panel according to claim 1, wherein the spacer column layer includes a top surface away from the substrate and a bottom surface close to the substrate; in the width direction, the top surface of the spacer column layer The width is smaller than the width of the bottom surface of the isolation pillar layer.
The display panel according to claim 1, wherein materials of two adjacent isolation pillar layers forming the step are the same; or materials of two adjacent isolation pillar layers forming the step are different.
The display panel according to claim 1, wherein the isolation pillar further includes at least one barrier layer; the barrier layer is disposed below the isolation pillar layer that forms the step and is located below.
The display panel according to claim 5, wherein an etching selection ratio of the barrier layer to the isolation pillar layer forming the step and in contact with the barrier layer is less than 1.
The display panel according to claim 1, wherein the isolation pillar further comprises at least one barrier layer; the barrier layer is disposed between the two isolation pillar layers.
The display panel according to claim 7, wherein an etching selection ratio of the barrier layer to any one of the two adjacent pillar layers adjacent thereto is less than 1.
The display panel according to claim 1, wherein the isolation column is provided with at least one spacing groove penetrating the isolation column in a direction perpendicular to the substrate, the at least one spacing groove is located The separation column is divided into at least two parts in the extending direction.
The display panel according to claim 9, wherein the spacing groove has a first end close to the substrate and a second end away from the substrate; in the width direction, the second end of the spacing groove The width is smaller than the width of the first end of the spacing groove.
The display panel according to claim 10, wherein the width of the second end of the spacing groove ranges from 0.5 to 1 micrometer.
The display panel according to claim 1, wherein the display panel includes a plurality of spacers arranged in parallel on the substrate; the maximum width of the spacers continuously changes or is intermittent in the extending direction of the spacers Variety.
The display panel according to claim 1, wherein the display panel is a PMOLED display panel, and the light transmittance of the material of each film layer of the PMOLED display panel is greater than 90%.
The display panel according to claim 1, wherein the material of the conductive traces of the display panel is at least one of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide Species.
The display panel according to claim 1, wherein the display panel further comprises a plurality of first electrodes disposed between the substrate and the spacer; the first electrodes are in a direction parallel to the substrate The upper part extends in a wave shape; the plurality of first electrodes extend in parallel in the same direction, and there is a gap between adjacent first electrodes in the width direction; the width of the first electrode is in the first The extending direction of the electrodes changes continuously or intermittently, and the spacing between adjacent first electrodes changes continuously or intermittently.
The display panel according to claim 1, wherein the display panel further comprises a pixel definition layer disposed between the substrate and the spacer, the pixel definition layer being formed with a plurality of pixel openings; the pixels Each side of the orthographic projection of the opening on the substrate is a curve, and the sides are not parallel to each other.
The display panel according to claim 16, wherein the orthographic projection of the pixel opening on the substrate is a circular unit or a plurality of circular units communicating with each other; the circular unit is circular or elliptical .
A display screen includes at least one display area; the at least one display area includes a first display area, and a photosensitive device can be disposed below the first display area;

Wherein, the first display area is provided with the display panel according to any one of claims 1 to 17, and each display area in the at least one display area is used to display a picture.
The display screen according to claim 18, wherein the at least one display area further comprises a second display area; the display panel provided in the first display area is a PMOLED display panel, and the AMOLED is provided in the second display area Display panel or AMOLED-like display panel.
A display terminal, including:

Device body; and

A display screen, the display screen is provided on the device body;

Wherein, the display screen includes at least one display area; the at least one display area includes a first display area; the first display area is provided with a display panel according to any one of claims 1 to 17, Each display area in at least one display area is used to display a picture;

Wherein, the device body is provided with a slotted area, the slotted area is located below the first display area, and a photosensitive device is provided in the slotted area.