WO2020085607A1 - Cross-point capacitor based weighting element and neural network using same - Google Patents

Cross-point capacitor based weighting element and neural network using same Download PDF

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Publication number
WO2020085607A1
WO2020085607A1 PCT/KR2019/007416 KR2019007416W WO2020085607A1 WO 2020085607 A1 WO2020085607 A1 WO 2020085607A1 KR 2019007416 W KR2019007416 W KR 2019007416W WO 2020085607 A1 WO2020085607 A1 WO 2020085607A1
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horizontal
vertical
capacitor
cross
conductive lines
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PCT/KR2019/007416
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French (fr)
Korean (ko)
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유인경
곽명훈
황현상
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포항공과대학교산학협력단
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Publication of WO2020085607A1 publication Critical patent/WO2020085607A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present invention relates to a cross-point capacitor-based weighting element and a neural network using the same.
  • Neuromorphic circuits can be effectively used to implement intelligent systems that can adapt themselves to unspecified environments. As this technology develops, it can develop into computers, robots, home appliances, small mobile devices, security and surveillance, intelligent vehicle safety, autonomous driving, etc. that perform recognition and estimation, such as voice recognition, risk recognition, real-time high-speed signal processing, etc. have.
  • synaptic weights should be non-volatile multi-level and linear, and neurons should have activation.
  • CMOS technology that is easy to manufacture, but when using the CMOS technology, there is a problem that the chip size increases as the circuit increases.
  • efforts have been made to use multi-level memory materials as synaptic weights and threshold switching materials as neurons, but they do not have the performance and manufacturability of CMOS technology.
  • An object of the present invention is to provide a structure of a cross-point capacitor-based weighting device having a linear multi-synaptic weight using a vertical stacked cross-point capacitor cell and a neural network using the same.
  • a cross-point capacitor-based weighting element includes horizontal conductive lines extending in a first direction and horizontal conductive lines in a third direction between the horizontal conductive lines.
  • a unit horizontal stacked structure including horizontal insulation line layers alternately positioned with each other;
  • a unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned in an orthogonal direction to the second direction, the horizontal conductive lines, the vertical conductive layer, and the capacitor formed of the vertical dielectric layer synaptic weight ( synaptic weight).
  • the charge discharged after being charged in the capacitor may be used as the synaptic weight.
  • the charge discharged after being charged in the capacitor may be proportional to an input voltage pulse.
  • the charge discharged after being charged in the capacitor may be proportional to the selected number of word lines corresponding to the horizontal conductive lines.
  • the weighting element may further include a selection transistor for storing the word line selection information.
  • the selection transistor may include a floating gate transistor.
  • the unit vertical stacked structure may be located between the plurality of unit horizontal stacked structures.
  • the vertical conductive layer may include a vertical conductive line and a vertical insulating line.
  • the capacitor may be formed of the horizontal conductive lines, the vertical conductive lines, and the vertical dielectric layer.
  • the horizontal conductive line and the vertical conductive layer may include polysilicon.
  • the horizontal insulation line may include SiO2.
  • the vertical dielectric layer may include at least one of SiO2, HfO2, ZrO2, Si3N4 and Al2O3.
  • the cross-point capacitor-based weighting element includes horizontal conductive lines extending in a first direction, and horizontally positioned alternately with the horizontal conductive lines in a third direction between the horizontal conductive lines.
  • a first horizontal stacked structure and a second horizontal stacked structure including insulating lines, and a vertical conductive layer and a vertical dielectric layer positioned alternately orthogonal to the second direction, wherein the first horizontal stacked structure and the second horizontal
  • a weight group including unit vertical stacked structures positioned between the stacked structures;
  • a capacitor formed between the plurality of weight groups includes a vertical insulating layer, and the capacitor formed of the horizontal conductive lines, the vertical conductive layer, and the vertical dielectric layer is used as a synaptic weight.
  • the vertical insulating layer may include SiO2.
  • the neural network is a unit including horizontal conductive lines extending in a first direction and horizontal insulating lines alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines.
  • Horizontal stacked structure and a unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned perpendicular to the second direction and charged in the capacitor formed of the horizontal conductive lines and the vertical conductive layer. It includes a weighting element used as a synaptic weight.
  • the charge discharged after being charged in the capacitor may be proportional to the input voltage pulse.
  • the charge discharged after being charged in the capacitor may be proportional to the selected number of word lines corresponding to the horizontal conductive lines.
  • the weighting element may further include a selection transistor for storing the word line selection information.
  • the selection transistor may include a floating gate transistor.
  • the neural network may further include a storage device for storing the word line selection information.
  • the learning efficiency can be increased by having a linear multi-synaptic weight using a vertical stacked cross-point capacitor cell.
  • the resistance value of the resistance weight can be changed to significantly reduce power consumption compared to a conductivity-based weighting device using a current proportional to this as an output signal.
  • FIG. 1 is a block diagram conceptually showing a neural network according to an embodiment of the present invention.
  • FIG. 2 is a perspective view schematically showing the structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • FIG 3 is a cross-sectional view schematically showing a structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • FIG. 4 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • FIG. 5 is a perspective view schematically showing a structure of a cross-point capacitor-based weighting device according to another embodiment of the present invention
  • FIG. 6 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to another embodiment of the present invention.
  • first, second, etc. may be used to describe various elements, elements, regions, layers, and / or sections, but such elements, elements, regions, layers, and / or Or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and / or section from another element, element, region, layer, or section. Thus, the first element, element, region, layer, and / or section in one embodiment may be referred to as the second element, element, region, layer, and / or section in another embodiment.
  • FIG. 1 is a block diagram conceptually showing a neural network according to an embodiment of the present invention.
  • a neural network includes an input neuron 10, an output neuron 20, and a weighting element 30.
  • the synapse 30 element is to be arranged at the intersection of row lines (R) extending horizontally from the input neuron 10 and column lines (C) extending vertically from the output neuron 20.
  • R row lines
  • C column lines
  • FIG. 1 illustratively shows four input neurons 10 and output neurons 20, respectively, but the present invention is not limited thereto.
  • the input neuron 10 transmits electrical pulses to the weight element 30 through the low line R in a learning mode, a reset mode, a correction or reading mode. You can.
  • the output neuron 20 may transmit electrical pulses to the weighting element 30 through the column line C during learning mode or reset mode or correction, and the weighting element 30 through the column line C in the read mode. Can receive electrical pulses.
  • the weight element 30 may have a multi-level value.
  • the weight element 30 varies its value according to whether write / erase of floating gate transistors is performed.
  • the floating gate transistor connected to the weight element 30 is in the erase state, the flow of the transistor current is smooth, so the charge and discharge operation of the connected capacitors is possible.
  • the capacitor value of the weight element 30 is determined in proportion to the number of floating gate transistors in the erased state. That is, the multilevel can be as many as the number of floating gate transistors connected to the weight element 30.
  • an output signal may be used as a synaptic weight.
  • FIG. 2 is a perspective view schematically showing the structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • 3 is a cross-sectional view schematically showing a structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • the cross-point capacitor-based weighting element 30 includes horizontal conductive lines 111 and horizontal conductive lines 111 extending in a first direction.
  • Unit horizontal stacked structure 110 including horizontal insulating lines 113 located therebetween, vertical stacked structure including vertical conductive layer 121 and vertical dielectric layer 123 alternately positioned in an orthogonal direction to the second direction 120.
  • a structure in which the vertical dielectric layer 123 and the vertical conductive layer 121 are alternately formed along one side of the unit horizontal stacked structure 110 is defined as the unit vertical stacked structure 120.
  • the manufacturing of the weight element 30 may apply a NAND process.
  • the horizontal conductive line 111 may be polysilicon. As an embodiment, the horizontal conductive line 111 may have a high dopant concentration to function as a conductor. As an embodiment, the horizontal conductive line 111 may be a word line.
  • the horizontal insulation line 113 insulates the plurality of horizontal conductive lines 111.
  • the horizontal insulation line 113 may include at least one of SiO2, Si3N4, metal oxide, metal nitride, and a polymer material film, but the present invention is not limited thereto.
  • the unit vertical stacked structure 120 may be located between the plurality of unit horizontal stacked structures 110.
  • the vertical conductive layer 121 is formed perpendicular to the second direction.
  • the vertical conductive layer 121 may be polysilicon, but is not limited thereto.
  • a vertical dielectric layer 123 is formed between the vertical conductive layer 121 and the horizontal conductive line 111 to form a capacitor with the vertical conductive layer 121 and the horizontal conductive line 111.
  • the vertical conductive layer 121 may be a plate, and the vertical dielectric layer 123 may use a dielectric material to effectively insulate between electrodes while improving the capacitor's power storage capacity.
  • the vertical dielectric layer 123 may include at least one of SiO2, HfO2, ZrO2, Si3N4, and Al2O3.
  • the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive layer 121 is used as a synaptic weight.
  • the amount of charge stored in the capacitor may be output through a line electrically connected to the horizontal conductive line 111.
  • the cross-point capacitor-based weighting element 30 includes a first unit horizontal stacked structure 110, a second unit horizontal stacked structure 110, and a unit vertical stacked structure 120.
  • the weight group and the vertical insulating layer 133 may be included.
  • the first unit horizontal stacked structure 110 and the second unit horizontal stacked structure 110 are horizontally conductive in the third direction between the horizontal conductive lines 111 extending in the first direction and the horizontal conductive lines 111. It may include horizontal insulation lines 113 alternately positioned with the lines 111.
  • the unit vertical stacked structure 120 may include a vertical conductive layer 121 and a vertical dielectric layer 123 alternately positioned in an orthogonal direction to the second direction.
  • the vertical insulating layer 133 may be positioned between a plurality of weight groups.
  • the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive layer 121 is used as a synaptic weight.
  • a group of horizontal conductive lines 111 and a group of right horizontal conductive lines 111 located on the left side of the vertical conductive layer 121 may be defined and used as positive and negative weights, respectively.
  • a voltage is applied to a stacked cross-point capacitor cell to use the weighting element 30 according to an embodiment of the present invention as a synaptic weight.
  • the input signal by on-chip AI learning uses the number of voltage pulses input over a period of time or inputs multiple values to the weighting device based on the cross-point capacitor using the voltage magnitude of the voltage pulse. can do.
  • voltages are applied to the vertical conductive layer 121, which is a common electrode, after selecting each of the horizontal conductive lines 111, that is, the word line, with the selection transistors S11, S14, and S1j.
  • the voltage pulse applied to the vertical conductive layer 121 may adjust the number of pulses or the magnitude of the pulse voltage according to an input situation.
  • the number of word lines corresponding to the weight value can be selected independently of the number of input pulses or the input voltage.
  • the cross point where the vertical conductive layer 121 and the horizontal conductive lines 111 intersect is formed with a capacitor and charge is accumulated by the input voltage.
  • the accumulated charge is summed and sent to the integrator, where it is converted into a voltage.
  • the output signal converted to voltage is greater than or equal to the threshold voltage level, it is transmitted to an input node constituting the next layer.
  • FIG. 4 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
  • charges are drawn toward the select transistor by selecting the number of word lines in the cross-point capacitor cell and applying a Vpp voltage to the common electrode of the capacitor.
  • the amount of charge Q stored in the capacitor is proportional to the capacitor's power storage capacity C and the applied voltage V.
  • the output signal according to the input signal may have a linear value by using several capacitors determined according to the number of conductive paths of the cross-point node.
  • the weight level may be determined by a selected number of word lines.
  • a voltage pulse is applied to an input node and a word line of capacitor cells is selected according to the magnitude of each weight. As an embodiment, if the weight is 1, one word line is selected, and if the weight is 5, five word lines are selected. By selecting each weight randomly, simultaneously, and independently directly, the output for the input is generated in a matrix.
  • the unit weight may consist of a capacitor cell block with a certain number of word lines.
  • the maximum number of selectable word lines may be the maximum dynamic range.
  • the sum of the charges discharged at each weight can be accumulated into an integrator and converted into a voltage.
  • information on the number of word line selections finally determined after learning or training may be stored in an external storage device.
  • a floating gate transistor can be used as a selection transistor.
  • a correction amount of weight is calculated during learning using a transpose weight matrix, and a word line can be selected in proportion to the correction amount of the obtained weight. .
  • FIG. 5 is a perspective view schematically showing a structure of a cross-point capacitor-based weighting device according to another embodiment of the present invention
  • a cross-point capacitor-based weighting element 30 is located between horizontal conductive lines 111 and horizontal conductive lines 111 extending in a first direction.
  • the unit vertical stack structure 120 is included.
  • the manufacturing of the weight element 30 may apply a NAND process.
  • the horizontal insulation line 113 insulates the plurality of horizontal conductive lines 111.
  • the horizontal insulation line 113 may include at least one of SiO2, Si3N4, metal oxide, metal nitride, and a polymer material film, but the present invention is not limited thereto.
  • the unit vertical stacked structure 120 may be located between the plurality of unit horizontal stacked structures 110.
  • the vertical conductive line 122 is formed perpendicular to the second direction.
  • the vertical conductive line 122 may be polysilicon, but is not limited thereto.
  • a vertical dielectric layer 123 is formed between the vertical conductive line 121 and the horizontal conductive line 111 to form a capacitor with the vertical conductive line 122 and the horizontal conductive line 111, and the vertical conductive lines 122 Vertical insulation lines 124 are formed to insulate between them.
  • a structure in which the vertical dielectric layer 123 and the vertical conductive line 122 and the vertical insulating line 124 are alternately formed along one side of the unit horizontal stacked structure 110 is defined as the unit vertical stacked structure 120.
  • the vertical conductive line 122 may be a bit line, and the vertical dielectric layer 123 may use a dielectric material to effectively insulate between electrodes while improving the capacitor's power storage capacity.
  • the vertical dielectric layer 123 may include at least one of SiO2, HfO2, ZrO2, Si3N4, and Al2O3.
  • the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive lines 122 is used as a synaptic weight.
  • the amount of charge stored in the capacitor may be output through a line electrically connected to the horizontal conductive line 111.
  • the weight element 30 includes a vertical conductive line 122 instead of the vertical conductive layer 121 of FIGS. 2 and 3. Therefore, the charge accumulated in each of the capacitors formed of the horizontal conductive lines 111 and the vertical conductive lines 122 can be used as a synaptic weight, when compared with a weight element including a vertical conductive layer of the same size. Multiple multilevel synaptic weights can be expressed.
  • information on the number of word line selections finally determined after learning or training may be stored in an external storage device.
  • a floating gate transistor can be used as a selection transistor.
  • a correction amount of weight is calculated during learning using a transpose weight matrix, and a word line can be selected in proportion to the correction amount of the obtained weight. .
  • FIG. 6 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to another embodiment of the present invention.
  • a NAND flash may be used as a weighting element according to another embodiment of the present invention.
  • Pass transistors and decoders are required when using NAND flash as a storage device, so they do not work when used as a synaptic element.
  • all NAND cells may be charged or discharging, and the capacitance of the gate oxide may be used as a weight. It may be desirable that the floating gate transistor is discharging.
  • the input voltage pulse is applied to the source line, and the output charge is discharged to the word line.
  • a selection transistor or a floating gate transistor may be attached to a word line and a storage function may be performed.
  • a floating gate transistor may be disposed opposite the pass transistor and the decoder to use NAND flash as a storage / weighting element.
  • the structure of the weighting device based on the cross-point capacitor according to an embodiment of the present invention and the neural network using the same are linear multiple synaptics using vertical stacked cross-point capacitor cells
  • learning efficiency can be increased.
  • the resistance value of the resistance weight can be changed to significantly reduce power consumption compared to a conductivity-based weighting device using a current proportional to this as an output signal.

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Abstract

A cross-point capacitor based weighting element according to an embodiment of the present invention, comprises: a unit horizontal stacked structure having horizontal conductive lines extending in a first direction, and horizontal insulating line layers alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines; and a unit vertical stacked structure having a vertical conductive layer and a vertical dielectric layer which are orthogonal to a second direction and are alternately positioned with respect to each other, wherein a capacitor formed of the horizontal conductive lines, the vertical conductive layer, and the vertical dielectric layer is utilized as a synaptic weight.

Description

크로스-포인트 커패시터 기반의 가중치 소자 및 이를 이용한 뉴럴 네트워크Cross-point capacitor-based weighting element and neural network using the same
본 발명은 크로스-포인트 커패시터 기반의 가중치 소자 및 이를 이용한 뉴럴 네트워크에 관한 것이다.The present invention relates to a cross-point capacitor-based weighting element and a neural network using the same.
최근 인간의 신경계를 닮은 뉴로모픽 회로(neuromorphic circuit)에 관한 관심이 증대되고 있다. 인간의 신경계에 존재하는 뉴런(neuron)과 시냅스(synapse)에 각각 대응되는, 뉴런 회로와 시냅스 회로를 설계하여, 뉴로모픽 회로를 구현하고자 하는 연구가 활발히 진행되고 있다.Recently, interest in a neuromorphic circuit resembling the human nervous system has been increasing. Researches to design neuronal circuits and synaptic circuits, which correspond to neurons and synapses existing in the human nervous system, are being actively conducted.
뉴로모픽 회로는 불특정한 환경에 스스로 적응할 수 있는 지능화된 시스템을 구현하는 데에 효과적으로 활용될 수 있다. 이 기술이 발전하면 음성인식, 위험 인지, 실시간 고속 신호처리, 등 인지 및 추정 등을 수행하는 컴퓨터, 로봇, 가전기기, 소형 이동 기기, 보안 및 감시, 지능형 차량 안전, 자율 주행 등으로 발전할 수 있다.Neuromorphic circuits can be effectively used to implement intelligent systems that can adapt themselves to unspecified environments. As this technology develops, it can develop into computers, robots, home appliances, small mobile devices, security and surveillance, intelligent vehicle safety, autonomous driving, etc. that perform recognition and estimation, such as voice recognition, risk recognition, real-time high-speed signal processing, etc. have.
위 기재된 내용은 오직 본 발명의 기술적 사상들에 대한 배경 기술의 이해를 돕기 위한 것이며, 따라서 그것은 본 발명의 기술 분야의 당업자에게 알려진 선행 기술에 해당하는 내용으로 이해될 수 없다.The above description is only to assist in understanding the background of the technical ideas of the present invention, and therefore it cannot be understood as the content corresponding to the prior art known to those skilled in the art of the present invention.
뉴럴 네트워크를 하드웨어(hardware)화 하는데 있어서 핵심 소자는 시냅틱 가중치(synaptic weight)와 뉴런이다. 시냅틱 가중치는 불휘발성 멀티레벨(multi level)이면서 선형성이 있어야 하고 뉴런은 활성화(activation) 기능이 있어야 한다. 이를 위하여 제작이 용이한 CMOS 기술을 사용하는 것이 바람직하나, CMOS 기술을 사용하는 경우 회로가 증가하면서 칩 사이즈가 커지는 문제가 있다. 이에 대해 멀티레벨 메모리 소재를 시냅틱 가중치로 사용하고 임계 스위칭(threshold switching) 소재를 뉴런으로 사용하려고 하는 노력이 있으나 CMOS 기술 정도의 성능과 제조성이 없다.The key elements in hardwareizing a neural network are synaptic weights and neurons. Synaptic weights should be non-volatile multi-level and linear, and neurons should have activation. For this, it is preferable to use a CMOS technology that is easy to manufacture, but when using the CMOS technology, there is a problem that the chip size increases as the circuit increases. In contrast, efforts have been made to use multi-level memory materials as synaptic weights and threshold switching materials as neurons, but they do not have the performance and manufacturability of CMOS technology.
본 발명의 실시예는 수직 적층형 크로스-포인트 커패시터 셀을 이용하여 선형적인 다중 시냅틱 가중치를 가지는 크로스-포인트 커패시터 기반의 가중치 소자의 구조 및 이를 이용한 뉴럴 네트워크를 제공함을 목적으로 한다.An object of the present invention is to provide a structure of a cross-point capacitor-based weighting device having a linear multi-synaptic weight using a vertical stacked cross-point capacitor cell and a neural network using the same.
상기 목적을 달성하기 위하여 본 발명의 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자는 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인층들을 포함하는 단위 수평 적층 구조체와; 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하는 단위 수직 적층 구조체를 포함하고, 상기 수평 도전 라인들, 상기 수직 도전층, 및 상기 수직 유전체층으로 형성된 커패시터를 시냅틱 가중치(synaptic weight)로 활용한다.To achieve the above object, a cross-point capacitor-based weighting element according to an embodiment of the present invention includes horizontal conductive lines extending in a first direction and horizontal conductive lines in a third direction between the horizontal conductive lines. A unit horizontal stacked structure including horizontal insulation line layers alternately positioned with each other; A unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned in an orthogonal direction to the second direction, the horizontal conductive lines, the vertical conductive layer, and the capacitor formed of the vertical dielectric layer synaptic weight ( synaptic weight).
상기 커패시터에 충전된 후 방전되는 전하를 상기 시냅틱 가중치로 활용할 수 있다.The charge discharged after being charged in the capacitor may be used as the synaptic weight.
상기 커패시터에 충전된 후 방전되는 전하는 입력 전압 펄스(input voltage pulse)에 비례할 수 있다.The charge discharged after being charged in the capacitor may be proportional to an input voltage pulse.
상기 커패시터에 충전된 후 방전되는 전하는 상기 수평 도전 라인들에 대응하는 워드 라인(word line)이 선택된 개수와 비례할 수 있다.The charge discharged after being charged in the capacitor may be proportional to the selected number of word lines corresponding to the horizontal conductive lines.
상기 가중치 소자는 상기 워드 라인 선택 정보를 저장하기 위한 선택 트랜지스터를 더 포함할 수 있다.The weighting element may further include a selection transistor for storing the word line selection information.
상기 선택 트랜지스터는 플로팅 게이트(floating gate) 트랜지스터를 포함할 수 있다.The selection transistor may include a floating gate transistor.
상기 단위 수직 적층 구조체는 상기 복수 개의 단위 수평 적층 구조체 사이에 위치할 수 있다.The unit vertical stacked structure may be located between the plurality of unit horizontal stacked structures.
상기 수직 도전층은 수직 도전 라인 및 수직 절연 라인을 포함할 수 있다.The vertical conductive layer may include a vertical conductive line and a vertical insulating line.
상기 커패시터는 상기 수평 도전 라인들, 상기 수직 도전 라인, 및 상기 수직 유전체층으로 형성될 수 있다.The capacitor may be formed of the horizontal conductive lines, the vertical conductive lines, and the vertical dielectric layer.
상기 수평 도전 라인 및 상기 수직 도전층은 폴리 실리콘을 포함할 수 있다.The horizontal conductive line and the vertical conductive layer may include polysilicon.
상기 수평 절연 라인은 SiO2를 포함할 수 있다.The horizontal insulation line may include SiO2.
상기 수직 유전체층은 SiO2, HfO2, ZrO2, Si3N4 및 Al2O3 중 적어도 하나를 포함할 수 있다.The vertical dielectric layer may include at least one of SiO2, HfO2, ZrO2, Si3N4 and Al2O3.
본 발명의 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자는 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인들을 포함하는 제1 수평 적층 구조체와 제2 수평 적층 구조체, 및 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하고, 상기 제1 수평 적층 구조체와 상기 제2 수평 적층 구조체 사이에 위치하는 단위 수직 적층 구조체를 포함하는 가중치 그룹과; 상기 복수 개의 가중치 그룹 사이에 위치하는 수직 절연층을 포함하고, 상기 수평 도전 라인들, 상기 수직 도전층, 및 상기 수직 유전체층으로 형성된 커패시터를 시냅틱 가중치(synaptic weight)로 활용한다.The cross-point capacitor-based weighting element according to an embodiment of the present invention includes horizontal conductive lines extending in a first direction, and horizontally positioned alternately with the horizontal conductive lines in a third direction between the horizontal conductive lines. A first horizontal stacked structure and a second horizontal stacked structure including insulating lines, and a vertical conductive layer and a vertical dielectric layer positioned alternately orthogonal to the second direction, wherein the first horizontal stacked structure and the second horizontal A weight group including unit vertical stacked structures positioned between the stacked structures; A capacitor formed between the plurality of weight groups includes a vertical insulating layer, and the capacitor formed of the horizontal conductive lines, the vertical conductive layer, and the vertical dielectric layer is used as a synaptic weight.
상기 수직 절연층은 SiO2를 포함할 수 있다.The vertical insulating layer may include SiO2.
본 발명의 실시예에 따른 뉴럴 네트워크는 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인들을 포함하는 단위 수평 적층 구조체; 및 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하는 단위 수직 적층 구조체를 포함하고, 상기 수평 도전 라인들과 상기 수직 도전층으로 형성된 커패시터에 충전된 후 방전되는 전하를 시냅틱 가중치(synaptic weight)로 활용하는 가중치 소자를 포함한다.The neural network according to an embodiment of the present invention is a unit including horizontal conductive lines extending in a first direction and horizontal insulating lines alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines. Horizontal stacked structure; And a unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned perpendicular to the second direction and charged in the capacitor formed of the horizontal conductive lines and the vertical conductive layer. It includes a weighting element used as a synaptic weight.
상기 커패시터에 충전된 후 방전되는 전하는 입력 전압 펄스에 비례할 수 있다.The charge discharged after being charged in the capacitor may be proportional to the input voltage pulse.
상기 커패시터에 충전된 후 방전되는 전하는 상기 수평 도전 라인들에 대응하는 워드 라인(word line)이 선택된 개수와 비례할 수 있다.The charge discharged after being charged in the capacitor may be proportional to the selected number of word lines corresponding to the horizontal conductive lines.
상기 가중치 소자는, 상기 워드 라인 선택 정보를 저장하기 위한 선택 트랜지스터를 더 포함할 수 있다.The weighting element may further include a selection transistor for storing the word line selection information.
상기 선택 트랜지스터는 플로팅 게이트(floating gate) 트랜지스터를 포함할 수 있다.The selection transistor may include a floating gate transistor.
상기 뉴럴 네트워크는 상기 워드 라인 선택 정보를 저장하기 위한 저장장치를 더 포함할 수 있다.The neural network may further include a storage device for storing the word line selection information.
이와 같은 본 발명의 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조 및 이를 이용한 뉴럴 네트워크에 의하면 수직 적층형 크로스-포인트 커패시터 셀을 이용한 선형적인 다중 시냅틱 가중치를 가짐으로써, 학습 효율을 증가시킬 수 있다.According to the structure of the weighting device based on the cross-point capacitor according to the embodiment of the present invention and the neural network using the same, the learning efficiency can be increased by having a linear multi-synaptic weight using a vertical stacked cross-point capacitor cell. have.
또한, 커패시터를 가중치로 사용함으로써 저항 가중치의 저항 값을 변화시켜 이에 비례하는 전류를 출력 신호로 사용하는 전도도 기반의(conductance-based) 가중치 소자에 비하여 전력 소모를 크게 감소 시킬 수 있다.In addition, by using a capacitor as a weight, the resistance value of the resistance weight can be changed to significantly reduce power consumption compared to a conductivity-based weighting device using a current proportional to this as an output signal.
도 1은 본 발명의 일 실시예에 따른 뉴럴 네트워크를 개념적으로 도시한 블록도이다.1 is a block diagram conceptually showing a neural network according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 사시도이다.2 is a perspective view schematically showing the structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
도 3은 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 단면도이다.3 is a cross-sectional view schematically showing a structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
도 4는 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 동작을 개략적으로 나타내는 회로도이다. 4 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 사시도이다5 is a perspective view schematically showing a structure of a cross-point capacitor-based weighting device according to another embodiment of the present invention
도 6은 본 발명의 다른 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 동작을 개략적으로 나타내는 회로도이다.6 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to another embodiment of the present invention.
위 발명의 배경이 되는 기술 란에 기재된 내용은 오직 본 발명의 기술적 사상에 대한 배경 기술의 이해를 돕기 위한 것이며, 따라서 그것은 본 발명의 기술 분야의 당업자에게 알려진 선행 기술에 해당하는 내용으로 이해될 수 없다.The contents described in the description column of the background of the present invention are only for helping the understanding of the background of the technical idea of the present invention, and therefore it can be understood as the content corresponding to the prior art known to those skilled in the art of the present invention. none.
아래의 서술에서, 설명의 목적으로, 다양한 실시예들의 이해를 돕기 위해 많은 구체적인 세부 내용들이 제시된다. 그러나, 다양한 실시예들이 이러한 구체적인 세부 내용들 없이 또는 하나 이상의 동등한 방식으로 실시될 수 있다는 것은 명백하다. 다른 예시들에서, 잘 알려진 구조들과 장치들은 다양한 실시예들을 불필요하게 이해하기 어렵게 하는 것을 피하기 위해 블록도로 표시된다. In the following description, for the purpose of explanation, many specific details are presented to aid understanding of various embodiments. However, it is apparent that various embodiments may be practiced without these specific details or in one or more equivalent ways. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily making various embodiments difficult to understand.
도면에서, 레이어들, 필름들, 패널들, 영역들 등의 크기 또는 상대적인 크기는 명확한 설명을 위해 과장될 수 있다. 또한, 동일한 참조 번호는 동일한 구성 요소를 나타낸다.In the drawings, the size or relative size of layers, films, panels, regions, etc. may be exaggerated for clarity. Also, the same reference numerals denote the same components.
명세서 전체에서, 어떤 부분이 다른 부분과 "연결"되어 있다고 할 때, 이는 "직접적으로 연결"되어 있는 경우뿐 아니라, 그 중간에 다른 소자를 사이에 두고 "간접적으로 연결"되어 있는 경우도 포함한다. 그러나, 만약 어떤 부분이 다른 부분과 "직접적으로 연결되어 있다"고 서술되어 있으면, 이는 해당 부분과 다른 부분 사이에 다른 소자가 없음을 의미할 것이다. "X, Y, 및 Z 중 적어도 어느 하나", 그리고 "X, Y, 및 Z로 구성된 그룹으로부터 선택된 적어도 어느 하나"는 X 하나, Y 하나, Z 하나, 또는 X, Y, 및 Z 중 둘 또는 그 이상의 어떤 조합 (예를 들면, XYZ, XYY, YZ, ZZ) 으로 이해될 것이다. 여기에서, "및/또는"은 해당 구성들 중 하나 또는 그 이상의 모든 조합을 포함한다.Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "indirectly connected" with another element in between. . However, if a part is described as being "directly connected" to another part, it will mean that there is no other element between the part and the other part. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" are one of X, one of Y, one of Z, or two of X, Y, and Z, or Any further combination (eg, XYZ, XYY, YZ, ZZ) will be understood. Here, “and / or” includes all combinations of one or more of the configurations.
여기에서, 첫번째, 두번째 등과 같은 용어가 다양한 소자들, 요소들, 지역들, 레이어들, 및/또는 섹션들을 설명하기 위해 사용될 수 있지만, 이러한 소자들, 요소들, 지역들, 레이어들, 및/또는 섹션들은 이러한 용어들에 한정되지 않는다. 이러한 용어들은 하나의 소자, 요소, 지역, 레이어, 및/또는 섹션을 다른 소자, 요소, 지역, 레이어, 및 또는 섹션과 구별하기 위해 사용된다. 따라서, 일 실시예에서의 첫번째 소자, 요소, 지역, 레이어, 및/또는 섹션은 다른 실시예에서 두번째 소자, 요소, 지역, 레이어, 및/또는 섹션이라 칭할 수 있다.Here, terms such as first, second, etc. may be used to describe various elements, elements, regions, layers, and / or sections, but such elements, elements, regions, layers, and / or Or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and / or section from another element, element, region, layer, or section. Thus, the first element, element, region, layer, and / or section in one embodiment may be referred to as the second element, element, region, layer, and / or section in another embodiment.
"아래", "위" 등과 같은 공간적으로 상대적인 용어가 설명의 목적으로 사용될 수 있으며, 그렇게 함으로써 도면에서 도시된 대로 하나의 소자 또는 특징과 다른 소자(들) 또는 특징(들)과의 관계를 설명한다. 이는 도면 상에서 하나의 구성 요소의 다른 구성 요소에 대한 관계를 나타내는 데에 사용될 뿐, 절대적인 위치를 의미하는 것은 아니다. 예를 들어, 도면에 도시된 장치가 뒤집히면, 다른 소자들 또는 특징들의 "아래"에 위치하는 것으로 묘사된 소자들은 다른 소자들 또는 특징들의 "위"의 방향에 위치한다. 따라서, 일 실시예에서 "아래" 라는 용어는 위와 아래의 양방향을 포함할 수 있다. 뿐만 아니라, 장치는 그 외의 다른 방향일 수 있다 (예를 들어, 90도 회전된 혹은 다른 방향에서), 그리고, 여기에서 사용되는 그런 공간적으로 상대적인 용어들은 그에 따라 해석된다.Spatially relative terms such as "below", "above", etc. can be used for the purpose of description, thereby explaining the relationship of one element or feature to another element (s) or feature (s) as shown in the figure do. This is only used to show the relationship of one component to another component in the drawing, and does not mean an absolute position. For example, when the device shown in the figure is turned over, elements depicted as being “below” other elements or features are positioned in a direction “above” the other elements or features. Thus, in one embodiment, the term "below" can include both the top and bottom. In addition, the device may be in other directions (eg, rotated 90 degrees or in other directions), and such spatially relative terms used herein are interpreted accordingly.
여기에서 사용된 용어는 특정한 실시예들을 설명하는 목적이고 제한하기 위한 목적이 아니다. 명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함"한다 고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있는 것을 의미한다. 다른 정의가 없는 한, 여기에 사용된 용어들은 본 발명이 속하는 분야에서 통상적인 지식을 가진 자에게 일반적으로 이해되는 것과 같은 의미를 갖는다.The terminology used herein is for the purpose of describing specific embodiments and not for limitation. Throughout the specification, when a part “includes” a certain component, this means that other components may be further included rather than excluding other components unless specifically stated to the contrary. Unless otherwise defined, terms used herein have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains.
도 1은 본 발명의 일 실시예에 따른 뉴럴 네트워크를 개념적으로 도시한 블록도이다.1 is a block diagram conceptually showing a neural network according to an embodiment of the present invention.
도 1을 참조하면, 본 발명의 일 실시예에 따른 뉴럴 네트워크(neural network)는 입력 뉴런(10), 출력 뉴런(20), 및 가중치 소자(30)를 포함한다. 시냅스(30) 소자는 입력 뉴런(10)으로부터 수평으로 연장하는 로우 라인(R)(row lines) 및 출력 뉴런(20)으로부터 수직으로 연장하는 컬럼 라인(C)(column lines)의 교차점에 배치될 수 있다. 설명의 편의를 위해 도 1에는 예시적으로 각각 네 개의 입력 뉴런(10) 및 출력 뉴런(20)이 도시되었으나, 본 발명은 이에 한정되지 않는다.Referring to FIG. 1, a neural network according to an embodiment of the present invention includes an input neuron 10, an output neuron 20, and a weighting element 30. The synapse 30 element is to be arranged at the intersection of row lines (R) extending horizontally from the input neuron 10 and column lines (C) extending vertically from the output neuron 20. You can. For convenience of description, FIG. 1 illustratively shows four input neurons 10 and output neurons 20, respectively, but the present invention is not limited thereto.
입력 뉴런(10)은 학습 모드(learning mode), 리셋 모드(reset mode), 보정 또는 읽기 모드(reading mode)에서 로우 라인(R)을 통하여 가중치 소자(30)로 전기적 펄스들(pulses)을 전송할 수 있다.The input neuron 10 transmits electrical pulses to the weight element 30 through the low line R in a learning mode, a reset mode, a correction or reading mode. You can.
출력 뉴런(20)은 학습 모드 또는 리셋 모드 또는 보정 시 컬럼 라인(C)을 통하여 가중치 소자(30)로 전기적 펄스를 전송할 수 있고, 및 읽기 모드에서 컬럼 라인(C)을 통하여 가중치 소자(30)로부터 전기적 펄스를 수신할 수 있다.The output neuron 20 may transmit electrical pulses to the weighting element 30 through the column line C during learning mode or reset mode or correction, and the weighting element 30 through the column line C in the read mode. Can receive electrical pulses.
가중치 소자(30)는 멀티레벨(multi-level) 값을 가질 수 있다. 실시예로서, 가중치 소자(30)는 플로팅게이트 트랜지스터들의 write/erase 여부에 따라 그 값을 달리한다. 가중치 소자(30)에 연결된 플로팅게이트 트랜지스터가 erase 상태일 때에는 트랜지스터 전류의 흐름이 원활하므로 연결된 커패시터들의 충방전 동작이 가능하며, write 상태일 때에는 플로팅게이트 트랜지스터 전류의 흐름을 막으므로 연결된 커패시터들의 충방전 동작이 불가능하다. 이때 erase 상태인 플로팅게이트 트랜지스터들의 수에 비례하여 가중치 소자(30)의 커패시터 값이 결정된다. 즉, 가중치 소자(30)에 연결된 플로팅게이트 트랜지스터의 수 만큼 멀티레벨을 가질 수 있다. 전압 펄스를 입력 신호로 인가하면 erase 상태인 플로팅게이트 트랜지스터에 연결된 커패시터만 충전 및 방전하며 이 전하들을 모아 전압으로 변환하여 출력 신호로 사용할 수 있다. 본 발명의 일 실시예에 따르면, 출력 신호를 시냅틱 가중치로 활용할 수 있다.The weight element 30 may have a multi-level value. As an embodiment, the weight element 30 varies its value according to whether write / erase of floating gate transistors is performed. When the floating gate transistor connected to the weight element 30 is in the erase state, the flow of the transistor current is smooth, so the charge and discharge operation of the connected capacitors is possible. In the write state, the flow of the floating gate transistor current is prevented, so the charge and discharge of the connected capacitors is prevented. Operation is impossible. At this time, the capacitor value of the weight element 30 is determined in proportion to the number of floating gate transistors in the erased state. That is, the multilevel can be as many as the number of floating gate transistors connected to the weight element 30. When a voltage pulse is applied as an input signal, only the capacitor connected to the floating gate transistor in an erased state is charged and discharged, and these charges can be collected and converted into a voltage to be used as an output signal. According to an embodiment of the present invention, an output signal may be used as a synaptic weight.
도 2는 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 사시도이다. 도 3은 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 단면도이다.2 is a perspective view schematically showing the structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention. 3 is a cross-sectional view schematically showing a structure of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
도 2 및 도 3을 참조하면, 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자(30)는 제1 방향으로 연장된 수평 도전 라인(111)들과 수평 도전 라인(111)들 사이에 위치한 수평 절연 라인(113)들을 포함하는 단위 수평 적층 구조체(110), 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층(121) 및 수직 유전체층(123)을 포함하는 단위 수직 적층 구조체(120)를 포함한다. 단위 수평 적층 구조체(110)의 일 측면을 따라 수직 유전체층(123)과 수직 도전층(121)이 교대로 형성된 구조를 단위 수직 적층 구조체(120)로 정의한다. 실시예로서, 가중치 소자(30)의 제조는 낸드(NAND) 공정을 적용할 수 있다.2 and 3, the cross-point capacitor-based weighting element 30 according to an embodiment of the present invention includes horizontal conductive lines 111 and horizontal conductive lines 111 extending in a first direction. Unit horizontal stacked structure 110 including horizontal insulating lines 113 located therebetween, vertical stacked structure including vertical conductive layer 121 and vertical dielectric layer 123 alternately positioned in an orthogonal direction to the second direction 120. A structure in which the vertical dielectric layer 123 and the vertical conductive layer 121 are alternately formed along one side of the unit horizontal stacked structure 110 is defined as the unit vertical stacked structure 120. As an embodiment, the manufacturing of the weight element 30 may apply a NAND process.
수평 도전 라인(111)은 폴리 실리콘(Poly silicon)일 수 있다. 실시예로서, 수평 도전 라인(111)은 도전체로 기능하기 위하여 높은 도펀트 농도를 가질 수 있다. 실시예로서, 수평 도전 라인(111)은 워드 라인일 수 있다.The horizontal conductive line 111 may be polysilicon. As an embodiment, the horizontal conductive line 111 may have a high dopant concentration to function as a conductor. As an embodiment, the horizontal conductive line 111 may be a word line.
수평 절연 라인(113)은 복수 개의 수평 도전 라인(111)들 사이를 절연한다. 실시예로서, 수평 절연 라인(113)은 SiO2, Si3N4, 금속 산화물, 금속 질화물 및 고분자 물질막 중 적어도 어느 하나를 포함할 수 있으나, 본 발명은 이에 한정되지 않는다. The horizontal insulation line 113 insulates the plurality of horizontal conductive lines 111. As an embodiment, the horizontal insulation line 113 may include at least one of SiO2, Si3N4, metal oxide, metal nitride, and a polymer material film, but the present invention is not limited thereto.
단위 수직 적층 구조체(120)는 상기 복수 개의 단위 수평 적층 구조체(110) 사이에 위치할 수 있다. The unit vertical stacked structure 120 may be located between the plurality of unit horizontal stacked structures 110.
수직 도전층(121)은 제2 방향과 직교를 이루며 형성된다. 실시예로서, 수직 도전층(121)은 폴리 실리콘일 수 있으나 이에 한정되는 것은 아니다. 수직 도전층(121)과 수평 도전 라인(111)으로 커패시터를 구성하기 위하여 수직 도전층(121)과 수평 도전 라인(111) 사이에 수직 유전체층(123)이 형성된다. 실시예로서, 수직 도전층(121)은 플레이트 일 수 있고, 수직 유전체층(123)은 커패시터의 축전 용량을 향상시키면서 효과적으로 전극 사이를 절연하기 위한 유전물질이 이용될 수 있다. 실시예로서, 수직 유전체층(123)은 SiO2, HfO2, ZrO2, Si3N4 및 Al2O3 중 적어도 하나를 포함할 수 있다.The vertical conductive layer 121 is formed perpendicular to the second direction. As an embodiment, the vertical conductive layer 121 may be polysilicon, but is not limited thereto. A vertical dielectric layer 123 is formed between the vertical conductive layer 121 and the horizontal conductive line 111 to form a capacitor with the vertical conductive layer 121 and the horizontal conductive line 111. As an embodiment, the vertical conductive layer 121 may be a plate, and the vertical dielectric layer 123 may use a dielectric material to effectively insulate between electrodes while improving the capacitor's power storage capacity. As an embodiment, the vertical dielectric layer 123 may include at least one of SiO2, HfO2, ZrO2, Si3N4, and Al2O3.
본 발명의 일 실시예에 따르면, 수평 도전 라인(111)들과 수직 도전층(121)으로 형성된 커패시터에 축적된 전하를 시냅틱 가중치(synaptic weight)로 활용한다. 실시예로서, 수평 도전 라인(111)과 전기적으로 접속되는 라인을 통해 커패시터에 저장된 전하량을 출력할 수 있다. According to an embodiment of the present invention, the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive layer 121 is used as a synaptic weight. As an embodiment, the amount of charge stored in the capacitor may be output through a line electrically connected to the horizontal conductive line 111.
본 발명의 다른 실시예에 따르면, 크로스-포인트 커패시터 기반의 가중치 소자(30)는 제1 단위 수평 적층 구조체(110)와 제2 단위 수평 적층 구조체(110), 및 단위 수직 적층 구조체(120)를 포함하는 가중치 그룹과 수직 절연층(133)을 포함할 수 있다. According to another embodiment of the present invention, the cross-point capacitor-based weighting element 30 includes a first unit horizontal stacked structure 110, a second unit horizontal stacked structure 110, and a unit vertical stacked structure 120. The weight group and the vertical insulating layer 133 may be included.
제1 단위 수평 적층 구조체(110)와 제2 단위 수평 적층 구조체(110)는 제1 방향으로 연장된 수평 도전 라인(111)들, 및 수평 도전 라인(111)들 사이에 제3 방향으로 수평 도전 라인(111)들과 교대로 위치하는 수평 절연 라인(113)들을 포함할 수 있다.The first unit horizontal stacked structure 110 and the second unit horizontal stacked structure 110 are horizontally conductive in the third direction between the horizontal conductive lines 111 extending in the first direction and the horizontal conductive lines 111. It may include horizontal insulation lines 113 alternately positioned with the lines 111.
단위 수직 적층 구조체(120)는 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층(121) 및 수직 유전체층(123)을 포함할 수 있다.The unit vertical stacked structure 120 may include a vertical conductive layer 121 and a vertical dielectric layer 123 alternately positioned in an orthogonal direction to the second direction.
수직 절연층(133)은 복수 개의 가중치 그룹 사이에 위치할 수 있다.The vertical insulating layer 133 may be positioned between a plurality of weight groups.
본 발명의 다른 실시예에 따르면, 수평 도전 라인(111)들과 수직 도전층(121)으로 형성된 커패시터에 축적된 전하를 시냅틱 가중치(synaptic weight)로 활용한다. 실시예로서, 수직 도전층(121)의 왼쪽에 위치하는 수평 도전 라인(111) 그룹과 오른쪽 수평 도전 라인(111) 그룹을 각각 positive 가중치, negative 가중치로 정의하여 활용할 수 있다.According to another embodiment of the present invention, the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive layer 121 is used as a synaptic weight. As an embodiment, a group of horizontal conductive lines 111 and a group of right horizontal conductive lines 111 located on the left side of the vertical conductive layer 121 may be defined and used as positive and negative weights, respectively.
도 2를 참조하면, 본 발명의 일 실시예에 따른 가중치 소자(30)를 시냅틱 가중치로 사용하기 위해 적층 크로스-포인트 커패시터 셀에 전압을 인가한다. 온-칩 인공지능 학습(On-Chip learning)에 의한 입력 신호는 일정 시간 동안에 입력되는 전압 펄스의 수를 이용하거나 전압 펄스의 전압 크기를 이용하여 다중 값을 크로스-포인트 커패시터 기반의 가중치 소자에 입력할 수 있다. 실시예로서, 선택 트랜지스터(S11, S14, S1j)로 각각의 수평 도전 라인(111)들, 즉 워드 라인을 선택한 후 공통 전극인 수직 도전층(121)에 전압을 인가한다. Referring to FIG. 2, a voltage is applied to a stacked cross-point capacitor cell to use the weighting element 30 according to an embodiment of the present invention as a synaptic weight. The input signal by on-chip AI learning uses the number of voltage pulses input over a period of time or inputs multiple values to the weighting device based on the cross-point capacitor using the voltage magnitude of the voltage pulse. can do. As an embodiment, voltages are applied to the vertical conductive layer 121, which is a common electrode, after selecting each of the horizontal conductive lines 111, that is, the word line, with the selection transistors S11, S14, and S1j.
수직 도전층(121)에 인가하는 전압 펄스는 입력(input) 상황에 맞추어 펄스 수 또는 펄스 전압의 크기를 조절할 수 있다. 가중치 값에 대응하는 워드 라인 수는 입력 펄스 수 또는 입력 전압과는 독립적으로 선택할 수 있다.The voltage pulse applied to the vertical conductive layer 121 may adjust the number of pulses or the magnitude of the pulse voltage according to an input situation. The number of word lines corresponding to the weight value can be selected independently of the number of input pulses or the input voltage.
수직 도전층(121)과 수평 도전 라인(111)들이 교차하는 크로스 포인트는 커패시터가 형성되고 입력 전압에 의해 전하가 축적되게 된다. 축적된 전하는 합산되어 적분기(integrator)로 보내지고 적분기에서는 전압으로 변환된다. 전압으로 변환된 출력 신호는 문턱 전압 크기 이상이 될 때 다음 레이어를 구성하는 입력 노드(input node)로 전달되게 된다.The cross point where the vertical conductive layer 121 and the horizontal conductive lines 111 intersect is formed with a capacitor and charge is accumulated by the input voltage. The accumulated charge is summed and sent to the integrator, where it is converted into a voltage. When the output signal converted to voltage is greater than or equal to the threshold voltage level, it is transmitted to an input node constituting the next layer.
도 4는 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 동작을 개략적으로 나타내는 회로도이다. 4 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to an embodiment of the present invention.
도 4를 참조하면, 다중 가중치를 구성하기 위해 크로스-포인트 커패시터 셀에서 워드 라인의 수를 선택하고 커패시터의 공통 전극에 Vpp 전압을 인가함으로써 선택 트랜지스터 쪽으로 전하들이 나오도록 한다. 커패시터에 저장되는 전하량(Q)은 커패시터의 축전 용량(C)과 인가되는 전압(V)에 비례한다. 이러한 원리를 이용하여 크로스-포인트 노드의 도전 경로 수에 따라 결정되는 여러 개의 커패시터를 사용함으로써 입력 신호에 따른 출력 신호가 선형적인(linear) 값을 가질 수 있다.Referring to FIG. 4, in order to configure multiple weights, charges are drawn toward the select transistor by selecting the number of word lines in the cross-point capacitor cell and applying a Vpp voltage to the common electrode of the capacitor. The amount of charge Q stored in the capacitor is proportional to the capacitor's power storage capacity C and the applied voltage V. Using this principle, the output signal according to the input signal may have a linear value by using several capacitors determined according to the number of conductive paths of the cross-point node.
시냅틱 가중치는 커패시턴스(capacitance)로 정의되고 출력(output)은 워드 라인에 연결된 n개의 커패시터에서 방전되는 전하(Q=nCVpp)로 결정된다. 실시예로서, 가중치 레벨은 워드 라인을 선택한 수로 결정될 수 있다.The synaptic weight is defined as capacitance, and the output is determined by the charge (Q = nCVpp) discharged from n capacitors connected to the word line. As an embodiment, the weight level may be determined by a selected number of word lines.
본 발명의 일 실시예에 따르면, 뉴럴 네트워크로 학습 혹은 훈련을 수행할 때 입력 노드로 전압 펄스(voltage pulse)가 인가되고 각각의 가중치의 크기에 따라 커패시터 셀들의 워드 라인을 선택한다. 실시예로서, 가중치가 1이면 워드 라인 한 개를 선택하고 가중치가 5이면 다섯 개의 워드 라인을 선택한다. 각 가중치를 무작위로(randomly), 동시에(simultaneously), 그리고 독립적(independently)으로 직접(directly) 선택함으로써 입력에 대한 출력이 매트릭스로 발생하도록 한다.According to an embodiment of the present invention, when performing learning or training with a neural network, a voltage pulse is applied to an input node and a word line of capacitor cells is selected according to the magnitude of each weight. As an embodiment, if the weight is 1, one word line is selected, and if the weight is 5, five word lines are selected. By selecting each weight randomly, simultaneously, and independently directly, the output for the input is generated in a matrix.
단위 가중치는 일정한 수의 워드 라인이 있는 커패시터 셀 블록으로 구성할 수 있다. 실시예로서, 선택할 수 있는 워드 라인의 최대 개수가 최대 다이내믹 레인지(dynamic range)가 될 수 있다. 각 가중치에서 방전되는 전하의 합은 적분기로 축적하여 전압으로 변환할 수 있다.The unit weight may consist of a capacitor cell block with a certain number of word lines. As an embodiment, the maximum number of selectable word lines may be the maximum dynamic range. The sum of the charges discharged at each weight can be accumulated into an integrator and converted into a voltage.
본 발명의 일 실시예에 따르면, 학습이나 training 후 최종으로 결정된 워드 라인 선택 개수의 정보는 외부 저장장치에 저장할 수 있다. 뉴럴 네트워크 회로 안에 저장기능을 장착하고자 할 때에는 선택 트랜지스터로서 플로팅 게이트 트랜지스터를 사용할 수 있다. 실시예로서, 역전파(back-propagation) 등의 알고리즘을 사용하면서 트랜스포즈 가중치 매트릭스(transpose weight matrix)를 이용하여 학습 시 가중치의 보정량을 구하고, 얻어진 가중치의 보정량에 비례하여 워드 라인을 선택할 수 있다.According to an embodiment of the present invention, information on the number of word line selections finally determined after learning or training may be stored in an external storage device. When a storage function is to be installed in a neural network circuit, a floating gate transistor can be used as a selection transistor. As an embodiment, while using an algorithm such as back-propagation, a correction amount of weight is calculated during learning using a transpose weight matrix, and a word line can be selected in proportion to the correction amount of the obtained weight. .
도 5는 본 발명의 다른 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조를 개략적으로 보여주는 사시도이다5 is a perspective view schematically showing a structure of a cross-point capacitor-based weighting device according to another embodiment of the present invention
도 5를 참조하면, 본 발명의 다른 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자(30)는 제1 방향으로 연장된 수평 도전 라인(111)들과 수평 도전 라인(111)들 사이에 위치한 수평 절연 라인(113)들을 포함하는 단위 수평 적층 구조체(110), 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전 라인(122), 수직 절연 라인(124) 및 수직 유전체층(123)을 포함하는 단위 수직 적층 구조체(120)를 포함한다. 실시예로서, 가중치 소자(30)의 제조는 낸드(NAND) 공정을 적용할 수 있다.Referring to FIG. 5, a cross-point capacitor-based weighting element 30 according to another embodiment of the present invention is located between horizontal conductive lines 111 and horizontal conductive lines 111 extending in a first direction. A unit horizontal stacked structure 110 including horizontal insulation lines 113, a vertical conductive line 122 alternately positioned in an orthogonal direction to the second direction, a vertical insulation line 124 and a vertical dielectric layer 123 The unit vertical stack structure 120 is included. As an embodiment, the manufacturing of the weight element 30 may apply a NAND process.
수평 절연 라인(113)은 복수 개의 수평 도전 라인(111)들 사이를 절연한다. 실시예로서, 수평 절연 라인(113)은 SiO2, Si3N4, 금속 산화물, 금속 질화물 및 고분자 물질막 중 적어도 어느 하나를 포함할 수 있으나, 본 발명은 이에 한정되지 않는다. The horizontal insulation line 113 insulates the plurality of horizontal conductive lines 111. As an embodiment, the horizontal insulation line 113 may include at least one of SiO2, Si3N4, metal oxide, metal nitride, and a polymer material film, but the present invention is not limited thereto.
단위 수직 적층 구조체(120)는 상기 복수 개의 단위 수평 적층 구조체(110) 사이에 위치할 수 있다. The unit vertical stacked structure 120 may be located between the plurality of unit horizontal stacked structures 110.
수직 도전 라인(122)은 제2 방향과 직교를 이루며 형성된다. 실시예로서, 수직 도전 라인(122)은 폴리 실리콘일 수 있으나 이에 한정되는 것은 아니다. 수직 도전 라인(122)과 수평 도전 라인(111)으로 커패시터를 구성하기 위하여 수직 도전 라인(121)과 수평 도전 라인(111) 사이에 수직 유전체층(123)이 형성되고, 수직 도전 라인(122)들 사이를 절연하기 위하여 수직 절연 라인(124)이 형성된다. 단위 수평 적층 구조체(110)의 일 측면을 따라 수직 유전체층(123)과 수직 도전 라인(122) 및 수직 절연 라인(124)이 교대로 형성된 구조를 단위 수직 적층 구조체(120)로 정의한다. 실시예로서, 수직 도전 라인(122)은 비트 라인일 수 있고, 수직 유전체층(123)은 커패시터의 축전 용량을 향상시키면서 효과적으로 전극 사이를 절연하기 위한 유전물질이 이용될 수 있다. 실시예로서, 수직 유전체층(123)은 SiO2, HfO2, ZrO2, Si3N4 및 Al2O3 중 적어도 하나를 포함할 수 있다.The vertical conductive line 122 is formed perpendicular to the second direction. As an embodiment, the vertical conductive line 122 may be polysilicon, but is not limited thereto. A vertical dielectric layer 123 is formed between the vertical conductive line 121 and the horizontal conductive line 111 to form a capacitor with the vertical conductive line 122 and the horizontal conductive line 111, and the vertical conductive lines 122 Vertical insulation lines 124 are formed to insulate between them. A structure in which the vertical dielectric layer 123 and the vertical conductive line 122 and the vertical insulating line 124 are alternately formed along one side of the unit horizontal stacked structure 110 is defined as the unit vertical stacked structure 120. As an embodiment, the vertical conductive line 122 may be a bit line, and the vertical dielectric layer 123 may use a dielectric material to effectively insulate between electrodes while improving the capacitor's power storage capacity. As an embodiment, the vertical dielectric layer 123 may include at least one of SiO2, HfO2, ZrO2, Si3N4, and Al2O3.
본 발명의 다른 실시예에 따르면, 수평 도전 라인(111)들과 수직 도전 라인(122)으로 형성된 커패시터에 축적된 전하를 시냅틱 가중치(synaptic weight)로 활용한다. 실시예로서, 수평 도전 라인(111)과 전기적으로 접속되는 라인을 통해 커패시터에 저장된 전하량을 출력할 수 있다. According to another embodiment of the present invention, the charge accumulated in the capacitor formed of the horizontal conductive lines 111 and the vertical conductive lines 122 is used as a synaptic weight. As an embodiment, the amount of charge stored in the capacitor may be output through a line electrically connected to the horizontal conductive line 111.
본 발명의 다른 실시예에 따르면, 가중치 소자(30)는 도 2 및 도 3의 수직 도전층(121) 대신 수직 도전 라인(122)을 포함한다. 따라서, 수평 도전 라인(111)들과 수직 도전 라인(122)으로 형성된 커패시터 각각에 축적된 전하를 시냅틱 가중치(synaptic weight)로 활용할 수 있어, 같은 크기의 수직 도전층을 포함하는 가중치 소자와 비교할 때 다수의 멀티레벨 시냅틱 가중치를 표현할 수 있다. According to another embodiment of the present invention, the weight element 30 includes a vertical conductive line 122 instead of the vertical conductive layer 121 of FIGS. 2 and 3. Therefore, the charge accumulated in each of the capacitors formed of the horizontal conductive lines 111 and the vertical conductive lines 122 can be used as a synaptic weight, when compared with a weight element including a vertical conductive layer of the same size. Multiple multilevel synaptic weights can be expressed.
수직 도전 라인(122)과 수평 도전 라인(111)들이 교차하는 크로스 포인트는 커패시터가 형성되고 전하가 축적되게 된다. 축적된 전하는 방전 후에 적분기(integrator)로 보내지고 적분기에서는 합산되는 동시에 전압으로 변환된다. 전압으로 변환된 출력 신호는 문턱 전압 크기 이상이 될 때 다음 레이어를 구성하는 입력 노드(input node)로 전달되게 된다.The cross point where the vertical conductive line 122 and the horizontal conductive line 111 intersect, a capacitor is formed and charge is accumulated. Accumulated charges are sent to the integrator after discharge, which are summed at the same time and converted into voltage. When the output signal converted to voltage is greater than or equal to the threshold voltage level, it is transmitted to an input node constituting the next layer.
본 발명의 일 실시예에 따르면, 학습이나 training 후 최종으로 결정된 워드 라인 선택 개수의 정보는 외부 저장장치에 저장될 수 있다. 뉴럴 네트워크 회로 안에 저장기능을 장착하고자 할 때에는 선택 트랜지스터로서 플로팅 게이트 트랜지스터를 사용할 수 있다. 실시예로서, 역전파(back-propagation) 등의 알고리즘을 사용하면서 트랜스포즈 가중치 매트릭스(transpose weight matrix)를 이용하여 학습 시 가중치의 보정량을 구하고, 얻어진 가중치의 보정량에 비례하여 워드 라인을 선택할 수 있다.According to an embodiment of the present invention, information on the number of word line selections finally determined after learning or training may be stored in an external storage device. When a storage function is to be installed in a neural network circuit, a floating gate transistor can be used as a selection transistor. As an embodiment, while using an algorithm such as back-propagation, a correction amount of weight is calculated during learning using a transpose weight matrix, and a word line can be selected in proportion to the correction amount of the obtained weight. .
도 6은 본 발명의 다른 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 동작을 개략적으로 나타내는 회로도이다. 6 is a circuit diagram schematically showing the operation of a cross-point capacitor-based weighting device according to another embodiment of the present invention.
도 6을 참조하면, 본 발명의 다른 실시예에 따른 가중치 소자는 낸드 플래시를 활용할 수 있다. 패스 트랜지스터(Pass transistor)와 디코더는 낸드 플래시를 저장장치로 사용할 때 필요하므로 시냅틱 소자로 사용할 때에는 작동하지 않는다. 실시예로서, 낸드 플래시를 시냅틱 소자로 사용할 때는 모든 낸드 셀을 charging 혹은 discharging 상태로 하고 게이트 옥사이드(gate oxide)의 커패시턴스를 가중치로 이용할 수 있다. 플로팅 게이트 트랜지스터는 discharging 되어 있는 것이 바람직할 수 있다.Referring to FIG. 6, a NAND flash may be used as a weighting element according to another embodiment of the present invention. Pass transistors and decoders are required when using NAND flash as a storage device, so they do not work when used as a synaptic element. As an embodiment, when using a NAND flash as a synaptic device, all NAND cells may be charged or discharging, and the capacitance of the gate oxide may be used as a weight. It may be desirable that the floating gate transistor is discharging.
본 발명의 다른 실시예에 따른 가중치 소자를 동작하기 위해 입력 전압 펄스는 소스 라인으로 인가되고, 출력 전하는 워드 라인으로 방전된다. 실시예로서, 워드 라인에 선택 트랜지스터 또는 플로팅 게이트 트랜지스터를 부착하고 저장 기능을 수행하게 할 수 있다. 다른 실시예로서, 플로팅 게이트 트랜지스터를 패스 트랜지스터 및 디코더 반대편에 배치하여 낸드 플래시를 저장장치/가중치 소자 겸용으로 사용할 수 있다.In order to operate the weighting element according to another embodiment of the present invention, the input voltage pulse is applied to the source line, and the output charge is discharged to the word line. As an embodiment, a selection transistor or a floating gate transistor may be attached to a word line and a storage function may be performed. As another embodiment, a floating gate transistor may be disposed opposite the pass transistor and the decoder to use NAND flash as a storage / weighting element.
전술한 바와 같은 본 발명의 실시예들에 따르면, 본 발명의 일 실시예에 따른 크로스-포인트 커패시터 기반의 가중치 소자의 구조 및 이를 이용한 뉴럴 네트워크는 수직 적층형 크로스-포인트 커패시터 셀을 이용한 선형적인 다중 시냅틱 가중치를 가짐으로써, 학습 효율을 증가시킬 수 있다. 또한, 커패시터를 가중치로 사용함으로써 저항 가중치의 저항 값을 변화시켜 이에 비례하는 전류를 출력 신호로 사용하는 전도도 기반의(conductance-based) 가중치 소자에 비하여 전력 소모를 크게 감소 시킬 수 있다. 또한, CMOS 기술을 사용하되 기존의 CMOS 소자의 작동 방식과 설계를 변형함으로써 시스템 크기를 줄이고 제품 공정 적용이 용이하게 할 수 있다.According to the embodiments of the present invention as described above, the structure of the weighting device based on the cross-point capacitor according to an embodiment of the present invention and the neural network using the same are linear multiple synaptics using vertical stacked cross-point capacitor cells By having a weight, learning efficiency can be increased. In addition, by using a capacitor as a weight, the resistance value of the resistance weight can be changed to significantly reduce power consumption compared to a conductivity-based weighting device using a current proportional to this as an output signal. In addition, it is possible to reduce the system size and facilitate application of the product process by using CMOS technology, but by modifying the operation method and design of the existing CMOS device.
이상과 같이 본 발명에서는 구체적인 구성 요소 등과 같은 특정 사항들과 한정된 실시예 및 도면에 의해 설명되었으나 이는 본 발명의 보다 전반적인 이해를 돕기 위해서 제공된 것일 뿐, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상적인 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, the present invention has been described by specific matters such as specific components and limited embodiments and drawings, but is provided to help a more comprehensive understanding of the present invention, and the present invention is not limited to the above embodiments , Anyone having ordinary knowledge in the field to which the present invention pertains can make various modifications and variations from these descriptions.
따라서, 본 발명의 사상은 설명된 실시예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐 아니라 이 특허청구범위와 균등하거나 등가적 변형이 있는 모든 것들은 본 발명 사상의 범주에 속한다고 할 것이다.Therefore, the spirit of the present invention is limited to the described embodiments, and should not be determined, and all claims that are equivalent to or equivalent to the claims, as well as the claims described below, will belong to the scope of the spirit of the present invention. .

Claims (20)

  1. 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인층들을 포함하는 단위 수평 적층 구조체; 및 A unit horizontal stacked structure comprising horizontal conductive lines extending in a first direction, and horizontal insulating line layers alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines; And
    제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하는 단위 수직 적층 구조체를 포함하고,A unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned in an orthogonal direction to the second direction, and
    상기 수평 도전 라인들, 상기 수직 도전층, 및 상기 수직 유전체층으로 형성된 커패시터를 시냅틱 가중치(synaptic weight)로 활용하는 크로스-포인트 커패시터 기반의 가중치 소자.A cross-point capacitor-based weighting element that utilizes the capacitor formed of the horizontal conductive lines, the vertical conductive layer, and the vertical dielectric layer as a synaptic weight.
  2. 제 1항에 있어서, 상기 커패시터에 충전된 후 방전되는 전하를 상기 시냅틱 가중치로 활용하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor-based weighting device of claim 1, wherein a charge discharged after being charged in the capacitor is used as the synaptic weight.
  3. 제 2항에 있어서, 상기 커패시터에 충전된 후 방전되는 전하는 입력 전압 펄스(input voltage pulse)에 비례하는 크로스-포인트 커패시터 기반의 가중치 소자.3. The cross-point capacitor-based weighting device according to claim 2, wherein the charge that is discharged after being charged in the capacitor is proportional to an input voltage pulse.
  4. 제 2항에 있어서, 상기 커패시터에 충전된 후 방전되는 전하는 상기 수평 도전 라인들에 대응하는 워드 라인(word line)이 선택된 개수와 비례하는 크로스-포인트 커패시터 기반의 가중치 소자.3. The cross-point capacitor-based weighting device according to claim 2, wherein a charge that is discharged after being charged in the capacitor is proportional to a selected number of word lines corresponding to the horizontal conductive lines.
  5. 제 4항에 있어서, The method of claim 4,
    상기 워드 라인 선택 정보를 저장하기 위한 선택 트랜지스터를 더 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.A cross-point capacitor-based weighting device further comprising a selection transistor for storing the word line selection information.
  6. 제 5항에 있어서, The method of claim 5,
    상기 선택 트랜지스터는 플로팅 게이트(floating gate) 트랜지스터를 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.The select transistor is a cross-point capacitor-based weighting device comprising a floating gate transistor.
  7. 제 1항에 있어서, 상기 단위 수직 적층 구조체는 상기 복수 개의 단위 수평 적층 구조체 사이에 위치하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor-based weighting device of claim 1, wherein the unit vertical stacked structure is located between the plurality of unit horizontal stacked structures.
  8. 제 1항에 있어서, 상기 수직 도전층은 수직 도전 라인 및 수직 절연 라인을 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor based weighting device of claim 1, wherein the vertical conductive layer includes a vertical conductive line and a vertical insulating line.
  9. 제 8항에 있어서, 상기 커패시터는 상기 수평 도전 라인들, 상기 수직 도전 라인, 및 상기 수직 유전체층으로 형성되는 크로스-포인트 커패시터 기반의 가중치 소자.The weighting device of claim 8, wherein the capacitor is formed of the horizontal conductive lines, the vertical conductive line, and the vertical dielectric layer.
  10. 제 1항에 있어서, 상기 수평 도전 라인 및 상기 수직 도전층은 폴리 실리콘을 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor based weighting device of claim 1, wherein the horizontal conductive line and the vertical conductive layer comprise polysilicon.
  11. 제 1항에 있어서, 상기 수평 절연 라인은 SiO2를 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor based weighting device of claim 1, wherein the horizontal insulation line comprises SiO2.
  12. 제 1항에 있어서, 상기 수직 유전체층은 SiO2, HfO2, ZrO2, Si3N4 및 Al2O3 중 적어도 하나를 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.The cross-point capacitor based weighting device of claim 1, wherein the vertical dielectric layer comprises at least one of SiO2, HfO2, ZrO2, Si3N4, and Al2O3.
  13. 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인들을 포함하는 제1 수평 적층 구조체와 제2 수평 적층 구조체, 및 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하고, 상기 제1 수평 적층 구조체와 상기 제2 수평 적층 구조체 사이에 위치하는 단위 수직 적층 구조체를 포함하는 가중치 그룹; 및A first horizontal stacked structure and a second horizontal stacked structure comprising horizontal conductive lines extending in a first direction, and horizontal insulating lines alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines. , And a weight group including a vertical conductive layer and a vertical dielectric layer, which are alternately orthogonal to the second direction, and a unit vertical stacked structure positioned between the first horizontal stacked structure and the second horizontal stacked structure; And
    상기 복수 개의 가중치 그룹 사이에 위치하는 수직 절연층을 포함하고,It includes a vertical insulating layer located between the plurality of weight groups,
    상기 수평 도전 라인들, 상기 수직 도전층, 및 상기 수직 유전체층으로 형성된 커패시터를 시냅틱 가중치(synaptic weight)로 활용하는 크로스-포인트 커패시터 기반의 가중치 소자.A cross-point capacitor-based weighting element that utilizes the capacitor formed of the horizontal conductive lines, the vertical conductive layer, and the vertical dielectric layer as a synaptic weight.
  14. 제 13항에 있어서, 상기 수직 절연층은 SiO2를 포함하는 크로스-포인트 커패시터 기반의 가중치 소자.14. The cross-point capacitor based weighting device of claim 13, wherein the vertical insulating layer comprises SiO2.
  15. 제1 방향으로 연장된 수평 도전 라인들, 및 상기 수평 도전 라인들 사이에 제3 방향으로 상기 수평 도전 라인들과 교대로 위치하는 수평 절연 라인들을 포함하는 단위 수평 적층 구조체; 및 제2 방향과 직교를 이루며 교대로 위치하는 수직 도전층 및 수직 유전체층을 포함하는 단위 수직 적층 구조체를 포함하고, 상기 수평 도전 라인들과 상기 수직 도전층으로 형성된 커패시터에 충전된 후 방전되는 전하를 시냅틱 가중치(synaptic weight)로 활용하는 가중치 소자를 포함하는 뉴럴 네트워크.A unit horizontal stacked structure including horizontal conductive lines extending in a first direction, and horizontal insulating lines alternately positioned with the horizontal conductive lines in a third direction between the horizontal conductive lines; And a unit vertical stacked structure including a vertical conductive layer and a vertical dielectric layer alternately positioned perpendicular to the second direction and charged in the capacitor formed of the horizontal conductive lines and the vertical conductive layer. A neural network including weighting elements utilized as synaptic weights.
  16. 제 15항에 있어서, 상기 커패시터에 충전된 후 방전되는 전하는 입력 전압 펄스에 비례하는 뉴럴 네트워크.16. The neural network of claim 15, wherein the charge that is discharged after being charged in the capacitor is proportional to the input voltage pulse.
  17. 제 15항에 있어서, 상기 커패시터에 충전된 후 방전되는 전하는 상기 수평 도전 라인들에 대응하는 워드 라인(word line)이 선택된 개수와 비례하는 뉴럴 네트워크.16. The neural network of claim 15, wherein charges discharged after being charged in the capacitor are proportional to a selected number of word lines corresponding to the horizontal conductive lines.
  18. 제 17항에 있어서, 상기 가중치 소자는, The method of claim 17, wherein the weight element,
    상기 워드 라인 선택 정보를 저장하기 위한 선택 트랜지스터를 더 포함하는 뉴럴 네트워크.A neural network further comprising a selection transistor for storing the word line selection information.
  19. 제 18항에 있어서, 상기 선택 트랜지스터는 플로팅 게이트(floating gate) 트랜지스터를 포함하는 뉴럴 네크워크.19. The neural network of claim 18, wherein the selection transistor comprises a floating gate transistor.
  20. 제 17항에 있어서,The method of claim 17,
    상기 워드 라인 선택 정보를 저장하기 위한 저장장치를 더 포함하는 뉴럴 네트워크.A neural network further comprising a storage device for storing the word line selection information.
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