WO2020082661A1

WO2020082661A1 - Display panel and display device

Info

Publication number: WO2020082661A1
Application number: PCT/CN2019/076892
Authority: WO
Inventors: 秦旭; 刘权; 张露
Original assignee: 昆山国显光电有限公司
Priority date: 2018-10-24
Filing date: 2019-03-04
Publication date: 2020-04-30
Also published as: CN109192073A

Abstract

A display panel (1) and a display device (3). The display panel (1) comprises: a first pixel region (11) and a second pixel region (12), which are adjacent, wherein the number of pixels (13) in each row in the first pixel region (11) is greater than the number of pixels (13) in each row in the second pixel region (12); first signal lines (14) extending in a row direction (X); and second signal lines (15) extending in the column direction (Y), wherein the degree of overlap of the first signal lines (14) and the second signal lines (15) in the second pixel region (12) is greater than or equal to the degree of overlap of the first signal lines (14) and the second signal lines (15) in the first pixel region (11), which can improve the display effect of the display panel.

Description

Display panel and display device

【Technical Field】

The present application relates to the technical field of display panels, in particular to a display panel and a display device.

【Background technique】

Electronic devices are usually equipped with a display screen as a human-computer interaction interface. With the popularity of electronic devices such as smart phones and tablet computers, display screens with rounded corners have been sought after by consumers. However, the display area at the rounded corners of the display screen is different from the load of the driving circuits in other areas, resulting in a problem of poor display on the display screen.

[Application content]

In view of this, the technical problem mainly solved by the present application is to provide a display panel and a display device, which can improve the display effect of the display panel.

To solve the above technical problems, a technical solution adopted by the present application is to provide a display panel including: a first pixel area and a second pixel area, the first pixel area being adjacent to the second pixel area; wherein, The number of pixels in each row in the first pixel area is greater than the number of pixels in each row in the second pixel area; the first signal line extending in the row direction; the second signal line extending in the column direction; wherein, the first signal in the second pixel area The overlapping degree of the line and the second signal line is greater than or equal to the overlapping degree of the first signal line and the second signal line of the first pixel area.

In an embodiment of the present application, the second pixel area is divided into a pixel arrangement area and a non-pixel arrangement area along the row direction; wherein, the overlapping degree of the first signal line and the second signal line in the pixel arrangement area Equal to the degree of overlap of the first signal line and the second signal line in the first pixel area; the degree of overlap of the first signal line and the second signal line in the non-pixel arrangement area is greater than or equal to that in the first pixel area The degree of overlap between the first signal line and the second signal line.

In an embodiment of the present application, the second signal line includes a data signal line and a power signal line; at least one of the first signal line, the data signal line, and the power signal line in the non-pixel arrangement area has a line width greater than Corresponding line widths of the first signal line, the data signal line, and the power signal line of the pixel arrangement area.

In an embodiment of the present application, the first signal line includes a first scan signal line and a second scan signal line electrically connected to the same scan circuit.

In an embodiment of the present application, the second signal line includes a data signal line and a power signal line; the portions of the first scan signal line and the second scan signal line in the non-pixel arrangement area are related to the data signal line and the power signal line The overlapping degree of is greater than or equal to the overlapping degree of the two in the pixel arrangement area with the data signal line and the power signal line.

In an embodiment of the present application, in the non-pixel arrangement area, the line width of the overlapping portion of the first scan signal line, the second scan signal line, the data signal line, and the power signal line is larger than the line width of the other portions.

In an embodiment of the present application, the first signal line includes a transmission signal line, and two or more transmission signal lines are electrically connected to the same transmission circuit.

In an embodiment of the present application, the second signal line includes a data signal line and a power signal line; the overlap of the portion of the emission signal line in the non-pixel arrangement area with the data signal line and the power signal line is greater than or equal to The overlapping degree of the portion in the pixel arrangement area with the data signal line and the power signal line.

In an embodiment of the present application, in the non-pixel arrangement area, the line width of the overlapping portion of the emission signal line, the data signal line, and the power signal line is larger than the line width of the other portions.

In order to solve the above technical problems, another technical solution adopted by the present application is to provide a display device including a driving circuit and a display panel. The driving circuit is coupled to the display panel and is used to drive the display panel to realize its display function.

In an embodiment of the present application, the display panel includes a first pixel area and a second pixel area, the first pixel area is adjacent to the second pixel area; the number of pixels in each row of the first pixel area is greater than that of each row in the second pixel area The number of pixels; the first signal line extending in the row direction; the second signal line extending in the column direction; the overlapping degree of the first signal line and the second signal line in the second pixel area is greater than or equal to that of the first pixel area The degree of overlap between the first signal line and the second signal line.

In an embodiment of the present application, the second pixel area is divided into a pixel arrangement area and a non-pixel arrangement area along the row direction; the overlapping degree of the first signal line and the second signal line in the pixel arrangement area is equal to the The overlapping degree of the first signal line and the second signal line in a pixel area; the overlapping degree of the first signal line and the second signal line in the non-pixel arrangement area is greater than or equal to the first in the first pixel area The degree of overlap between the signal line and the second signal line.

The beneficial effect of the present application is that the display panel provided by the present application includes a first signal line extending in a row direction and a second signal line extending in a column direction. The display panel further includes a first pixel area and a second pixel area, the first pixel area is adjacent to the second pixel area. The number of pixels in each row in the first pixel area is greater than the number of pixels in each row in the second pixel area, resulting in a difference in the load of the first signal line between the first pixel area and the second pixel area, that is, the load of the second pixel area is less than the first Pixel area load. On the display panel, the first signal line and the second signal line overlap to form a parasitic capacitance (parasitic capacitance is one of the load of the pixel driving circuit). The overlapping degree of the first signal line and the second signal line of the second pixel area is greater than or equal to the overlapping degree of the first signal line and the second signal line of the first pixel area, thereby increasing the second pixel to a certain extent The parasitic capacitance of the area, that is, increasing the load of the second pixel area, can reduce the load difference of the first signal line between the first pixel area and the second pixel area, thereby improving the display effect of the display panel.

【Explanation of Drawing】

1 is a schematic structural diagram of a first embodiment of a display panel of this application;

FIG. 2 is a partial structural schematic diagram of the display panel shown in FIG. 1;

FIG. 3 is a schematic structural diagram of an embodiment in which the first signal line and the second signal line of the display panel shown in FIG. 1 overlap;

4 is a schematic structural diagram of a second embodiment of a display panel of this application;

5 is a schematic structural diagram of an embodiment of a display device of the present application.

【detailed description】

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application.

In order to solve the technical problem of a large difference in the load of the driving circuit in different areas of the display panel, an embodiment of the present application provides a display panel. The display panel includes: a first pixel area and a second pixel area, the first pixel area is adjacent to the second pixel area; wherein, the number of pixels in each row in the first pixel area is greater than the number of pixels in each row in the second pixel area; A first signal line extending in the row direction; a second signal line extending in the column direction; wherein the degree of overlap between the first signal line and the second signal line of the second pixel area is greater than or equal to the first signal of the first pixel area The degree of overlap between the line and the second signal line. This is explained in detail below.

Please refer to FIGS. 1-2, FIG. 1 is a schematic structural diagram of a first embodiment of a display panel of the present application, and FIG. 2 is a partial structural schematic diagram of the display panel shown in FIG.

In one embodiment, the display panel 1 serves as a human-computer interaction medium for electronic devices such as smart phones, tablet computers, etc. The novelty of its appearance is an important means to improve the market competitiveness of products, the most typical of which is a display with a special shape The display panel 1 of the area (the conventional display area is rectangular). For example, the corners of the display area of the display panel 1 are different from the conventional right angles, but arc angles, and it has become a design trend. In this embodiment, the corners of the display area of the display panel 1 are curved corners as an example for description.

The display panel 1 includes a first pixel area 11 and a second pixel area 12. The first pixel area 11 is adjacent to the second pixel area 12. The display panel 1 further includes a plurality of pixels 13 arranged on the display panel 1 in a matrix along the row direction X and the column direction Y. Each pixel 13 is in the display area of the display panel 1. Since the corner of the display area of the display panel 1 is an arc-shaped angle, in order to define the arc-shaped angle of the display area, some pixels 13 at corresponding positions on the display panel 1 default. On the display area of the display panel 1, the default area where the pixel 13 exists is the second pixel area 12, and the default area where there is no pixel row 131 is the first pixel area 11. The first pixel area 11 and the second pixel area 12 appear on the display panel 1 as follows: the opposite ends of the display panel 1 are the second pixel areas 12, and the intermediate area sandwiched by the second pixel areas 12 on both ends is the first Pixel area 11.

Please refer to Figures 1 and 3. The display panel 1 further includes a first signal line 14 extending in the row direction X, and a second signal line 15 extending in the column direction Y. The first signal line 14 extending in the row direction X and the second signal line 15 extending in the column direction Y are layered in the display panel, and the first signal line 14 and the second signal line 15 are spaced apart from each other in the stacking direction An interlayer insulating layer 16 is spaced between the two to insulate the overlapping signal lines from each other, thereby causing parasitic capacitance between the overlapping signal lines. The parasitic capacitance is one of the load of the pixel driving circuit, which will share a part of the voltage and cause a voltage drop, thereby affecting the light-emitting process of the pixel 13, which affects the display effect of the display panel 1 macroscopically.

Since some pixels 13 in the second pixel area 12 default, each row of pixels 13 in the second pixel area 12 contains fewer pixels 13 than each row of pixels 13 in the first pixel area 11, that is, in the second pixel area 12 The number of pixels 13 corresponding to each first signal line 14 is less than the number of pixels 13 corresponding to each first signal line 14 in the first pixel area 11, resulting in the load and The load of each first signal line 14 in the first pixel area 11 is different, that is, the load of the second pixel area is smaller than that of the first pixel area, which in turn causes the first pixel area 11 and the second pixel area 12 to display unevenly. The display effect of the display panel 1 has an adverse effect.

In an embodiment, the overlapping degree of the first signal line 14 and the second signal line 15 of the second pixel area 12 is greater than or equal to the overlap of the first signal line 14 and the second signal line 15 of the first pixel area 11 The degree increases the parasitic capacitance of the second pixel area to a certain extent, that is, increases the load of the second pixel area, so as to reduce the difference in the load of the first signal line 14 between the first pixel area 11 and the second pixel area 12.

The overlapping degree is defined as the ratio of the total overlapping area of the first signal line 14 and the second signal line 15 in the pixel area to the area of the pixel area.

The second pixel area 12 is divided into a pixel arrangement area 121 and a non-pixel arrangement area 122 along the row direction X. Among the areas defined by the outermost pixel row 131, pixel column 132, and corresponding extension line in the second pixel area 12, the area where the pixel 13 is arranged is the pixel arrangement area 121, and the pixel arrangement area 121 is excluded The area outside is the non-pixel arrangement area 122. The first signal line 14 penetrates the pixel arrangement area 121 and the non-pixel arrangement area 122 along the row direction X; similarly, the second signal line 15 penetrates the pixel arrangement area 121 and the non-pixel arrangement area 122 along the column direction Y. Therefore, even if the non-pixel arrangement area 122 is not provided with the pixels 13, the non-pixel arrangement area 122 is also provided with the first signal line 14 corresponding to the pixel row 131 and the second signal line 15 corresponding to the pixel column 132.

The overlapping degree of the first signal line 14 and the second signal line 15 in the pixel arrangement area 121 is equal to the overlapping degree of the first signal line 14 and the second signal line 15 in the first pixel area 11. The overlapping degree of the first signal line 14 and the second signal line 15 in the non-pixel arrangement area 122 is greater than or equal to the overlapping degree of the first signal line 14 and the second signal line 15 in the first pixel area 11.

The stacked structure of the pixel arrangement area 121 is the same or similar. Therefore, in the same unit area (such as sub-pixel areas of the same color), the pixel arrangement area 121 and the first signal line 14 of the first pixel area 11 The load is consistent, which corresponds to the case where the overlapping degree of the first signal line 14 and the second signal line 15 of the second pixel area 12 is equal to the overlapping degree of the first signal line 14 and the second signal line 15 of the first pixel area 11 .

The overlap degree of the first signal line 14 and the second signal line 15 in the non-pixel arrangement area 122 is at least equal to the overlap degree of the first signal line 14 and the second signal line 15 in the pixel arrangement area 121, The difference in the parasitic capacitance generated by the overlapping of the first signal line 14 and the second signal line 15 in the balanced pixel arrangement area 121 and the non-pixel arrangement area 122 balances the first signal line 14 in the second pixel area 12 And the load of the first signal line 14 in the first pixel area 11 reduce the difference in the load of the first signal line 14 between them, thereby improving the display effect of the display panel 1.

In an alternative embodiment, the overlapping degree of the first signal line 14 and the second signal line 15 in the non-pixel arrangement area 122 is greater than the intersection of the first signal line 14 and the second signal line 15 in the pixel arrangement area 121 Stacking. The inventor found that in the non-pixel arrangement area 122, although the pixel 13 is not provided, the load of the first signal line 14 is less than the load of the first signal line 14 in the first pixel area 11 and the pixel arrangement area 121, but It is still possible to balance the load of the first signal lines 14 in the non-pixel arrangement area 122 and the pixel arrangement area 121, reduce the difference in the load of the first signal lines 14 between them, and further improve the display effect of the display panel 1.

It can be seen that when the overlap degree of the first signal line 14 and the second signal line 15 in the non-pixel arrangement area 122 is equal to the overlap degree of the first signal line 14 and the second signal line 15 in the pixel arrangement area 121 The overlapping degree of the first signal line 14 and the second signal line 15 of the second pixel area 12 is equal to the overlapping degree of the first signal line 14 and the second signal line 15 of the first pixel area 11. When the overlap degree of the first signal line 14 and the second signal line 15 in the non-pixel arrangement area 122 is greater than the overlap degree of the first signal line 14 and the second signal line 15 in the pixel arrangement area 121, The overlapping degree of the first signal line 14 and the second signal line 15 of the second pixel area 12 is greater than the overlapping degree of the first signal line 14 and the second signal line 15 of the first pixel area 11.

The wiring design of the first signal line and the second signal line is explained in detail below.

In an embodiment, the second signal line includes a data signal line and a power signal line. The first signal line includes a first scan signal line, a second scan signal line, and an emission signal line. Each row of pixels corresponds to a first scan signal line and a second scan signal line. The first scan signal line is used to control the pixel to allow data signals on the data signal line to be written into the pixel, and the second scan signal line is used to control the pixel Voltage reset. Each row of pixels corresponds to an emission signal line, and the emission signal line is used to control the pixel to drive the power signal on the power signal line to be written into the pixel together with the data signal line.

Optionally, in the GIP pixel driving circuit, the first scan signal line may be a SCAN2 signal line, the second scan signal line may be a SCAN1 & 3 signal line, and the emission signal line may be an EM signal line. Among them, one scanning circuit corresponds to one SCAN1 & 3 signal line and one SCAN2 signal line, and one transmitting circuit can correspond to a number of EM signal lines.

Please refer to FIG. 4, which is a schematic structural diagram of a second embodiment of a display panel of the present application.

In an embodiment, at least one of the first signal line 22, the data signal line 23, and the power signal line 24 in the non-pixel arrangement area 21 has a line width greater than that of the first signal line 22 in the pixel arrangement area 25, The corresponding line widths of the data signal line 23 and the power signal line 24 are such that the overlapping degree of the first signal line 22 and the data signal line 23 and the power signal line 24 in the non-pixel arrangement area 21 is greater than or equal to the pixel arrangement area The overlapping degree of the first signal line 22, the data signal line 23, and the power signal line 24 in 25.

The pixel signal area 25 and the non-pixel signal area 21 generally have the same width of the data signal line 23 and the power signal line 24. Therefore, in this embodiment, the line width of the first signal line 22 in the non-pixel arrangement area 21 is increased to reduce the load difference between the non-pixel arrangement area 21 and the pixel arrangement area 25 of the first signal line 22.

Specifically, the line width of the scan signal bus 221 in the non-pixel arrangement area 21 is greater than the line width of the first scan signal line 222 and the second scan signal line 223 in the pixel arrangement area 25, wherein the line of the scan signal bus 221 The width A is preferably the sum of the line width a of the first scan signal line 222 and the second scan signal line 223 participating in the parallel connection, so that the scan signal bus 221 and the data signal line 23 and the power signal line in the non-pixel arrangement area 21 The overlap degree of 24 is equal to the overlap degree of the first scan signal line 222, the second scan signal line 223, the data signal line 23, and the power signal line 24 in the pixel arrangement area 25.

Similarly, the line width of the transmission signal bus 224 in the non-pixel arrangement area 21 is larger than the line width of the transmission signal line 225 in the pixel arrangement area 25, wherein the line width B of the transmission signal bus 224 is preferably the transmission signal participating in the parallel The sum of the line width 225 b (for example, if two transmission signal lines 225 participate in the parallel connection, the line width B of the transmission signal bus 224 is equal to the sum of the line width b of the two transmission signal lines 225), so that the non-pixel arrangement area The overlapping degree of the transmission signal bus 224 and the data signal line 23 and the power signal line 24 in 21 is equal to the overlapping degree of the corresponding transmission signal line 225 and the data signal line 23 and the power signal line 24 in the pixel arrangement area 25.

Further, the overall signal width of the scan signal bus 221 and the emission signal bus 224 in the non-pixel arrangement area 21 can be further increased to further balance the first signal line 22 between the non-pixel arrangement area 21 and the pixel arrangement area 25 load. Correspondingly, the line width of the scan signal bus 221 is greater than the sum of the line widths of the first scan signal line 222 and the second scan signal line 223 participating in the merge, and the line width of the transmit signal bus 224 is greater than the line 225 of the transmit signal line participating in the merge The wide sum.

Please continue to refer to Figure 2. In an embodiment, the second signal line 15 includes a data signal line 151 and a power signal line 152. The first signal line 14 includes a first scan signal line 141, a second scan signal line 142, and an emission signal line 143.

In one embodiment, the first scan signal line 141 and the second scan signal line 142 corresponding to the pixels 13 in each row are electrically connected to the same scan circuit 171, and the emission signal line 143 corresponding to the pixels 13 in two rows and above are electrically connected to The same transmitting circuit 172.

The overlapping degree of the first scan signal line 141 and the data signal line 151 and the power signal line 152 in the non-pixel arrangement area 122 is at least equal to the first scan signal line 141 and the data signal line 151 and the power supply in the pixel arrangement area 121 The degree of overlap of the signal lines 152. The overlapping degree of the second scan signal line 142 and the data signal line 151 and the power signal line 152 in the non-pixel arrangement area 122 is at least equal to the second scan signal line 142 and the data signal line 151 and the power supply in the pixel arrangement area 121 The degree of overlap of the signal lines 152. Thereby, the load difference between the non-pixel arrangement area 122 and the pixel arrangement area 121 of the first signal line 14 is reduced.

Further, in the non-pixel arrangement area 122, the line width of the overlapping portion of the first scan signal line 141, the second scan signal line 142, the data signal line 151, and the power signal line 152 is greater than the line width of the other parts, so that The portion of the first scan signal line 141 and the second scan signal line 142 in the non-pixel arrangement area 122 and the data signal line 151 and the power signal line 152 overlap more than the first scan signal line 141 and the second scan signal line The overlapping degree of the portion 142 in the pixel arrangement area 121 with the data signal line 151 and the power signal line 152 further balances the load of the first signal line 14 in the non-pixel arrangement area 122 and the pixel arrangement area 121.

In one embodiment, the overlap of the portion of the emission signal line 143 in the non-pixel arrangement area 122 with the data signal line 151 and the power signal line 152 is greater than or equal to its portion in the pixel arrangement area 121 and the data signal The overlapping degree of the line 151 and the power signal line 152.

In this embodiment, the emission signal line 143 corresponding to each pixel row in the pixel arrangement area 121 continues to extend along the row direction and passes through the non-pixel arrangement area 122. The portion of the emission signal line 143 in the non-pixel arrangement area 122 overlaps with the data signal line 151 and the power signal line 152 at least equal to its portion in the pixel arrangement area 121 and the data signal line 151 and the power signal line 152 To overlap the load of the first signal line 14 between the non-pixel arrangement area 122 and the pixel arrangement area 121.

Further, in the non-pixel arrangement area 122, the line width of the overlapping portion of the emission signal line 143 with the data signal line 151 and the power signal line 152 is greater than the line width of the other portions, so that the emission signal line 143 is arranged in the non-pixel The overlapping degree of the portion in the area 122 with the data signal line 151 and the power signal line 152 is greater than the overlapping degree of the portion in the pixel arrangement area 121 with the data signal line 151 and the power signal line 152 to further balance the non-pixel arrangement The load of the first signal line 14 in the layout area 122 and the pixel layout area 121.

In summary, the display panel provided by this application. In the display panel, the overlapping degree of the first signal line and the data signal line and the power signal line in the non-pixel arrangement area is greater than or equal to the overlapping degree of the first signal line, the data signal line and the power signal line in the pixel arrangement area , To balance the load of the first signal line in the non-pixel arrangement area and the pixel arrangement area, thereby balancing the load of the first signal line in the first pixel area and the second pixel area, and reducing the first pixel area and the second pixel The load difference of the first signal line in the area improves the display effect of the display panel. It does not require additional design of a load compensation circuit in the non-pixel arrangement area, which can minimize the load difference of the first signal line in the first pixel area and the second pixel area, simplifying the wiring design of the non-pixel arrangement area .

Please refer to FIG. 5, which is a schematic structural diagram of an embodiment of a display device of the present application.

In an embodiment, the display device 3 includes a driving circuit 31 and a display panel 32. The driving circuit 31 is coupled to the display panel 32. The driving circuit 31 is used to drive the display panel 32 to realize its display function. The display panel 32 is the display panel described in the above embodiment, and will not be repeated here.

The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any changes to the equivalent structure or equivalent process made by the description and drawings of this application, or directly or indirectly used in other related technologies In the field, the same reason is included in the patent protection scope of this application.

Claims

A display panel, wherein the display panel includes:

A first pixel area and a second pixel area, the first pixel area is adjacent to the second pixel area, and the number of pixels in each row in the first pixel area is greater than the number of pixels in each row in the second pixel area;

The first signal line extending in the row direction;

A second signal line extending in the column direction;

The overlap degree of the first signal line and the second signal line of the second pixel area is greater than or equal to the overlap of the first signal line and the second signal line of the first pixel area degree.
The display panel according to claim 1, wherein the second pixel area is divided into a pixel arrangement area and a non-pixel arrangement area along the row direction;

The overlapping degree of the first signal line and the second signal line in the pixel arrangement area is equal to the overlap of the first signal line and the second signal line in the first pixel area degree;

The overlapping degree of the first signal line and the second signal line in the non-pixel arrangement area is greater than or equal to the first signal line and the second signal line in the first pixel area Of overlap.
The display panel according to claim 2, wherein the second signal line includes a data signal line and a power signal line;

At least one of the first signal line, the data signal line, and the power signal line in the non-pixel arrangement area has a line width greater than the first signal line in the pixel arrangement area, Corresponding line widths of the data signal line and the power signal line.
The display panel according to claim 2, wherein the first signal line includes a first scan signal line and a second scan signal line electrically connected to the same scan circuit.
The display panel according to claim 4, wherein the second signal line includes a data signal line and a power signal line;

The overlapping degree of the portion of the first scanning signal line and the second scanning signal line in the non-pixel arrangement area with the data signal line and the power supply signal line is greater than or equal to The overlapping degree of the portion in the pixel arrangement area with the data signal line and the power signal line.
The display panel according to claim 5, wherein, in the non-pixel arrangement area, the first scan signal line and the second scan signal line intersect the data signal line and the power signal line The line width of the overlapping part is larger than the line width of the other parts.
The display panel according to claim 2, wherein the first signal line includes a transmission signal line, and two or more of the transmission signal lines are electrically connected to the same transmission circuit.
The display panel according to claim 7, wherein the second signal line includes a data signal line and a power signal line;

A portion of the emission signal line in the non-pixel arrangement area overlaps with the data signal line and the power signal line is greater than or equal to its portion in the pixel arrangement area and the data The overlapping degree of the signal line and the power signal line.
The display panel according to claim 8, wherein, in the non-pixel arrangement area, a line width of a portion where the emission signal line overlaps the data signal line and the power supply signal line is larger than lines of other portions width.
A display device, wherein the display device includes a drive circuit and a display panel, and the drive circuit is coupled to the display panel and used to drive the display panel to realize its display function.
The display device according to claim 10, wherein the display panel comprises:

A first pixel area and a second pixel area, the first pixel area is adjacent to the second pixel area, and the number of pixels in each row in the first pixel area is greater than the number of pixels in each row in the second pixel area;

The first signal line extending in the row direction;

A second signal line extending in the column direction;

The overlap degree of the first signal line and the second signal line of the second pixel area is greater than or equal to the overlap of the first signal line and the second signal line of the first pixel area degree.
The display device according to claim 11, wherein the second pixel area is divided into a pixel arrangement area and a non-pixel arrangement area along the row direction;

The overlapping degree of the first signal line and the second signal line in the pixel arrangement area is equal to the overlap of the first signal line and the second signal line in the first pixel area degree;

The overlapping degree of the first signal line and the second signal line in the non-pixel arrangement area is greater than or equal to the first signal line and the second signal line in the first pixel area Of overlap.
The display device according to claim 12, wherein the second signal line includes a data signal line and a power signal line;

At least one of the first signal line, the data signal line, and the power signal line in the non-pixel arrangement area has a line width greater than the first signal line in the pixel arrangement area, Corresponding line widths of the data signal line and the power signal line.
The display device according to claim 12, wherein the first signal line includes a first scan signal line and a second scan signal line electrically connected to the same scan circuit.
The display device according to claim 14, wherein the second signal line includes a data signal line and a power signal line;

The overlapping degree of the portion of the first scanning signal line and the second scanning signal line in the non-pixel arrangement area with the data signal line and the power supply signal line is greater than or equal to The overlapping degree of the portion in the pixel arrangement area with the data signal line and the power signal line.
The display device according to claim 15, wherein, in the non-pixel arrangement area, the first scan signal line and the second scan signal line intersect the data signal line and the power signal line The line width of the overlapping part is larger than the line width of the other parts.
The display device according to claim 12, wherein the first signal line includes a transmission signal line, and two or more of the transmission signal lines are electrically connected to the same transmission circuit.
The display device according to claim 17, wherein the second signal line includes a data signal line and a power signal line;

A portion of the emission signal line in the non-pixel arrangement area overlaps with the data signal line and the power signal line is greater than or equal to its portion in the pixel arrangement area and the data The overlapping degree of the signal line and the power signal line.
The display device according to claim 18, wherein, in the non-pixel arrangement area, a line width of a portion where the emission signal line overlaps the data signal line and the power supply signal line is larger than lines of other portions width.