WO2020079932A1 - Display device - Google Patents

Abstract

This display device comprises an inorganic light emitting element that is provided in each of a plurality of pixels, and a drive circuit that supplies a drive signal to a plurality of inorganic light emitting elements on the basis of a period control signal and an amplitude control signal, wherein: a one-frame period during which an image corresponding to one frame is displayed includes a plurality of time-divided sub-frames; first signal data is associated with the period control signal for every plurality of sub-frames; second signal data indicating any of a plurality of second signal values having different signal values is associated with the amplitude control signal; and the inorganic light emitting element expresses gradation by being supplied with a drive signal corresponding to third signal data obtained by integrating the first signal data and the second signal data in each of the sub-frames.

Description

Display device

The present invention relates to a display device.

In recent years, an inorganic EL display using an inorganic light emitting diode (micro LED) as a display element has been receiving attention (for example, refer to Patent Document 1). In an inorganic EL display, a plurality of light emitting elements that emit light of different colors are arranged on an array substrate. Since the inorganic EL display uses a self-luminous element, it does not require a light source, and light is emitted without passing through a color filter, so that the light utilization efficiency is high. Further, the inorganic EL display is superior in environment resistance to organic EL displays using organic light emitting diodes (OLED: Organic Light Emitting Diode) as display elements.

Japanese Patent Publication No. 2017-5295557

▽ The front inorganic light emitting diode is gradation controlled by current drive. When the current value is controlled to express a low gradation, the current value becomes unstable, and thus there is a possibility that the variation in luminance between pixels becomes large. On the other hand, when the gradation is expressed by controlling the lighting time with a constant current value, it takes on / off operation of the switching element and driving time until the current value rises to a desired current value. Could be.

An object of the present invention is to provide a display device capable of excellent gradation control.

A display device according to one embodiment of the present invention includes an inorganic light emitting element provided in each of a plurality of pixels, and a drive circuit that supplies a drive signal to the plurality of inorganic light emitting elements based on a period control signal and an amplitude control signal. , One frame period for displaying an image for one frame includes a plurality of time-divided subframes, and the period control signal is associated with the first signal data for each of the plurality of subframes. That is, the amplitude control signal is associated with second signal data indicating one of a plurality of second signal values having different signal values, and the inorganic light emitting element, for each subframe, The drive signal corresponding to the third signal data, which is the combination of the first signal data and the second signal data, is supplied to express a gray scale.

FIG. 1 is a plan view showing a display device according to the first embodiment. FIG. 2 is a plan view showing a plurality of pixels. FIG. 3 is a circuit diagram showing a configuration example of a pixel circuit of a display device. 4 is a sectional view taken along the line IV-IV 'of FIG. FIG. 5: is sectional drawing which shows the structural example of an inorganic light emitting element. FIG. 6 is a cross-sectional view showing a modified example of the inorganic light emitting element. FIG. 7 is a block diagram showing the configuration of the display device. FIG. 8 is an explanatory diagram for explaining the relationship between subframes and video signals. FIG. 9 is a table showing the relationship between the video signal and the period and current value. FIG. 10 is an explanatory diagram showing waveforms of the first signal data for different period control signals. FIG. 11 is a graph showing the relationship between the second signal data and the subframe for each different amplitude control signal. FIG. 12 is an explanatory diagram showing the waveform of the third signal data for each different video signal. FIG. 13 is a graph showing voltage-current characteristics of the inorganic light emitting device. FIG. 14 is a graph showing the relationship between the second signal data and the subframe for each different video signal in the display device according to the second embodiment. FIG. 15 is an explanatory diagram showing the waveform of the third signal data of the display device according to the second embodiment. FIG. 16 is a block diagram showing the configuration of the display device according to the third embodiment. FIG. 17 is a table showing the relationship between the correction signal and the period and current value. FIG. 18 is an explanatory diagram showing the waveform of the fourth signal data for each correction signal. FIG. 19 is an explanatory diagram showing the waveform of the third signal data according to the third embodiment. FIG. 20 is an explanatory diagram for explaining the relationship between subframes and video signals according to the fourth embodiment. FIG. 21 is a circuit diagram showing a configuration example of the pixel circuit according to the fourth embodiment. FIG. 22 is a circuit diagram showing a modified example of the pixel circuit.

A mode (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the embodiments below. Further, the constituent elements described below include those that can be easily conceived by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and a person skilled in the art can easily think of appropriate modifications while keeping the gist of the invention, and are naturally included in the scope of the invention. Further, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example, and the interpretation of the present invention will be understood. It is not limited. In the specification and the drawings, the same elements as those described above with reference to the already-existing drawings are designated by the same reference numerals, and detailed description thereof may be appropriately omitted.

(First embodiment)
FIG. 1 is a plan view showing a configuration example of the display device according to the first embodiment. As shown in FIG. 1, the display device 1 includes an array substrate 2, a pixel Pix, a gate driver 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60. The array substrate 2 is a drive circuit substrate for driving each pixel Pix, and is also called a backplane or an active matrix substrate.

As shown in FIG. 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area in which a plurality of pixels Pix are arranged, and is an area for displaying an image. The peripheral area GA is an area that does not overlap the plurality of pixels Pix, and is arranged outside the display area AA.

The plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area AA. The first direction Dx and the second direction Dy are parallel to the first surface 10a (see FIG. 4) of the substrate 10 of the array substrate 2. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy instead of being orthogonal to each other. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to the normal line direction of the substrate 10, for example. Hereinafter, the plan view refers to a positional relationship when viewed from the third direction Dz.

The gate driver 12 is a circuit that drives a plurality of gate lines GCL (see FIG. 3) based on various control signals from the drive IC 210. The gate driver 12 sequentially or simultaneously selects a plurality of gate lines GCL and supplies a gate drive signal to the selected gate line GCL. As a result, the gate driver 12 selects the plurality of pixels Pix connected to the gate line GCL.

The drive IC 210 is a circuit that controls the display of the display device 1. The drive IC 210 may be mounted as a COG (Chip On Glass) in the peripheral area GA of the substrate 10. The drive IC 210 is not limited to this, and may be mounted as a COF (Chip On Film) on a flexible printed board or a rigid board connected to the peripheral area GA of the board 10.

The cathode wiring 60 is provided in the peripheral area GA of the substrate 10. The cathode wiring 60 is provided so as to surround the plurality of pixels Pix in the display area AA and the gate driver 12 in the peripheral area GA. The cathodes (cathode terminals 90p (see FIG. 4)) of the plurality of inorganic light emitting elements 100 (see FIG. 4) are connected to a common cathode wiring 60 and are supplied with a fixed potential (eg, ground potential). More specifically, the cathode terminal 90p (second terminal) of the inorganic light emitting device 100 is connected to the cathode wiring 60 via the cathode electrode 90e (second electrode) on the TFT substrate side.

FIG. 2 is a plan view showing a plurality of pixels. As shown in FIG. 2, one pixel Pix includes a plurality of pixels 49. For example, the pixel Pix has a first pixel 49R, a second pixel 49G, and a third pixel 49B. The first pixel 49R displays the primary color red as the first color. The second pixel 49G displays the primary color green as the second color. The third pixel 49B displays the primary color blue as the third color. As shown in FIG. 2, in one pixel Pix, the first pixel 49R and the third pixel 49B are arranged in the first direction Dx. Further, the second pixel 49G and the third pixel 49B are arranged in the second direction Dy. The first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected. Hereinafter, when it is not necessary to distinguish the first pixel 49R, the second pixel 49G, and the third pixel 49B from each other, it is referred to as a pixel 49. The number of pixels 49 included in one pixel Pix is not limited to three, and four or more pixels 49 may be associated with each other. For example, the fourth pixel 49W associated with white as the fourth color may be included.

Each pixel 49 has an inorganic light emitting element 100. The display device 1 displays an image by emitting different light for each inorganic light emitting element 100 in the first pixel 49R, the second pixel 49G, and the third pixel 49B. The inorganic light emitting element 100 is an inorganic light emitting diode (LED: Light Emitting Diode) chip having a size of 3 μm or more and 300 μm or less in a plan view, and is called a micro LED (micro LED) or a mini LED (mini LED). . A display device having a micro LED in each pixel is also called a micro LED display device. Note that the size of the inorganic light emitting element 100 is not limited by the size of the micro of the micro LED.

FIG. 3 is a circuit diagram showing a configuration example of a pixel circuit of a display device. The pixel circuit PIC is a drive circuit that drives the inorganic light emitting element 100. As shown in FIG. 3, the pixel circuit PIC includes a driving transistor Tr1, a current switching transistor Tr2, and an inorganic light emitting element 100. The transistors Tr1 and Tr2, and a transistor Tr5 (see FIG. 4) described later are thin film transistors (Thin Film Transistors: TFTs).

The transistor Tr1 has a gate connected to the drain of the transistor Tr2, a source connected to the power supply line LVCC, and a drain connected to the anode of the inorganic light emitting element 100. The transistor Tr2 has a gate connected to the gate line GCL, a source connected to the signal line SGL, and a drain connected to the gate of the transistor Tr1.

The capacitor CS has one end connected to the gate of the transistor Tr1 and the drain of the transistor Tr2, and the other end connected to the power supply line LVCC. The capacitor CS is added to the pixel circuit PIC in order to suppress the fluctuation of the gate voltage due to the parasitic capacitance of the transistor Tr1 and the leak current. The cathode of the inorganic light emitting element 100 is connected to the cathode wiring 60 and is supplied with the reference potential VCOM. A ground potential is exemplified as the reference potential VCOM.

The power line LVCC is connected to a constant voltage source. The power supply line LVCC supplies the DC constant voltage VCC to the source of the transistor Tr1 and one end of the capacitor CS. The signal line SGL is connected to a constant current source. The signal line SGL supplies a DC constant current Idata to the source of the transistor Tr2. The gate line GCL is connected to the gate driver 12 (see FIG. 1). The gate line GCL supplies the voltage Vgcl as a gate drive signal to the gate of the transistor Tr2.

When the display device 1 makes the potential of the gate line GCL high, the transistors Tr1 and Tr2 are turned on. As a result, the constant current Idata is supplied to the inorganic light emitting element 100 from the signal line SGL. When the display device 1 sets the potential of the gate line GCL to low (Low), the transistor Tr2 is turned off and the transistor Tr1 is turned on. As a result, the constant voltage VCC is supplied to the inorganic light emitting element 100 from the power supply line LVCC. Further, the reference potential VCOM, which is a reverse bias, is supplied from the reference potential line LVCOM to the cathode of the inorganic light emitting element 100.

FIG. 4 is a sectional view taken along the line IV-IV ′ of FIG. As shown in FIG. 4, the display device 1 includes a substrate 10, an undercoat layer 20, and a plurality of transistors. The substrate 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. The substrate 10 is, for example, a glass substrate, a quartz substrate, or a flexible substrate made of acrylic resin, epoxy resin, polyimide resin, or polyethylene terephthalate (PET) resin.

The undercoat layer 20 is provided on the first surface 10 a of the substrate 10. The plurality of transistors are provided on the undercoat layer 20. For example, in the display area AA of the substrate 10, transistors Tr1 and Tr2 included in the pixel 49 are provided as a plurality of transistors, respectively. In the peripheral area GA of the substrate 10, a transistor Tr5 included in the gate driver 12 is provided as a plurality of transistors.

The transistors Tr1, Tr2, Tr5 are, for example, double-sided gate structure TFTs. Each of the transistors Tr1, Tr2, Tr5 has a first gate electrode 21, a second gate electrode 31, a semiconductor layer 25, a source electrode 41s, and a drain electrode 41d. The first gate electrode 21 is provided on the undercoat layer 20. The insulating film 24 is provided on the undercoat layer 20 and covers the first gate electrode 21. The semiconductor layer 25 is provided on the insulating film 24. The insulating film 29 is provided on the semiconductor layer 25. The second gate electrode 31 is provided on the insulating film 29.

The insulating films 24 and 29 are inorganic insulating films, and are made of, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN). In the third direction Dz, the first gate electrode 21 and the second gate electrode 31 face each other with the insulating film 24, the semiconductor layer 25, and the insulating film 29 in between. In the insulating films 24 and 29, the portion sandwiched between the first gate electrode 21 and the second gate electrode 31 functions as a gate insulating film. Further, in the semiconductor layer 25, a portion sandwiched between the first gate electrode 21 and the second gate electrode 31 becomes a channel 27 of the TFT. In the semiconductor layer 25, the portion connected to the source electrode 41s is the source of the TFT, and the portion connected to the drain electrode 41d is the drain of the TFT.

The gate line 31a is connected to the second gate electrode 31 of the transistor Tr1. The insulating film 29 is provided between the substrate 10 and the gate line 31a, and the capacitor CS is formed between the gate line 31a and the substrate 10.

In the present embodiment, the transistors Tr1, Tr2, Tr5 are not limited to the double-sided gate structure. The transistors Tr1, Tr2, Tr5 may be of a bottom gate type in which the gate electrode is composed of only the first gate electrode 21. Further, the transistors Tr1, Tr2, Tr5 may be of a top gate type in which the gate electrode is composed of only the second gate electrode 31. Further, the undercoat layer 20 may be omitted.

The display device 1 has an insulating film 35 provided on the first surface 10a of the substrate 10 and covering the plurality of transistors Tr1, Tr2, Tr5. The source electrode 41s is provided on the insulating film 35, and is connected to each source of the plurality of transistors Tr1, Tr2, Tr5 via a through hole provided in the insulating film 35. The drain electrode 41d is provided on the insulating film 35 and is connected to the drains of the plurality of transistors Tr1, Tr2, Tr5 via the through holes provided in the insulating film 35. In the peripheral area GA, the cathode wiring 60 is provided on the insulating film 35. The insulating film 42 covers the source electrode 41s, the drain electrode 41d, and the cathode wiring 60. The insulating film 35 is an inorganic insulating film, and the insulating film 42 is an organic insulating film.

The display device 1 includes a source connection wiring 43s, a drain connection wiring 43d, an insulating film 45, an anode electrode 50e (first electrode), an insulating film 70, a flattening film 80, and a cathode electrode 90e. The source connection wiring 43s is provided on the insulating film 42 and is connected to the source electrode 41s via a through hole provided in the insulating film 42. The drain connection wiring 43d is provided on the insulating film 42 and is connected to the drain electrode 41d through a through hole provided in the insulating film 42. The insulating film 45 is provided on the insulating film 42 and covers the source connection wiring 43s and the drain connection wiring 43d. The anode electrode 50e is provided on the insulating film 45 and is connected to the drain connection wiring 43d of the transistor Tr1 via a through hole provided in the insulating film 45. The inorganic light emitting element 100 is provided on the anode electrode 50e (first electrode), and the anode electrode 50e is connected to the anode terminal 50p (first terminal) of the inorganic light emitting element 100.

The insulating film 70 is provided on the insulating film 45 and covers the side surface of the anode electrode 50e. The planarization film 80 is provided on the insulating film 70 and covers the side surface of the inorganic light emitting device 100. The cathode electrode 90e is provided on the flattening film 80. The insulating film 70 is an inorganic insulating film and is made of, for example, a silicon nitride film (SiN). The flattening film 80 is an organic insulating film or an inorganic-organic hybrid insulating film (a material in which an organic group (methyl group or phenyl group) is bonded to the Si—O main chain). The upper surface (cathode terminal 90p) of the inorganic light emitting device 100 is exposed from the flattening film 80. The cathode electrode 90e is connected to the cathode terminal 90p of the inorganic light emitting device 100.

Here, the configuration of the inorganic light emitting device 100 will be described. FIG. 5: is sectional drawing which shows the structural example of an inorganic light emitting element. As shown in FIG. 5, the inorganic light emitting device 100 includes a p-type clad layer 101, an active layer 102 provided on the p-type clad layer 101, an n-type clad layer 103 provided on the active layer 102, It has a p-type electrode layer 104 and an n-type electrode layer 105. The p-type electrode layer 104 includes the anode terminal 50p. The p-type electrode layer 104 is located between the anode electrode 50e and the p-type cladding layer 101, and is in contact with the anode electrode 50e and the p-type cladding layer 101. A p-type clad layer 101, an active layer 102, an n-type clad layer 103, and an n-type electrode layer 105 are laminated in this order on the p-type electrode layer 104.

The n-type clad layer 103, the active layer 102, and the p-type clad layer 101 are light emitting layers, and for example, compound semiconductors such as gallium nitride (GaN) and aluminum indium phosphide (AlInP) are used. The n-type electrode layer 105 is a translucent conductive material such as ITO. The n-type electrode layer 105 is the cathode terminal 90p of the inorganic light emitting device 100 and is connected to the cathode electrode 90e. The p-type electrode layer 104 is the anode terminal 50p of the inorganic light emitting element 100, and has a Pt layer and a thick film Au layer formed by plating. The thick film Au layer is connected to the anode electrode 50e.

The side surface of the inorganic light emitting element 100 is covered with a flattening film 80. The flattening film 80 is, for example, an SOG (Spin On Glass) film. A recess H11 is provided in the upper portion of the flattening film 80. The upper part of the n-type cladding layer 103 projects from the recess H11. The n-type electrode layer 105 is provided in the recess H11 and is in contact with the n-type cladding layer 103 and the cathode electrode 90e. As a result, a current can flow between the anode electrode 50e and the cathode electrode 90e with the inorganic light emitting element 100 interposed therebetween.

FIG. 6 is a cross-sectional view showing a modified example of the inorganic light emitting element. In the above-described embodiment, the inorganic light emitting device 100 has a lower part (anode terminal 50p) connected to the anode electrode 50e and an upper part (cathode terminal 90p) connected to the cathode electrode 90e (hereinafter referred to as face-up type). I explained that. However, the inorganic light emitting device 100 is not limited to the face-up type. As shown in FIG. 6, the inorganic light emitting device 100A of the modified example may be a face-down type in which the lower portion is connected to both the anode electrode 50e and the cathode electrode 90eA.

The substrate 111 is made of sapphire. The n-type cladding layer 113 is composed of n-type GaN. The active layer 114 is composed of InGaN. The p-type cladding layer 115 is made of p-type GaN. The P-type electrode 116 is composed of palladium (Pd) and gold (Au), and has a laminated structure in which Au is laminated on Pd. The n-type electrode 117 is made of indium (In).

In the inorganic light emitting device 100A, the p-type cladding layer 115 and the n-type cladding layer 113 are not directly joined, but another layer (active layer 114) is introduced therebetween. As a result, carriers such as electrons and holes can be concentrated in the active layer 114, and recombination (light emission) can be efficiently performed. A multi-quantum well structure (MQW structure) in which a well layer composed of several atomic layers and a barrier layer are periodically stacked may be adopted as the active layer 114 for higher efficiency.

Next, the gradation control of the display device 1 will be described. FIG. 7 is a block diagram showing the configuration of the display device. FIG. 8 is an explanatory diagram for explaining the relationship between subframes and video signals. FIG. 9 is a table showing the relationship between the video signal and the period and current value.

As shown in FIG. 7, the display device 1 includes a control circuit 200, a signal output circuit 15, and a drive circuit 211. The display device 1 of the present embodiment performs multicolor display with the number of gradations of the video signal Sg output from the control circuit 200. The video signal Sg is, for example, an 8-bit signal for each color of red, green, and blue, and displays 256 gradations for each color. The video signal Sg is a signal of 8 bits × 3, which is a total of 24 bits, and the display device 1 performs display of 16.77 million colors. In the following description, a case where the gradation control is performed by the 8-bit video signal Sg will be described.

As shown in FIG. 9, the upper bit (Sg7-3) of the video signal Sg is a signal for controlling the amplitude of the signal (current value) according to the gradation of the video signal Sg. In the following description, the amplitude control signal It is represented as Sg7-3. The amplitude control signals Sg7, Sg6, Sg5, Sg4, and Sg3 are 1-bit digital signals, and the amplitude control signal Sg7-3 is a 5-bit signal. The amplitude control signal Sg7-3 is associated with a plurality of second signal values I2-0, I2-1, I2-2, ..., I2-31 having different current values depending on the gradation.

The lower bit (Sg2-0) of the video signal Sg is a signal for controlling the period during which the signal is output according to the gradation of the video signal Sg, and will be referred to as the period control signal Sg2-0 in the following description. The period control signals Sg2, Sg1, Sg0 are 1-bit digital signals, and the period control signal Sg2-0 is a 3-bit signal. A common first signal value I1 is associated with each of the period control signals Sg2-0.

In FIG. 8, the horizontal axis represents time t and the vertical axis represents the scanning direction Scan. The gate driver 12 (see FIG. 1) sequentially selects the gate lines GCL according to the scanning direction Scan. Further, the display device 1 displays an image for one frame in the one frame period F. One frame period F includes a plurality of time-divided first subframes SF1, second subframes SF2, and third subframes SF3. The plurality of first subframes SF1, second subframes SF2, and third subframes SF3 have periods of different lengths. The second sub-frame SF2 has a longer period than the first sub-frame SF1. The third subframe SF3 has a longer period than the second subframe SF2. Note that in the following description, the first subframe SF1, the second subframe SF2, and the third subframe SF3 may be simply referred to as the subframe SF unless it is necessary to distinguish between them.

As shown in FIGS. 8 and 9, the period control signal Sg2 is associated with the third subframe SF3. The second sub-frame SF2 is associated with the period control signal Sg1. The first sub-frame SF1 is associated with the period control signal Sg0. The amplitude control signal Sg7-3 is associated with all subframe periods SF. In other words, in the first sub-frame SF1, gradation control is performed by the period control signal Sg0 and the amplitude control signal Sg7-3. In the second sub-frame SF2, gradation control is performed by the period control signal Sg1 and the amplitude control signal Sg7-3. In the third sub-frame SF3, gradation control is performed by the period control signal Sg2 and the amplitude control signal Sg7-3.

In the 8-bit signal of the video signal Sg, the upper bit is the amplitude control signal Sg7-3 and the lower bit is the period control signal Sg2-0, but the invention is not limited to this. The number of bits of the amplitude control signal Sg7-3 and the period control signal Sg2-0 can be changed according to the number of bits of the video signal Sg. The arrangement of the amplitude control signal Sg7-3 and the period control signal Sg2-0 can be changed as appropriate. Further, one frame period F may include two subframes SF, or may include four or more subframes SF. The number of subframes SF may be equal to or larger than the number corresponding to the number of bits of the period control signal Sg2-0.

As shown in FIG. 7, the control circuit 200 is a circuit that controls the operation of the display device 1 according to the present embodiment. The signal output circuit 15 generates the third signal data SIc according to the gradation of the video signal Sg based on the video signal Sg supplied from the control circuit 200. The signal output circuit 15 is a circuit that outputs the third signal data SIc to the drive circuit 211. The drive circuit 211 is, for example, a constant current circuit, and supplies a constant current Idata corresponding to the third signal data SIc to the inorganic light emitting element 100 via the signal line SGL.

The control circuit 200 and the signal output circuit 15 may be included in the drive IC 210 (see FIG. 1). Alternatively, at least one of the control circuit 200 and the signal output circuit 15 may be mounted on a wiring board connected to the board 10. Alternatively, at least one of the control circuit 200 and the signal output circuit 15 may be mounted on a control board connected to the board 10 via a wiring board.

The control circuit 200 has a video signal output circuit 201 and a clock signal output circuit 202. In addition, the signal output circuit 15 includes a first buffer circuit 151, a second buffer circuit 152, a first signal processing circuit 153, a second signal processing circuit 154, an arithmetic circuit 155, a buffer control circuit 158, and a subframe counter 159.

The video signal output circuit 201 separates the 8-bit video signal Sg into an amplitude control signal Sg7-3 and a period control signal Sg2-0. The video signal output circuit 201 outputs the period control signal Sg2-0 to the first buffer circuit 151 of the signal output circuit 15, and outputs the amplitude control signal Sg7-3 to the second buffer circuit 152.

The clock signal output circuit 202 outputs the clock signal CLK to the buffer control circuit 158 and the subframe counter 159. The buffer control circuit 158 and the sub-frame counter 159 cause the first buffer circuit 151, the second buffer circuit 152, the first signal processing circuit 153, and the second signal processing circuit 154 of the signal output circuit 15 to operate based on the clock signal CLK. Control. Accordingly, the first buffer circuit 151, the second buffer circuit 152, the first signal processing circuit 153, and the second signal processing circuit 154 operate in synchronization with each other or asynchronously.

The first buffer circuit 151 is a circuit that holds the period control signal Sg2-0 for one frame period F. The second buffer circuit 152 is a circuit that holds the amplitude control signal Sg7-3 for one frame period F.

The sub-frame counter 159 supplies the control signal Sgf related to the sub-frame SF to the first signal processing circuit 153 and the second signal processing circuit 154. The first signal processing circuit 153 extracts the period control signal Sg2-0 associated with each subframe SF from the first buffer circuit 151 based on the control signal Sgf. Then, the first signal processing circuit 153 generates the first signal data SIa based on the control signal Sgf and the period control signal Sg2-0. The period control signal Sg2-0 is associated with the first signal data SIa for each of the plurality of subframes SF. The period control signal Sg2-0 is associated with the first signal value I1 common to the plurality of subframes SF as the first signal data SIa.

The second signal processing circuit 154 takes out the amplitude control signal Sg7-3 associated with each subframe SF from the second buffer circuit 152 based on the control signal Sgf. Then, the second signal processing circuit 154 generates the second signal data SIb based on the control signal Sgf and the amplitude control signal Sg7-3. The amplitude control signal Sg7-3 is associated with the second signal data SIb indicating any one of the plurality of second signal values I2 having different signal values. In the present embodiment, the second signal value I2 having the same signal value in each subframe SF is associated with one amplitude control signal Sg7-3. However, the second signal value I2 may have a different signal value for each subframe SF. Further, the second signal processing circuit 154 may receive the period control signal Sg2-0 from the first signal processing circuit 153 and generate the second signal data SIb according to the pattern of the period control signal Sg2-0.

The first signal processing circuit 153 outputs the first signal data SIa to the arithmetic circuit 155. The second signal processing circuit 154 outputs the second signal data SIb to the arithmetic circuit 155. The arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the second signal value I2 of the second signal data SIb for each sub-frame SF to generate the third signal data SIc. The arithmetic circuit 155 outputs the third signal data SIc to the drive circuit 211.

Next, an operation example of the first signal processing circuit 153, the second signal processing circuit 154, and the arithmetic circuit 155 will be described. FIG. 10 is an explanatory diagram showing waveforms of the first signal data for different period control signals. FIG. 10 shows the case where the amplitude control signal Sg7-3 is 0, that is, the amplitude control signal Sg7-3 of the upper 5 bits is (Sg7, Sg6, Sg5, Sg4, Sg3) = (00000). In this case, the second signal value I2-0 associated with the amplitude control signal Sg7-3 becomes 0 (signal value I0). The third signal data SIc shown in FIG. 10 is equal to the first signal data SIa output from the first signal processing circuit 153. When the amplitude control signal Sg7-3 is 0, the second signal data SIb may not be output, and the arithmetic circuit 155 may output the first signal data SIa as the third signal data SIc.

In FIG. 10, the 3-bit period control signals Sg2-0 are (Sg2, Sg1, Sg0) = (000), (001), (010), (011), (100), (101), (110). ) And (111), the third signal data SIc (first signal data SIa) is shown.

As shown in FIG. 10, when the period control signal Sg2-0 is (000), the first signal processing circuit 153 does not output the first signal value I1 as the first signal data SIa, and in all subframes SF. The signal value I0 is output. When the period control signal Sg2-0 is (001), the first signal processing circuit 153 outputs the first signal value I1 as the first signal data SIa in the first subframe SF1 associated with the period control signal Sg0. Then, the signal value I0 is output in the second subframe SF2 and the third subframe SF3. When the period control signal Sg2-0 is (010), the first signal processing circuit 153 outputs the first signal value I1 as the first signal data SIa in the second subframe SF2 associated with the period control signal Sg1. Then, the signal value I0 is output in the first subframe SF1 and the third subframe SF3.

Hereinafter, similarly, in each of the period control signals Sg2-0 (011), (100), (101), (110), (111), the first signal processing circuit 153 outputs the first signal data SIa as The first signal value I1 is output in the subframe SF corresponding to the signal "1" of the period control signal Sg2-0. In other words, the first signal processing circuit 153 switches between the subframe SF in which the first signal data SIa is output and the subframe SF in which the first signal data SIa is not output, based on the period control signal Sg2-0. As a result, the first signal processing circuit 153 causes the first signal data SIa (third signal data SIc) in which the sub-frame SF in which the first signal value I1 is output differs depending on the 3-bit period control signal Sg2-0. Is output. The number of different first signal data SIa is eight corresponding to the number of bits of the period control signal Sg2-0.

In other words, the display device 1 is associated with the pixel 49-2 and the video signal SgA (for example, (00000001)) having the tone value GD1 (first tone value) associated with the pixel 49-1. When a video signal SgB (for example, (00000010)) having a gradation value GD2 (second gradation value) larger than the gradation value GD1 is input, one frame period F of the inorganic light emitting element 100 of the pixel 49-1 is input. From the lighting period (first lighting period, eg, first sub-frame SF1) in 1 frame period F of the inorganic light emitting element 100 of the pixel 49-2 (second lighting period, eg, second sub-frame SF2). Driven to be long. The lighting period of the pixel 49-1 and the pixel 49-2 refers to a period during which the drive signal corresponding to the signal value of the first signal value I1 or more is input to the inorganic light emitting element 100. Further, for the video signal SgA and the video signal SgB, for example, the amplitude control signal Sg7-3 has the same value, and the period control signal Sg2-0 is associated with a different signal. When the amplitude control signal Sg7-3 is 0, the brightness (first brightness) of the inorganic light emitting elements 100 of the pixels 49-1 and 49-2 when the drive signal corresponding to the first signal value I1 is input Is lit up with.

FIG. 11 is a graph showing the relationship between the second signal data and the subframe for each different amplitude control signal. FIG. 11 shows a case where the period control signal Sg2-0 is 0, that is, the period control signal Sg2-0 of the lower 3 bits is (000) and the first signal value I1 is 0 (signal value I0). Show. When the period control signal Sg2-0 is 0, the first signal data SIa may not be output, and the arithmetic circuit 155 may output the second signal data SIb as the third signal data SIc.

As shown in FIG. 11, the second signal processing circuit 154 uses, as the second signal data SIb0-31, second signal values I2-0 (I0), I2-1, I2- that differ for each amplitude control signal Sg7-3. 2, ..., I2-31 are output. The second signal processing circuit 154 outputs 32 different second signal values I2-0, I2-1, I2-2, ..., I2-31 based on the amplitude control signal Sg7-3 of the upper 5 bits. . For example, the second signal processing circuit 154 outputs the second signal data SIb1 having the second signal value I2-1 (I2) corresponding to the video signal Sg = (00001000). The second signal processing circuit 154 outputs the second signal data SIb31 having the second signal value I2-31 corresponding to the highest gradation video signal Sg = (11111000). The second signal processing circuit 154 outputs the second signal data SIb0 having the second signal value I2-0 (I0) corresponding to the video signal Sg = (00000000). The second signal value I2-0 corresponds to the signal value I0, for example.

The second signal processing circuit 154 outputs the same second signal value I2-1 as the second signal data SIb1 from the first sub-frame SF1 to the third sub-frame SF3, for example. In other words, the second signal values I2-1, I2-2, ..., I2-31 have the same signal value from the first subframe SF1 to the third subframe SF3, respectively. Further, the difference between the second signal values I2-1, I2-2, ..., I2-3 corresponding to the adjacent amplitude control signals Sg7-3 is defined as a difference ΔI2. The difference ΔI2 in the first sub-frame SF1, the difference ΔI2 in the second sub-frame SF2, and the difference ΔI2 in the third sub-frame SF3 are equal.

In other words, the display device 1 is associated with the pixel 49-4 and the video signal SgC (for example, (00001000)) having the tone value GD3 (third tone value) associated with the pixel 49-3. When a video signal SgD (for example, (00010000)) having a grayscale value GD4 (fourth grayscale value) larger than the grayscale value GD3 is input, one frame period F of the inorganic light emitting element 100 of the pixel 49-3 is input. From the luminance (third luminance, for example, the luminance of the inorganic light emitting element 100 turned on by the drive signal corresponding to the second signal value I2-1) in the one-frame period F of the inorganic light emitting element 100 of the pixel 49-4 ( The fourth luminance, for example, the luminance of the inorganic light emitting element 100 that is turned on by the driving signal corresponding to the second signal value I2-2) is driven to be large. Further, for the video signal SgC and the video signal SgD, for example, the period control signal Sg2-0 has the same value and the amplitude control signal Sg7-3 is associated with a different signal. The luminance of the pixel 49-3 and the pixel 49-4 in the one frame period F indicates the maximum luminance in the one frame period F.

FIG. 12 is an explanatory diagram showing the waveform of the third signal data for each different video signal. FIG. 12 shows the third signal data SIc output for each of the different period control signals Sg2-0 when the upper 5 bits of the amplitude control signal Sg7-3 is (00001). That is, the second signal processing circuit 154 outputs the second signal value I2 (I2-1) as the second signal data SIb1 in each subframe SF. According to the amplitude control signal Sg7-3, the arithmetic circuit 155 can output the second signal value I2 and the third signal value I3 having an amplitude different from that of the third signal data SIc shown in FIG.

When the video signal Sg is (00001000), the first signal data SIa has a signal value I0 in each subframe SF (see FIG. 10). Therefore, as shown in FIG. 12, the arithmetic circuit 155 integrates the signal value I0 of the first signal data SIa and the second signal value I2 of the second signal data SIb for each subframe SF. Then, the arithmetic circuit 155 outputs the second signal value I2 as the third signal data SIc over the first subframe SF1 to the third subframe SF3. The second signal value I2 is larger than the first signal value I1.

When the video signal Sg is (000010101), the first signal data SIa has the first signal value I1 in the first subframe SF1 and the signal value I0 in the second subframe SF2 and the third subframe SF3. As shown in FIG. 12, the arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the first sub-frame SF1 to generate the first signal value I2. 3 signal value I3 is output. Here, the third signal value I3 is a signal value (I3 = I1 + I2) obtained by adding the first signal value I1 and the second signal value I2. Further, the arithmetic circuit 155 integrates the signal value I0 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the second sub-frame SF2 and the third sub-frame SF3 to generate a second The signal value I2 is output. The signal values (third signal value I3, second signal value I2) are constant in each subframe SF.

However, the arithmetic circuit 155 is not limited to the case where the first signal value I1 and the second signal value I2 are added to calculate the third signal value I3. That is, the difference (I3-I2) between the third signal value I3 and the second signal value I2 may be different from the difference (I1-I0) between the first signal value I1 and the signal value I0. The third signal data SIc may be a signal corresponding to the gradation of the video signal Sg, and the arithmetic circuit 155 performs a predetermined arithmetic process based on the first signal value I1 and the second signal value I2 to generate a third signal data. The signal value I3 may be calculated.

When the video signal Sg is Sg = (00001010), the first signal data SIa has a first signal value I1 in the second sub-frame SF2 and a signal value I0 in the first sub-frame SF1 and the third sub-frame SF3. . As illustrated in FIG. 12, the arithmetic circuit 155 integrates the signal value I0 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the first subframe SF1 and the third subframe SF3. Then, the second signal value I2 is output. Further, the arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the second sub-frame SF2 to obtain the third signal value I3. Output.

Similarly, when the video signal Sg is Sg = (00001011) or (00001100), the arithmetic circuit 155 similarly causes the first signal value I1 or the signal value I0 of the first signal data SIa and the second value to be calculated for each subframe SF. The second signal value I2 of the signal data SIb is integrated to generate the third signal data SIc. Although FIG. 12 shows the third signal data SIc of 5 gradations, the arithmetic circuit 155 has a combination of 32 gradations of the amplitude control signal Sg7-3 and 8 gradations of the period control signal Sg2-0. , The third signal data SIc corresponding to 256 gradations of the video signal Sg can be output.

The arithmetic circuit 155 outputs the third signal data SIc to the drive circuit 211. The drive circuit 211 outputs a constant current Idata according to the third signal data SIc to the signal line SGL. The gradation of the inorganic light emitting device 100 is determined in accordance with the integrated value of the third signal data SIc, that is, the value obtained by multiplying the time of each subframe SF by the signal value of each subframe SF. As a result, the inorganic light emitting device 100 outputs the drive signal corresponding to the second signal value I2 or the third signal value I3 in which the first signal value I1 and the second signal value I2 are integrated for each sub-frame SF. Corresponding drive signals are supplied to express the gradation.

In other words, the display device 1 is associated with the video signal SgA (for example, (00000001)) having the grayscale value GD1 (first grayscale value) associated with the pixel 49-1 and the pixel 49-5. When a video signal SgE (for example, (00010010)) having a gradation value GD5 (fifth gradation value) larger than the gradation value GD1 is input, one frame period F of the inorganic light emitting element 100 of the pixel 49-1 is input. From the luminance (first luminance, for example, the luminance of the inorganic light emitting element 100 turned on by the drive signal corresponding to the first signal value I1) in the one frame period F of the inorganic light emitting element 100 of the pixel 49-5 (fifth luminance The brightness is increased, for example, the brightness of the inorganic light emitting element 100 that is turned on by the drive signal corresponding to the second signal value I2-2 + the first signal value I1. Note that the luminance of the pixel 49-1 and the pixel 49-5 in one frame period F is the maximum luminance in one frame period F. The brightness of the first sub-frame SF1 and the third sub-frame SF3 of the pixel 49-5 is the brightness (third brightness) of the inorganic light emitting element 100 that is turned on by the drive signal corresponding to the second signal value I2-2. Yes, the luminance of the second sub-frame SF2 of the pixel 49-5 is the fifth luminance.

In addition, the pixel 49-1 and the pixel 49-5 are included in the pixel 49-5 from the lighting period (first lighting period, for example, the first sub-frame SF1) in the one frame period F of the inorganic light emitting element 100 of the pixel 49-1. The inorganic light emitting element 100 is driven so that the lighting period in the one frame period F (fifth lighting period, for example, one frame period F) becomes longer. In addition, the pixel 49-1 and the pixel 49-5 have a lighting period in one frame period at the maximum luminance (for example, the fifth luminance) in one frame period F of the inorganic light emitting element 100 of the pixel 49-1 and the pixel 49-5. Is the maximum luminance lighting period, the maximum luminance lighting period (first maximum luminance lighting period, for example, 0) of the inorganic light emitting element 100 of the pixel 49-1 in one frame period F starts from the maximum luminance lighting period of the pixel 49-5. The maximum luminance lighting period (fifth maximum luminance lighting period, for example, the second sub-frame SF2) in the one frame period F is driven to be long.

The lighting amount of the pixel 49-1 in the one frame period F (first lighting amount = first luminance × first lighting period) is the lighting amount of the pixel 49-5 in the one frame period F (fifth lighting amount = third lighting amount). It is smaller than 3 luminance × (first sub-frame SF1 + third sub-frame SF3) + fifth luminance × (second sub-frame SF2). The gradation value GD5 indicates a gradation value higher than at least one of the gradation value GD2, the gradation value GD3, and the gradation value GD4 described above.

FIG. 13 is a graph showing voltage-current characteristics of the inorganic light emitting device. As shown in FIG. 13, the first signal value I1 is a value near the threshold of the stable operation region P of the inorganic light emitting device 100. The unstable operation region Q of the inorganic light emitting device 100 is a region having a current value smaller than the first signal value I1. The second signal value I2 has a larger current value than the first signal value I1. The third signal value I3 has a larger current value than the second signal value I2. The second signal value I2 and the third signal value I3 are included in the stable operation region P.

The display device 1 of the present embodiment performs gradation control based on the period control signal Sg2-0 and the amplitude control signal Sg7-3. That is, the display device 1 controls the period in which the subframe SF in which the first signal value I1 is output and the subframe SF in which the first signal value I1 is not output are controlled, and the amplitude control by a plurality of different second signal values I2. The gradation control is performed by combining and. Therefore, the display device 1 can operate the inorganic light emitting element 100 in the stable operation region P even in a low gradation, and can suppress variations in the brightness of the inorganic light emitting element 100. Further, the display device 1 is capable of fine gradation control.

(Second embodiment)
FIG. 14 is a graph showing the relationship between the second signal data for each video signal and the subframe in the display device according to the second embodiment. FIG. 15 is an explanatory diagram showing the waveform of the third signal data of the display device according to the second embodiment. In addition, in the following description, the components described in the above-described embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 14, the second signal processing circuit 154 outputs, as the second signal data SIb0-31, the different second signal value I2 for each subframe SF. The plurality of second signal values I2 associated with the amplitude control signal Sg7-3 include a first partial signal value I2a, a second partial signal value I2b, and a third partial signal value I2c. The first partial signal value I2a, the second partial signal value I2b, and the third partial signal value I2c correspond to the first subframe SF1, the second subframe SF2, and the third subframe SF3, respectively, and have different magnitudes. Is the signal value of. In other words, the second signal data SIb is composed of the first partial signal data SIba, the second partial signal data SIbb, and the third partial signal data SIbc.

For example, the second signal processing circuit 154 outputs the first partial signal value I2a-1 in the first subframe SF1 and the second partial signal value I2b-1 in the second subframe SF2 as the second signal data SIb1. And outputs the third partial signal value I2c-1 in the third sub-frame SF3. The first partial signal value I2a-1 of the first subframe SF1 is larger than the second partial signal value I2b-1 of the second subframe SF2. The second partial signal value I2b-1 of the second subframe SF2 is larger than the third partial signal value I2c-1 of the third subframe SF3.

Also, the second signal processing circuit 154 outputs the first partial signal value I2a-31 in the first subframe SF1 and the second partial signal value I2b-31 in the second subframe SF2 as the second signal data SIb31. Then, the third partial signal value I2c-31 is output in the third sub-frame SF3. The difference between the first partial signal value I2a-31 and the second partial signal value I2b-31 on the high gradation side is the difference between the first partial signal value I2a-1 and the second partial signal value I2b-1 on the low gradation side. Greater than the difference.

The first difference ΔIa in the first subframe SF1 is larger than the second difference ΔIb in the second subframe SF2. The second difference ΔIb in the second subframe SF2 is larger than the third difference ΔIc in the third subframe SF3. The shorter the sub-frame SF period, the larger the first difference ΔIa, and the longer the sub-frame SF period, the smaller the third difference ΔIc. The second signal data SIb2-0 indicates the signal value I0 (second signal value I2-0) in any of the first subframe SF1, the second subframe SF2, and the third subframe SF3.

In other words, the display device 1 is associated with the pixel 49-7 and the video signal SgF (for example, (00001000)) having the tone value GD6 (sixth tone value) associated with the pixel 49-6. When a video signal SgG (for example, (00010000)) having a grayscale value GD7 (seventh grayscale value) larger than the grayscale value GD6 is input, the first subframe of the inorganic light emitting element 100 of the pixel 49-6. The first sub-pixel of the inorganic light-emitting element 100 of the pixel 49-7 is calculated from the luminance in SF1 (the 6-1th luminance, for example, the luminance of the inorganic light-emitting element 100 turned on by the drive signal corresponding to the first partial signal value I2a-1). It is driven so that the luminance in the frame SF1 (the 7-1th luminance, for example, the luminance of the inorganic light emitting element 100 which is turned on by the drive signal corresponding to the first partial signal value I2a-2) is increased.Similarly, for the second sub-frame SF2 and the third sub-frame SF3, the luminance of the pixel 49-6 in the second sub-frame SF2 is more than that of the pixel 49-6 in the second sub-frame SF2. The luminance of the pixel 49-6 is larger than that of the pixel 49-6 in the third sub-frame SF3 (sixth-3 luminance), and the luminance of the pixel 49-7 in the third sub-frame SF3 (seventh luminance is the seventh luminance) -3 brightness) is increased. Further, at least one of the pixel 49-6 and the pixel 49-7 (for example, the 6-1th luminance and the 6th-2nd luminance) has different luminance between two different sub-frames SF. In addition, the maximum luminance (for example, the 6-1th luminance) of the inorganic light emitting element 100 of the pixel 49-6 in the 1st frame period F of the inorganic light emitting element 100 of the pixel 49-4 (for example, the 6th luminance). 7-1) brightness is large.

FIG. 15 shows a comparison between the third signal data SIc of the display device 1 of the first embodiment and the third signal data SIc of the display device 1A of the present embodiment. FIG. 15 shows a case where the video signal Sg is (00001011). The first signal data SIa has a first signal value I1 in the first sub-frame SF1 and the third sub-frame SF3 and a signal value I0 in the second sub-frame SF2 according to the lower-order bit period control signal Sg2-0. Have.

As shown in FIG. 15, in the display device 1, the arithmetic circuit 155 calculates the first signal value I1 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the first subframe SF1. The integrated signal is output as the third signal value I3. The arithmetic circuit 155 integrates the signal value I0 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the second subframe SF2, and outputs the second signal value I2. The arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the second signal value I2 of the second signal data SIb in the third sub-frame SF3, and outputs the third signal value I3. .

In the display device 1A of the present embodiment, the arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the first partial signal value I2a of the second signal data SIb in the first sub-frame SF1. Then, the third signal value I3a is output. The arithmetic circuit 155 integrates the signal value I0 of the first signal data SIa and the second partial signal value I2b of the second signal data SIb in the second subframe SF2, and outputs the second signal value I2. The arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa and the third partial signal value I2c of the second signal data SIb in the third sub-frame SF3, and outputs the third signal value I3b. To do. The third signal value I3a is larger than the third signal value I3. The third signal value I3b is smaller than the third signal value I3.

As shown in FIG. 15, the period of each subframe SF is set to a period t1, a period t2, and a period t3. The period of each subframe SF has a relationship of t1 <t2 <t3. In the display device 1A, the signal value change between the first subframe SF1 and the second subframe SF2 is I3a-I2. The signal value change between the second subframe SF2 and the third subframe SF3 is I3b-I2. The signal value change (I3b-I2) between the second subframe SF2 and the third subframe SF3 is smaller than the signal value change (I3a-I2) between the first subframe SF1 and the second subframe SF2. small.

In the display device 1 in the upper diagram of FIG. 15, the signal value change between the first subframe SF1 and the second subframe SF2 and the signal value change between the second subframe SF2 and the third subframe SF3 are both Is also I3-I2. In this case, the lower the lighting frequency of the inorganic light emitting device 100, the more likely the change in brightness is visually recognized. For example, the luminance variation between the second sub-frame SF2 and the third sub-frame SF3 is more visible than the luminance variation between the first sub-frame SF1 and the second sub-frame SF2. In the display device 1A, the change in signal value is smaller as the period of the subframe SF is longer. In other words, the lower the lighting frequency of the inorganic light emitting device 100, the smaller the change in signal value. As a result, in the display device 1A, even if a current change occurs in the one frame period F, it is difficult for the brightness variation to be visually recognized, and it is possible to suppress deterioration in display quality.

In the display device 1 in the upper diagram of FIG. 15 and the display device 1A in the lower diagram, the third signal data SIc satisfies the following equations (1), (2), and (3). As a result, the display device 1A can reduce the signal value change between the second subframe SF2 and the third subframe SF3 without changing the integrated value of the signal value as a whole.

I3 × t1 + I2 × t2 + I3 × t3 = I3a × t1 + I2 × t2 + I3b × t3 (1)
I3a>I3> I3b (2)
I3a-I3> I3-I3b (3)

Although FIG. 15 shows the case where the period control signal Sg2-0 is (101), it can be applied to other period control signals Sg2-0. As shown in FIG. 10, when the period control signal Sg2-0 is (010), (011), (100), (110), a signal change between the second subframe SF2 and the third subframe SF3. Occurs. The second signal processing circuit 154 receives the period control signal Sg2-0 from the first signal processing circuit 153, and when a signal change occurs between the second sub-frame SF2 and the third sub-frame SF3 described above, The second signal data SIb shown in 14 can be applied.

In other words, the display device 1 is associated with the pixel 49-8 and the video signal SgA (for example, (00000001)) having the tone value GD1 (first tone value) associated with the pixel 49-1. When a video signal SgH (for example, (00010010)) having a grayscale value GD8 (eighth grayscale value) larger than the grayscale value GD1 is input, the first subframe of the inorganic light emitting element 100 of the pixel 49-1. The brightness in the first sub-frame SF1 of the inorganic light emitting element 100 of the pixel 49-8 from the brightness in SF1 (first brightness, for example, the brightness of the inorganic light emitting element 100 turned on by the drive signal corresponding to the first signal value I1) ( The 8th luminance, for example, the luminance of the inorganic light emitting element 100 which is turned on by the driving signal corresponding to the first partial signal value I2a-2, is driven to be large. Similarly, in the second sub-frame SF2 and the third sub-frame SF3, the brightness (first brightness) of the pixel 49-1 in the second sub-frame SF2 is the brightness (first brightness) of the pixel 49-8 in the second sub-frame SF2. 8-2 luminance, for example, the luminance of the inorganic light emitting element 100 which is turned on by the drive signal corresponding to the second partial signal value I2b-2 + the first signal value I1), and in the third sub-frame SF3 of the pixel 49-1. The luminance (first luminance) is the luminance of the pixel 49-8 in the third sub-frame SF3 (8th-3rd luminance, for example, the inorganic light emitting element 100 turned on by the drive signal corresponding to the third partial signal value I2c-2). Brightness) is less than. Further, the luminance (first luminance) of the pixel 49-1 in the one frame period F is smaller than the luminance (8th luminance) of the pixel 49-8 in the one frame period F. Note that the luminance of the pixel 49-1 and the pixel 49-8 in one frame period F refers to the maximum luminance in one frame period F.

In addition, the pixel 49-1 and the pixel 49-8 are included in the pixel 49-8 from the lighting period (first lighting period, for example, the first subframe SF1) in the one frame period F of the inorganic light emitting element 100 of the pixel 49-1. The inorganic light emitting device 100 is driven so that the lighting period in the one frame period F (eighth lighting period, for example, one frame period F) becomes longer. In addition, the pixel 49-1 and the pixel 49-8 have a maximum luminance (for example, 8-2 luminance) in one frame period in the one frame period F of the inorganic light emitting element 100 of the pixel 49-1 and the pixel 49-8. When the lighting period is the maximum brightness lighting period, the inorganic light emitting element of the pixel 49-8 starts from the maximum brightness lighting period (first maximum brightness lighting period, for example, 0) in the one frame period F of the inorganic light emitting element 100 of the pixel 49-1. The maximum luminance lighting period (eighth maximum luminance lighting period, for example, the second sub-frame SF2) in one frame period F of 100 is driven to be long. Further, in the pixel 49-1 and the pixel 49-8, the total of the lighting periods at the maximum brightness for each sub-frame SF of the inorganic light emitting element 100 of the pixel 49-1 and the pixel 49-8 is the maximum in one frame period F. In the brightness lighting period, the maximum brightness of the first sub-frame SF1 is the 8-1 brightness, the maximum brightness of the second sub-frame SF2 is the 8-2 brightness, and the maximum brightness of the third sub-frame SF3 is the 8th brightness. Since the brightness is three, the inorganic light-emitting element 100 of the pixel 49-8 can be operated from the total maximum brightness lighting period (first total maximum brightness lighting period, for example, 0) of the inorganic light-emitting element 100 of the pixel 49-1 in one frame period F. The driving is performed so that the total maximum brightness lighting period in the one frame period F (eighth total maximum brightness lighting period, for example, one frame period F) is long.

The lighting amount of the pixel 49-1 in the one frame period F (first lighting amount = first luminance × first lighting period) is the lighting amount of the pixel 49-8 in the one frame period F (eighth lighting amount = third lighting amount). 8-1 luminance × first sub-frame SF1 + 8th-2 luminance × second sub-frame SF2 + 8th-3 luminance × third sub-frame SF3). The gradation value GD8 indicates a gradation value higher than at least one of the gradation value GD2, the gradation value GD6, and the gradation value GD7 described above.

(Third Embodiment)
FIG. 16 is a block diagram showing the configuration of the display device according to the third embodiment. FIG. 17 is a table showing the relationship between the correction signal and the period and current value. FIG. 18 is an explanatory diagram showing the waveform of the fourth signal data for each correction signal. FIG. 19 is an explanatory diagram showing the waveform of the third signal data according to the third embodiment.

As shown in FIG. 16, in the display device 1B of this embodiment, the control circuit 200 has a correction signal output circuit 203. The correction signal output circuit 203 outputs the correction signal Sgc to the first buffer circuit 151. The correction signal Sgc is set for each pixel 49 on the basis of the result of the lighting test, which is performed by performing a lighting test on the plurality of inorganic light emitting elements 100.

As shown in FIG. 17, the correction signal Sgc includes 3-bit correction signals Sgc2, Sgc1, and Sgc0. The correction signal Sgc is associated with the fourth signal value I4. The third sub-frame SF3 is associated with the correction signal Sgc2. The second sub-frame SF2 is associated with the correction signal Sgc1. The first sub-frame SF1 is associated with the correction signal Sgc0.

FIG. 18 shows the fourth signal data SId when the correction signal Sgc is (001), (011), (111). However, the correction signal Sgc is 3-bit data, and like the period control signal Sg2-0, the correction signal output circuit 203 can output the correction signal Sgc of 8 gradations. The plurality of correction signals Sgc shown in FIG. 18 are associated with different pixels 49-1, 49-2, 49-3, respectively.

As shown in FIG. 18, when the correction signal Sgc is (001), the first signal processing circuit 153 outputs the fourth signal value I4 in the first sub-frame SF1 as the fourth signal data SId, and The signal value I0 is output in the frame SF2 and the third sub-frame SF3. When the correction signal Sgc is (011), the first signal processing circuit 153 outputs the fourth signal value I4 as the fourth signal data SId in the first subframe SF1 and the second subframe SF2, and the third subframe The signal value I0 is output at SF3. When the correction signal Sgc = (111), the first signal processing circuit 153 outputs the fourth signal value I4 as the fourth signal data SId in the first subframe SF1, the second subframe SF2, and the third subframe SF3. To do.

The first signal processing circuit 153 may individually output the first signal data SIa based on the period control signal Sg2-0 and the fourth signal data SId to the arithmetic circuit 155. The first signal processing circuit 153 may perform signal processing to integrate the first signal data SIa and the fourth signal data SId for each subframe SF, and output the integrated data to the arithmetic circuit 155.

The upper diagram of FIG. 19 shows the third signal data SIc when the correction signal Sgc is (000), that is, when there is no correction. The lower diagram of FIG. 19 shows the third signal data SIc when the correction signal Sgc is (001), that is, when there is correction.

As shown in the lower diagram of FIG. 19, in the display device 1B of the present embodiment, the arithmetic circuit 155, in the first sub-frame SF1, the first signal value I1 of the first signal data SIa and the second signal value SIb of the second signal data SIb. The signal value I2 and the fourth signal value I4 of the fourth signal data SId are integrated to output the fifth signal value I5. The arithmetic circuit 155 combines the signal value I0 of the first signal data SIa, the second signal value I2 of the second signal data SIb, and the signal value I0 of the fourth signal data SId in the second subframe SF2. , The second signal value I2 is output. The arithmetic circuit 155 integrates the first signal value I1 of the first signal data SIa, the second signal value I2 of the second signal data SIb, and the signal value I0 of the fourth signal data SId in the third sub-frame SF3. Then, the third signal value I3 is output.

The fifth signal value I5 of the first subframe SF1 is larger than the third signal value I3 of the first subframe SF1 when the correction signal Sgc is (000). Further, the fourth signal value I4 is smaller than the difference ΔI2 (see FIG. 11) of the second signal value I2 associated with the amplitude control signal Sg7-3.

The arithmetic circuit 155 outputs the fifth signal data SIe obtained by correcting the third signal data SIc based on the correction signal Sgc to the drive circuit 211. As a result, the drive circuit 211 outputs a signal (constant current Idata) corresponding to the fifth signal data SIE for each of the plurality of pixels 49. As a result, the inorganic light emitting element 100 outputs the drive signal corresponding to the fifth signal value I5, which is the integration of the third signal value I3 and the fourth signal value I4, for each sub-frame SF based on the correction signal Sgc. Supplied. As a result, the inorganic light emitting device 100 can correct the brightness.

When the correction signal Sgc is (011) (see FIG. 18), the arithmetic circuit 155 outputs the fifth signal value I5 in the first sub-frame SF1 and the second signal value in the second sub-frame SF2. A signal value obtained by integrating I2 and the fourth signal value I4 is output. When the correction signal Sgc is (111) (see FIG. 18), the arithmetic circuit 155 outputs the fifth signal value I5 in the first subframe SF1 and the third subframe SF3, and at the same time outputs the second subframe SF2. Then, a signal value obtained by integrating the second signal value I2 and the fourth signal value I4 is output. The correction signal Sgc may have a signal of 4 bits or more. Further, the first signal processing circuit 153 may output a plurality of different fourth signal values I4 as the fourth signal data SId. In this case, the display device 1B can be finely corrected according to the lighting characteristics of the inorganic light emitting element 100.

(Fourth Embodiment)
FIG. 20 is an explanatory diagram for explaining the relationship between subframes and video signals according to the fourth embodiment. FIG. 21 is a circuit diagram showing a configuration example of the pixel circuit according to the fourth embodiment. FIG. 22 is a circuit diagram showing a modified example of the pixel circuit.

As shown in FIG. 20, in the present embodiment, each subframe SF of one frame period F includes a light emitting period PBL and a non-light emitting period PBM. In the light emission period PBL of each subframe SF, gradation control based on the video signal Sg is performed. The gradation control described in the first to third embodiments can also be applied to this embodiment. Further, the duty ratio between the light emitting period PBL and the non-light emitting period PBM can be appropriately changed.

As shown in FIG. 21, the pixel circuit PIC has a driving transistor Tr1, a current switching transistor Tr2, and a switching transistor Tr3 in addition to the current switching transistor Tr2. The gate of the transistor Tr2 is connected to the first gate line GCL1. The transistor Tr3 has a gate connected to the second gate line GCL2, a source connected to the drain of the transistor Tr1, and a drain connected to the anode of the inorganic light emitting device 100.

During the light emission period PBL, when the display device 1 sets the potentials of the first gate line GCL1 and the second gate line GCL2 to high, the transistors Tr1, Tr2, Tr3 are turned on. As a result, the constant current Idata is supplied to the inorganic light emitting element 100 from the signal line SGL. In the non-light emission period PBM, when the display device 1 sets the potentials of the first gate line GCL1 and the second gate line GCL2 to low (Low), the transistors Tr2 and Tr3 are turned off. As a result, the reference potential VCOM as a reverse bias is supplied from the reference potential line LVCOM to the cathode of the inorganic light emitting element 100.

As shown in FIG. 22, in the pixel circuit PIC of the modified example, the transistor Tr3 has a source connected to the cathode wiring 60 and a drain connected to the cathode of the inorganic light emitting element 100. In the non-light emitting period PBM, the display device 1 sets the potential of the first gate line GCL1 to low (Low) and sets the potential of the second gate line GCL2 to high (High). As a result, the transistors Tr1 and Tr2 are turned off and the transistor Tr3 is turned on. As a result, the reference potential VCOM as a reverse bias is supplied from the reference potential line LVCOM to the cathode of the inorganic light emitting element 100.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, replacements, and changes of the constituent elements can be performed without departing from the gist of the above-described embodiments and modified examples.

1 Display Device 2 Array Substrate 10 Substrate 12 Gate Driver 15 Signal Output Circuit 49 Pixel 50e Anode Electrode 60 Cathode Wiring 90e, 90eA Cathode Electrode 100, 100A Inorganic Light Emitting Element 151 First Buffer Circuit 152 Second Buffer Circuit 153 First Signal Processing Circuit 154 Second signal processing circuit 155 Operation circuit 158 Buffer control circuit 159 Subframe counter 210 Drive IC
AA Display area GA Peripheral area LVCC Power supply line LVCOM Reference potential line Tr1, Tr2, Tr3, Tr5 Transistor Sg Video signal Sg2-0, Sg2, Sg1, Sg0 Period control signal Sg7-3, Sg7, Sg6, Sg5, Sg4, Sg3 Amplitude Control signal Sgc Correction signal SIa First signal data SIb Second signal data SIc Third signal data SId Fourth signal data SF1 First subframe SF2 Second subframe SF3 Third subframe I1 First signal value I2 Second signal value I3 third signal value I4 fourth signal value

Claims (11)

1. An inorganic light emitting element provided in each of the plurality of pixels,
   A drive circuit that supplies a drive signal to the plurality of the inorganic light emitting elements based on a period control signal and an amplitude control signal,
   One frame period for displaying an image for one frame includes a plurality of time-divided subframes,
   The period control signal is associated with first signal data for each of the plurality of subframes,
   The amplitude control signal is associated with second signal data indicating any one of a plurality of second signal values having different signal values,
   The inorganic light emitting device expresses gradation by being supplied with the drive signal corresponding to the third signal data in which the first signal data and the second signal data are integrated for each subframe. .
2. The plurality of subframes have periods of different lengths,
   The display device according to claim 1, wherein the subframe in which the first signal data is output and the subframe in which the first signal data is not output are switched based on the period control signal.
3. The display device according to claim 1, wherein the period control signal is associated with a first signal value common to a plurality of the subframes as the first signal data.
4. The display device according to any one of claims 1 to 3, wherein a plurality of the sub-frames are equal to or more than the number of bits of the period control signal.
5. The plurality of second signal data associated with the amplitude control signal have signal values of the same magnitude over the plurality of subframes,
   The display device according to any one of claims 1 to 4.
6. The display device according to claim 1, wherein the plurality of second signal data associated with the amplitude control signal have signal values of different magnitudes for each of the plurality of subframes. .
7. The one frame period includes a first subframe and a second subframe having a longer period than the first subframe,
   The second signal data is associated with any of the plurality of first partial signal values in the first subframe, and is associated with any of the plurality of second partial signal values in the second subframe. And
   The display device according to claim 6, wherein a first difference that is a difference between the plurality of first partial signal values is larger than a second difference that is a difference between the plurality of second partial signal values.
8. The one frame period includes a third subframe having a longer period than the second subframe,
   The plurality of second signal data are associated with any of the plurality of third partial signal values in the third subframe,
   The display device according to claim 7, wherein the second difference is larger than a third difference which is a difference between the plurality of third partial signal values.
9. The said inorganic light emitting element is the 5th signal data which integrated the said 3rd signal data and the 4th signal data matched with the said correction signal based on the correction signal matched with every said some pixel. The display device according to claim 1, wherein the drive signal corresponding to is supplied.
10. The display device according to claim 1, wherein the plurality of sub-frames include a light emitting period and a non-light emitting period.
11. A first signal processing circuit that outputs the first signal data associated with each subframe based on the period control signal;
    A second signal processing circuit that outputs the second signal data associated with the second signal value based on the amplitude control signal;
    The display device according to claim 1, further comprising: an arithmetic circuit that integrates the first signal data and the second signal data for each subframe.

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