WO2020073451A1 - 阵列基板制作方法及阵列基板 - Google Patents

阵列基板制作方法及阵列基板 Download PDF

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Publication number
WO2020073451A1
WO2020073451A1 PCT/CN2018/118056 CN2018118056W WO2020073451A1 WO 2020073451 A1 WO2020073451 A1 WO 2020073451A1 CN 2018118056 W CN2018118056 W CN 2018118056W WO 2020073451 A1 WO2020073451 A1 WO 2020073451A1
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Prior art keywords
layer
gate
metal layer
array substrate
substrate
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PCT/CN2018/118056
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English (en)
French (fr)
Inventor
吴川
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/313,094 priority Critical patent/US10910413B2/en
Publication of WO2020073451A1 publication Critical patent/WO2020073451A1/zh
Priority to US17/133,667 priority patent/US11362119B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the display field, and in particular, to an array substrate manufacturing method and an array substrate.
  • the flat panel display device has many advantages such as wide color gamut and power saving, and is widely used in various fields.
  • the existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD), organic light emitting diode (Organic Light Emitting Diodes, OLED) display devices and quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display devices.
  • a thin film transistor Thin Film Transistor, TFT
  • TFT Thin Film Transistor
  • An object of the present application is to provide a method for manufacturing an array substrate, including but not limited to reducing static buildup on the array substrate and improving the quality of a flat display panel or a flat display device.
  • a method for manufacturing an array substrate including:
  • a protective layer is provided on the insulating layer to cover the active layer.
  • the gate layer is spaced from the metal layer.
  • the gate layer and the metal layer are perpendicular to each other.
  • the metal layer and the gate layer are formed in the same process.
  • the distance between the adjacent metal layer and the gate layer is 3 ⁇ m to 20 ⁇ m.
  • the metal layer is a floating gate layer or a floating electrode layer.
  • the active layer is provided at the intersection of the gate line and the source line.
  • the active layer includes a source layer or a drain layer.
  • the active layer includes a source layer and a drain layer.
  • Another object of the present application is to provide a method for manufacturing an array substrate, including:
  • the gate layer being disposed above the substrate
  • the active layer being provided on the insulating layer
  • a protective layer is provided, the protective layer covers the metal layer and the active layer, and is located on the insulating layer.
  • the metal layer and the active layer are formed in the same process.
  • the metal layer is spaced from the active layer.
  • the distance between the adjacent metal layer and the active layer is 3 ⁇ m to 20 ⁇ m.
  • the metal layer is a floating active layer or a floating electrode layer.
  • the active layer includes a source layer or a drain layer.
  • the active layer includes a source layer and a drain layer.
  • Another object of the present application is to provide an array substrate, including:
  • An insulating layer provided on the substrate
  • a gate layer provided on the substrate, the insulating layer covering the gate layer;
  • An active layer on the insulating layer is an active layer on the insulating layer.
  • it further includes a protective layer provided on the insulating layer and arranged to cover the active layer.
  • the gate layer is spaced from the metal layer.
  • the distance between the adjacent metal layer and the gate layer is 3 ⁇ m to 20 ⁇ m.
  • FIG. 1a is a schematic structural diagram of a display device according to an embodiment of the present application.
  • FIG. 1b is a schematic structural diagram of a pixel unit according to an embodiment of the present application.
  • FIG. 1c is a schematic diagram of a pixel unit configuration of an array substrate according to an embodiment of the present application.
  • FIG. 1d is a cross-sectional view of A1 in FIG. 1c.
  • FIG. 1e is a cross-sectional view of A2 in FIG. 1c.
  • 2a is a schematic diagram of a pixel area of an array substrate according to an embodiment of the application.
  • FIG. 2b is a schematic cross-sectional view of the source line in FIG. 2a along the S1 line.
  • FIG. 2c is a schematic cross-sectional view of the source line in FIG. 2a along the S2 line.
  • FIG. 2d is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G1.
  • FIG. 2e is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G2.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an array substrate manufacturing process according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an array substrate manufacturing process according to another embodiment of this application.
  • FIG. 6 is a schematic diagram of an array substrate manufacturing process according to another embodiment of the present application.
  • FIG. 1a is a schematic structural diagram of an exemplary display device.
  • a display device 200 includes: a control board 100 including a timing module (Timing Controller, TCON) 101; a printed circuit board 103 and a flexible flat cable (Flexible Flat Cable) between the control board 100 and the control board 100 , FFC) 102 is connected; the source driving unit 104 and the gate driving unit 105 are disposed in the wiring area 109, and are respectively connected to the source line 104a and the gate line 105a in the display area.
  • the gate driving unit 105 and the source driving unit 104 include, but are not limited to, flip-chip films.
  • the driving method of the display device 200 includes: the system motherboard provides color (for example: R / G / B) compressed signals, control signals, and power transmission to the control board 100.
  • the Timing Controller (TCON) 101 on the control board 100 and the processing of these signals, together with the power processed by the drive circuit, are transmitted to the printed circuit board through a flexible flat cable (Flexible Flat Cable, FFC) 102 103, the gate driving unit 105 and the source driving unit 104, the gate driving unit 105 and the source driving unit 104 transmit the necessary data and power to the display area, so that the display device 200 obtains the power and signals required to display the picture .
  • FFC Flexible Flat Cable
  • FIG. 1b is a partial schematic diagram of an exemplary equivalent circuit of a pixel unit.
  • FIG. 1c is a schematic diagram of pixel unit configuration of an exemplary array substrate
  • FIG. 1d is a cross-sectional view of A1 in FIG. 1c
  • FIG. 1e is a cross-sectional view of A2 in FIG. 1c.
  • the array substrate 300 includes a substrate 310 including an active switch T, a gate line 105a, a source line 104a, and a pixel electrode P.
  • the active switch T is electrically coupled to the intersection of the gate line 105a and the source line 104a
  • the pixel electrode P is electrically coupled to the active switch T and forms a capacitor with the shared line (Com) C.
  • the gate line 105 a includes a gate layer 320, an insulating layer 330 and a protective layer 350 from the substrate 310.
  • the source line 104 a includes an insulating layer 330, an active layer 340 and a protective layer 350 from the substrate 310.
  • FIG. 2a is a schematic diagram of a pixel area of an array substrate provided by an embodiment of the present application.
  • FIG. 2b is a schematic cross-sectional view of the source line in FIG. 2a along the S1 line.
  • 2c is a schematic cross-sectional view of the source line in FIG. 2a along the S2 line.
  • FIG. 2d is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G1.
  • FIG. 2e is a schematic cross-sectional view of the source line in FIG. 2a taken along the line G2.
  • FIGS. 1a to 1e please refer to FIGS. 1a to 1e to facilitate understanding. Referring to FIG.
  • an array substrate 300 includes: a substrate 310, and the substrate 310 includes a display area configured with a plurality of active switches T and a plurality of pixel electrodes P, a plurality of pixel electrodes P Electrically coupled to a plurality of active switches T; a plurality of driving line segments, disposed on the substrate 310, electrically coupled to a plurality of active switches T, each driving line segment includes: an insulating layer 330, disposed on the substrate 310; a protective layer 350 , Set on the substrate 310, the protective layer 350 covers the insulating layer 330; the metal layer (360a, 360b), set within the coverage of the drive line segment, set to the metal layer (360a, 360b) for floating (floating), this application
  • the floating connections in are all ungrounded; wherein, the metal layer is disposed between the substrate 310 and the insulating layer 330, and at least one part between the insulating layer 330 and the protective layer 350.
  • the electrostatic charge generated in the manufacturing process can be more dispersed and the potential difference can be reduced, even if static electricity occurs in the floating metal layer , Which will cause the floating metal layer to burn, and will not affect the display quality, which can improve the product yield; because the metal layer is disposed between the substrate and the insulating layer, and at least one of the insulating layer and the protective layer
  • the part can be manufactured in the same layer as the drive circuit of the array substrate without increasing the number of photomasks, so the existing production process can not be changed significantly to maintain the original process requirements and product costs.
  • the driving line segment includes a source line 104a, an active layer 340 is disposed between the insulating layer 330 and the protective layer 350, and a metal layer 360a is disposed on the insulating layer Between 330 and the substrate 310.
  • the metal layer 360a is a floating gate layer (Floating Gate) or a floating electrode layer (Floating ITO).
  • the driving line segment includes a gate line 105a, a gate layer 320 at the intersection of the source line 104a and the gate line 105a, the gate layer 320 is disposed between the substrate 310 and the insulating layer 330, and the metal layer 360a is disposed In the adjacent gate layer 320.
  • the metal layer 360a is spaced apart from the two adjacent gate layers 320 by a distance x. Since the signal delay time is inversely proportional to the distance between the metal layer 360a and the gate layer 320, the space between the metal layer 360a and the gate layer 320 is set to effectively shorten the signal delay time, thereby ensuring the user experience.
  • the separation distance x is between 3 microns and 20 microns.
  • the metal layer 360a and the gate layer 320 are perpendicular to each other, so that the overlapping area of the metal layer 360a and the gate layer 320 can be reduced due to the signal delay time and the overlapping area of the metal layer 360a and the gate layer 320 Proportional, therefore, can effectively reduce the signal delay time.
  • the active layer 340 includes a source layer and a drain layer.
  • the driving line segment includes a gate line 105a, a gate layer 320 is provided between the insulating layer 330 and the substrate 310, and a metal layer is provided on the insulating layer 330 and Between the protective layer 350.
  • the metal layer 360b is a floating active layer (Floating SD) or a floating electrode layer (Floating ITO).
  • the driving line segment includes a source line 104a, an active layer 340 at the intersection of the gate line 105a and the source line 104a, an active layer 360b disposed between the insulating layer 330 and the protective layer 350, and a metal layer 360b It is disposed between two adjacent active layers 340.
  • the metal layer 360b is spaced apart from the two adjacent gate layers 340, and the spaced distance is x. Since the signal delay time is inversely proportional to the distance between the metal layer 360b and the gate layer 340, the distance between the metal layer 360b and the gate layer 340 is set to effectively shorten the signal delay time, thereby ensuring the user experience.
  • the separation distance x is between 3 microns and 20 microns.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the method of the present application. Please refer to FIGS. 2a to 2e to facilitate understanding. Please refer to FIG. 1a to FIG. 1e for current display device components.
  • a display panel includes: an array substrate 300; a counter substrate 400, which is opposite to the array substrate 300, and the counter substrate 400 may be a color filter substrate, or a color filter arrangement On the array substrate 300, the counter substrate 400 is a matching substrate configured with necessary components; wherein, the array substrate 300 includes: a substrate 310, including a display area, the display area is configured with a plurality of active switches T and a plurality of pixel electrodes P, a plurality of pixels The electrode P is electrically coupled to a plurality of active switches T; a plurality of driving line segments are provided on the substrate 310, and each of the driving line segments includes: an insulating layer 330, disposed on the substrate 310; protection The layer 350 is disposed on the substrate 310,
  • the array substrate 300 further includes various previous implementation methods.
  • an array substrate 300 includes: a substrate 310 including a display area configured with a plurality of active switches T and a plurality of pixel electrodes P, a plurality of The pixel electrode P is electrically coupled to a plurality of active switches T; a plurality of source lines 104a are disposed on the substrate 310, and are electrically coupled to the plurality of active switches T, and each source line 104a includes: an insulating layer 330 disposed on On the substrate 310; the active layer 340 is disposed between the insulating layer 330 and the protective layer 350; the protective layer 350 is disposed on the substrate 310, the protective layer 350 covers the insulating layer 330 and the active layer 340; a plurality of gate lines 105a , Disposed on the substrate 310, electrically coupled to a plurality of active switches T, each gate line 105a includes: a gate layer 320, disposed on the substrate 310; an insulating layer
  • a method for manufacturing an array substrate includes:
  • step S410 a substrate 310 is provided, and the substrate 310 has a predetermined setting range of the source line.
  • a metal layer 360a is provided on the substrate 310, and the metal layer 360a is disposed within a predetermined setting range of the source line 104a.
  • step S430 a gate layer 320 is formed and disposed on the substrate 310.
  • step S440 an insulating layer 330 is formed.
  • the insulating layer 330 is disposed on the substrate 310 to cover the metal layer 360a and the gate layer 320.
  • step S450 an active layer 340 is formed on the insulating layer 330.
  • a protective layer 350 is formed.
  • the protective layer 350 covers the active layer 340 and is disposed on the insulating layer 330.
  • the metal layer 360a and the gate layer 320 are perpendicular to each other.
  • the metal layer 360a and the gate layer 320 are formed in the same process.
  • the gate layer 320 and the metal layer 360a are disposed perpendicular to each other.
  • the metal layer 360a and the gate layer 320 have a separation distance x.
  • the active layer 340 is disposed at the intersection of the gate line 105a and the source line 104a.
  • the distance between the adjacent metal layer 360a and the gate layer 105a is 3 microns to 20 microns.
  • FIG. 5 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application. Please cooperate with Figure 2a, Figure 2d and Figure 2e at the same time to facilitate understanding.
  • a method for manufacturing an array substrate includes:
  • step S510 a substrate 310 is provided.
  • step S520 a gate layer 320 is formed on the substrate 310.
  • step S530 an insulating layer 330 is formed.
  • the insulating layer 330 covers the gate layer 320 and is disposed on the substrate 310.
  • a metal layer 360b is formed on the insulating layer 330.
  • the metal layer 360 is disposed on the insulating layer and is disposed above the gate layer 320.
  • Step S550 a protective layer 350 is formed, the protective layer 350 covers the metal layer 360b and is disposed on the insulating layer 330;
  • An active layer 340 is formed, and the active layer 340 is provided on the insulating layer 330.
  • the metal layer 360b and the active layer 340 are formed in the same process.
  • FIG. 6 is a schematic diagram showing an embodiment of an array substrate manufacturing process according to the method of the present application. Please cooperate with Figures 2a to 2c at the same time to facilitate understanding.
  • a metal layer 360a (referred to as a first metal layer) is disposed in the range of the source line 104a, and a metal layer 360b (referred to as a second metal layer) is disposed in the range of the gate line 105a.
  • An array substrate manufacturing method including:
  • step S610 a substrate 310 is provided.
  • Step S620 a first metal layer 360a and a gate layer 320 are formed on the substrate 310, the first metal layer 360a is disposed within a predetermined setting range of the source line 104a, and is disposed between the first metal layer 360a and the gate layer 320 With separation distance x.
  • step S630 an insulating layer 330 is formed.
  • the insulating layer 330 covers the metal layer 360a and the gate layer 320 and is disposed on the substrate 310.
  • Step S640 a second metal layer 360b and an active layer 340 are formed on the insulating layer 330, the active layer 340 is located above the first metal layer 360a, and there is a separation distance x between the second metal layer 360b and the active layer 340.
  • the two metal layers 360b are disposed on the insulating layer 330, and are disposed above the gate layer 320.
  • a protective layer 350 is formed.
  • the protective layer 350 covers the second metal layer 360b and the active layer 340 and is disposed on the insulating layer 330.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto, it may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, a curved display panel Or other types of display panels.
  • the electrostatic charge generated in the manufacturing process can be more dispersed and the potential difference can be reduced, even if static electricity occurs in the floating metal layer 360a This will cause the floating metal layer 360a to burn out, which will not affect the display quality, and can improve the product yield.
  • This application does not need to increase the number of photomasks, but only needs to draw the required layers accordingly during design. Therefore, it is not necessary to significantly change the existing production process to maintain the original process requirements and product costs. Because there is no need to adjust the production process, there are no special process requirements and difficulties, so it will not increase costs and is extremely competitive in the market.
  • the setting is not required to increase the area of the array wiring, and is suitable for a variety of display panel designs today. Of course, it is also suitable for the narrow border design of the panel, which is in line with the market and technology trends.
  • the above are only optional embodiments of the present application, and are not intended to limit the present application.
  • the beneficial object of this application is to provide an array substrate, including:
  • the gate layer 320 is provided on the substrate 310;
  • the insulating layer 330 is provided on the substrate 310 and covers the gate layer 320;
  • the active layer 340 is provided on the insulating layer 330;
  • the protective layer 350 is provided on the active layer 340;
  • the metal layer 360a is provided between the substrate 310 and the insulating layer 330 or between the insulating layer 330 and the protective layer 350.
  • the metal layer 360a is disposed between the substrate 310 and the insulating layer 330, and the gate layer 320 is spaced apart from the metal layer 360a.
  • the distance between the adjacent metal layer 360a and the gate layer 320 is 3 microns to 20 microns.
  • the metal layer 360a is disposed between the protective layer 350 and the insulating layer 330, and the active layer 340 is spaced apart from the metal layer 360a.
  • the distance between the adjacent metal layer 360a and the active layer 340 is 3-20 microns.

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Abstract

一种阵列基板制作方法，包括：提供一基板（310）；依序形成金属层（360a）、栅极层（320）、绝缘层（330）与保护层（350）于基板（310）上；其中，形成金属层（360a）于基板（310）上的驱动线路，金属层（360a）设置于基板（310）与绝缘层（330）之间，以及绝缘层（330）与保护层（350）之间的至少其一部位。通过浮接金属层（360a），增加静电释放路径，即使浮接金属层（360a）烧毁，亦不会影响显示品质，较能提高产品良率。同时仅需调整光罩图形，故不需调整生产流程。

Description

阵列基板制作方法及阵列基板 技术领域
本申请涉及显示领域，特别是涉及一种阵列基板制作方法及阵列基板。
背景技术
平板显示装置，其具有色域广、省电等众多优点，在各领域得到广泛应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)，有机发光二极管(Organic Light Emitting Diodes，OLED)显示装置和量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示装置。其中，薄膜晶体管(Thin Film Transistor，TFT)，可形成在玻璃基板或塑料基板上，通常作为主动开关，是平板显示装置的重要组成部分之一。而随着发展，也对显示面板及显示装置提出了更多、更高的要求，如抗静电性能，部分产品由于灵敏度高，因而对主动开关等组件的抗静电性能的要求特别高。
在TFT的生产和制造过程中，会在阵列基板中镀上多个具有不同功能的膜层，而不同的膜层是在不同的机械设备和反应室中完成。一般而言，在镀膜和基板搬运的过程中，基板与其他媒介的接触会产生大量的静电荷，该些静电荷堆积于阵列基板上，当与传送设备接触时，会形成较大的电势差，进而将接触点附近的膜层击穿，严重影响平板显示面板或平板显示装置的质量。
申请内容
本申请的一个目的在于提供一种阵列基板制作方法，包括但不限于减少阵列基板上静电堆积，提升平板显示面板或平板显示装置的质量。
本申请实施例采用的技术方案是：一种阵列基板制作方法，包括：
提供基板，所述基板具有源极线的预定设置范围；
提供金属层，设于所述基板上，所述金属层设置于所述预定设置范围内；
提供栅极层，设于所述源极线与栅极线的交汇处，位于所述基板与所述绝缘层之间；
提供绝缘层，设于所述基板上，设置为覆盖所述金属层以及所述栅极层；
提供有源层，设于所述绝缘层上；
提供保护层，设于所述绝缘层上，设置为覆盖所述有源层。
在一个实施例中，所述栅极层与所述金属层间隔设置。
在一个实施例中，所述栅极层与所述金属层相互垂直设置。
在一个实施例中，所述金属层与所述栅极层于同一制程形成。
在一个实施例中，相邻的所述金属层与所述栅极层的间距为3微米至20微米。
在一个实施例中，所述金属层为浮接的栅极层或浮接的电极层。
在一个实施例中，所述有源层设于所述栅极线与所述源极线的交汇处。
在一个实施例中，所述有源层包括源极层或漏极层。
在一个实施例中，所述有源层包括源极层和漏极层。
本申请的再一目的在于提供一种阵列基板制作方法，包括：
提供基板；
提供栅极层，所述栅极层设于所述基板上方
提供绝缘层，设于所述基板上，覆盖所述栅极层；
提供金属层，设于所述绝缘层上，位于所述栅极层的上方；
提供有源层，所述有源层设于所述绝缘层上；
提供保护层，所述保护层覆盖所述金属层与所述有源层，位于所述绝缘层上。
在一个实施例中，所述金属层与所述有源层于同一制程形成。
在一个实施例中，所述金属层与所述有源层间隔设置。
在一个实施例中，相邻的所述金属层与所述有源的间距为3微米至20微米。
在一个实施例中，所述金属层为浮接的有源层或浮接的电极层。
在一个实施例中，所述有源层包括源极层或漏极层。
在一个实施例中，所述有源层包括源极层和漏极层。
本申请的又一目的在于提供一种阵列基板，包括：
基板；
绝缘层，设于所述基板上；
金属层，设于所述基板上，所述绝缘层覆盖所述金属层；
栅极层，设于所述基板上，所述绝缘层覆盖所述栅极层；
有源层，所述绝缘层上。
在一个实施例中，还包括保护层，设于所述绝缘层上，设置为覆盖所述有源层。
在一个实施例中，所述栅极层与所述金属层间隔设置。
在一个实施例中，相邻的所述金属层与所述栅极层的间距为3微米至20微米。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1a为本申请实施例的显示装置的架构示意图。
图1b为本申请实施例的像素单元结构示意图。
图1c为本申请实施例的阵列基板的像素单元配置示意图。
图1d为图1c的A1剖面图。
图1e为图1c的A2剖面图。
图2a为本申请一实施例的阵列基板的像素区域示意图。
图2b为图2a中源极线就S1剖线的剖面示意图。
图2c为图2a中源极线就S2剖线的剖面示意图。
图2d为图2a中源极线就G1剖线的剖面示意图。
图2e为图2a中源极线就G2剖线的剖面示意图。
图3为本申请实施例的显示面板示意图。
图4为本申请实施例的阵列基板制作流程示意图。
图5为本申请另一实施例的阵列基板制作流程示意图。
图6为本申请又一实施例的阵列基板制作流程示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不 用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1a为范例性的显示装置的架构示意图。请参照图1a，一种显示装置200，包括：控制板100，控制板100包括时序模块(Timing Controller，TCON)101；印刷电路板103，与控制板100之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极驱动单元104与栅极驱动单元105配置于布线区109，分别与显示区内的源极线104a及栅极线105a连接。在一个实施例中，栅极驱动单元105及源极驱动单元104包括但不限制为覆晶薄膜形式。
显示装置200的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的时序控制器(Timing Controller，TCON)101与处理此等信号后，连同被驱动电路处理的电源，通过柔性扁平电缆(Flexible Flat Cable，FFC)102，一并传输至印刷电路板103的栅极驱动单元105及源极驱动单元104，栅极驱动单元105及源极驱动单元104将必要性的数据与电源传输于显示区，从而使得显示装置200获得呈现画面需求的电源、信号。
图1b为范例性的像素单元等效电路局部示意图。图1c为范例性的阵列基板的像素单元配置示意图，图1d为图1c的A1剖面图，图1e为图1c的A2剖面图。请同时配合图1a及图1b以利于了解。阵列基板300包括基板310，其上包括主动开关T、栅极线105a、源 极线104a与像素电极P，主动开关T电性耦接栅极线105a与源极线104a的交集处，像素电极P电性耦接主动开关T，与共享线路(Com)C形成电容。栅极线105a自基板310起包括栅极层320、绝缘层330与保护层350。源极线104a自基板310起包括绝缘层330、有源层340与保护层350。
然而，在显示面板生产制造的过程中，由于基板310与其他媒介的接触会产生大量的静电荷，而这些感应电荷会经金属层吸附后，传输至膜层较薄弱的地方释放，比如栅极层320与有源层340交叠处，有源层340的沟道处。当与传送设备接触时，会形成较大的电势差，进而将接触点附近的膜层击穿，较会影响显示面板、显示装置的质量。
图2a为本申请一实施例提供的阵列基板的像素区域示意图。图2b为图2a中源极线就S1剖线的剖面示意图。图2c为图2a中源极线就S2剖线的剖面示意图。图2d为图2a中源极线就G1剖线的剖面示意图。图2e为图2a中源极线就G2剖线的剖面示意图。范例性的装置架构及组件，请参考图1a至图1e以利于了解。请参照图2a，在本申请一实施例中，一种阵列基板300，包括：基板310，基板310包括显示区，显示区配置多个主动开关T与多个像素电极P，多个像素电极P电性耦接多个主动开关T；多条驱动线段，设置于基板310上，电性耦接多个主动开关T，每一驱动线段包括：绝缘层330，设置于基板310上；保护层350，设置于基板310上，保护层350覆盖绝缘层330；金属层(360a，360b)，设置于驱动线段的涵盖范围内，设置为金属层(360a，360b)为浮接(floating)，本申请中的浮接均为不接地；其中，金属层设置于基板310与绝缘层330之间，以及绝缘层330与保护层350之间的至少其一部位。
本申请实施例通过增加驱动线路的浮接的金属层，增加静电电荷的吸附释放路径，可以使得制造过程中产生的静电荷得以更分散，减小电势差，即便有静电发生在浮接的金属层，造成浮接的金属层有烧毁的情形，也不会影响显示品质，较能提高产品良率；由于金属层设置于基板与绝缘层之间，以及绝缘层与保护层之间的至少其一部位，进而可以和阵 列基板的驱动线路同层制作，进而不用增加光罩数量，故可以不大幅改变现有生产流程，以维持原制程需求和产品成本。因不需调整生产流程，故没有特别的制程要求与难度，故不会提升成本，极具备市场竞争性。而且，不用增加阵列走线面积，适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势。
如图2a、图2b与图2c所绘示，在一个实施例中，驱动线段包括源极线104a，绝缘层330与保护层350之间设置有有源层340，金属层360a设置于绝缘层330与基板310之间。
在一个实施例中，金属层360a为浮接栅极层(Floating Gate)或浮接电极层(Floating ITO)。
在一个实施例中，驱动线段包括栅极线105a，源极线104a与栅极线105a交集处具有栅极层320，栅极层320设置于基板310与绝缘层330之间，金属层360a设置于邻近栅极层320。
在一个实施例中，金属层360a与相邻的两个栅极层320间隔设置，设置为间隔距离为x。由于信号延迟时间与金属层360a与栅极层320的间距成反比，通过将金属层360a以及栅极层320间隔设置，使得有效减短信号延迟时间，进而保障用户体验。
在一个实施例中，间隔距离x为3微米至20微米之间。通过将间距x设置为3微米至20微米之间，使得在保障阵列基板的厚度较低时，减短信号延迟时间。
在一个实施例中，金属层360a与栅极层320相互垂直设置，这样，可降低金属层360a与栅极层320的重叠面积，由于信号延迟时间与金属层360a与栅极层320的重叠面积成正比，因此，可有效减短信号延迟时间。
在一个实施例中，有源层340包括源极层与漏极层。
如图2a、图2d与图2e所绘示，在一个实施例中，驱动线段包括栅极线105a，绝缘层330与基板310之间设置有栅极层320，金属层设置于绝缘层330与保护层350之间。
在一个实施例中，金属层360b为浮接有源层(Floating SD)或浮接电极层(Floating ITO)。
在一个实施例中，驱动线段包括源极线104a，栅极线105a与源极线104a交集处具有有源层340，有源层360b设置于绝缘层330与保护层350之间，金属层360b设置于相邻的两个有源层340之间。
在一个实施例中，金属层360b与相邻的两个栅极层340间隔设置，设置为间隔距离为x。由于信号延迟时间与金属层360b与栅极层340的间距成反比，通过将金属层360b以及栅极层340间隔设置，使得有效减短信号延迟时间，进而保障用户体验。
在一个实施例中，间隔距离x为3微米至20微米之间。通过将间距x设置为3微米至20微米之间，使得在保障阵列基板的厚度较低时，减短信号延迟时间。
图3为显示依据本申请的方法，一实施例显示面板示意图，请配合图2a至图2e以利于理解。现行显示装置组件请同时参阅图1a至图1e。在本申请一实施例中，一种显示面板，包括：阵列基板300；对向基板400，与阵列基板300相对设置，对向基板400可为彩色滤光片基板，或者，彩色滤光片设置于阵列基板300上，对向基板400为配置必要组件的配套基板；其中，阵列基板300包括：基板310，包括显示区，显示区配置多个主动开关T与多个像素电极P，多个像素电极P电性耦接多个主动开关T；多条驱动线段，设置于基板310上，电性耦接多个主动开关T，每一驱动线段包括：绝缘层330，设置于基板310上；保护层350，设置于基板310上，保护层350覆盖绝缘层330；金属层(360a，360b)，设置于驱动线段的涵盖范围内，设置为金属层(360a，360b)为浮接；其中，金属层(360a，360b)设置于基板310与绝缘层330之间，以及绝缘层330与保护层350之间的至少其一部位。
在一个实施例中，阵列基板300还包括先前的各种施行方式。
请参阅如图2a至图2e，在本申请一实施例中，一种阵列基板300，其包括：基板310，包括显示区，显示区配置多个主动开关T与多个像素电极P，多个像素电极P电性耦接多个主动开关T；多条源极线104a，设置于基板310上，电性耦接多个主动开关T，每一源 极线104a包括：绝缘层330，设置于基板310上；有源层340，设置于绝缘层330与保护层350之间；保护层350，设置于基板310上，保护层350覆盖绝缘层330及有源层340；多条栅极线105a，设置于基板310上，电性耦接多个主动开关T，每一栅极线105a包括：栅极层320，设置于基板310上；绝缘层330，设置于栅极层320上；保护层350，设置于基板310上，保护层350覆盖绝缘层330；金属层(360a，360b)，设置于驱动线段的涵盖范围内，设置为金属层(360a，360b)为浮接；其中，金属层(360a，360b)包括浮接栅极层与浮接有源层；浮接栅极层(金属层360a)设置于源极线104a范围的基板310与绝缘层330之间，设置为邻近栅极层320；浮接有源层(金属层360b)设置于栅极线105a范围的保护层350与绝缘层330之间，设置为相邻的两个有源层340之间；有源层340包括源极层与漏极层至少其一；金属层360a与相邻的栅极层320之间间隔3微米至20微米；金属层360b与相邻的有源层340之间间隔3微米至20微米。
图4为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a至图2c以利于理解。本申请的一实施例，以金属层360a设置于源极线104a范围为例，一种阵列基板制作方法，其包括：
步骤S410，提供一基板310，基板310具有源极线的预定设置范围。
步骤S420，提供金属层360a，设于基板310上，金属层360a设置于源极线104a的预定设置范围内。
步骤S430，形成栅极层320，设于基板310上。
步骤S440，形成绝缘层330，绝缘层330设置于基板310上，设置为覆盖金属层360a以及栅极层320。
步骤S450，形成有源层340，设于绝缘层330上。
步骤S460，形成保护层350，保护层350覆盖有源层340而设置于绝缘层330上。
在一个实施例中，金属层360a与栅极层320相互垂直设置。
在一个实施例中，金属层360a与栅极层320于同一制程形成。
在一个实施例中，栅极层320与金属层360a相互垂直设置。
在一个实施例中，金属层360a与栅极层320之间具有间隔距离x。
在一个实施例中，有源层340设于栅极线105a与源极线104a的交汇处。
在一个实施例中，相邻的金属层360a与栅极层105a的间距为3微米至20微米。
图5为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a、图2d与图2e以利于理解。本申请的一实施例，以金属层360b设置于栅极线105a范围为例，一种阵列基板制作方法，其包括：
步骤S510，提供一基板310。
步骤S520，形成栅极层320于基板310上。
步骤S530，形成绝缘层330，绝缘层330覆盖栅极层320而设置于基板310上。
步骤S540，形成金属层360b于绝缘层330上，金属层360设置于绝缘层上，设置为位于栅极层320的上方。
步骤S550，形成保护层350，保护层350覆盖金属层360b而设置于绝缘层330上；
形成有源层340，有源层340设于绝缘层330上。
在一个实施例中，金属层360b与有源层340于同一制程形成。
在一个实施例中，金属层360b与有源层340之间具有间隔距离x。
图6为显示依据本申请的方法，一实施例阵列基板制作流程示意图。请同时配合图2a至图2c以利于理解。本申请的一实施例，以金属层360a(视为第一金属层)设置于源极线104a范围，及金属层360b(视为第二金属层)设置于栅极线105a范围为例。一种阵列基板制作方法，其包括：
步骤S610，提供一基板310。
步骤S620，形成第一金属层360a与栅极层320于基板310上，第一金属层360a设置 于源极线104a的预定设置范围内，设置为第一金属层360a与栅极层320之间具有间隔距离x。
步骤S630，形成绝缘层330，绝缘层330覆盖金属层360a与栅极层320而设置于基板310上。
步骤S640，形成第二金属层360b与有源层340在绝缘层330上，有源层340位于第一金属层360a上方，第二金属层360b与有源层340之间具有间隔距离x，第二金属层360b设置于绝缘层330上，设置为位于栅极层320的上方。
步骤S650，形成保护层350，保护层350覆盖第二金属层360b及有源层340而设置于绝缘层330上。
在一个实施例中，本申请的显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请通过增加驱动线路的浮接的金属层360a，增加静电电荷的吸附释放路径，可以使得制造过程中产生的静电荷得以更分散，减小电势差，即便有静电发生在浮接的金属层360a，造成浮接的金属层360a有烧毁的情形，也不会影响显示品质，较能提高产品良率。本申请不用增加光罩数量，只需在设计时，将所需层别相应画出即可，故可以不大幅改变现有生产流程，以维持原制程需求和产品成本。因不需调整生产流程，故没有特别的制程要求与难度，故不会提升成本，极具备市场竞争性。而设置为，不用增加阵列走线面积，适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势。以上仅为本申请的可选实施例而已，并不用于限制本申请。
本申请的有益目的在于提供一种阵列基板，包括：
基板310；
栅极层320，设于基板310上；
绝缘层330，设于基板310上，覆盖栅极层320；
有源层340，设于绝缘层330上；
保护层350，设于有源层340上；
金属层360a，设于基板310和绝缘层330间或者设于绝缘层330与保护层350之间。
本申请通过增设浮接的金属层360a，增加了静电电荷的释放路径，可以使得制造过程中产生的静电荷得以更分散，减小电势差，即便有静电发生在浮接的金属层360a，造成浮接的金属层360a有烧毁的情形，也不会影响显示品质，较能提高产品良率。
在一个实施例中，金属层360a，设于基板310和绝缘层330间，栅极层320与金属层360a间隔设置。
在一个实施例中，相邻的金属层360a与栅极层320的间距为3微米至20微米。
在一个实施例中，金属层360a设于保护层350和绝缘层330间，有源层340与金属层360a间隔设置。
在一个实施例中，相邻的金属层360a与有源层340的间距为3微米至20微米。
对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (19)

  1. 一种阵列基板制作方法，包括：
    提供基板，所述基板具有源极线的预定设置范围；
    提供金属层，设于所述基板上，所述金属层设置于所述预定设置范围内；
    提供栅极层，设于所述基板上；
    提供绝缘层，设于所述基板上，设置为覆盖所述金属层以及所述栅极层；
    提供有源层，设于所述绝缘层上；
    提供保护层，设于所述绝缘层上，设置为覆盖所述有源层。
  2. 根据权利要求1所述的阵列基板制作方法，其中，所述金属层与所述栅极层间隔设置。
  3. 根据权利要求2所述的阵列基板制作方法，其中，所述栅极层与所述金属层相互垂直设置。
  4. 根据权利要求2所述的阵列基板制作方法，其中，所述金属层与所述栅极层于同一制程形成。
  5. 根据权利要求4所述的阵列基板制作方法，其中，相邻的所述金属层与所述栅极层的间距为3微米至20微米。
  6. 根据权利要求1所述的阵列基板制作方法，其中，在所述的提供栅极层的步骤中，还包括设置栅极线的步骤，所述栅极线与所述栅极层连接，所述有源层设于所述栅极线与所述源极线的交汇处。
  7. 根据权利要求1所述的阵列基板制作方法，其中，所述有源层包括源极层或漏极层。
  8. 根据权利要求1所述的阵列基板制作方法，其中，所述有源层包括源极层和漏极层。
  9. 一种阵列基板制作方法，其特征在于，包括：
    提供基板；
    提供栅极层，所述栅极层设于所述基板上方；
    提供绝缘层，设于所述基板上，覆盖所述栅极层；
    提供金属层，设于所述绝缘层上，位于所述栅极层的上方；
    提供有源层，设于所述绝缘层上；
    提供保护层，所述保护层覆盖所述金属层与所述有源层。
  10. 根据权利要求9所述的阵列基板制作方法，其中，所述金属层与所述有源层于同一制程形成。
  11. 根据权利要求10所述的阵列基板制作方法，其中，所述金属层与所述栅极层间隔设置。
  12. 根据权利要求11所述的阵列基板制作方法，其中，相邻的所述金属层与所述有源层的间距为3微米至20微米。
  13. 根据权利要求9所述的阵列基板制作方法，其中，所述有源层包括源极层或漏极层。
  14. 根据权利要求9所述的阵列基板制作方法，其中，所述有源层包括源极层和漏极层。
  15. 一种阵列基板，包括：
    基板；
    栅极层，设于所述基板上；
    绝缘层，设于所述基板上，覆盖所述栅极层；
    有源层，设于所述绝缘层上；
    保护层，设于所述有源层上；
    金属层，设于所述基板和所述绝缘层之间或者设于所述绝缘层和所述保护层之间。
  16. 如权利要求15所述的阵列基板，其中，所述金属层设于所述基板和所述绝缘层之间，与所述栅极层间隔设置。
  17. 如权利要求16所述的阵列基板，其中，相邻的所述金属层与所述栅极层的间距为3微米至20微米。
  18. 如权利要求15所述的阵列基板，其中，所述金属层设于所述绝缘层和所述保护层之间，与所述有源层间隔设置。
  19. 如权利要求18所述的阵列基板，其中，相邻的所述金属层与所述有源层的间距为3微米至20微米。
PCT/CN2018/118056 2018-10-10 2018-11-29 阵列基板制作方法及阵列基板 Ceased WO2020073451A1 (zh)

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CN104064516A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 阵列基板及其制造方法
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