WO2020069163A1

WO2020069163A1 - Estimation of signal to noise ratio margin for synchronization signal block radio link monitoring out of sync and in sync

Info

Publication number: WO2020069163A1
Application number: PCT/US2019/053207
Authority: WO
Inventors: Zhibin Yu; Hua Li; Jie Cui; Qiming Li; Yang Tang
Original assignee: Intel Corporation
Priority date: 2018-09-28
Filing date: 2019-09-26
Publication date: 2020-04-02
Also published as: EP3857743A4; EP3857743A1

Abstract

Embodiments of the present disclosure provide techniques for determining margins for signal-to-noise ratio (SNR) levels during an out-of-sync test and/or in-sync test for a user equipment (UE). Other embodiments may be described and claimed.

Description

ESTIMATION OF SIGNAL TO NOISE RATIO MARGIN FOR SYNCHRONIZATION SIGNAL BLOCK RADIO LINK MONITORING OUT OF SYNC AND IN SYNC

Cross Reference to Related Application

The present application claims priority to U.S. Provisional Patent Application No.

62/739,013, filed September 28, 2018, and entitled“METHOD TO ESTIMATE SIGNAL TO NOISE RATIO MARGIN FOR SYNCHRONIZATION SIGNAL BLOCK RADIO LINK MONITORING OUT OF SYNC AND IN SYNC.”

Field

Embodiments of the present invention relate generally to the technical field of wireless communications.

Background

For synchronization signal block (SSB) based radio link monitoring (RLM) out of sync (OOS) and in sync (INS) tests, signal-to-noise ratio (SNR) margin is important to make sure that the margin is enough to distinguish the OOS and INS. The legacy Long Term Evolution (LTE) SNR margin cannot be used for new radio (NR).

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 illustrates a network in accordance with some embodiments.

Figure 2 illustrates signal to noise ratio (SNR) test signal levels for out of sync testing in accordance, with some embodiments.

Figure 3 illustrates SNR test signal levels for in sync testing, in accordance with some embodiments.

Figure 4 illustrates simulation results for SNR estimation error based on SSB, in accordance with some embodiments.

Figure 5 illustrates the cumulative distribution function (CDF) curve of estimated SNR when SNR3 = -l6dB, in accordance with some embodiments.

Figure 6 illustrates CDF of estimated SNR when SNR3 = -l4dB, in accordance with some embodiments.

Figure 7 illustrates an operation flow/algorithmic structure in accordance with some embodiments.

Figure 8 illustrates an operation flow/algorithmic structure in accordance with some embodiments. Figure 9 illustrates an operation flow/algorithmic structure in accordance with some embodiments.

Figure 10 illustrates an example of infrastructure equipment in accordance with various embodiments.

Figure 11 depicts example components of a computer platform or device in accordance with various embodiments.

Figure 12 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (for example, a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein.

Detailed Description

The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail. For the purposes of the present document, the phrases“A or B” and“A/B” mean (A), (B), or (A and B).

Figure 1 illustrates a network 100 in accordance with some embodiments. In general, the components shown in the network 100 may be similar to, and substantially interchangeable with, like-named components in other figures described herein. The network 100 may include a UE 104 to communicate with a base station 108 of a radio access network (RAN) 112 using one or more radio access technologies.

The base station 108 may be referred to as a base station (“BS”), NodeB, evolved NodeB (“eNB”), next generation NodeB (“gNB”), RAN node, Road Side Unit (“RSU”), and so forth, and can comprise a ground station (e.g., a terrestrial access point) or a satellite station providing coverage within a geographic area (for example, a cell). An RSU may refer to any transportation infrastructure entity implemented in or by a gNB/eNB/RAN node or a stationary (or relatively stationary) UE, where an RSU implemented in or by a UE may be referred to as a“UE-type RSU,” and an RSU implemented in or by an gNB may be referred to as a“gNB-type RSU.”

In some embodiments, the RAN may be a next generation (“NG”) radio access network (“RAN”), in which case the base station 108 may be a gNB that communicates with the UE 104 using a new radio (“NR”) access technology. Accordingly, the RAN 112 may be a NR wireless cellular network.

The UE 104 may be any mobile or non-mobile computing device that is connectable to one or more cellular networks. For example, the UE 104 may be a smartphone, a laptop computer, a desktop computer, a vehicular computer, a smart sensor, etc. In some embodiments, the UE 104 may be an Internet of Things (“IoT”) UE, which may include a network access layer designed for low-power IoT applications utilizing short-lived UE connections. An IoT UE can utilize technologies such as machine-to-machine (“M2M”) or machine-type communications (“MTC”) for exchanging data with an MTC server or device via a public land mobile network (“PLMN”), Proximity-Based Service (“ProSe”) or device-to-device (“D2D”) communication, sensor networks, or IoT networks. The M2M or MTC exchange of data may be a machine- initiated exchange of data. An IoT network describes interconnecting IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. The IoT UEs may execute background applications (for example, keep-alive messages, status updates, etc.) to facilitate the connections of the IoT network.

In accordance with some embodiments, the UE 104 can be configured to communicate using Orthogonal Frequency -Division Multiplexing (“OFDM”) communication signals with the base station 108 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, an Orthogonal Frequency -Division Multiple Access (“OFDMA”) communication technique (for example, for downlink

communications) or a Single Carrier Frequency Division Multiple Access (“SC-FDMA”) communication technique (for example, for uplink or sidelink communications), although the scope of the embodiments is not limited in this respect. The OFDM signals can comprise a plurality of orthogonal subcarriers.

In some embodiments, a downlink resource grid can be used for downlink transmissions from the base station 108 to the UE 104, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time-frequency unit in a resource grid is denoted as a resource element. Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical channels that are conveyed using such resource blocks.

In various embodiments, the UE 104 may perform radio link monitoring, in which the UE 104 may make measurements of signal quality on one or more cells. The UE 104 may perform the measurements on a reference signal, such as a synchronization signal (SS)/physical broadcast channel (PBCH) block (SSB). The measurements may include one or more of a received signal received power (RSRP), a received signal received quality (RSRQ), a signal to interference plus noise ratio (SINR), and/or another suitable measurement.

As part of radio link monitoring, the UE 104 may determine it is out of sync with a cell if the signal quality is below an out-of-sync threshold Qout. The UE 104 may determine it is in sync (e.g., after being out of sync) with the cell if the signal quality is greater than an in-sync threshold Qin. The threshold Qout may correspond to a level at which the downlink radio link cannot be reliably received (e.g., the physical downlink control channel (PDCCH) cannot be successfully received). The threshold Qin may correspond to a level at which the downlink radio link quality can be significantly more reliably received than at Qout. In some embodiments, the threshold Qout may correspond to a block error rate (BLER) of 10% and/or the threshold Qin may correspond to a BLER of 2%.

In various embodiments, the UE 104 may perform out of sync (OOS) and in sync (INS) tests. The OOS and INS tests may validate the UE performance requirements with respect to radio link monitoring. Various embodiments herein describe techniques to determine SNR margin for NR SSB-based radio link monitoring OOS and INS tests. Additionally, various embodiments define Ll- received signal received power (RSRP) measurement period and accuracy for beam reporting.

For out-of-sync and in-sync tests, the SNR of a downlink test signal is changed at different time instants as per the required target SNR as shown in Figure 1 (out-of-sync test) and Figure 2 (in-sync test). For example, the SNR may be sequentially adjusted to have five different SNR levels, referred to as SNR1, SNR2, SNR3, SNR4, and SNR5. Each SNR level may be maintained for a respective time period (which may be different or the same for different signal levels). The test signal may be transmitted by the base station 108 (e.g., a base station of the wireless cellular network, or a test apparatus that emulates a base station for purposes of performing the OOS and INS tests).

In various embodiments, the test SNR signal levels SNR1-SNR5 may be determined according to:

1. SNR2 = Qout + margin 1 dB 2. SNR3 = Qout - margin 1 dB

3. SNR4 = Qin - margin2 dB

4. SNR5 = Qin + margin2 dB

5. SNR1 = SNR5.

Various embodiments may be directed to techniques to determine the values for margin 1 and/or margin 2 for the OOS and INS tests.

There is an agreed physical downlink control channel (PDCCH) simulation configuration for the OOS and INS tests. For test case 1 of FR1, which may represent Frequency Range 1 (FR1), e.g., 450 MHz-6 GHz, the channel is tapped delay line (TDL)-C and antenna is 2*2. Bandwidth (BW) is lOMHz with subcarrier spacing (SCS) =l5kHz.

In embodiments, the techniques of LTE may be used and still set marginl=3dB of fading channel. If the user equipment (UE) will declare Qout, SNR3 and SNRout should be distinguished. The gap of SNR3 and SNRout is 3dB. From simulation results of PDCCH block error ratio (BLER), the OOS SNR point (e.g., corresponding to Qout) is -1 ldB after power boosting for NR RLM. Then the SNR3 and SNR2 should be -14 dB and -8dB respectively.

Simulation results for Signal to Interference and Noise Ratio (SINR) estimation is provided in Fig.3. The SINR estimation error is 3.7dB for SNR=-l4dB with 10 samples. If ldB margin is considered, the total estimation error is 4.7 dB which is larger than 3dB.

In some embodiments, margin 1 may be determined according to a cumulative distribution function (CDF) curve of measured SNR to make sure that the detection probability of OOS is larger than 80%.

If the marginl is 5dB, then:

SNR2 = Qout + marginl dB = -6dB

SNR3 = Qout - marginl dB = -l6dB

Alternatively, if the marginl is 4dB, then:

SNR2 = Qout + marginl dB = -7dB

SNR3 = Qout - marginl dB = -l5dB

The CDF of estimated SNR when SNR3= -l6dB is plotted in Fig.4. It shows that the estimated SNR is lower than SNRout= -l ldB in 85% cases, then UE can declare OOS in 85% cases.

In embodiments, if the legacy LTE margin 1 of 3 dB is used, the CDF of estimated SNR when SNR3= -l4dB is plotted in Fig.5. It shows that UE can declare OOS in only 70% cases. When marginl increases to 5dB, the detection probability of OOS can increase to 85%. Therefore, in embodiments, the marginl to derive SNR2 and SNR3 should be modified from the value used for LTE. According to some embodiments, margin 1 can be set to be 4 or 5dB to improve the detection probability of OOS.

Another option is that marginl may be different (not identical) for SNR2 and SNR3, for example,

SNR2 = Qout + marginl a dB

SNR3 = Qout - marginl b dB

Where marginl a and marginl b are not identical. In this way, the SNR2 and SNR3 are beter distinguished.

In embodiments, for a Qin test, the methodology of LTE may be followed and still set margin2=2.5dB of fading channel. From simulation results, the INS SNR point (e.g., corresponding to the INS threshold Qin) is -2dB. Then, with the margin2 of 2.5dB, the SNR4 and SNR5 would be -4.5dB and 0.5dB, respectively. From simulation results, the SINR estimation error is less than 1.5 dB for SNR4 and SNR5. If 1 dB margin is considered, the total estimation error is within 2.5dB. Therefore, in embodiments, the margin2 to derive SNR4 and SNR5 can be 2.5dB. Accordingly, with Qin of -2dB:

SNR4 = Qin - margin2 dB = -4.5dB

SNR5 = Qin + margin2 dB = 0.5dB

In some embodiments, the margin2 may be different to derive SNR4 and SNR5 (whether or not the marginl is different to derive SNR2 and SNR3, as described above). For example,

SNR4 = Qin - margin2a dB

SNR5 = Qin + margin2b dB

Where margin2a and margin2b are different (not identical). The different margins may beter distinguish SNR4 and SNR5, SNR2 and SNR3.

For example, in some embodiments margin2a may be 2.5dB and margin2b may be 3dB. Accordingly, with Qin of -2dB:

SNR4 = Qin - margin2a dB = -4.5dB

SNR5 = Qin + margin2b dB = ldB

Figure 7 illustrates an operation flow/algorithmic structure 700 in accordance with some embodiments. The operation flow/algorithmic structure 700 may be performed, in part or in whole, by the base station 108 or components thereof (e.g., a gNB of a wireless cellular network, or a test apparatus that emulates a gNB for purposes of conducting the OOS and INS tests). For example, in some embodiments the operation flow/algorithmic structure 700 may be performed by the baseband circuitry implemented in the base station 108. In some embodiments, the operation flow/algorithmic structure 700 may implement INS and/or OOS tests for a UE (e.g., UE 104).

The operation flow/algorithmic structure 700 may include, at 704, transmitting or causing transmission of a downlink signal, to the UE, with a first target signal-to-noise ratio (SNR).

The operation flow/algorithmic structure 700 may further include, at 708, adjusting the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR has a value equal to Qout plus a first margin, wherein Qout corresponds to an out-of- sync threshold of the UE, and wherein the first margin is 4 decibels (dB) or 5 dB. In some embodiments, the out-of-sync threshold may correspond to an SNR of -11 dB.

The operation flow/algorithmic structure 700 may further include, at 712, adjusting the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR has a value equal to Qout minus a second margin. In some embodiments, the second margin may be the same as the first margin (e.g., 4 or 5 dB). In other embodiments, the second margin may be different than the first margin.

In some embodiments, when the operation flow/algorithmic structure 700 implements the INS test, the operation flow/algorithmic structure 700 may further include adjusting the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR has a value equal to Qin minus a third margin, wherein Qin corresponds to an in-sync threshold of the UE; and adjusting the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR has a value equal to Qin plus a fourth margin, and wherein the fourth margin is different than the third margin.

Figure 8 illustrates another operation flow/algorithmic structure 800 in accordance with some embodiments. The operation flow/algorithmic structure 800 may be performed, in part or in whole, by the base station 108 or components thereof (e.g., a gNB of a wireless cellular network, or a test apparatus that emulates a gNB for purposes of conducting the OOS and INS tests). For example, in some embodiments the operation flow/algorithmic structure 800 may be performed by the baseband circuitry implemented in the base station 108. In some

embodiments, the operation flow/algorithmic structure 800 may implement INS and/or OOS tests for a UE (e.g., UE 104).

The operation flow/algorithmic structure 800 may include, at 804, transmitting or causing transmission of a downlink signal, to the UE, with a first target signal-to-noise ratio (SNR). The operation flow/algorithmic structure 800 may further include, at 808, adjusting the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR is -7 dB.

The operation flow/algorithmic structure 800 may further include, at 812, adjusting the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR is -15 dB.

In some embodiments, when the operation flow/algorithmic structure 800 implements the INS test, the operation flow/algorithmic structure 800 may further include adjusting the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR is -4.5 dB; and adjusting the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR is 1.

Figure 9 illustrates an operation flow/algorithmic structure 900 in accordance with some embodiments. The operation flow/algorithmic structure 900 may be performed, in part or in whole, by the UE 104 or components thereof. For example, in some embodiments the operation flow/algorithmic structure 900 may be performed by the baseband circuitry implemented in the UE 104. In some embodiments, the operation flow/algorithmic structure 900 may implement INS and/or OOS tests for the UE.

The operation flow/algorithmic structure 900 may include, at 904, receiving a downlink test signal that has a first target signal-to-noise ratio (SNR) for a first time period, a second target SNR for a second time period after the first time period, and a third target SNR for a third time period after the second time period, wherein the second target SNR is -7 dB, and wherein the third target SNR is -15 dB.

The operation flow/algorithmic structure 900 may further include, at 908, determining that a signal quality of the downlink test signal during the third time period is lower than an out- of-sync threshold of the UE.

The operation flow/algorithmic structure 900 may further include, at 912, generating an out-of-sync indication based on the determination.

In some embodiments, when the operation flow/algorithmic structure 900 implements the INS test, the operation flow/algorithmic structure 900 the downlink test signal may further have a fourth target SNR for a fourth time period after the third time period, wherein the fourth target SNR is -4.5 dB; and a fifth target SNR for a fifth time period after the fourth time period, wherein the fifth target SNR is 1. The UE may determine that a signal quality of the downlink test signal during the fifth time period is greater than an in-sync threshold of the UE. The UE may generate an in-sync indication based on the determination that the signal quality is greater than the in-sync threshold Figure 10 illustrates an example of infrastructure equipment 1000 in accordance with various embodiments. The infrastructure equipment 1000 (or “system 1000”) may be implemented as a base station, radio head, RAN node such as the base station 108 shown and described previously, and/or any other element/device discussed herein. In other examples, the system 1000 could be implemented in or by a UE.

The system 1000 includes application circuitry 1005, baseband circuitry 1010, one or more radio front end modules (RFEMs) 1015, memory circuitry 1020, power management integrated circuitry (PMIC) 1025, power tee circuitry 1030, network controller circuitry 1035, network interface connector 1040, satellite positioning circuitry 1045, and user interface 1050. In some embodiments, the device 1000 may include additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device. For example, said circuitries may be separately included in more than one device for CRAN, vBBU, or other like implementations.

Application circuitry 1005 includes circuitry such as, but not limited to one or more processors (or processor cores), cache memory, and one or more of low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I²C or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose input/output (I/O or IO), memory card controllers such as Secure Digital (SD) MultiMediaCard (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports. The processors (or cores) of the application circuitry 1005 may be coupled with or may include memory /storage elements and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the system 1000. In some implementations, the memory /storage elements may be on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology, such as those discussed herein.

The processor(s) of application circuitry 1005 may include, for example, one or more processor cores (CPUs), one or more application processors, one or more graphics processing units (GPUs), one or more reduced instruction set computing (RISC) processors, one or more Acom RISC Machine (ARM) processors, one or more complex instruction set computing (CISC) processors, one or more digital signal processors (DSP), one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, or any suitable combination thereof. In some embodiments, the application circuitry 1005 may comprise, or may be, a special- purpose processor/controller to operate according to the various embodiments herein. As examples, the processor(s) of application circuitry 1005 may include one or more Intel Pentium®, Core®, or Xeon® processor(s); Advanced Micro Devices (AMD) Ryzen® processor(s), Accelerated Processing Units (APUs), or Epyc® processors; ARM-based processor(s) licensed from ARM Holdings, Ltd. such as the ARM Cortex-A family of processors and the ThunderX2® provided by Cavium(TM), Inc.; a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior P-class processors; and/or the like. In some embodiments, the system 1000 may not utilize application circuitry 1005, and instead may include a special-purpose processor/controller to process IP data received from an EPC or 5GC, for example.

In some implementations, the application circuitry 1005 may include one or more hardware accelerators, which may be microprocessors, programmable processing devices, or the like. The one or more hardware accelerators may include, for example, computer vision (CV) and/or deep learning (DL) accelerators. As examples, the programmable processing devices may be one or more a field-programmable devices (FPDs) such as field-programmable gate arrays (FPGAs) and the like; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high- capacity PLDs (HCPLDs), and the like; ASICs such as structured ASICs and the like; programmable SoCs (PSoCs); and the like. In such implementations, the circuitry of application circuitry 1005 may comprise logic blocks or logic fabric, and other interconnected resources that may be programmed to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such embodiments, the circuitry of application circuitry 1005 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), anti-fuses, etc.)) used to store logic blocks, logic fabric, data, etc. in look-up-tables (LUTs) and the like.

The baseband circuitry 1010 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

User interface circuitry 1050 may include one or more user interfaces designed to enable user interaction with the system 1000 or peripheral component interfaces designed to enable peripheral component interaction with the system 1000. User interfaces may include, but are not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., light emitting diodes (LEDs)), a physical keyboard or keypad, a mouse, a touchpad, a touchscreen, speakers or other audio emitting devices, microphones, a printer, a scanner, a headset, a display screen or display device, etc. Peripheral component interfaces may include, but are not limited to, a nonvolatile memory port, a universal serial bus (USB) port, an audio jack, a power supply interface, etc.

The radio front end modules (RFEMs) 1015 may comprise a millimeter wave (mmWave) RFEM and one or more sub-mmWave radio frequency integrated circuits (RFICs). In some implementations, the one or more sub-mmWave RFICs may be physically separated from the mmWave RFEM. The RFICs may include connections to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In alternative implementations, both mmWave and sub-mmWave radio functions may be implemented in the same physical RFEM 1015, which incorporates both mmWave antennas and sub-mmWave.

The memory circuitry 1020 may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous dynamic random access memory (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc., and may incorporate the three- dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®. Memory circuitry 1020 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

The PMIC 1025 may include voltage regulators, surge protectors, power alarm detection circuitry, and one or more backup power sources such as a battery or capacitor. The power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions. The power tee circuitry 1030 may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the infrastructure equipment 1000 using a single cable.

The network controller circuitry 1035 may provide connectivity to a network using a standard network interface protocol such as Ethernet, Ethernet over GRE Tunnels, Ethernet over Multiprotocol Label Switching (MPLS), or some other suitable protocol. Network connectivity may be provided to/from the infrastructure equipment 1000 via network interface connector 1040 using a physical connection, which may be electrical (commonly referred to as a“copper interconnect”), optical, or wireless. The network controller circuitry 1035 may include one or more dedicated processors and/or FPGAs to communicate using one or more of the aforementioned protocols. In some implementations, the network controller circuitry 1035 may include multiple controllers to provide connectivity to other networks using the same or different protocols.

The positioning circuitry 1045 includes circuitry to receive and decode signals transmitted/broadcasted by a positioning network of a global navigation satellite system (GNSS). Examples of navigation satellite constellations (or GNSS) include United States’ Global Positioning System (GPS), Russia’s Global Navigation System (GLONASS), the European Union’s Galileo system, China’s BeiDou Navigation Satellite System, a regional navigation system or GNSS augmentation system (e.g., Navigation with Indian Constellation (NAVIC), Japan’s Quasi-Zenith Satellite System (QZSS), France’s Doppler Orbitography and Radio positioning Integrated by Satellite (DORIS), etc.), or the like. The positioning circuitry 1045 comprises various hardware elements (e.g., including hardware devices such as switches, filters, amplifiers, antenna elements, and the like to facilitate OTA communications) to communicate with components of a positioning network, such as navigation satellite constellation nodes. In some embodiments, the positioning circuitry 1045 may include a Micro-Technology for Positioning, Navigation, and Timing (Micro-PNT) IC that uses a master timing clock to perform position tracking/estimation without GNSS assistance. The positioning circuitry 1045 may also be part of, or interact with, the baseband circuitry 1010 and/or RFEMs 1015 to communicate with the nodes and components of the positioning network. The positioning circuitry 1045 may also provide position data and/or time data to the application circuitry 1005, which may use the data to synchronize operations with various infrastructure (e.g., RAN nodes, etc.), or the like.

The components shown by Figure 10 may communicate with one another using interface circuitry, which may include any number of bus and/or interconnect (IX) technologies such as industry standard architecture (ISA), extended ISA (EISA), peripheral component interconnect (PCI), peripheral component interconnect extended (PCIx), PCI express (PCIe), or any number of other technologies. The bus/IX may be a proprietary bus, for example, used in a SoC based system. Other bus/IX systems may be included, such as an I²C interface, an SPI interface, point to point interfaces, and a power bus, among others.

Figure 11 illustrates an example of a platform 1100 (or“device 1100”) in accordance with various embodiments. In embodiments, the computer platform 1100 may be suitable for use as a UE, such as UE 104, and/or any other element/device discussed herein. The platform 1100 may include any combinations of the components shown in the example. The components of platform 1100 may be implemented as integrated circuits (ICs), portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or a combination thereof adapted in the computer platform 1100, or as components otherwise incorporated within a chassis of a larger system. The block diagram of Figure 11 is intended to show a high level view of components of the computer platform 1100. However, some of the components shown may be omitted, additional components may be present, and different arrangement of the components shown may occur in other implementations. Application circuitry 1105 includes circuitry such as, but not limited to one or more processors (or processor cores), cache memory, and one or more of LDOs, interrupt controllers, serial interfaces such as SPI, I²C or universal programmable serial interface module, RTC, timer- counters including interval and watchdog timers, general purpose I/O, memory card controllers such as SD MMC or similar, USB interfaces, MIPI interfaces, and JTAG test access ports. The processors (or cores) of the application circuitry 1105 may be coupled with or may include memory /storage elements and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the system 1100. In some implementations, the memory /storage elements may be on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology, such as those discussed herein.

The processor(s) of application circuitry 1005 may include, for example, one or more processor cores, one or more application processors, one or more GPUs, one or more RISC processors, one or more ARM processors, one or more CISC processors, one or more DSP, one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, a multithreaded processor, an ultra-low voltage processor, an embedded processor, some other known processing element, or any suitable combination thereof. In some embodiments, the application circuitry 1005 may comprise, or may be, a special-purpose processor/controller to operate according to the various embodiments herein.

As examples, the processor(s) of application circuitry 1105 may include an Intel® Architecture Core™ based processor, such as a Quark™, an Atom™, an i3, an i5, an i7, or an MCU-class processor, or another such processor available from Intel® Corporation, Santa Clara, CA. The processors of the application circuitry 1105 may also be one or more of Advanced Micro Devices (AMD) Ryzen® processor(s) or Accelerated Processing Units (APUs); A5-A9 processor(s) from Apple® Inc., Snapdragon™ processor(s) from Qualcomm® Technologies, Inc., Texas Instruments, Inc.® Open Multimedia Applications Platform (OMAP)™ processor(s); a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior M-class, Warrior I- class, and Warrior P-class processors; an ARM-based design licensed from ARM Holdings, Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M family of processors; or the like. In some implementations, the application circuitry 1105 may be a part of a system on a chip (SoC) in which the application circuitry 1105 and other components are formed into a single integrated circuit, or a single package, such as the Edison™ or Galileo™ SoC boards from Intel® Corporation.

Additionally or alternatively, application circuitry 1105 may include circuitry such as, but not limited to, one or more a field-programmable devices (FPDs) such as FPGAs and the like; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), and the like; ASICs such as structured ASICs and the like; programmable SoCs (PSoCs); and the like. In such embodiments, the circuitry of application circuitry 1105 may comprise logic blocks or logic fabric, and other interconnected resources that may be programmed to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such embodiments, the circuitry of application circuitry 1105 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), anti-fuses, etc.)) used to store logic blocks, logic fabric, data, etc. in look-up tables (LUTs) and the like.

The baseband circuitry 1110 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

The RFEMs 1115 may comprise a millimeter wave (mmWave) RFEM and one or more sub-mmWave radio frequency integrated circuits (RFICs). In some implementations, the one or more sub-mmWave RFICs may be physically separated from the mmWave RFEM. The RFICs may include connections to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In alternative implementations, both mmWave and sub-mmWave radio functions may be implemented in the same physical RFEM 1115, which incorporates both mmWave antennas and sub-mmWave.

The memory circuitry 1120 may include any number and type of memory devices used to provide for a given amount of system memory. As examples, the memory circuitry 1120 may include one or more of volatile memory including random access memory (RAM), dynamic RAM (DRAM) and/or synchronous dynamic RAM (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc. The memory circuitry 1120 may be developed in accordance with a Joint Electron Devices Engineering Council (JEDEC) low power double data rate (LPDDR)-based design, such as LPDDR2, LPDDR3, LPDDR4, or the like. Memory circuitry 1120 may be implemented as one or more of solder down packaged integrated circuits, single die package (SDP), dual die package (DDP) or quad die package (Q17P), socketed memory modules, dual inline memory modules (DIMMs) including microDIMMs or MiniDIMMs, and/or soldered onto a motherboard via a ball grid array (BGA). In low power implementations, the memory circuitry 1120 may be on-die memory or registers associated with the application circuitry 1105. To provide for persistent storage of information such as data, applications, operating systems and so forth, memory circuitry 1120 may include one or more mass storage devices, which may include, inter alia, a solid state disk drive (SSDD), hard disk drive (HDD), a micro HDD, resistance change memories, phase change memories, holographic memories, or chemical memories, among others. For example, the computer platform 1100 may incorporate the three-dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®.

Removable memory circuitry 1123 may include devices, circuitry, enclosures/housings, ports or receptacles, etc. used to couple portable data storage devices with the platform 1100. These portable data storage devices may be used for mass storage purposes, and may include, for example, flash memory cards (e.g., Secure Digital (SD) cards, microSD cards, xD picture cards, and the like), and USB flash drives, optical discs, external HDDs, and the like.

The platform 1100 may also include interface circuitry (not shown) that is used to connect external devices with the platform 1100. The external devices connected to the platform 1100 via the interface circuitry include sensor circuitry 1121 and electro-mechanical components (EMCs) 1122, as well as removable memory devices coupled to removable memory circuitry 1123.

The sensor circuitry 1121 include devices, modules, or subsystems whose purpose is to detect events or changes in its environment and send the information (sensor data) about the detected events to some other a device, module, subsystem, etc. Examples of such sensors include, inter alia, inertia measurement units (IMUs) comprising accelerometers, gyroscopes, and/or magnetometers; microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) comprising 3-axis accelerometers, 3-axis gyroscopes, and/or magnetometers; level sensors; flow sensors; temperature sensors (e.g., thermistors); pressure sensors; barometric pressure sensors; gravimeters; altimeters; image capture devices (e.g., cameras or lensless apertures); light detection and ranging (LiDAR) sensors; proximity sensors (e.g., infrared radiation detector and the like), depth sensors, ambient light sensors, ultrasonic transceivers; microphones or other like audio capture devices; etc.

EMCs 1122 include devices, modules, or subsystems whose purpose is to enable platform 1100 to change its state, position, and/or orientation, or move or control a mechanism or (sub)system. Additionally, EMCs 1122 may be configured to generate and send messages/signalling to other components of the platform 1100 to indicate a current state of the EMCs 1122. Examples of the EMCs 1122 include one or more power switches, relays including electromechanical relays (EMRs) and/or solid state relays (SSRs), actuators (e.g., valve actuators, etc.), an audible sound generator, a visual warning device, motors (e.g., DC motors, stepper motors, etc.), wheels, thrusters, propellers, claws, clamps, hooks, and/or other like electro mechanical components. In embodiments, platform 1100 is configured to operate one or more EMCs 1122 based on one or more captured events and/or instructions or control signals received from a service provider and/or various clients.

In some implementations, the interface circuitry may connect the platform 1100 with positioning circuitry 1145. The positioning circuitry 1145 includes circuitry to receive and decode signals transmitted/broadcasted by a positioning network of a GNSS. Examples of navigation satellite constellations (or GNSS) include United States’ GPS, Russia’s GLONASS, the European Union’s Galileo system, China’s BeiDou Navigation Satellite System, a regional navigation system or GNSS augmentation system (e.g., NAVIC), Japan’s QZSS, France’s DORIS, etc.), or the like. The positioning circuitry 1145 comprises various hardware elements (e.g., including hardware devices such as switches, filters, amplifiers, antenna elements, and the like to facilitate OTA communications) to communicate with components of a positioning network, such as navigation satellite constellation nodes. In some embodiments, the positioning circuitry 1145 may include a Micro-PNT IC that uses a master timing clock to perform position tracking/estimation without GNSS assistance. The positioning circuitry 1145 may also be part of, or interact with, the baseband circuitry 1010 and/or RFEMs 1115 to communicate with the nodes and components of the positioning network. The positioning circuitry 1145 may also provide position data and/or time data to the application circuitry 1105, which may use the data to synchronize operations with various infrastructure (e.g., radio base stations), for tum-by-tum navigation applications, or the like

In some implementations, the interface circuitry may connect the platform 1100 with Near- Field Communication (NFC) circuitry 1140. NFC circuitry 1140 is configured to provide contactless, short-range communications based on radio frequency identification (RFID) standards, wherein magnetic field induction is used to enable communication between NFC circuitry 1140 and NFC-enabled devices external to the platform 1100 (e.g., an “NFC touchpoint”). NFC circuitry 1140 comprises an NFC controller coupled with an antenna element and a processor coupled with the NFC controller. The NFC controller may be a chip/IC providing NFC functionalities to the NFC circuitry 1140 by executing NFC controller firmware and an NFC stack. The NFC stack may be executed by the processor to control the NFC controller, and the NFC controller firmware may be executed by the NFC controller to control the antenna element to emit short-range RF signals. The RF signals may power a passive NFC tag (e.g., a microchip embedded in a sticker or wristband) to transmit stored data to the NFC circuitry 1140, or initiate data transfer between the NFC circuitry 1140 and another active NFC device (e.g., a smartphone or an NFC-enabled POS terminal) that is proximate to the platform 1100.

The driver circuitry 1146 may include software and hardware elements that operate to control particular devices that are embedded in the platform 1100, attached to the platform 1100, or otherwise communicatively coupled with the platform 1100. The driver circuitry 1146 may include individual drivers allowing other components of the platform 1100 to interact with or control various input/output (I/O) devices that may be present within, or connected to, the platform 1100. For example, driver circuitry 1146 may include a display driver to control and allow access to a display device, a touchscreen driver to control and allow access to a touchscreen interface of the platform 1100, sensor drivers to obtain sensor readings of sensor circuitry 1121 and control and allow access to sensor circuitry 1121, EMC drivers to obtain actuator positions of the EMCs 1122 and/or control and allow access to the EMCs 1122, a camera driver to control and allow access to an embedded image capture device, audio drivers to control and allow access to one or more audio devices.

The power management integrated circuitry (PMIC) 1125 (also referred to as“power management circuitry 1125”) may manage power provided to various components of the platform 1100. In particular, with respect to the baseband circuitry 1110, the PMIC 1125 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMIC 1125 may often be included when the platform 1100 is capable of being powered by a battery 1130, for example, when the device is included in a UE (e.g., UE 104).

In some embodiments, the PMIC 1125 may control, or otherwise be part of, various power saving mechanisms of the platform 1100. For example, if the platform 1100 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the platform 1100 may power down for brief intervals of time and thus save power. If there is no data traffic activity for an extended period of time, then the platform 1100 may transition off to an RRC Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The platform 1100 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The platform 1100 may not receive data in this state; in order to receive data, it must transition back to RRC Connected state. An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

A battery 1130 may power the platform 1100, although in some examples the platform 1100 may be mounted deployed in a fixed location, and may have a power supply coupled to an electrical grid. The battery 1130 may be a lithium ion battery, a metal-air battery, such as a zinc- air battery, an aluminum-air battery, a lithium-air battery, and the like. In some implementations, such as in V2X applications, the battery 1130 may be a typical lead-acid automotive battery.

In some implementations, the battery 1130 may be a“smart battery,” which includes or is coupled with a Battery Management System (BMS) or battery monitoring integrated circuitry. The BMS may be included in the platform 1100 to track the state of charge (SoCh) of the battery 1130. The BMS may be used to monitor other parameters of the battery 1130 to provide failure predictions, such as the state of health (SoH) and the state of function (SoF) of the battery 1130. The BMS may communicate the information of the battery 1130 to the application circuitry 1105 or other components of the platform 1100. The BMS may also include an analog-to-digital (ADC) convertor that allows the application circuitry 1105 to directly monitor the voltage of the battery 1130 or the current flow from the battery 1130. The battery parameters may be used to determine actions that the platform 1100 may perform, such as transmission frequency, network operation, sensing frequency, and the like.

A power block, or other power supply coupled to an electrical grid may be coupled with the BMS to charge the battery 1130. In some examples, the power block XS30 may be replaced with a wireless power receiver to obtain the power wirelessly, for example, through a loop antenna in the computer platform 1100. In these examples, a wireless battery charging circuit may be included in the BMS. The specific charging circuits chosen may depend on the size of the battery 1130, and thus, the current required. The charging may be performed using the Airfuel standard promulgated by the Airfuel Alliance, the Qi wireless charging standard promulgated by the Wireless Power Consortium, or the Rezence charging standard promulgated by the Alliance for Wireless Power, among others.

User interface circuitry 1150 includes various input/output (I/O) devices present within, or connected to, the platform 1100, and includes one or more user interfaces designed to enable user interaction with the platform 1100 and/or peripheral component interfaces designed to enable peripheral component interaction with the platform 1100. The user interface circuitry 1150 includes input device circuitry and output device circuitry. Input device circuitry includes any physical or virtual means for accepting an input including, inter alia, one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphones, scanner, headset, and/or the like. The output device circuitry includes any physical or virtual means for showing information or otherwise conveying information, such as sensor readings, actuator position(s), or other like information. Output device circuitry may include any number and/or combinations of audio or visual display, including, inter alia, one or more simple visual outputs/indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., Liquid Chrystal Displays (LCD), LED displays, quantum dot displays, projectors, etc.), with the output of characters, graphics, multimedia objects, and the like being generated or produced from the operation of the platform 1100. The output device circuitry may also include speakers or other audio emitting devices, printer(s), and/or the like. In some embodiments, the sensor circuitry 1121 may be used as the input device circuitry (e.g., an image capture device, motion capture device, or the like) and one or more EMCs may be used as the output device circuitry (e.g., an actuator to provide haptic feedback or the like). In another example, NFC circuitry comprising an NFC controller coupled with an antenna element and a processing device may be included to read electronic tags and/or connect with another NFC-enabled device. Peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a USB port, an audio jack, a power supply interface, etc.

Although not shown, the components of platform 1100 may communicate with one another using a suitable bus or interconnect (IX) technology, which may include any number of technologies, including ISA, EISA, PCI, PCIx, PCIe, a Time-Trigger Protocol (TTP) system, a FlexRay system, or any number of other technologies. The bus/IX may be a proprietary bus/IX, for example, used in a SoC based system. Other bus/IX systems may be included, such as an I²C interface, an SPI interface, point-to-point interfaces, and a power bus, among others.

Figure 12 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically, Figure 12 shows a diagrammatic representation of hardware resources 1200 including one or more processors (or processor cores) 1210, one or more memory /storage devices 1220, and one or more communication resources 1230, each of which may be communicatively coupled via a bus 1240. For embodiments where node virtualization (e.g., NFV) is utilized, a hypervisor 1202 may be executed to provide an execution environment for one or more network slices/sub-slices to utilize the hardware resources 1200.

The processors 1210 may include, for example, a processor 1212 and a processor 1214. The processor(s) 1210 may be, for example, a central processing unit (CPU), areduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a DSP such as a baseband processor, an ASIC, an FPGA, a radio- frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

The memory /storage devices 1220 may include main memory, disk storage, or any suitable combination thereof. The memory /storage devices 1220 may include, but are not limited to, any type of volatile or nonvolatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), Flash memory, solid-state storage, etc.

The communication resources 1230 may include interconnection or network interface components or other suitable devices to communicate with one or more peripheral devices 1204 or one or more databases 1206 via a network 1208. For example, the communication resources 1230 may include wired communication components (e.g., for coupling via USB), cellular communication components, NFC components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components..

Instructions 1250 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least any of the processors 1210 to perform any one or more of the methodologies discussed herein. The instructions 1250 may reside, completely or partially, within at least one of the processors 1210 (e.g., within the processor’s cache memory), the memory /storage devices 1220, or any suitable combination thereof. Furthermore, any portion of the instructions 1250 may be transferred to the hardware resources 1200 from any combination of the peripheral devices 1204 or the databases 1206. Accordingly, the memory of processors 1210, the memory/storage devices 1220, the peripheral devices 1204, and the databases 1206 are examples of computer-readable and machine-readable media.

For one or more embodiments, at least one of the components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the example section below. For example, the baseband circuitry as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below. For another example, circuitry associated with a UE, base station, network element, etc. as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below in the example section.

Some non-limiting Examples of various embodiments are provided below.

Example 1 is one or more computer-readable media (CRM) having instructions, stored thereon, that when executed by one or more processors of an apparatus, cause the apparatus to, as part of an in-sync test for a user equipment (UE): transmit a downlink signal, to the UE, with a first target signal-to-noise ratio (SNR); adjust the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR has a value equal to Qout plus a first margin, wherein Qout corresponds to an out-of-sync threshold of the UE, and wherein the first margin is 4 decibels (dB) or 5 dB; and adjust the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR has a value equal to Qout minus a second margin.

Example 2 is the one or more CRM of Example 1 or another example herein, wherein the second margin is equal to the first margin.

Example 3 is the one or more CRM of Example 1 or another example herein, wherein the second margin is different than the first margin.

Example 4 is the one or more CRM of Example 1 -2 or another example herein, wherein the first and second margins are 4 dB and wherein Qout corresponds to -11 dB.

Example 5 is the one or more CRM of Example 1 -4 or another example herein, wherein the instructions, when executed, are further to cause the apparatus to, as part of the in-sync test: adjust the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR has a value equal to Qin minus a third margin, wherein Qin corresponds to an in-sync threshold of the UE; and adjust the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR has a value equal to Qin plus a fourth margin, and wherein the fourth margin is different than the third margin.

Example 6 is the one or more CRM of Example 5 or another example herein, wherein Qin corresponds to -2 dB, and wherein the third margin is 2.5 dB.

Example 7 is the one or more CRM of Example 5-6 or another example herein, wherein the fifth target SNR is equal to the first target SNR.

Example 8 is the one or more CRM of Example 5-7 or another example herein, wherein the instructions, when executed, are further to cause the apparatus to: receive an out-of-sync indication from the UE after transmission of the downlink signal with the third target SNR, the out-of-sync indication to indicate that the UE is out of sync with a cell on which the downlink signal is transmitted; and receive an in-sync indication from the UE after transmission of the downlink signal with the fifth target SNR, the in-sync indication to indicate that the UE is in sync with the cell.

Example 9 is the one or more CRM of any one of Examples 1-8 or another example herein, wherein the downlink signal is a first downlink signal, and wherein the instructions, when executed, are further to cause the apparatus to, as part of an out-of-sync test for the UE: transmit a second downlink signal, to the UE, with the first target SNR; adjust the second downlink signal to have the second target SNR after the first target SNR; and adjust the second downlink signal to have the third target SNR after the second target SNR.

Example 10 is an apparatus comprising: a memory to store instructions for an in-sync test for a user equipment (UE); and one or more processors coupled to the memory, the one or more processors to, as part of the in-sync test: cause transmission of a downlink signal, to the UE, with a first target signal -to-noise ratio (SNR); adjust the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR is -7 dB; and adjust the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR is -15 dB.

Example 11 is the apparatus of Example 10 or another example herein, wherein an out- of-sync threshold to be used by the UE for the in-sync test corresponds to an SNR of -11 dB.

Example 12 is the apparatus of Example 10-11 or another example herein, wherein the apparatus is further to, as part of the in-sync test: adjust the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR is -4.5 dB; and adjust the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR is 1.

Example 13 is the apparatus of Example 12 or another example herein, wherein the fifth target SNR is equal to the first target SNR.

Example 14 is the apparatus of Example 12-13 or another example herein, wherein the processor is further to: receive an out-of-sync indication from the UE after transmission of the downlink signal with the third target SNR, the out-of-sync indication to indicate that the UE is out of sync with a cell on which the downlink signal is transmitted; and receive an in-sync indication from the UE after transmission of the downlink signal with the fifth target SNR, the in-sync indication to indicate that the UE is in sync with the cell.

Example 15 is the apparatus of any one of Examples 10-14 or another example herein, wherein the downlink signal is a first downlink signal, and wherein the apparatus is further to, as part of an out-of-sync test for the UE: cause transmission of a downlink signal, to the UE, with the first target SNR; adjust the downlink signal to have the second target SNR after the first target SNR; and adjust the downlink signal to have the third target SNR after the second target SNR.

Example 16 is one or more computer-readable media (CRM) having instructions, stored thereon, that when executed cause a user equipment (UE) to, as part of an out-of-sync test: receive a downlink signal that has a first target signal-to-noise ratio (SNR) for a first time period, a second target SNR for a second time period after the first time period, and a third target SNR for a third time period after the second time period, wherein the second target SNR is -7 dB, and wherein the third target SNR is -15 dB; determine that a signal quality of the downlink signal during the third time period is lower than an out-of-sync threshold of the UE; and generate an out-of-sync indication based on the determination.

Example 17 is the one or more CRM of Example 16 or another example herein, wherein an out-of-sync threshold to be used by the UE for the in-sync test is -11 dB. Example 18 is the one or more CRM of Example 16-17 or another example herein, wherein the downlink signal is a first downlink signal, and wherein the instructions, when executed, are further to cause the UE to, as part of an in-sync test: receive a second downlink signal that has the first target SNR for a fourth time period, the second target SNR for a fifth time period, the third target SNR for a sixth time period, a fourth target SNR for a seventh time period, and a fifth target SNR for an eighth time period, wherein the fourth target SNR is -4.5 dB, and wherein the fifth target SNR is 1 dB; determine that a signal quality of the downlink signal during the eighth time period is greater than an in-sync threshold of the UE; and generate an in-sync indication based on the determination that the signal quality is greater than the in- sync threshold.

Example 19 is the one or more CRM of Example 18 or another example herein, wherein the in-sync threshold is -2 dB.

Example 20 is the apparatus of Example 18-19 or another example herein, wherein the fifth target SNR is equal to the first target SNR.

Any of the above described examples may be combined with any other example (or combination of examples), unless explicitly stated otherwise. The foregoing description of one or more implementations provides illustration and description, but is not intended to be exhaustive or to limit the scope of embodiments to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of various embodiments.

Claims

Claims What is claimed is:

1. One or more computer-readable media (CRM) having instructions, stored thereon, that when executed by one or more processors of an apparatus, cause the apparatus to, as part of an in-sync test for a user equipment (UE):

transmit a downlink signal, to the UE, with a first target signal-to-noise ratio (SNR); adjust the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR has a value equal to Qout plus a first margin, wherein Qout corresponds to an out-of-sync threshold of the UE, and wherein the first margin is 4 decibels (dB) or 5 dB; and

adjust the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR has a value equal to Qout minus a second margin.

2. The one or more CRM of claim 1, wherein the second margin is equal to the first margin.

3. The one or more CRM of claim 1, wherein the second margin is different than the first margin.

4. The one or more CRM of claim 1, wherein the first and second margins are 4 dB and wherein Qout corresponds to -11 dB.

5. The one or more CRM of claim 1, wherein the instructions, when executed, are further to cause the apparatus to, as part of the in-sync test:

adjust the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR has a value equal to Qin minus a third margin, wherein Qin corresponds to an in-sync threshold of the UE; and

adjust the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR has a value equal to Qin plus a fourth margin, and wherein the fourth margin is different than the third margin.

6. The one or more CRM of claim 5, wherein Qin corresponds to -2 dB, and wherein the third margin is 2.5 dB.

7. The one or more CRM of claim 5, wherein the fifth target SNR is equal to the first target SNR.

8. The one or more CRM of claim 5, wherein the instructions, when executed, are further to cause the apparatus to:

receive an out-of-sync indication from the UE after transmission of the downlink signal with the third target SNR, the out-of-sync indication to indicate that the UE is out of sync with a cell on which the downlink signal is transmitted; and

receive an in-sync indication from the UE after transmission of the downlink signal with the fifth target SNR, the in-sync indication to indicate that the UE is in sync with the cell.

9. The one or more CRM of any one of claims 1-8, wherein the downlink signal is a first downlink signal, and wherein the instructions, when executed, are further to cause the apparatus to, as part of an out-of-sync test for the UE:

transmit a second downlink signal, to the UE, with the first target SNR;

adjust the second downlink signal to have the second target SNR after the first target SNR; and

adjust the second downlink signal to have the third target SNR after the second target

SNR.

10. An apparatus comprising:

a memory to store instructions for an in-sync test for a user equipment (UE); and one or more processors coupled to the memory, the one or more processors to, as part of the in-sync test:

cause transmission of a downlink signal, to the UE, with a first target signal-to- noise ratio (SNR);

adjust the downlink signal to have a second target SNR after the first target SNR, wherein the second target SNR is -7 dB; and

adjust the downlink signal to have a third target SNR after the second target SNR, wherein the third target SNR is -15 dB.

11. The apparatus of claim 10, wherein an out-of-sync threshold to be used by the UE for the in-sync test corresponds to an SNR of -11 dB.

12. The apparatus of claim 10, wherein the apparatus is further to, as part of the in sync test:

adjust the downlink signal to have a fourth target SNR after the third target SNR, wherein the fourth target SNR is -4.5 dB; and

adjust the downlink signal to have a fifth target SNR after the fourth target SNR, wherein the fifth target SNR is 1.

13. The apparatus of claim 12, wherein the fifth target SNR is equal to the first target

SNR.

14. The apparatus of claim 12, wherein the processor is further to:

15. The apparatus of any one of claims 10-14, wherein the downlink signal is a first downlink signal, and wherein the apparatus is further to, as part of an out-of-sync test for the UE:

cause transmission of a downlink signal, to the UE, with the first target SNR;

adjust the downlink signal to have the second target SNR after the first target SNR; and adjust the downlink signal to have the third target SNR after the second target SNR.

16. One or more computer-readable media (CRM) having instructions, stored thereon, that when executed cause a user equipment (UE) to, as part of an out-of-sync test: receive a downlink signal that has a first target signal-to-noise ratio (SNR) for a first time period, a second target SNR for a second time period after the first time period, and a third target SNR for a third time period after the second time period, wherein the second target SNR is -7 dB, and wherein the third target SNR is -15 dB;

determine that a signal quality of the downlink signal during the third time period is lower than an out-of-sync threshold of the UE; and

generate an out-of-sync indication based on the determination.

17. The one or more CRM of claim 16, wherein an out-of-sync threshold to be used by the UE for the in-sync test is -11 dB.

18. The one or more CRM of claim 16, wherein the downlink signal is a first downlink signal, and wherein the instructions, when executed, are further to cause the UE to, as part of an in-sync test:

receive a second downlink signal that has the first target SNR for a fourth time period, the second target SNR for a fifth time period, the third target SNR for a sixth time period, a fourth target SNR for a seventh time period, and a fifth target SNR for an eighth time period, wherein the fourth target SNR is -4.5 dB, and wherein the fifth target SNR is 1 dB;

determine that a signal quality of the downlink signal during the eighth time period is greater than an in-sync threshold of the UE; and

generate an in-sync indication based on the determination that the signal quality is greater than the in-sync threshold.

19. The one or more CRM of claim 18, wherein the in-sync threshold is -2 dB.

20. The apparatus of claim 18, wherein the fifth target SNR is equal to the first target

SNR.