WO2020052321A1 - 数据处理方法和系统 - Google Patents

数据处理方法和系统 Download PDF

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Publication number
WO2020052321A1
WO2020052321A1 PCT/CN2019/094139 CN2019094139W WO2020052321A1 WO 2020052321 A1 WO2020052321 A1 WO 2020052321A1 CN 2019094139 W CN2019094139 W CN 2019094139W WO 2020052321 A1 WO2020052321 A1 WO 2020052321A1
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ssd
address
logical address
physical address
attribute
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PCT/CN2019/094139
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English (en)
French (fr)
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朱志明
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Definitions

  • the present application relates to the field of memory technology, and in particular, to a data processing method and system.
  • a solid state drive is composed of multiple flash media. After the data is written to the storage space, it needs to be erased before it can be written again. Data is written to the SSD in units of pages, and invalid data is erased in units of pages. As data is continuously written, less and less storage space is available.
  • the solid-state hard disk periodically performs garbage collection, relocates valid data in the blocks to be recycled to other free pages, and then erases the data of the blocks to be recycled to realize the recovery of storage space. However, if garbage collection is performed during the data writing process, the read and write speed of the SSD will be slowed down, which will affect the performance of the SSD.
  • the present application provides a data processing method and system, which can reduce the impact of garbage collection on SSD write operations and improve the SSD write speed.
  • the present application provides a data processing system.
  • the system includes a host and a solid-state drive SSD.
  • the host communicates with the SSD through a first storage transmission protocol:
  • the host is configured to send a pre-allocation instruction to the SSD, where the pre-allocation instruction is used to instruct the SSD to allocate a first storage space in the SSD, and the pre-allocation instruction includes a start logical address and a length;
  • the SSD is configured to receive the pre-assignment instruction, determine at least one first logical address according to the starting logical address and the length, and for each first logical address in the at least one first logical address, A first physical address is mapped in the SSD to obtain the first storage space.
  • the first storage transmission protocol may be any one of the following: a non-volatile high-speed transmission bus NVMe protocol, a network-based non-volatile high-speed transmission bus NoF protocol, an Internet small computer system interface iSCSI protocol, a small Computer system interface SCSI protocol.
  • the host sends a pre-allocation instruction to the SSD.
  • the SSD pre-allocates storage space in the SSD and allocates a reserved storage area in advance according to the pre-allocation instruction. Therefore, when data is written in the SSD of the system, The mapping relationship between the logical address and the physical address of the storage space is allocated, and the data is written to the pre-allocated storage area, which avoids triggering garbage collection, realizes fast data writing, and improves data writing speed.
  • the host is further configured to: when the input / output I / O load of the system is less than or equal to a first threshold, send the pre-allocation instruction to the SSD.
  • the system of this scheme can reduce the impact of the pre-allocation process on other performance of the system.
  • the host is further configured to: when the system is initialized, send the pre-allocation instruction to the SSD.
  • the system of this solution is applicable to a scenario where the system is protected from power failure.
  • the storage space corresponding to the pre-allocated instruction is the allocated metadata used to store file system or operating system or other application metadata when power is lost. At least part of the storage space. Therefore, when the system is initialized, the pre-allocation instruction is sent to the SSD, so that the system of this solution can maximize the implementation of the file system or operating system or other applications that are urgently maintained when the system is powered off.
  • the metadata is quickly written to the SSD. This is because power failure may occur at any time. The sooner the pre-allocation instruction is sent, the faster the metadata of the file system or the operating system or other applications that are urgently maintained when the system is powered off is written to the SSD. The greater the chance.
  • the host is further configured to: after the host allocates a hot spare space for a RAID group created by the host, send the pre-allocation instruction to the SSD.
  • This solution is applicable to the scenario of creating a RAID group.
  • the storage space corresponding to the pre-allocation instruction is at least part of the hot spare space allocated by the host for the RAID group.
  • the RAID group created by the host for the host is allocated.
  • the pre-allocation instruction is sent to the SSD, so that the system of this solution can realize the maximum write of the data corresponding to the failed data disk in the RAID group to the SSD to the maximum extent. This is also because the RAID group A faulty data disk may occur at any time.
  • the SSD includes a first mapping table, a first attribute table, and a second attribute table, and the first mapping table is used to identify a mapping relationship between a logical address and a physical address of the SSD.
  • the first attribute table is used to identify the pre-allocated attributes of each logical address, and the pre-assigned attributes include pre-allocated, free, and written; and the second attribute table is used to identify the assigned attributes of each physical address,
  • the allocation attribute includes idle, pre-allocation, valid, and invalid; the SSD is further configured to initialize a physical address mapped by each logical address in the first mapping table to an invalid address or Zero; initialize the attributes of each logical address in the first attribute table as idle; initialize the attributes of each physical address in the second attribute table as idle; after receiving the pre-allocation instruction, initialize the attribute Updating the physical address mapped by the first logical address in the first mapping table to the first physical address mapped by the SSD in the SSD according to the pre-allocation instruction to the first logical address,
  • the setting of the first mapping table enables the SSD to know the physical address mapped by the pre-assigned logical address.
  • the setting of the first attribute table enables the SSD to know the attributes of each logical address of the SSD, and the second attribute table. The setting can make the SSD know the attributes of each physical address of the SSD.
  • the hot spare space of the RAID group includes at least one of the first storage space.
  • all The hot spare space is used for data recovery of the failed data disk.
  • data corresponding to the failed data disk can be quickly written into the hot spare space.
  • the host is further configured to send a read instruction to the SSD; the SSD is further configured to determine, according to the first attribute table, whether a logical address corresponding to the read instruction includes The attribute is a pre-allocated second logical address, and if so, a read response is sent to the host, the read response includes a preset result, and the preset result is used to indicate a first mapping relationship with the second logical address.
  • a physical address has not been written with data; the second logical address is an address in the at least one first logical address.
  • the system of this solution can perform data processing when the logical address corresponding to the read instruction includes a second logical address whose attribute is pre-allocated.
  • the host is further configured to send a write instruction to the SSD, where the write instruction includes data to be written; and the SSD is further configured to determine a location based on the first attribute table. It is stated whether the logical address corresponding to the write instruction includes a third logical address whose attribute is pre-allocated, and if so, the first logical table having a mapping relationship with the third logical address is determined according to the first mapping table and the third logical address.
  • a physical address writing data corresponding to the third logical address in the data to be written into a first physical address that has a mapping relationship with the third logical address, and storing the data in the first attribute table
  • the attribute of the third logical address is updated to be written, and the attribute of the first physical address in the second attribute table that has a mapping relationship with the third logical address is updated to be valid; wherein the third logical address Is an address in the at least one first logical address.
  • the system of this solution can perform data processing when the logical address corresponding to the write instruction includes a third logical address whose attribute is pre-allocated.
  • the host is further configured to send a TRIM instruction to the SSD;
  • the SSD is further configured to determine, according to the first attribute table, whether a logical address corresponding to the TRIM instruction includes The attribute is a pre-assigned fourth logical address, and if it is, the attribute of the fourth logical address in the first attribute table is updated to idle; and an AND is determined according to the first mapping table and the fourth logical address.
  • the system of this solution can perform data processing when the logical address corresponding to the TRIM instruction includes a fourth logical address whose attribute is pre-allocated.
  • the SSD further records a second mapping table, where the second mapping table is used to record a mapping relationship between a pre-allocated first physical address and a pre-allocated first logical address.
  • the SSD is further configured to determine whether the physical address corresponding to the target block to be erased includes a second physical address with an attribute pre-allocated according to the second attribute table when performing a garbage collection operation;
  • the fifth logical address mapped by the second physical address maps a third physical address to the SSD, and updates the second physical address in the second mapping table and the first mapping table to the first physical address.
  • the system of this solution can perform data processing when the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated.
  • the setting of the second mapping table can speed up the update of the first mapping table by the SSD in the system after the garbage collection operation.
  • the SSD is further configured to determine whether the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated according to the second attribute table when performing a garbage collection operation. If yes, re-mapping a third physical address on the SSD for the fifth logical address mapped with the second physical address, and updating the second physical address in the first mapping table to the second physical address A third physical address; updating the attribute of the third physical address in the second attribute table to pre-allocation, and updating the attribute of the second physical address to idle.
  • This solution system can perform data processing when the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated.
  • the SSD is further configured to update an attribute of a fourth physical address in the second attribute table to be invalid after receiving the pre-allocation instruction, and the fourth physical address is The address is a physical address in which the sixth logical address is mapped in the first mapping table before the pre-allocation instruction is received, and the sixth logical address is an address in the at least one logical address.
  • the system of this scheme can perform data processing when there is a write instruction before the pre-allocated instruction.
  • the present application provides a data processing method, which includes: a host generates a pre-allocation instruction, the pre-allocation instruction includes a start logical address and a length; and the pre-allocation instruction is used to instruct the SSD in the SSD Allocate a first storage space, the starting logical address and length are used by the SSD to determine at least one first logical address, and the first logical address is the one that requires the SSD to map a first physical address in the SSD Address; the host sends the pre-allocation instruction to the SSD; wherein the host communicates with the SSD through a first storage transfer protocol.
  • the first storage transmission protocol may be any one of the following: a non-volatile high-speed transmission bus NVMe protocol, a network-based non-volatile high-speed transmission bus NoF protocol, an Internet small computer system interface iSCSI protocol, and a small computer system Interface SCSI protocol.
  • the host sends a pre-allocation instruction to the SSD, so that the SSD pre-allocates storage space for the SSD and allocates a reserved storage area in advance.
  • the data can be written to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoiding triggering garbage collection, achieving fast data writing, and improving data writing. Into the speed.
  • the host sending the pre-allocation instruction to the SSD includes: when an input / output I / O load of a system where the host is located is less than or equal to a first threshold, the host sends The SSD sends the pre-allocation instruction.
  • the host sending the pre-allocation instruction to the SSD includes: when the system in which the host is located is initialized, the host sends the pre-allocation instruction to the SSD.
  • the host sending the pre-allocation instruction to the SSD includes: after the host allocates a hot spare space for a RAID group created by the host, the host sends the SSD to the SSD Sending the pre-allocation instruction.
  • the data corresponding to the failed data disks in the RAID group can be written to the SSD to the maximum extent.
  • the specific reason is described in the first aspect.
  • the hot spare space of the RAID group includes at least one first storage space.
  • the hot spare space is used for data recovery of the failed data disk.
  • the method further includes: the host sends a read instruction to the SSD; the host receives a read response from the SSD, the read response includes a preset result, and the preset result is used for The first physical address indicating that there is a mapping relationship with the second logical address has not written data; the second logical address is an address in a logical address corresponding to the read instruction, and the second logical address is the at least one The address in a logical address.
  • This solution provides a data processing method of the host when the logical address corresponding to the read instruction includes a second logical address whose attribute is pre-allocated.
  • the present application provides a data processing method, including: a solid-state hard disk SSD receiving a pre-allocation instruction from a host, the pre-allocation instruction including a starting logical address and a length; The SSD performs communication; the SSD determines at least one first logical address according to the start logical address and the length, and each first logical address in the at least one first logical address is in the SSD Map a first physical address to obtain the first storage space.
  • the first storage transmission protocol may be any one of the following: a non-volatile high-speed transmission bus NVMe protocol, a network-based non-volatile high-speed transmission bus NoF protocol, an Internet small computer system interface iSCSI protocol, a small Computer system interface SCSI protocol.
  • the SSD pre-allocates storage space in the SSD according to a pre-allocation instruction, and allocates a reserved storage area in advance.
  • the data can be written to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoiding triggering garbage collection, achieving fast data writing, and improving data writing Into the speed.
  • the SSD includes a first mapping table, a first attribute table, and a second attribute table, and the first mapping table is used to identify a mapping relationship between a logical address and a physical address in the SSD.
  • the first attribute table is used to identify the pre-allocated attributes of each logical address, and the pre-assigned attributes include pre-allocated, free, and written; and the second attribute table is used to identify the assigned attributes of each physical address
  • the allocation attribute includes idle, pre-allocation, valid, and invalid; when the system is initialized, the SSD initializes the physical address mapped by each logical address in the first mapping table to an invalid address or zero; and Initialize the attributes of each logical address in the first attribute table to idle; initialize the attributes of each physical address in the second attribute table to idle; after the SSD receives a pre-allocation instruction from the host, Including: the SSD updates the physical address mapped by the first logical address in the first mapping table to the SSD according to the pre-allocation instruction for the first logical address in the SSD.
  • the setting of the first mapping table enables the SSD to know the physical address mapped by the pre-assigned logical address.
  • the setting of the first attribute table enables the SSD to know the attributes of each logical address of the SSD, and the second attribute table The setting can make the SSD know the attributes of each physical address of the SSD.
  • the method further includes: the SSD receives a read instruction from the host; and the SSD judges, according to the first attribute table, whether a logical address corresponding to the read instruction includes an attribute that is pre-allocated.
  • a second logical address where the second logical address is an address in the at least one first logical address; if so, the SSD sends a read response to the host, where the read response includes a preset result, and the pre- The setting result is used to indicate that no data has been written to the first physical address that has a mapping relationship with the second logical address.
  • the method further includes: receiving, by the SSD, a write instruction from the host; and determining, according to the first attribute table, whether a logical address corresponding to the write instruction includes a third logic whose attribute is pre-allocated.
  • the third logical address is an address in the at least one first logical address; if yes, the SSD determines that a mapping exists with the third logical address according to the first mapping table and the third logical address The first physical address of the relationship; the SSD writes data corresponding to the third logical address in the data to be written into the first physical address having a mapping relationship with the third logical address, and The attribute of the third logical address in the first attribute table is updated to be written, and the attribute of the first physical address in the second attribute table having a mapping relationship with the third logical address is updated to be valid.
  • This solution provides a data processing method of the SSD when the logical address corresponding to the write instruction includes a third logical address whose attribute is pre-allocated.
  • the method further includes: the SSD receives a TRIM instruction from the host; the SSD judges, according to the first attribute table, whether a logical address corresponding to the TRIM instruction includes an attribute as a pre-allocation A fourth logical address, the fourth logical address is an address in the at least one first logical address; if yes, the SSD determines a relationship with the fourth according to the first mapping table and the fourth logical address.
  • the attribute of the first physical address with the mapping relationship is updated to idle; the SSD updates the first physical address mapped by the four logical addresses in the first mapping table to an invalid address or zero.
  • the SSD further records a second mapping table, where the second mapping table is used to record a mapping relationship between a pre-allocated physical address and a pre-allocated logical address; when the SSD executes During the garbage collection operation, the SSD determines whether the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated according to the second attribute table; if it is, the SSD is re-assigned to the first physical address.
  • a second physical address mapped from two physical addresses maps a third physical address to the SSD; the SSD updates the second physical address in the second mapping table and the first mapping table to the first physical address Three physical addresses, updating attributes of the third physical address in the second attribute table to pre-allocation, and updating attributes of the second physical address to idle.
  • This solution provides data processing of the SSD when the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated.
  • the setting of the second mapping table can speed up the update of the first mapping table by the SSD after the garbage collection operation.
  • the method further includes: when the SSD performs a garbage collection operation, the SSD determines whether the physical address corresponding to the target block to be erased includes an attribute that is pre-allocated according to the second attribute table. A second physical address; if so, the SSD maps a third physical address on the SSD to a second logical address mapped to the second physical address; the SSD maps all the addresses in the first mapping table The second physical address is updated to the third physical address, the attribute of the third physical address in the second attribute table is updated to pre-allocation, and the attribute of the second physical address is updated to idle.
  • This solution provides data processing of the SSD when the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated.
  • the attribute of the fourth physical address in the second attribute table is updated to be invalid, and the fourth physical address is after receiving the pre-allocation instruction.
  • the sixth logical address is a physical address mapped in the first mapping table, and the sixth logical address is an address in the at least one logical address.
  • the present application provides a data processing apparatus, and the apparatus includes various modules for performing the data processing method in the second aspect or any possible implementation manner of the second aspect.
  • the present application provides a data processing apparatus, where the apparatus includes various modules for performing the third aspect or the data processing method in any possible implementation manner of the third aspect.
  • the present application provides a computer-readable storage medium, where the computer-readable storage medium stores instructions, and when the computer-readable storage medium is run on a computer, causes the computer to execute the methods described in the above aspects.
  • the present application provides a computer program product containing instructions that, when run on a computer, causes the computer to perform the methods described in the above aspects.
  • This application pre-allocates storage space for SSDs and allocates reserved storage areas in advance.
  • the data can be written to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoiding triggering garbage collection, realizing fast data writing, and improving data writing speed.
  • FIG. 1 is a system architecture diagram I provided by the present application.
  • FIG. 2 is a second system architecture diagram provided by the present application.
  • FIG. 3 is an interaction diagram I of a data processing method provided by this application.
  • FIG. 4 is a schematic diagram of a write instruction processing process provided by the present application.
  • FIG. 5 is a schematic diagram of a read instruction processing process provided by the present application.
  • FIG. 6 is a schematic diagram of a TRIM instruction processing process provided by the present application.
  • FIG. 7 is a schematic diagram of a garbage collection operation process provided by the present application.
  • FIG. 8 is a schematic diagram of another garbage collection operation process provided by the present application.
  • FIG. 9 is a first schematic structural diagram of a data processing system provided by this application.
  • FIG. 10 is a second structural schematic diagram of a data processing device provided by this application.
  • FIG. 11 is a third structural schematic diagram of a data processing apparatus provided by this application.
  • the storage disk of the present application may be a storage disk in which new data can be written if data is already written on the physical address when data is written to the physical address.
  • the storage disk When the storage disk is a hard disk, it may be a solid state drive (SSD).
  • Logical address The logical address in this application is the logical address of the storage disk, and is expressed as the address of the storage space provided by the storage disk to the outside. It can be understood that if the storage disk is an SSD, the logical address in this application is the logical address of the SSD, and it is expressed as the address of the external storage space provided by the SSD.
  • the physical address in this application refers to the address of the internal storage unit of the memory, also called the actual address or the absolute address. It can be understood that if the storage disk is an SSD, the physical address in this application is the physical address of the SSD.
  • the memory determines the physical address of the storage disk mapped to the logical address corresponding to the write instruction according to the corresponding mapping algorithm, thereby writing the data to be written in the write instruction to the actual storage space corresponding to the physical address.
  • the following uses the storage disk as an SSD to describe the data processing method and system of this embodiment.
  • FIG. 1 is a system architecture diagram I provided by the present application.
  • the system architecture of this embodiment includes a host 11 and an SSD 12, and an internal device of the SSD has a controller 13.
  • the host 11 stores information of the SSD12, and the information of the SD12 includes a drive letter and a disk capacity of the SSD12.
  • the drive letter of the SSD12 is used to identify the SSD, and a start logical address and an end logical address of the SSD12 can be determined according to the disk capacity.
  • the host 11 includes a central processing unit (CPU).
  • the host 11 and the SSD 12 communicate with each other through a first storage transmission protocol.
  • the first storage transmission protocol is any one of the following: a non-volatile high-speed transmission bus (Non-volatile Memory Express) protocol, a network-based non-volatile high-speed transmission bus (NVMe over fabrics, NoF) protocol, Internet Small Computer System Interface (Internet Small Computer System Interface) (iSCSI) protocol, Small Computer System Interface (Internet Small Computer System Interface) protocol.
  • FIG. 1 shows only one SSD.
  • the host 11 is located on the first device, and multiple SSDs 12 are located on the second device.
  • the first device is different from the second device.
  • FIG. 2 is a system architecture diagram provided by the present application.
  • the system architecture shown in Figure 2 also includes a redundant array of independent disks (RAID) controller.
  • the RAID controller can be implemented by software or hardware.
  • the RAID controller can be located in the same place as the host.
  • a device can also be an independent device.
  • the RAID controller is located on the same device as the host, and the RAID controller is implemented by software in the host as an example.
  • FIG. 3 is an interaction diagram I of the data processing method provided by the present application. Referring to FIG. 3, the method includes:
  • Step S101 The host sends a pre-allocation instruction to the SSD; the pre-allocation instruction includes a start logical address and a length.
  • the host needs to determine whether the SSD has a pre-allocation function before sending a pre-allocation instruction to the SSD.
  • the pre-allocation function refers to pre-allocation of the first storage space in the storage space of the SSD according to a pre-allocation instruction sent by the host.
  • the host sends a function check instruction to each SSD. After each SSD receives the function check instruction, it sends a first response to the RAID controller. The first response carries whether the corresponding SSD has a pre-allocation function. , The host determines whether each SSD has a pre-allocation function according to each first response.
  • the identification of the pre-assigned function of the SSD can be implemented by setting a specific function register.
  • each SSD After the host learns whether each SSD has a pre-allocation function, it determines the M-segment logical address of the physical address that needs to be pre-allocated mapping among multiple SSDs with pre-allocation function according to the current business requirements, and determines the pre-allocation according to the M-segment logical address.
  • the starting logical address and length carried in the instruction where M is a positive integer.
  • a piece of logical address in this embodiment corresponds to a starting logical address and a length, that is, a storage space with a certain size.
  • the starting logical address and length included in the pre-allocation instruction sent to an SSD is determined according to the corresponding starting logical address and length of the M segment logical address belonging to the S segment logical address in the SSD.
  • S is a positive integer and S ⁇ M. It can be understood that the RAID controller sends pre-allocation instructions to which SSDs corresponds to the M segment logical addresses.
  • a pre-allocation instruction may include two or more starting logical addresses and lengths, that is, one pre-allocation instruction may include multiple groups of starting logical addresses and lengths.
  • Start logical address and length Each set of start logical address and length includes a start logical address and a length.
  • a pre-allocation instruction includes a start logical address 1 and a corresponding length 1, ..., a start logical address n and a corresponding length n, ..., a start logical address N and a corresponding length N, 1 ⁇ n ⁇ N, N ⁇ 1.
  • the start logical address 1 and the corresponding length 1 correspond to a logical address
  • the start logical address n and the corresponding length n correspond to another logical address.
  • the current business requirements may include: when a data disk of a RAID group fails, the data reconstructed according to the data in the failed data disk is quickly written into the RAID group.
  • Hot spare disk Specifically, when a RAID controller creates a RAID group, it is necessary to allocate a hot spare disk (or hot spare space) for the RAID group. When any data disk in the RAID group fails, the hot spare disk is used for data recovery of the failed data disk. , Under the business requirement, it is determined that the allocated hot spare space is at least part of the storage space corresponding to the above M segment logical address. In other words, the hot spare space includes at least one pre-allocated storage space.
  • one pre-allocated storage space is a storage space corresponding to a logical address in the above M-segment logical addresses, and is also a group included in a pre-allocated instruction.
  • the size of a hot spare disk is related to the composition rules of each RAID group. For example, RAID 5 includes data disks and hot spare disks. Each disk in the same RAID group is the same size. If each disk is 500G, a 500G disk is required.
  • the storage space serves as the hot spare disk of the RAID group.
  • the pre-allocated storage space constituting the hot spare disk can be continuous storage space or intermittent storage space.
  • the pre-allocated storage space constituting the hot spare disk may be from one or more storage areas of the same SSD, or may be multiple storage areas from different SSDs, which is not limited in this application.
  • the RAID controller may allocate a storage space that matches the storage space size of the data disks of the RAID group as a hot spare disk. You can also allocate the first sub-hot spare space for the RAID group. The ratio of the first sub-hot spare space to the size of the hot-spare disk required by the RAID group is greater than or equal to the first value.
  • the first value can be set according to business requirements. The first value can be 0.3, 0.5, or 0.8.
  • the RAID controller then dynamically increases the size of the hot spare disk of the RAID group according to the data writing situation in the RAID group, ensuring that the size of the first sub hot spare space is always greater than the second value, and the second value is the data in the RAID group.
  • the amount of data written to the most written disk For example, the hot spare disk in RAID group 1 requires 500G and the default value is 0.3. At this time, the first sub hot spare space needs to be greater than or equal to 150G. As the data in the RAID group is continuously written, the size of the first sub-hot spare space needs to be continuously increased to ensure that the size of the first sub-hot spare space is always greater than or equal to the data write amount of the disk with the most data disk writes.
  • the pre-allocation instruction sent to the SSD may be a RAID controller included in the host, and the timing for the RAID controller to send the pre-allocation instruction to the SSD may be: the RAID controller allocates a heat for the RAID group created by the RAID controller. After preparing the space, the pre-allocation instruction is sent to the SSD.
  • the current business requirements include: power failure protection is required, so that when a power failure occurs on the system corresponding to the host, the system corresponding to the host can quickly write the saved metadata of the operating system, file system, or other applications to SSD.
  • the host needs to pre-allocate storage for storing emergency data (emergency data is the saved metadata of the operating system, file system, or other applications) in at least one SSD in advance for the operating system, file system, or other applications during initialization.
  • emergency data is the saved metadata of the operating system, file system, or other applications
  • Space under this business requirement, it is determined that the host needs to pre-allocate the storage space for storing emergency data on at least one SSD for the operating system, file system, or other applications in advance at least one of the storage space corresponding to the M segment logical address section.
  • the timing for the host to send the pre-allocation instruction to the SSD may be: when the system corresponding to the host is initialized, the host sends the pre-allocation instruction to the SSD.
  • the current business requirements include: preparing storage space in the SSD in advance for the writing of other unexpected large amounts of data, such as determining the start logical address and length carried in the pre-allocation instruction in conjunction with the TRIM instruction. At this time, To determine the storage space corresponding to the logical address corresponding to the at least one TRIM instruction sent by the host within a preset time period before sending the pre-allocation instruction at least part of the storage space corresponding to the M segment logical address.
  • the invalid data can be cleared by the TRIM instruction, and a part of the storage space is reserved for the above pre-allocation.
  • a pre-allocation instruction can also be directly issued, and the TRIM instruction does not need to be executed to clear invalid data to obtain free storage space.
  • the timing for the host to send a pre-allocation instruction to the SSD at this time may be: when the input / output (I / O) load of the system corresponding to the host is less than or equal to the first threshold, the host sends a pre-allocation to the SSD. Assign instructions.
  • Step S102 The SSD determines at least one first logical address according to the starting logical address and the length, and maps a first physical address in the SSD for each logical address in the at least one first logical address to obtain a first storage space.
  • the first storage space is an idle storage space.
  • the controller that actually performs this step is an SSD controller.
  • the SSD slices the storage space corresponding to the starting logical address and length for a set of starting logical addresses and lengths included in the pre-allocation instruction, and each sub-storing space obtained by the slicing corresponds to a first logic Address to obtain at least one first logical address; the SSD maps a first physical address in the SSD for each first logical address of the at least one first logical address to obtain a first storage space, and the first storage space is free Storage space.
  • the SSD is the first logical address and a first physical address is mapped in the SSD, that is, the SSD pre-allocates a mapped first physical address in the SSD for the first logical address.
  • a first physical address is mapped in the SSD. Therefore, it can be considered that the SSD is a mapping relationship between a first physical address to which the first logical address is mapped in the SSD and the first logical address.
  • the first storage space is the at least one first physical address Composed of storage space.
  • the first storage space may be a continuous storage space or a discrete storage space.
  • a set of starting logical addresses and lengths of the pre-allocation commands correspond to a first storage space; the first storage space is the pre-allocated storage space in step S101.
  • the SSD determines a set of logical addresses according to the start logical address 1 and corresponding length 1. It is called a group A logical address, the group A logical address includes at least one first logical address, and then a first physical address is mapped in the SSD for each first logical address included in the group A logical address to obtain a first storage space A, the first storage space A is a storage space composed of a plurality of first physical addresses mapped to each of the first logical addresses included in the group A logical addresses in the SSD.
  • the SSD uses the starting logical address 1 and Corresponding length 1 determines a group of logical addresses, which can be referred to as a group A logical address.
  • the group A logical address includes at least one first logical address, and then maps each first logical address included in the group A logical address in the SSD.
  • a first physical address to obtain a first storage space A where the first storage space A is a storage space composed of each of the first physical addresses mapped to each of the first logical addresses included in the group A logical addresses; the SSD also A group of logical addresses is determined according to the starting logical address 2 and the corresponding length 2. It can be called a group B logical address.
  • the group B logical address includes at least one first logical address, and then for each A logical address is mapped to a first physical address in the SSD to obtain a first storage space B.
  • the first storage space B is each first logical address included in the B group of logical addresses and each first mapped in the SSD.
  • the physical addresses of the composition of storage space is each first logical address included in the B group of logical addresses and each first mapped in the SSD.
  • the non-page-aligned logical address is discarded, and it is not foreseen. Assign a first physical address.
  • the SSD stores a first mapping table, a first attribute table, and a second attribute table.
  • the first mapping table is used to identify a mapping relationship between a logical address and a physical address
  • the first attribute table is used to identify each logical address.
  • Pre-allocated attributes The pre-allocated attributes of each logical address include pre-allocated, free, and written.
  • the second attribute table is used to identify the assigned attributes of each physical address.
  • the assigned attributes of each physical address include idle, pre-allocated. Allocation, valid, and invalidation; among them, the free logical address (the logical address whose property is free) refers to the logical address that has not been written with data and the SSD has not previously mapped a physical address in the SSD according to the pre-allocation instruction.
  • the assigned logical address (the attribute is a pre-allocated logical address) is a logical address to which a physical address mapped in the first mapping table exists, and the written logical address (the attribute is a written logical address) refers to the corresponding The physical address has been written to the logical address of the data; the free physical address (the attribute is the free physical address) is the physical address of the unwritten data, the pre-allocated physical address (the The pre-assigned physical address is a physical address that has a mapping relationship with the pre-assigned logical address.
  • the valid physical address (the attribute is a valid physical address) is the physical address to which data has been written and the data is valid.
  • the invalid physical address (Attribute is invalid physical address) is the physical address where the data has been written but the data is invalid.
  • the first mapping table, the first attribute table, and the second attribute table can all be implemented by using arrays; they can also be implemented by using bitmaps or linked lists; and they can also be implemented by text or databases.
  • each logical address in the first mapping table is initialized to an invalid address or zero, as shown in Table 1.
  • the attributes of each logical address in the first attribute table are initialized to idle, such as As shown in Table 2; the attributes of each physical address in the second attribute table are initialized to idle, as shown in Table 3.
  • Table 1 An example of a first mapping table
  • the numbers in the first line of Table 1 indicate the logical address
  • MAX in the first line indicates the last logical address of the SSD
  • N in the second line indicates an invalid address, which indicates that the controller of the SSD pair has not Map a physical address to the corresponding logical address in the SSD.
  • Table 1 is only an implementation manner of the first mapping table, and also has other implementation manners.
  • the implementation form of the first mapping table may be in addition to the array shown in Table 1, and may also have no Table 1. In the first line, but the first line as the index of the array.
  • Table 2 An example of a first attribute table
  • the number in the first row of Table 2 indicates the logical address
  • MAX in the first row indicates the last logical address of the SSD
  • X in the second row indicates that the attribute of the logical address is idle.
  • Table 2 is only an implementation manner of the first attribute table, and also has other implementation manners, for example, the implementation form of the first attribute may be in addition to the array shown in Table 2, or it may not be in Table 2.
  • the first line is the index of the array.
  • Table 3 An example of a second attribute table
  • the number in the first line in Table 3 indicates the physical address
  • MAX in the first line indicates the last physical address of the SSD
  • F in the second line indicates that the attribute of the physical address is idle.
  • Table 3 is only an implementation manner of the second attribute table, and also has other implementation manners.
  • the implementation form of the second attribute may be in addition to the array shown in Table 3.
  • the physical address mapped by the first logical address in the first mapping table is updated to the SSD.
  • the first physical address mapped by the first logical address in the SSD is used to update the first attribute table.
  • the attribute of the first logical address in the update is pre-allocated, and the attribute of the first physical address in the second attribute table is updated to the pre-allocation.
  • each logical address corresponding to the M-segment logical address can be mapped in the SSD in advance through the above process.
  • a physical address when a data disk of a RAID group is damaged, for each SSD in each SSD corresponding to the hot spare space, the RAID controller in the host sends a write instruction to the SSD, and the logic corresponding to the write instruction The address is at least a part of the logical address corresponding to the M segment logical address.
  • the SSD obtains a physical address mapped in the SSD for the logical address corresponding to the write instruction in advance according to the first mapping table, and writes data to be written in the write instruction ( At least part of the data reconstructed from the data in the damaged data disk is directly written to the physical address mapped in the SSD for the logical address corresponding to the write instruction in advance, without the need to use a mapping algorithm to calculate the logical address corresponding to the write instruction in real time
  • the mapped physical address and because the logical address corresponding to the write instruction is mapped in advance in the SSD, the storage space corresponding to the physical address is free memory. Space, therefore, will not trigger garbage collection operations, improve the speed of writing.
  • the storage space corresponding to the M-segment logical address of the physical address that needs to be pre-allocated maps includes the storage space allocated by the host for the operating system, file system, or other application in advance on at least one SSD for storing emergency data, as described above,
  • a physical address can be mapped in the SSD in advance. Therefore, when a power failure occurs in the system corresponding to the host, for each SSD in the storage space corresponding to the storage space for emergency data, For each SSD, the host sends a write instruction to the SSD.
  • the logical address corresponding to the write instruction is at least part of the logical address corresponding to the M segment logical address.
  • the SSD obtains the logical address corresponding to the write instruction in advance on the SSD according to the first mapping table.
  • the physical address mapped in the write instruction write the data to be written in the write instruction (at least part of the data in the emergency data) directly to the physical address mapped in the SSD for the logical address corresponding to the write instruction in advance, no mapping is required
  • the algorithm calculates the physical address mapped to the logical address corresponding to the write instruction in real time. Physical address in the address mapping Series SSD corresponding free storage space for storage, and therefore, does not trigger a garbage collection operation, increase the speed of writing.
  • the logical address corresponding to the M-segment logical address of the physical address that needs to be pre-allocated mapping includes the logical address corresponding to at least one TRIM instruction sent by the host within a preset time period before the pre-allocation instruction is sent, it is equivalent to always existing
  • the logical address of the physical address is pre-allocated.
  • a reserved storage area is allocated in advance by pre-allocating storage space in an SSD.
  • the data can be written to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoiding triggering garbage collection, realizing fast data writing, and improving data writing speed.
  • the following describes the data processing method provided by the present application with reference to FIGS. 4 to 8 by taking write instructions, read instructions, TRIM instructions, and garbage collection processes as examples.
  • the method executed by the SSD in the embodiments shown in FIG. 4 to FIG. 8 is actually a method executed by the controller of the SSD.
  • FIG. 4 is a schematic diagram of a write instruction processing process provided by the present application. Referring to FIG. 4, the method in this embodiment includes:
  • Step S201 The host sends a write instruction to the SSD, where the write instruction includes data to be written.
  • the host when data needs to be written to the SSD, the host sends a write instruction to the SSD, where the write instruction includes data to be written; it can be understood that the write instruction also includes a start logical address and a length.
  • Step S202 The SSD judges, according to the first attribute table, whether the logical address corresponding to the write instruction includes a third logical address whose attribute is pre-allocated;
  • the SSD determines at least one logical address according to a start logical address and a length included in the write instruction, and the at least one logical address is a logical address corresponding to the write instruction.
  • the SSD determines whether there is a third logical address with a pre-allocated attribute in the logical address corresponding to the write instruction according to the first attribute table.
  • the logical address corresponding to the write instruction may have a third logical address with a pre-allocated attribute, or may have a plurality of third logical addresses with a pre-allocated attribute, and may have zero attributes with Pre-assigned third logical address.
  • Step S203 If yes, the SSD determines a first physical address having a mapping relationship with the third logical address according to the first mapping table and the third logical address.
  • the SSD determines a first physical address having a mapping relationship with the third logical address according to the first mapping table and the third logical address.
  • the first physical address that has a mapping relationship with the third logical address refers to the physical address mapped in advance by the SSD to the third logical address in the SSD, and is also the first physical address mapped to the second logical address in the first mapping table. address.
  • Step S204 The SSD writes data corresponding to the third logical address in the data to be written into the first physical address having a mapping relationship with the third logical address, and updates the attribute of the third logical address in the first attribute table. As written, the attribute of the first physical address in the second attribute table that has a mapping relationship with the third logical address is updated to be valid.
  • the SSD after receiving the pre-allocation instruction, updates the attribute of the fourth physical address in the second attribute table to be invalid, and the fourth physical address is after receiving the pre-allocation instruction.
  • the sixth logical address is a physical address mapped in the first mapping table, and the sixth logical address is an address in the at least one logical address.
  • This embodiment provides a data processing method when a logical address corresponding to a write instruction has a pre-assigned third logical address.
  • FIG. 5 is a schematic diagram of a read instruction processing process provided in this application. Referring to FIG. 5, the method in this embodiment includes:
  • Step S301 The host sends a read instruction to the SSD.
  • the host when data needs to be read from the SSD, the host sends a read instruction to the SSD, where the read instruction includes a start logical address and a length.
  • Step S302 The SSD determines whether the logical address corresponding to the read instruction includes a second logical address whose attribute is pre-allocated according to the first attribute table.
  • the SSD After the SSD receives the read instruction, it determines at least one logical address according to the start logical address and length included in the read instruction, and the at least one logical address is the logical address corresponding to the read instruction. Next, the SSD determines whether there is a second logical address with a pre-allocated attribute in the logical address corresponding to the read instruction according to the first attribute table.
  • the logical address corresponding to the read instruction may have a second logical address with a pre-allocated attribute, or may have a plurality of second logical addresses with a pre-allocated attribute, and may have zero attributes with Pre-allocated second logical address.
  • Step S303 If yes, the SSD sends a read response to the host, the read response includes a preset result, and the preset result is used to indicate that no data is written to the first physical address that has a mapping relationship with the second logical address.
  • the logical address corresponding to the read instruction has a pre-assigned second logical address, it means that the first physical address that has a mapping relationship with the second logical address does not store data. Therefore, in the read response sent by the SSD to the host, It includes a preset result, which is used to indicate that no data has been written to the first physical address that has a mapping relationship with the second logical address.
  • the first physical address that has a mapping relationship with the second logical address is an SSD that is a physical address mapped in advance in the SSD by the second logical address, and is also a first physical address that is mapped by the second logical address in the first mapping table. .
  • the preset result may be 1 or 0.
  • the read response sent by the SSD to the host includes the preset result; if the logical address corresponding to the read instruction is Some are pre-assigned addresses. According to the read command, some information in the read response sent by the SSD to the host is the preset result.
  • This embodiment provides a data processing method when a logical address corresponding to a read instruction has a second logical address that is pre-allocated.
  • FIG. 6 is a schematic diagram of a TRIM instruction processing process provided in this application. Referring to FIG. 6, the method in this embodiment includes:
  • Step S401 The host sends a TRIM instruction to the SSD.
  • the host sends a TRIM instruction to the SSD, where the TRIM instruction includes a start logical address and a length.
  • the TRIM instruction is explained below;
  • the operating system When a file is deleted in a system that supports TRIM, the operating system will send a TRIM instruction to the SSD to let the SSD know that the data of this file is no longer used and the page on which it is located can be recycled. After the SSD receives the TRIM instruction, the mapping relationship between the logical address and the physical address of the file is released, so that the physical address corresponding to the data of the file is in an invalid state, and the page where the data of the file is located can be recovered during subsequent garbage collection.
  • Step S402 The SSD judges whether the logical address corresponding to the TRIM instruction includes a fourth logical address whose attribute is pre-allocated according to the first attribute table.
  • the SSD determines at least one logical address according to a start logical address and a length included in the TRIM instruction, and the at least one logical address is a logical address corresponding to the TRIM instruction.
  • the SSD determines whether there is a fourth logical address whose attribute is pre-allocated in the logical address corresponding to the TRIM instruction according to the first attribute table.
  • the logical address corresponding to the TRIM instruction may have a fourth logical address with a pre-allocated attribute, or a plurality of fourth logical addresses with a pre-allocated attribute, and may have zero attributes as Pre-assigned fourth logical address.
  • Step S403 If yes, the SSD determines a first physical address having a mapping relationship with the fourth logical address according to the first mapping table and the fourth logical address.
  • the SSD determines a first physical entity having a mapping relationship with the fourth logical address according to the first mapping table and the fourth logical address. address.
  • the first physical address that has a mapping relationship with the fourth logical address is the physical address mapped in advance by the SSD to the fourth logical address in the SSD, and is also the first physical address mapped to the fourth logical address in the first mapping table.
  • Step S404 The SSD updates the attribute of the fourth logical address in the first attribute table to idle, and updates the attribute of the first physical address in the second attribute table that has a mapping relationship with the fourth logical address to idle.
  • Step S405 The SSD updates the first physical address in the first mapping table that has a mapping relationship with the fourth logical address to an invalid address or 0.
  • mapping relationship between the fourth logical address and the first physical address mapped in the SSD for the fourth logical address is released. That is, the TRIM instruction can release the mapping relationship between the logical address and the physical address mapped in the SSD for the logical address in advance.
  • This embodiment provides a data processing method when a logical address corresponding to a TRIM instruction exists with a fourth logical address whose attribute is pre-allocated.
  • FIG. 7 is a schematic diagram of a garbage collection operation process provided in this application. Referring to FIG. 7, the method in this embodiment includes:
  • Step S501 When the SSD performs a garbage collection operation, the SSD determines whether the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated according to the second attribute table.
  • the SSD determines whether the physical address corresponding to the target block to be erased includes a second physical address with a pre-allocation attribute according to the second attribute table.
  • the application scenario of this embodiment is a case where the SSD further stores a second mapping table.
  • Step S502 If yes, the SSD maps a third physical address to the fifth logical address mapped to the second physical address on the SSD.
  • the SSD maps a third physical address to the fifth logical address mapped to the second physical address on the SSD.
  • the third physical address is different from the second physical address.
  • step S503 the SSD updates the second physical address in the second mapping table and the first mapping table to the third physical address, updates the attribute of the third physical address in the second attribute table to pre-allocation, and updates the second physical address.
  • the attribute of the address is updated to idle; the second mapping table is used to record the mapping relationship between the pre-allocated physical address and the pre-allocated logical address.
  • the fifth logical address mapped to the second physical address is a logical address mapped to the second physical address in the first mapping table or the second mapping table before performing the garbage collection operation.
  • the second mapping table includes physical addresses with pre-allocated attributes and logical addresses with pre-allocated attributes, excluding physical addresses and logical addresses with non-pre-allocated attributes, and the first mapping table includes all of the SSDs. Logical address.
  • the second mapping table may be as shown in Table 4.
  • Table 4 is a schematic diagram of a second mapping table
  • mapping table does not include physical addresses and logical addresses whose attributes are not pre-allocated, and corresponds to a lookup of physical addresses to logical addresses, it is more convenient to find the logical addresses corresponding to the physical addresses whose pre-allocation is attributed.
  • the speed of updating the first mapping table in the scenario of the embodiment is relatively fast.
  • This embodiment is equivalent to remapping a second physical address in the SSD for the fifth logical address in the second mapping table and / or the first mapping table.
  • This embodiment provides a data processing method when a physical address corresponding to a pre-allocated second physical address exists in a corresponding physical address during garbage collection.
  • FIG. 8 is a schematic diagram of a garbage collection operation process provided in this application. Referring to FIG. 8, the method in this embodiment includes:
  • Step S601 When the SSD performs a garbage collection operation, the SSD determines whether the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated according to the second attribute table.
  • the application scenario of this embodiment is a case where the second mapping table is not stored in the SSD.
  • Step S602 If yes, the SSD remaps a third physical address on the SSD for the fifth logical address mapped with the second physical address.
  • Step S603 The SSD updates the second physical address in a mapping table to the third physical address, updates the attribute of the third physical address in the second attribute table to pre-allocation, and updates the attribute of the second physical address to idle.
  • the fifth logical address mapped to the second physical address is a logical address mapped to the second physical address in the first mapping table or the second mapping table before performing the garbage collection operation.
  • This embodiment provides a data processing method when a physical address corresponding to a pre-allocated second physical address exists in a corresponding physical address during garbage collection.
  • FIGS. 4 to 8 are also applicable to the system architecture shown in FIG. 1. The difference is that under the architecture shown in FIG. 1, if there is no RAID application scenario, the SSD or the controller that interacts with the SSD may be a host or a CPU included in the host.
  • FIG. 9 is a schematic structural diagram of a data processing apparatus provided in the present application.
  • the data processing apparatus 200 of this embodiment includes: a generating module 21, a sending module 22, and a receiving module 23.
  • the generating module 21 is configured to generate a pre-allocation instruction, where the pre-allocation instruction includes a start logical address and a length; the pre-allocation instruction is used to instruct an SSD to allocate a first storage space in the SSD, and the start The logical address and length are used by the SSD to determine at least one first logical address, and the first logical address is an address that requires the SSD to map a first physical address in the SSD.
  • the first storage space is a free storage space.
  • the sending module 22 is configured to send the pre-allocation instruction to the SSD
  • the data processing device communicates with the SSD through a first storage transmission protocol.
  • the first storage transmission protocol may be any one of the following: a non-volatile high-speed transmission bus NVMe protocol, a network-based non-volatile high-speed transmission bus NoF protocol, an Internet small computer system interface iSCSI protocol, and a small computer system Interface SCSI protocol.
  • the sending module 22 is further configured to:
  • the pre-allocation instruction is sent to the SSD.
  • the hot spare disk of the RAID includes at least one of the first storage space, and when any data disk in the RAID group fails, the hot spare disk The spare disk is used for data recovery of the failed data disk.
  • the sending module 22 is further configured to send a read instruction to the SSD;
  • the receiving module 23 is configured to receive a read response from the SSD, the read response includes a preset result, and the preset result is used to indicate that no data is written to the first physical address that has a mapping relationship with the second logical address.
  • the second logical address is an address in a logical address corresponding to the read instruction, and the second logical address is an address in the at least one logical address.
  • the data processing device may correspond to executing the method described in the present application, and the respective modules and other operations and / or functions in the data processing device are corresponding to the hosts that implement the methods in FIGS. 3 to 8 respectively.
  • the corresponding process is omitted here for brevity.
  • the apparatus for data processing in this embodiment generates a pre-allocation instruction through a generation module included therein, and sends a pre-allocation instruction to the SSD through a transmission module included therein, so that the SSD pre-allocates storage space for the SSD according to the pre-allocation instruction, Allocate reserved storage areas in advance.
  • the data can be written to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoiding triggering garbage collection, realizing rapid data writing, and improving Data writing speed.
  • the data processing device in this embodiment may be implemented through an application-specific integrated circuit (ASIC) or a programmable logic device (PLD).
  • the PLD may be complex program logic.
  • a device complex programmable device, CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • CPLD complex programmable device
  • FPGA field-programmable gate array
  • GAL general array logic
  • FIG. 10 is a second structural schematic diagram of a data processing apparatus provided in this application.
  • the data processing apparatus 300 in this embodiment includes a receiving module 31 and a determining module 32;
  • the receiving module 31 is configured to receive a pre-allocation instruction from a host, where the pre-allocation instruction includes a start logical address and a length; the host communicates with the data processing device through a first storage transmission protocol; the first A storage transmission protocol includes a non-volatile high-speed transmission bus NVMe protocol, a network-based non-volatile high-speed transmission bus NoF protocol, an Internet small computer system interface iSCSI protocol, and a small computer system interface SCSI protocol;
  • the determining module 32 is configured to determine at least one first logical address according to the starting logical address and the length, and process the first logical address in the data processing for each of the at least one first logical address.
  • a first physical address is mapped in the device to obtain the first storage space.
  • the first storage space is a free storage space.
  • the data processing device includes a first mapping table, a first attribute table, and a second attribute table
  • the first mapping table is used to identify a mapping between a logical address and a physical address of the data processing device. Relationship, the first attribute table is used to identify the pre-allocated attributes of each logical address, and the pre-assigned attributes include pre-allocated, free, and written; and the second attribute table is used to identify the allocation of each physical address Attributes, which include idle, pre-allocated, valid, and invalid.
  • the determining module 32 is further configured to initialize a physical address mapped by each logical address in the first mapping table to an invalid address or zero when the data processing device is initialized; and, to initialize the first attribute
  • the attribute of each logical address in the table is initialized as idle, and the attribute of each physical address in the second attribute table is initialized as idle; after the receiving module 31 receives a pre-allocation instruction from the host, the first mapping is performed.
  • the receiving module 31 is further configured to receive a read instruction from the host; the determining module 32 is further configured to determine whether a logical address corresponding to the read instruction includes an attribute according to the first attribute table A pre-assigned second logical address, the second logical address being an address in the at least one first logical address; if so, sending a read response to the host, the read response including a preset result, the The preset result is used to indicate that no data has been written to the first physical address that has a mapping relationship with the second logical address.
  • the receiving module 31 is further configured to receive a write instruction from the host; the determining module 32 is further configured to determine, according to the first attribute table, whether a logical address corresponding to the write instruction includes an attribute A pre-assigned third logical address, where the third logical address is an address in the at least one first logical address; and if yes, determining the first logical address based on the first mapping table and the third logical address A first physical address having a mapping relationship between three logical addresses; and writing data corresponding to the third logical address in the data to be written into a first physical address having a mapping relationship with the third logical address, And update the attribute of the third logical address in the first attribute table to be written, and update the attribute of the first physical address in the second attribute table that has a mapping relationship with the third logical address to effective.
  • the receiving module 31 is further configured to: receive a TRIM instruction from the host; and the determining module 32 is further configured to determine whether a logical address corresponding to the TRIM instruction includes the TRIM instruction according to the first attribute table.
  • the attribute is a pre-assigned fourth logical address, and the fourth logical address is an address in the at least one first logical address, and if it is, the first logical address is determined according to the first mapping table and the fourth logical address.
  • a first physical address in which a fourth logical address has a mapping relationship and updating an attribute of the fourth logical address in the first attribute table to idle, and updating the second logical table with the fourth logical address
  • the attribute of the first physical address with the mapping relationship is updated to idle, and the first physical address mapped by the four logical addresses in the first mapping table is updated to an invalid address or zero.
  • a second mapping table is further recorded in the data processing device, and the second mapping table is used to record a mapping relationship between a pre-allocated physical address and a pre-allocated logical address; when the data processing device executes During the garbage collection operation, the determining module 32 is further configured to determine, according to the second attribute table, whether the physical address corresponding to the target block to be erased includes a second physical address whose attribute is pre-allocated; if so, the SSD is re-assigned Mapping a third physical address on the SSD for a second logical address mapped with the second physical address; and updating the second physical address in the second mapping table and the first mapping table For the third physical address, the attribute of the third physical address in the second attribute table is updated to pre-allocation, and the attribute of the second physical address is updated to idle.
  • the determining module 32 is further configured to determine, according to the second attribute table, whether the physical address corresponding to the target block to be erased includes an attribute that is pre-allocated A second physical address; if it is, the SSD maps a third physical address on the SSD to a second logical address mapped to the second physical address again; and The second physical address is updated to the third physical address, the attribute of the third physical address in the second attribute table is updated to pre-allocation, and the attribute of the second physical address is updated to idle.
  • the determining module 32 is further configured to update the attribute of the fourth physical address in the second attribute table to be invalid after receiving the pre-allocation instruction, and the fourth physical address is at Before receiving the pre-allocation instruction, the sixth logical address is a physical address mapped in the first mapping table, and the sixth logical address is an address in the at least one logical address.
  • the data processing device may correspond to executing the method described in the present application, and each module and other operations and / or functions in the data processing device are respectively corresponding to the corresponding SSD corresponding to the methods in FIGS. 3 to 8. For the sake of brevity, we will not repeat them here.
  • the device for data processing in this embodiment receives a pre-allocation instruction through a receiving module included therein, and pre-allocates storage space in the data processing device according to the pre-allocation instruction through a determination module included therein, and allocates reserved storage in advance. region.
  • data can be written into the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space to avoid triggering garbage collection. Achieve fast data writing and improve data writing speed.
  • the data processing device in this embodiment may be implemented through an application-specific integrated circuit (ASIC) or a programmable logic device (PLD).
  • the PLD may be complex program logic.
  • a device complex programmable device, CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • CPLD complex programmable device
  • FPGA field-programmable gate array
  • GAL general array logic
  • FIG. 11 is a third schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
  • the data processing device includes a processor 601, a communication interface 602, a first memory 603, a bus 604, and a solid state hard disk 605.
  • the processor 601, the communication interface 602, the first memory 603, and the solid state hard disk 605 pass through
  • the bus 604 communicates;
  • the first memory 603 is used to store instructions, and the processor 601 is used to execute the instructions stored in the first memory 603;
  • the solid-state hard disk 605 includes a controller 6051 and a second memory 6052, and the second memory 6052 is used to store instructions,
  • the controller 6051 is configured to execute an instruction stored in the second memory 6052.
  • the first memory 603 stores a first program code 6031
  • the processor 601 can call the first program code 6031 stored in the first memory 603 to perform the following operation: sending a pre-allocation instruction to the solid-state hard disk 605, the pre-allocation The instruction is used to instruct the solid-state hard disk 605 to allocate a first storage space in the solid-state hard disk 605.
  • the pre-allocation instruction includes a start logical address and a length.
  • the second memory 6052 stores the second program code 6053 of the controller 6051, and the processor controller 6051 can call the second program code 6053 stored in the second memory 6052 to perform the following operation: receiving the pre-allocation instruction, and according to the Determine a starting logical address and the length of at least one first logical address, and map a first physical address in the solid state hard disk 605 for each of the at least one first logical address to obtain the first logical address, First storage space.
  • the apparatus for data processing in this embodiment may further include a RAID controller 606; the RAID controller 606 and the processor 601 may have the same structure or two independent structures.
  • the processor 601 or the RAID controller 606 in the data processing device in this embodiment may be a host in the system shown in FIG. 1 or FIG. 2, and the solid-state hard disk 605 in this embodiment may be the one shown in FIG. 1 or FIG. 2. Shown in the system.
  • the processor 601 or the RAID controller 606 of the data processing device of this embodiment may also implement communication with a solid-state hard disk of another data processing device by means of wireless transmission or the like;
  • the solid state hard disk 605 may also communicate with a processor or a RAID controller of another data processing device through wireless transmission or other means.
  • the structure of the data processing device in this embodiment is the same as that of the other data processing device.
  • the processor 601 may be a CPU, and the processor 601 may also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a field programmable gate array. (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor or any conventional processor.
  • the first memory 603 may include a read-only memory and a random access memory, and provide instructions and data to the processor 601. Memory
  • the first memory 603 may further include a non-volatile random access memory.
  • the first memory 603 may further store information of a device type.
  • the second memory 6052 may include a read-only memory and a random access memory, and provide instructions and data to the controller 6051.
  • the second memory 6052 may further include a non-volatile random access memory.
  • the second memory 6052 may also store information of a device type.
  • the first memory 603 and the second memory 6052 may each be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrical memory Erase programmable read-only memory (EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory
  • direct RAMbus RAM direct RAMbus RAM, DR RAM
  • the bus 604 may include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as the bus 604 in the figure.
  • the data processing device, processor or RAID controller in this implementation may send a pre-allocation instruction to the solid-state hard disk.
  • the solid-state hard disk pre-allocates storage space in the solid-state hard disk according to the pre-allocation instruction, and allocates a reserved storage area in advance.
  • the solid-state hard disk can write data to the pre-allocated storage area according to the mapping relationship between the logical address and the physical address of the pre-allocated storage space, avoid triggering garbage collection, and achieve rapid data writing, thereby improving Data writing speed.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination.
  • the above embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded or executed on a computer, the processes or functions according to the present application are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server, or data center Transmission by wire (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) to another website site, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, and the like, including one or more sets of available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium.
  • the semiconductor medium may be a solid state drive (SSD).

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Abstract

本申请提供一种数据处理方法和系统，该系统包括主机和固态硬盘SSD，主机通过第一存储传输协议与SSD进行通信；主机，用于向SSD发送预分配指令，预分配指令用于指示SSD根据预分配指令在SSD中预分配第一存储空间，预分配指令包括起始逻辑地址和长度；SSD，用于接收预分配指令，并根据起始逻辑地址和长度确定至少一个第一逻辑地址，以及为至少一个第一逻辑地址中的每个第一逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间。以此提高SSD的数据写入的速度。

Description

数据处理方法和系统 技术领域
本申请涉及存储器技术领域，尤其涉及一种数据处理方法和系统。
背景技术
固态硬盘(solid state drives，SSD)由多个闪存(flash)介质组成，存储空间在写入数据后，需要先擦除才能再次写入。数据以页为单位写入SSD，以页为单位擦除无效数据。随着数据不断写入，可用存储空间越来越少。固态硬盘会定期执行垃圾回收，将待回收的块中有效数据搬迁至其他空闲页，然后，擦除待回收的块的数据，以此实现存储空间的回收。但是，如果在数据写入过程中执行垃圾回收，会导致SSD的读写速度变慢，影响SSD的性能。
如何降低垃圾回收对SSD写操作的影响成为亟待解决的技术问题。
发明内容
本申请提供了一种数据处理方法和系统，可以降低垃圾回收对SSD写操作的影响，提高了SSD的写入速度。
第一方面，本申请提供一种数据处理的系统，该系统包括主机和固态硬盘SSD，所述主机通过第一存储传输协议与所述SSD进行通信：
所述主机，用于向所述SSD发送预分配指令，所述预分配指令用于指示所述SSD在所述SSD中分配第一存储空间，所述预分配指令包括起始逻辑地址和长度；
所述SSD，用于接收所述预分配指令，根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，以及为所述至少一个第一逻辑地址中每个第一逻辑地址在所述SSD中映射一个第一物理地址，得到所述第一存储空间。
其中，所述第一存储传输协议可为如下中的任一项：非易失性高速传输总线NVMe协议、基于网络的非易失性高速传输总线NoF协议、因特网小型计算机系统接口iSCSI协议、小型计算机系统接口SCSI协议。
该方案的系统，主机向SSD发送预分配指令，SSD根据预分配指令在SSD中预分配存储空间，提前分配预留的存储区域，因此，当该系统的SSD中数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
在一种可能的实现方式中，所述主机还用于：当所述系统的输入/输出I/O负载小于或等于第一阈值时，向所述SSD发送所述预分配指令。该方案的系统，可以减少预分配过程对系统的其它性能的影响。
在一种可能的实现方式中，所述主机还用于：当所述系统初始化时，向所述SSD发送所述预分配指令。该方案的系统，适用为所述系统做掉电保护的场景，所述预分 配指令对应的存储空间为所述分配的在掉电时用于存储文件系统或者操作系统或者其它应用的元数据的存储空间的至少部分。因此，在所述系统初始化时，即向所述SSD发送所述预分配指令，使得该方案的系统可以最大限度的实现将所述系统掉电时紧急保持的文件系统或者操作系统或者其它应用的元数据快速的写入SSD中。这是因为，掉电是随时都可能发生的，越早发送所述预分配指令，实现将所述系统掉电时紧急保持的文件系统或者操作系统或者其它应用的元数据快速的写入SSD中的几率就越大。
在一种可能的实现方式中，所述主机还用于：在所述主机为所述主机创建的RAID组分配热备空间后，向所述SSD发送所述预分配指令。该方案适用于创建RAID组的场景，所述预分配指令对应的存储空间为所述主机为所述RAID组分配的热备空间的至少部分，在所述主机为所述主机创建的RAID组分配热备空间后，即向所述SSD发送所述预分配指令，使得该方案的系统可最大限度的实现将RAID组中的故障数据盘对应的数据快速的写入SSD中，这也是因为RAID组中出现故障数据盘是随时可能发生的。
在一种可能的实现方式中，所述SSD中包括第一映射表、第一属性表和第二属性表，所述第一映射表用于标识所述SSD的逻辑地址和物理地址的映射关系，所述第一属性表用于标识各个逻辑地址的预分配属性，所述预分配属性包括预分配、空闲和已写入；所述第二属性表，用于标识各个物理地址的分配属性，所述分配属性包括空闲、预分配、有效和失效；所述SSD，还用于在所述系统初始化时，将所述第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零；将所述第一属性表中每个逻辑地址的属性初始化为空闲；将所述第二属性表中每个物理地址的属性初始化为空闲；在接收所述预分配指令后，将所述第一映射表中所述第一逻辑地址映射的物理地址更新为所述SSD根据所述预分配指令为所述第一逻辑地址在所述SSD中映射的第一物理地址，将所述第一属性表中的所述第一逻辑地址的属性更新为预分配，将所述第二属性表中的所述第一物理地址的属性更新为预分配。该方案中，第一映射表的设置，可以使得SSD获知属性为预分配的逻辑地址映射的物理地址，第一属性表的设置，可以使得SSD获知SSD的各逻辑地址的属性，第二属性表的设置，可以使得SSD获知SSD的各物理地址的属性。
在一种可能的实现方式中，若所述主机创建了RAID组，所述RAID组的热备空间包括至少一个所述第一存储空间，在所述RAID组中任一数据盘故障时，所述热备空间用于故障数据盘的数据恢复。该方案的系统，可以实现在所述RAID组中任一数据盘故障时，快速的将故障数据盘对应的数据写入到热备空间中。
在一种可能的实现方式中，所述主机，还用于向所述SSD发送读指令；所述SSD，还用于根据所述第一属性表判断所述读指令对应的逻辑地址中是否包括属性为预分配的第二逻辑地址，若是，则向所述主机发送读响应，所述读响应包括预置结果，所述预置结果用于指示与所述第二逻辑地址存在映射关系的第一物理地址未写过数据；所述第二逻辑地址为所述至少一个第一逻辑地址中的地址。该方案的系统，能够在读指令对应的逻辑地址中包括属性为预分配的第二逻辑地址时，进行数据处理。
在一种可能的实现方式中，所述主机，还用于向所述SSD发送写指令，所述写指令包括待写入数据；所述SSD，还用于根据所述第一属性表判断所述写指令对应的逻 辑地址中是否包括属性为预分配的第三逻辑地址，若是，则根据所述第一映射表和所述第三逻辑地址确定与所述第三逻辑地址存在映射关系的第一物理地址，将所述待写入数据中与所述第三逻辑地址对应的数据写入与所述第三逻辑地址存在映射关系的第一物理地址，并将所述第一属性表中所述第三逻辑地址的属性更新为已写入，将所述第二属性表中与所述第三逻辑地址存在映射关系的第一物理地址的属性更新为有效；其中，所述第三逻辑地址为所述至少一个第一逻辑地址中的地址。该方案的系统，能够在写指令对应的逻辑地址中包括属性为预分配的第三逻辑地址时，进行数据处理。
在一种可能的实现方式中，所述主机，还用于向所述SSD发送TRIM指令；所述SSD，还用于根据所述第一属性表判断所述TRIM指令对应的逻辑地址中是否包括属性为预分配的第四逻辑地址，若是，则将所述第一属性表中的所述第四逻辑地址的属性更新为空闲；根据所述第一映射表和所述第四逻辑地址确定与所述第四逻辑地址存在映射关系的第一物理地址，将所述第二属性表中与所述第四逻辑地址存在映射关系的第一物理地址的属性更新为空闲，并将所述第一映射表中所述四逻辑地址映射的第一物理地址更新为无效地址或零；其中，所述第四逻辑地址为所述至少一个第一逻辑地址中的地址。该方案的系统，能够在TRIM指令对应的逻辑地址中包括属性为预分配的第四逻辑地址时，进行数据处理。
在一种可能的实现方式中，所述SSD中还记录有第二映射表，所述第二映射表用于记录预分配的第一物理地址和预分配的第一逻辑地址之间的映射关系；所述SSD，还用于当执行垃圾回收操作时，根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址，若是，则重新为与所述第二物理地址映射的第五逻辑地址在所述SSD映射一个第三物理地址，并将所述第二映射表和所述第一映射表中的所述第二物理地址更新为所述第三物理地址；将所述第二属性表中的所述第三物理地址的属性更新为预分配，所述第二物理地址的属性更新为空闲。该方案的系统，能够在待擦除目标块对应的物理地址中包括属性为预分配的第二物理地址时，进行数据处理。第二映射表的设置，可以加快系统中的SSD在垃圾回收操作后对第一映射表的更新。
在一种可能的实现方式中，所述SSD，还用于当执行垃圾回收操作时，根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址，若是，则重新为与所述第二物理地址映射的第五逻辑地址在所述SSD映射一个第三物理地址，并将所述第一映射表中的所述第二物理地址更新为所述第三物理地址；将所述第二属性表中的所述第三物理地址的属性更新为预分配，所述第二物理地址的属性更新为空闲。该方案系统，能够在在待擦除目标块对应的物理地址中包括属性为预分配的第二物理地址时，进行数据处理。
在一种可能的实现方式中，所述SSD还用于，在接收到所述预分配指令后，将所述第二属性表中的第四物理地址的属性更新为无效，所述第四物理地址为在接收到所述预分配指令之前，所述第六逻辑地址在所述第一映射表中映射的物理地址，所述第六逻辑地址为所述至少一个逻辑地址中的地址。该方案的系统，能够在预分配指令前具有写指令时，进行数据处理。
第二方面，本申请提供一种数据处理的方法，包括：主机生成预分配指令，所述 预分配指令包括起始逻辑地址和长度；所述预分配指令用于指示所述SSD在所述SSD中分配第一存储空间，所述起始逻辑地址和长度用于所述SSD确定至少一个第一逻辑地址，所述第一逻辑地址为需要所述SSD在所述SSD中映射第一物理地址的地址；所述主机向所述SSD发送所述预分配指令；其中，所述主机通过第一存储传输协议与所述SSD进行通信。
所述第一存储传输协议可为如下中的任一项：非易失性高速传输总线NVMe协议、基于网络的非易失性高速传输总线NoF协议、因特网小型计算机系统接口iSCSI协议、小型计算机系统接口SCSI协议。
该方案中，所述主机通过发送预分配指令至SSD，使得SSD在为SSD中预分配存储空间，提前分配预留的存储区域。当SSD中有数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
在一种可能的实现方式中，所述主机向所述SSD发送所述预分配指令，包括：当主机所在的系统的输入/输出I/O负载小于或等于第一阈值时，所述主机向所述SSD发送所述预分配指令。该方案，可以减少预分配过程对所述系统的其它性能的影响。
在一种可能的实现方式中，所述主机向所述SSD发送所述预分配指令，包括：当主机所在的系统初始化时，所述主机向所述SSD发送所述预分配指令。该方案，可以最大限度的实现将所述系统掉电时紧急保持的文件系统或者操作系统或者其它应用的元数据快速的写入SSD中。具体原因参见第一方面中的阐述。
在一种可能的实现方式中，所述主机向所述SSD发送所述预分配指令，包括：在所述主机为所述主机创建的RAID组分配热备空间后，所述主机向所述SSD发送所述预分配指令。
该方案，可最大限度的实现将RAID组中的故障数据盘对应的数据快速的写入SSD中。具体原因参见第一方面中的阐述。
在一种可能的实现方式中，若所述主机创建了RAID组，所述RAID组的热备空间包括至少一个第一存储空间，在所述RAID组中任一数据盘故障时，所述热备空间用于故障数据盘的数据恢复。该方案，可以实现在所述RAID组中任一数据盘故障时，快速的将故障数据盘对应的数据写入到热备空间中。
在一种可能的实现方式中，还包括：所述主机向所述SSD发送读指令；所述主机从所述SSD接收读响应，所述读响应包括预置结果，所述预置结果用于指示与第二逻辑地址存在映射关系的第一物理地址未写过数据；所述第二逻辑地址为所述读指令对应的逻辑地址中的地址，且所述第二逻辑地址为所述至少一个逻辑地址中的地址。该方案，提供了在读指令对应的逻辑地址中包括属性为预分配的第二逻辑地址时所述主机的数据处理方法。
第三方面，本申请提供一种数据处理的方法，包括：固态硬盘SSD从主机接收预分配指令，所述预分配指令包括起始逻辑地址和长度；所述主机通过第一存储传输协议与所述SSD进行通信；所述SSD，根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，并为所述至少一个第一逻辑地址中每个第一逻辑地址在所述SSD中映射一个第一物理地址，得到所述第一存储空间。其中，所述第一存储传输协议可为如 下中的任一项：非易失性高速传输总线NVMe协议、基于网络的非易失性高速传输总线NoF协议、因特网小型计算机系统接口iSCSI协议、小型计算机系统接口SCSI协议。该方案中，所述SSD根据预分配指令，在SSD中预分配存储空间，提前分配预留的存储区域。当SSD中有数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
在一种可能的实现方式中，所述SSD中包括第一映射表、第一属性表和第二属性表，所述第一映射表用于标识所述SSD中逻辑地址和物理地址的映射关系，所述第一属性表用于标识各个逻辑地址的预分配属性，所述预分配的属性包括预分配、空闲和已写入；所述第二属性表，用于标识各个物理地址的分配属性，所述分配属性包括空闲、预分配、有效和失效；在所述系统初始化时，所述SSD将所述第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零；以及，将所述第一属性表中每个逻辑地址的属性初始化为空闲；将所述第二属性表中每个物理地址的属性初始化为空闲；在所述SSD从主机接收预分配指令之后，还包括：所述SSD将所述第一映射表中所述第一逻辑地址映射的物理地址更新为所述SSD根据所述预分配指令为所述第一逻辑地址在所述SSD中映射的第一物理地址；所述SSD将所述第一属性表中的所述第一逻辑地址的属性更新为预分配，将所述第二属性表中的所述第一物理地址的属性更新为预分配。该方案中，第一映射表的设置，可以使得SSD获知属性为预分配的逻辑地址映射的物理地址，第一属性表的设置，可以使得SSD获知SSD的各逻辑地址的属性，第二属性表的设置，可以使得SSD获知SSD的各物理地址的属性。
在一种可能的实现方式中，还包括：所述SSD从所述主机接收读指令；所述SSD根据所述第一属性表判断所述读指令对应的逻辑地址中是否包括属性为预分配的第二逻辑地址，所述第二逻辑地址为所述至少一个第一逻辑地址中的地址；若是，则所述SSD向所述主机发送读响应，所述读响应包括预置结果，所述预置结果用于指示与所述第二逻辑地址存在映射关系的第一物理地址未写过数据。该方案，提供了在读指令对应的逻辑地址中包括属性为预分配的第二逻辑地址时，所述SSD的数据处理方法。
在一种可能的实现方式中，还包括：所述SSD从所述主机接收写指令；根据所述第一属性表判断所述写指令对应的逻辑地址中是否包括属性为预分配的第三逻辑地址，所述第三逻辑地址为所述至少一个第一逻辑地址中的地址；若是，所述SSD根据所述第一映射表和所述第三逻辑地址确定与所述第三逻辑地址存在映射关系的第一物理地址；所述SSD将所述待写入数据中与所述第三逻辑地址对应的数据写入与所述第三逻辑地址存在映射关系的第一物理地址，并将所述第一属性表中所述第三逻辑地址的属性更新为已写入，将所述第二属性表中与所述第三逻辑地址存在映射关系的第一物理地址的属性更新为有效。该方案，提供了在写指令对应的逻辑地址中包括属性为预分配的第三逻辑地址时，所述SSD的数据处理方法。
在一种可能的实现方式中，还包括：所述SSD从所述主机接收TRIM指令；所述SSD，根据所述第一属性表判断所述TRIM指令对应的逻辑地址中是否包括属性为预分配的第四逻辑地址，所述第四逻辑地址为所述至少一个第一逻辑地址中的地址；若是，所述SSD根据所述第一映射表和所述第四逻辑地址确定与所述第四逻辑地址存在 映射关系的第一物理地址；所述SSD将所述第一属性表中的所述第四逻辑地址的属性更新为空闲，将所述第二属性表中与所述第四逻辑地址存在映射关系的第一物理地址的属性更新为空闲；所述SSD将所述第一映射表中所述四逻辑地址映射的第一物理地址更新为无效地址或零。该方案，提供了在TRIM指令对应的逻辑地址中包括属性为预分配的第四逻辑地址时，所述SSD的数据处理方法。
在一种可能的实现方式中，所述SSD中还记录有第二映射表，所述第二映射表用于记录预分配的物理地址和预分配的逻辑地址的映射关系；当所述SSD执行垃圾回收操作时，所述SSD根据所述第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址；若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；所述SSD将所述第二映射表和所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。该方案，提供了待擦除目标块对应的物理地址中包括属性为预分配的第二物理地址时，所述SSD的数据处理。第二映射表的设置，可以加快SSD在垃圾回收操作后对第一映射表的更新。
在一种可能的实现方式中，还包括：当所述SSD执行垃圾回收操作时，所述SSD根据所述第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址；若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；所述SSD将所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。该方案，提供了待擦除目标块对应的物理地址中包括属性为预分配的第二物理地址时，所述SSD的数据处理。
在一种可能的实现方式中，在接收到所述预分配指令后，将所述第二属性表中的第四物理地址的属性更新为无效，所述第四物理地址为在接收到所述预分配指令之前，所述第六逻辑地址在所述第一映射表中映射的物理地址，所述第六逻辑地址为所述至少一个逻辑地址中的地址。
第四方面，本申请提供一种数据处理的装置，所述装置包括用于执行第二方面或第二方面任一种可能实现方式中的数据处理的方法的各个模块。
第五方面，本申请提供一种数据处理的装置，所述装置包括用于执行第三方面或第三方面任一种可能实现方式中的数据处理的方法的各个模块。
第六方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
第七方面，本申请提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请通过在为SSD中预分配存储空间，提前分配预留的存储区域。数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
图1为本申请提供的系统架构图一；
图2为本申请提供的系统架构图二；
图3为本申请提供的数据处理方法的交互图一；
图4为本申请提供的一种写指令处理过程的示意图；
图5为本申请提供的一种读指令处理过程的示意图；
图6为本申请提供的一种TRIM指令处理过程的示意图；
图7为本申请提供的一种垃圾回收操作处理过程的示意图；
图8为本申请提供的另一种垃圾回收操作处理过程的示意图；
图9为本申请提供的数据处理的系统的结构示意图一；
图10为本申请提供的数据处理的装置的结构示意图二；
图11为本申请提供的数据处理的装置的结构示意图三。
具体实施方式
下面对本申请涉及的相关名词进行说明。
本申请的存储盘可为在写入数据至一物理地址时，若该物理地址上已经写有数据，需要将之前写入的数据擦除后，才能写入新的数据的存储盘。当存储盘为硬盘时，可以为固态硬盘(solid state drive，SSD)。
逻辑地址：本申请中的逻辑地址是存储盘的逻辑地址，表现为存储盘对外提供的存储空间的地址。可以理解的是，若存储盘为SSD，则本申请中的逻辑地址是SSD的逻辑地址，表现为SSD对外提供的存储空间的地址。
物理地址：本申请中的物理地址指的是存储器内部存储单元的地址，又叫实际地址或绝对地址。可以理解的是，若存储盘为SSD，则本申请中的物理地址是SSD的物理地址。
目前，在写入数据时，存储器根据相应的映射算法确定写入指令对应的逻辑地址映射的存储盘的物理地址，从而将写入指令中待写入数据写入该物理地址对应的实际存储空间。
下面以存储盘为SSD为例，说明本实施例的数据处理方法和系统。
图1为本申请提供的系统架构图一。参见图1，本实施例的系统架构包括：主机11和SSD12，SSD内部设备有控制器13。其中，主机11中存储有SSD12的信息，SD12的信息包括：SSD12的盘符和盘容量，其中SSD12的盘符用于标识SSD，根据盘容量可以确定SSD12的起始逻辑地址和终止逻辑地址。主机11包括中央处理器(central processing unit，CPU)。
主机11和SSD12之间通过第一存储传输协议进行通信。第一存储传输协议为如下中的任一项：非易失性高速传输总线(Non-volatile Memory Express，NVMe)协议、基于网络的非易失性高速传输总线(NVMe over Fabrics，NoF)协议、因特网小型计算机系统接口(Internet Small Computer System Interface，iSCSI)协议，小型计算机系统接口(Internet Small Computer System Interface，SCSI)协议。
在图1所示的系统架构下，主机11和SSD12属于同一设备的两个结构，同一个系统架构中包括多个SSD，图1仅示出了一个SSD。作为一个可能的实施例，主机11位于第一设备，多个SSD12位于第二设备，该第一设备和该第二设备不相同。作为另一种可能的实施例，图2为本申请提供的系统架构图。图2所示的系统架构中还包括独立磁盘冗余阵列(redundant array of independent disks，RAID)控制器，RAID控制器可以由软件实现，也可以由硬件实现，该RAID控制器可以与主机位于同一个设备中，也可以是独立的设备。为了便于描述，本申请的以下实施例中，以RAID控制器与主机位于同一设备，且RAID控制器由主机中软件实现为例进行描述。
接下来结合图2所示的系统架构，介绍本实施例说明本实施例提供的数据处理方法。
图3为本申请提供的数据处理方法的交互图一。参见图3，该方法，包括：
步骤S101、主机向SSD发送预分配指令；该预分配指令包括起始逻辑地址和长度。
具体地，由于本实施例基于的系统架构包括多个SSD，因此，主机在向SSD发送预分配指令之前，需要先确定SSD是否具有预分配功能。其中，预分配功能是指可以根据主机发送的预分配指令，在SSD的存储空间中预分配第一存储空间。
在一种可能的方式中，主机向每个SSD发送功能检查指令，每个SSD接收到功能检查指令后，向RAID控制器发送第一响应，第一响应中携带相应的SSD是否具有预分配功能，主机根据各第一响应，确定各SSD是否具有预分配功能。其中，对于SSD的预分配功能的标识可以通过设置特定的功能寄存器实现。
在主机获知各SSD是否具有预分配功能后，根据当前的业务需求在多个具有预分配功能的SSD中确定需要预分配映射的物理地址的M段逻辑地址，根据该M段逻辑地址确定预分配指令中携带的起始逻辑地址和长度，其中M为正整数。本实施例中的一段逻辑地址对应一个起始逻辑地址和长度，也就是具有一定大小的存储空间。可以理解的是，发送给某一SSD的预分配指令包括的起始逻辑地址和长度是根据M段逻辑地址中属于该SSD中的S段逻辑地址各自对应的起始逻辑地址和长度确定的，S为正整数，且S≤M。可以理解的是，M段逻辑地址与哪些SSD对应，RAID控制器就向哪些SSD发送预分配指令。
作为一个可能的实施例，一个预分配指令中除了仅包括一个起始逻辑地址和长度外，还可以包括两个或两个以上起始逻辑地址和长度，即一个预分配指令可包括多组起始逻辑地址和长度，每组起始逻辑地址和长度包括一个起始逻辑地址和一个长度。比如一个预分配指令中包括起始逻辑地址1和相应的长度1，……，起始逻辑地址n和相应的长度n，……，起始逻辑地址N和相应的长度N，1≤n≤N，N≥1。起始逻辑地址1和相应的长度1对应一段逻辑地址，起始逻辑地址n和相应的长度n对应另一段逻辑地址。
示例性地，当主机中包括RAID控制器时，当前的业务需求可以包括：在RAID组的数据盘发生故障时，快速的将根据故障数据盘中的数据重构出的数据写入RAID组的热备盘。具体地，RAID控制器创建RAID组时，需要为RAID组分配热备盘(或者称为热备空间)，在RAID组中任一数据盘故障时，热备盘用于故障数据盘的数据恢复，则在该业务需求下，确定分配的热备空间为上述M段逻辑地址对应的存储空间 的至少部分。或者说，热备空间包括至少一个预分配的存储空间；其中，一个预分配的存储空间为上述M段逻辑地址中的一段逻辑地址对应的存储空间，也为一个预分配指令中包括的一组起始逻辑地址和长度对应的逻辑地址所对应的存储空间。热备盘的大小与各个RAID组的组成规则有关，比如，RAID 5中包括数据盘和热备盘，同一RAID组中各个盘的大小相同，若每个盘大小均为500G，则需要500G的存储空间作为该RAID组的热备盘。组成热备盘的预分配的存储空间可以是连续的存储空间，也可以是间断的存储空间。另外，组成热备盘的预分配的存储空间可以来自同一个SSD的一个或多个存储区域，也可以是来自不同SSD的多个存储区域，本申请不作限定。
在一种可能的方式中，在创建RAID组时，RAID控制器可以一次性为该RAID组分配与RAID组的数据盘的存储空间大小相匹配的存储空间作为热备盘。也可以先为RAID组分配第一子热备空间，第一子热备空间与该RAID组所需的热备盘大小的比例大于或等于第一值，第一值可以根据业务需求设置，例如，第一值可以为0.3、0.5或0.8。RAID控制器再根据该RAID组中数据写入情况，动态增加该RAID组的热备盘的大小，保证第一子热备空间的大小始终大于第二值，第二值为该RAID组中数据写入最多的盘的数据写入量。例如，RAID组1的热备盘需要500G，预设值为0.3，此时，第一子热备空间需要大于或等于150G。随着RAID组中数据不断写入，第一子热备空间大小需要不断增加，保证第一子热备空间大小始终大于或等于该RAID组中数据盘写入最多的盘的数据写入量。
可选地，此时向SSD发送预分配指令的可为主机包括的RAID控制器，RAID控制器向SSD发送预分配指令的时机可为：在RAID控制器为RAID控制器创建的RAID组分配热备空间后，向所述SSD发送所述预分配指令。
示例性地，当前的业务需求包括：需要做掉电保护，以在主机对应的系统发生掉电时，主机对应的系统可将保存的操作系统、文件系统或其它应用的元数据快速写入到SSD中。具体地，主机在初始化时需要为操作系统、文件系统或其它应用预先在至少一个SSD中分配用于存储紧急数据(紧急数据为上述保存的操作系统、文件系统或其它应用的元数据)的存储空间，则在该业务需求下，确定主机在初始化时需要为操作系统、文件系统或其它应用预先在至少一个SSD分配用于存储紧急数据的存储空间为上述M段逻辑地址对应的存储空间的至少部分。
可选地，此时主机向SSD发送预分配指令的时机可为：当主机对应的系统初始化时，主机向SSD发送预分配指令。
示例性地，当前的业务需求包括：提前为其它未预料到的大量的数据的写入在SSD中准备存储空间，比如结合TRIM指令确定预分配指令中携带的起始逻辑地址和长度，此时，确定主机在发送该次发送预分配指令之前的预设时长内发送的至少一个TRIM指令对应的逻辑地址所对应的存储空间上述M段逻辑地址对应的存储空间的至少部分。
可以理解的是，当空闲存储空间小于或等于预设值时，可以通过TRIM指令清除无效数据，预留部分存储空间用于上述预分配。另外，在系统初始化阶段或存储空间充足的情况下，也可以直接下发预分配指令，不需要执行TRIM指令清除无效数据以获得空闲的存储空间。
可选地，此时主机向SSD发送预分配指令的时机可为：当主机对应的系统的输入 /输出(input/output，I/O)负载小于或等于第一阈值时，主机向SSD发送预分配指令。
步骤S102、SSD根据起始逻辑地址和长度确定至少一个第一逻辑地址，并为至少一个第一逻辑地址中的每个逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间。其中，第一存储空间为空闲的存储空间。
具体地，可以理解的是，执行该步骤的实际上为SSD的控制器。
SSD接收预分配指令后，对于预分配指令包括的一组起始逻辑地址和长度，SSD会将起始逻辑地址和长度对应的存储空间进行切片，切片得到的每个子存储空间对应一个第一逻辑地址，从而得到至少一个第一逻辑地址；SSD为该至少一个第一逻辑地址中的每个第一逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间，第一存储空间为空闲的存储空间。其中，SSD为第一逻辑地址在SSD中映射一个第一物理地址，也就是SSD为第一逻辑地址在SSD中预分配一个映射的第一物理地址，或者说，SSD预先为第一逻辑地址在SSD中映射一个第一物理地址。因此，可以认为，SSD为第一逻辑地址在SSD中映射的一个第一物理地址与该第一逻辑地址存在映射关系。
由于为该至少一个第一逻辑地址中的每个第一逻辑地址在SSD中映射了一个第一物理地址，因此，具有至少一个第一物理地址，第一存储空间为该至少一个第一物理地址组成的存储空间。第一存储空间可为连续的存储空间，也可为离散的存储空间。
可以理解的是，预分配命令的一组起始逻辑地址和长度对应一个第一存储空间；第一存储空间即为步骤S101中的预分配的存储空间。
示例性地，若预分配指令中携带一组起始逻辑地址和长度：起始逻辑地址1和相应的长度1，则SSD根据起始逻辑地址1和相应的长度1确定一组逻辑地址，可称为A组逻辑地址，该A组逻辑地址包括至少一个第一逻辑地址，然后为该A组逻辑地址包括的每个第一逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间A，该第一存储空间A为A组逻辑地址包括的各个第一逻辑地址各自在SSD中映射的多个第一物理地址组成的存储空间。
示例性地，若预分配指令中携带两组起始逻辑地址和长度：起始逻辑地址1和相应的长度1，起始逻辑地址2和相应的长度2，则SSD根据起始逻辑地址1和相应的长度1确定一组逻辑地址，可称为A组逻辑地址，该A组逻辑地址包括至少一个第一逻辑地址，然后为该A组逻辑地址包括的每个第一逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间A，该第一存储空间A为该A组逻辑地址包括的各第一逻辑地址各自在SSD中映射的各第一物理地址组成的存储空间；SSD还根据起始逻辑地址2和相应的长度2确定一组逻辑地址，可称为B组逻辑地址，该B组逻辑地址包括至少一个第一逻辑地址，然后为该B组逻辑地址包括的每个第一逻辑地址在SSD中映射一个第一物理地址，得到第一存储空间B，该第一存储空间B为该B组逻辑地址包括的各第一逻辑地址各自在SSD中映射的各第一物理地址组成的存储空间。
可以理解的是，若SSD根据一组起始逻辑地址和长度确定的至少一个第一逻辑地址中存在非按页对齐的逻辑地址，则将该非按页对齐的逻辑地址舍弃，不为其预分配第一物理地址。
进一步地，SSD中存储有第一映射表、第一属性表和第二属性表，第一映射表用于标识逻辑地址和物理地址的映射关系，第一属性表用于标识每个逻辑地址的预分配 属性，每个逻辑地址的预分配的属性包括预分配、空闲和已写入；第二属性表，用于标识每个物理地址的分配属性，每个物理地址的分配属性包括空闲、预分配、有效和失效；其中，空闲的逻辑地址(属性为空闲的逻辑地址)是指未写入数据的且SSD也未根据预分配指令预先在SSD中为其映射一个物理地址的逻辑地址，预分配的逻辑地址(属性为预分配的逻辑地址)为在第一映射表中存在与其映射的物理地址的逻辑地址，已写入的逻辑地址(属性为已写入的逻辑地址)是指对应的物理地址已经写入数据的逻辑地址；空闲的物理地址(属性为空闲的物理地址)为未写入数据的物理地址，预分配的物理地址(属性为预分配的物理地址)为与预分配的逻辑地址具有映射关系的物理地址，有效的物理地址(属性为有效的物理地址)为已写入数据且数据有效的物理地址，失效的物理地址(属性为失效的物理地址)为已经写入的数据但数据无效已物理地址。
其中，第一映射表、第一属性表和第二属性表均可以采用数组实现；也可以通过使用位图或者链表实现；还可以采用文本或数据库实现。
在系统初始化时，将第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零，如表1所示；将第一属性表中每个逻辑地址的属性初始化为空闲，如表2所示；将第二属性表中每个物理地址的属性初始化为空闲，如表3所示。
表1一种第一映射表的示例
Figure PCTCN2019094139-appb-000001
参见表1，表1中的第一行中的数字指示逻辑地址，第一行中的MAX指示SSD的最后一个逻辑地址，第二行中N指示无效地址，即指示SSD对的控制器未预先在SSD中为相应的逻辑地址映射一个物理地址。
可以理解的是，表1只是第一映射表的一种实现方式，还具有其它的实现方式，比如：第一映射表的实现形式除了如表1所示的数组外，还可为没有表1中的第一行，而是第一行作为数组的下标。
表2一种第一属性表的示例
Figure PCTCN2019094139-appb-000002
参见表2，表2中的第一行中的数字指示逻辑地址，第一行中的MAX指示SSD的最后一个逻辑地址，第二行中X指示逻辑地址的属性为空闲。
可以理解的是，表2只是第一属性表的一种实现方式，还具有其它的实现方式，比如：第一属性的实现形式除了如表2所示的数组外，还可为没有表2中的第一行， 而是第一行作为数组的下标。
表3一种第二属性表的示例
Figure PCTCN2019094139-appb-000003
参见表3，表3中的第一行中的数字指示物理地址，第一行中的MAX指示SSD的最后一个物理地址，第二行中F指示物理地址的属性为空闲。
可以理解的是，表3只是第二属性表的一种实现方式，还具有其它的实现方式，比如：第二属性的实现形式除了如表3所示的数组外，还可为没有表3中的第一行，而是第一行作为数组的下标。
在接收到预分配指令后，将第一映射表中第一逻辑地址映射的物理地址更新为SSD根据预分配指令为该第一逻辑地址在SSD中映射的第一物理地址，将第一属性表中的第一逻辑地址的属性更新为预分配，将第二属性表中的第一物理地址的属性更新为预分配。
通过上述过程，实现了为逻辑地址预先在SSD中映射物理地址的目的。
在上述需要预分配映射的物理地址的M段逻辑地址对应的存储空间包括RAID组的热备空间时，由于通过上述过程可为该M段逻辑地址对应的每个逻辑地址均预先在SSD中映射一个物理地址，因此，在RAID组的某一数据盘发生损坏时，对于热备空间对应的各SSD中的每个SSD，主机中的RAID控制器向该SSD发送写指令，写指令对应的逻辑地址为该M段逻辑地址对应的至少部分逻辑地址，该SSD根据第一映射表获取预先为该写指令对应的逻辑地址在SSD中映射的物理地址，将该写指令中的待写入数据(根据损坏的数据盘中的数据重构出的至少部分数据)直接写入至预先为该写指令对应的逻辑地址在SSD中映射的物理地址，无需采用映射算法实时计算该写指令对应的逻辑地址映射的物理地址，又由于预先为该写指令对应的逻辑地址在SSD中映射的物理地址对应的存储空间为空闲的存储空间，因此，也不会触发垃圾回收的操作，提高了写入的速度。
在上述需要预分配映射的物理地址的M段逻辑地址对应的存储空间包括主机为操作系统、文件系统或其它应用预先在至少一个SSD分配的用于存储紧急数据的存储空间时，由于通过上述过程可为该M段逻辑地址对应的每个逻辑地址均预先在SSD中映射一个物理地址，因此，在主机对应的系统发生掉电时，对于用于存储紧急数据的存储空间对应的各SSD中的每个SSD，主机向该SSD发送写指令，写指令对应的逻辑地址为该M段逻辑地址对应的至少部分逻辑地址，该SSD根据第一映射表获取预先为该写指令对应的逻辑地址在SSD中映射的物理地址，将该写指令中的待写入数据(紧急数据中的至少部分数据)直接写入至预先为该写指令对应的逻辑地址在SSD中映射的物理地址中，无需采用映射算法实时计算该写指令对应的逻辑地址映射的物理地址，又由于预先为该写指令对应的逻辑地址在SSD中映射的物理地址对应的存储空间为空闲的存储空间，因此，也不会触发垃圾回收的操作，提高了写入的速度。
在上述需要预分配映射的物理地址的M段逻辑地址对应的逻辑地址包括主机获取该次发送预分配指令之前的预设时长内发送的至少一个TRIM指令对应的逻辑地址时，相当于一直存在已经预分配好物理地址的逻辑地址，当有数据写入时，可以先写入为该M段逻辑地址对应的至少部分逻辑地址预先在SSD中映射的物理地址中，参照上述的分析，可以提高写入的速度。
本实施例的数据处理方法，通过在为SSD中预分配存储空间，提前分配预留的存储区域。数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
下面在图3所述方法基础上，结合图4至图8分别以写指令、读指令、TRIM指令和垃圾回收过程为例，进一步介绍本申请提供的数据处理方法。图4至图8所示的实施例中SSD执行的方法实际上为SSD的控制器执行的方法。
图4为本申请提供的一种写指令处理过程的示意图。参见图4，本实施例的方法包括：
步骤S201、主机向SSD发送写指令，该写指令包括待写入数据。
具体地，当需要向SSD写入数据时，主机向SSD发送写指令，该写指令包括待写入数据；可以理解的是，该写指令还包括起始逻辑地址和长度。
步骤S202、SSD根据第一属性表判断写指令对应的逻辑地址中是否包括属性为预分配的第三逻辑地址；
具体地，SSD接收到该写指令后，根据该写指令中包括的起始逻辑地址和长度确定至少一个逻辑地址，该至少一个逻辑地址即为该写指令对应的逻辑地址。接着，SSD根据第一属性表判断该写指令对应的逻辑地址中是否存在属性为预分配的第三逻辑地址。
可以理解的是，该写指令对应的逻辑地址中可能具有1个属性为预分配的第三逻辑地址，也可能具有多个属性为预分配的第三逻辑地址，还有可能具有0个属性为预分配的第三逻辑地址。
步骤S203、若是，则SSD根据第一映射表和第三逻辑地址确定与第三逻辑地址存在映射关系的第一物理地址。
若该写指令对应的逻辑地址中存在属性为预分配的第三逻辑地址，则SSD根据第一映射表和第三逻辑地址确定与第三逻辑地址存在映射关系的第一物理地址。其中，与第三逻辑地址存在映射关系的第一物理地址指的是SSD在SSD中预先为该第三逻辑地址映射的物理地址，也是第一映射表中该第二逻辑地址映射的第一物理地址。
步骤S204、SSD将待写入数据中与第三逻辑地址对应的数据写入与该第三逻辑地址存在映射关系的第一物理地址，并将第一属性表中该第三逻辑地址的属性更新为已写入，将第二属性表中与该第三逻辑地址存在映射关系的第一物理地址的属性更新为有效。
进一步地，在一种实施方式中，SSD在接收到预分配指令后，将第二属性表中的第四物理地址的属性更新为无效，该第四物理地址为在接收到所述预分配指令之前， 第六逻辑地址在上述第一映射表中映射的物理地址，该第六逻辑地址为上述至少一个逻辑地址中的地址。
本实施例提供了写指令对应的逻辑地址存在属性为预分配的第三逻辑地址时的数据处理方法。
图5为本申请提供的一种读指令处理过程的示意图，参见图5，本实施例的方法包括：
步骤S301、主机向SSD发送读指令。
具体地，当需要从SSD读数据时，主机向SSD发送读指令，该读指令包括起始逻辑地址和长度。
步骤S302、SSD根据第一属性表判断读指令对应的逻辑地址中是否包括属性为预分配的第二逻辑地址。
SSD接收到该读指令后，根据该读指令中包括的起始逻辑地址和长度确定至少一个逻辑地址，该至少一个逻辑地址即为该读指令对应的逻辑地址。接着，SSD根据第一属性表判断该读指令对应的逻辑地址中是否存在属性为预分配的第二逻辑地址。
可以理解的是，该读指令对应的逻辑地址中可能具有1个属性为预分配的第二逻辑地址，也可能具有多个属性为预分配的第二逻辑地址，还有可能具有0个属性为预分配的第二逻辑地址。
步骤S303、若是，SSD向主机发送读响应，读响应包括预置结果，预置结果用于指示与该第二逻辑地址存在映射关系的第一物理地址未写过数据。
若该读指令对应的逻辑地址中存在属性为预分配的第二逻辑地址，则说明与该第二逻辑地址存在映射关系的第一物理地址没有存储数据，因此，SSD向主机发送的读响应中包括预置结果，预置结果用于指示与该第二逻辑地址存在映射关系的第一物理地址未写过数据。其中，与该第二逻辑地址存在映射关系的第一物理地址为SSD为该第二逻辑地址预先在SSD中映射的物理地址，也是第一映射表中该第二逻辑地址映射的第一物理地址。
可选地，预置结果可为1或者0。
若该读指令对应的逻辑地址中全部是属性为预分配的地址，则根据该次读指令，SSD向主机发送的读响应中包括的均是预置结果；若该读指令对应的逻辑地址中部分是属性为预分配的地址，则根据该次读指令，SSD向主机发送的读响应中部分信息为预置结果。
本实施例提供了读指令对应的逻辑地址中存在属性为预分配的第二逻辑地址时的数据处理方法。
图6为本申请提供的一种TRIM指令处理过程的示意图，参见图6，本实施例的方法包括：
步骤S401、主机向SSD发送TRIM指令。
具体地，主机向SSD发送TRIM指令，该TRIM指令包括起始逻辑地址和长度。
下面对TRIM指令进行说明；
当一个文件在支持TRIM的系统里被删除后，操作系统会发个TRIM指令给SSD，让SSD获知这个文件的数据不再被使用，其所在的页(page)可以被回收。SSD接收 到TRIM指令后，会解除该文件对应的逻辑地址和物理地址的映射关系，使该文件的数据对应的物理地址处于失效状态，后期垃圾回收时可回收该文件的数据所在的页。
步骤S402、SSD根据第一属性表判断该TRIM指令对应的逻辑地址中是否包括属性为预分配的第四逻辑地址。
具体地，SSD接收到该TRIM指令后，根据该TRIM指令中包括的起始逻辑地址和长度确定至少一个逻辑地址，该至少一个逻辑地址即为该TRIM指令对应的逻辑地址。接着，SSD根据第一属性表判断该TRIM指令对应的逻辑地址中是否存在属性为预分配的第四逻辑地址。
可以理解的是，该TRIM指令对应的逻辑地址中可能具有1个属性为预分配的第四逻辑地址，也可能具有多个属性为预分配的第四逻辑地址，还有可能具有0个属性为预分配的第四逻辑地址。
步骤S403、若是，SSD根据第一映射表和该第四逻辑地址确定与该第四逻辑地址存在映射关系的第一物理地址。
具体地，若该TRIM指令对应的逻辑地址中存在属性为预分配的第四逻辑地址，则SSD根据第一映射表和该第四逻辑地址确定与该第四逻辑地址存在映射关系的第一物理地址。其中，与该第四逻辑地址存在映射关系的第一物理地址为SSD预先为第四逻辑地址在SSD中映射的物理地址，也是第一映射表中该第四逻辑地址映射的第一物理地址。
步骤S404、SSD将第一属性表中的该第四逻辑地址的属性更新为空闲，将第二属性表中与该第四逻辑地址存在映射关系的第一物理地址的属性更新为空闲。
步骤S405、SSD将第一映射表中与该第四逻辑地址存在映射关系的第一物理地址更新为无效地址或0。
也就是解除为该第四逻辑地址以及为该第四逻辑地址在SSD中映射的第一物理地址之间的映射关系。也就是说，TRIM指令可以解除逻辑地址以及预先为该逻辑地址在SSD中映射的物理地址之间的映射关系。
本实施例提供了TRIM指令对应的逻辑地址中存在属性为预分配的第四逻辑地址时的数据处理方法。
图7为本申请提供的一种垃圾回收操作处理过程的示意图，参见图7，本实施例的方法包括：
步骤S501、当SSD执行垃圾回收操作时，SSD根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址。
为了使得SSD具有足够的空闲存储空间，需要对SSD执行垃圾回收，此时，SSD根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址。
具体地，本实施例的应用场景为SSD中还存储有第二映射表的情况。
步骤S502、若是，SSD重新为与该第二物理地址映射的第五逻辑地址在SSD映射一个第三物理地址。
若待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址，SSD重新为与第二物理地址映射的第五逻辑地址在SSD映射一个第三物理地址。
可以理解的是，第三物理地址与第二物理地址不相同。
步骤S503、SSD将第二映射表和第一映射表中的第二物理地址更新为该第三物理地址，将第二属性表中该第三物理地址的属性更新为预分配，将第二物理地址的属性更新为空闲；第二映射表用于记录预分配的物理地址和预分配的逻辑地址之间的映射关系。其中，与第二物理地址映射的第五逻辑地址为执行该垃圾回收操作前第一映射表或者第二映射表中与该第二物理地址映射的逻辑地址。
也就是说第二映射表中包括属性为预分配的物理地址和属性为预分配的逻辑地址，不包括属性不为预分配的物理地址和逻辑地址，而第一映射表中包括SSD中所有的逻辑地址。第二映射表可如表4所示。
表4一种第二映射表的示意图
物理地址 2 3 4 5
逻辑地址 4 5 6 7
由于垃圾回收过程中拷贝有效数据时涉及物理地址到逻辑地址的反向查找，由于第一映射表中的地址太多，且第一映射表对应的是逻辑地址到物理地址的查找，若采用第一映射表查找属性为预分配的物理地址对应的逻辑地址，则比较麻烦，因此，可建立第二映射表。由于第二映射表不包括属性不为预分配的物理地址和逻辑地址，且对应的是物理地址到逻辑地址的查找，因此查找属性为预分配的物理地址对应的逻辑地址比较方便，即在本实施例的场景下更新第一映射表的速度比较快。
本实施例相当于为第二映射表和/或第一映射表中的第五逻辑地址重新在SSD中映射一个第二物理地址。
本实施例提供了垃圾回收时对应的物理地址中存在属性为预分配的第二物理地址时的数据处理方法。
图8为本申请提供的一种垃圾回收操作处理过程的示意图，参见图8，本实施例的方法包括：
步骤S601、当SSD执行垃圾回收操作时，SSD根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址。
具体地，本实施例的应用场景为SSD中未存储有第二映射表的情况。
步骤S602、若是，SSD重新为与该第二物理地址映射的第五逻辑地址在SSD映射一个第三物理地址。
步骤S603、SSD将一映射表中的第二物理地址更新为该第三物理地址，将第二属性表中该第三物理地址的属性更新为预分配，将第二物理地址的属性更新为空闲。其中，与第二物理地址映射的第五逻辑地址为执行该垃圾回收操作前第一映射表或者第二映射表中与该第二物理地址映射的逻辑地址。
本实施例提供了垃圾回收时对应的物理地址中存在属性为预分配的第二物理地址时的一种数据处理方法。
可以理解的是，图4～图8所示的数据处理方法，也同样适用于图1所示的系统架 构，不同的是，在图1所示的架构下，若没有RAID应用场景，则与SSD或者与SSD的控制器进行交互的可为主机或者主机包括的CPU。
上文中结合图1至图8，详细描述了根据本申请所提供的数据处理的方法，下面将结合图9-11，描述根据本申请所提供的数据处理的装置。
图9为本申请提供的数据处理的装置的结构示意图一，参见图9，本实施例的数据处理的装置200包括：生成模块21、发送模块22和接收模块23；
所述生成模块21，用于生成预分配指令，所述预分配指令包括起始逻辑地址和长度；所述预分配指令用于指示SSD在所述SSD中分配第一存储空间，所述起始逻辑地址和长度用于所述SSD确定至少一个第一逻辑地址，所述第一逻辑地址为需要所述SSD在SSD中映射第一物理地址的地址。所述第一存储空间为空闲的存储空间。
所述发送模块22，用于向所述SSD发送所述预分配指令；
其中，所述数据处理的装置通过第一存储传输协议与所述SSD进行通信。所述第一存储传输协议可为如下中的任一项：非易失性高速传输总线NVMe协议、基于网络的非易失性高速传输总线NoF协议、因特网小型计算机系统接口iSCSI协议、小型计算机系统接口SCSI协议。
可选地，所述发送模块22，还用于：
当数据处理的装置所在的系统的输入/输出I/O负载小于或等于第一阈值时，向所述SSD发送所述预分配指令；或者，
当数据处理的装置所在的系统初始化时，向所述SSD发送所述预分配指令；或者，
在所述数据处理的装置为所述数据处理的装置创建的RAID组分配热备空间后，向所述SSD发送所述预分配指令。
可选地，若所述数据处理的装置创建了RAID组，则所述RAID的热备盘包括至少一个所述第一存储空间，在所述RAID组中任一数据盘故障时，所述热备盘用于故障数据盘的数据恢复。
可选地，所述发送模块22，还用于向所述SSD发送读指令；
所述接收模块23，用于从所述SSD接收读响应，所述读响应包括预置结果，所述预置结果用于指示与第二逻辑地址存在映射关系的第一物理地址未写过数据；所述第二逻辑地址为所述读指令对应的逻辑地址中的地址，且所述第二逻辑地址为所述至少一个逻辑地址中的地址。
根据本申请的数据处理装置可对应于执行本申请中描述的方法，并且数据处理装置中的各个模块的和其它操作和/或功能分别为了实现图3至图8中的各个方法的主机对应的相应流程，为了简洁，在此不再赘述。
本实施例中的数据处理的装置，通过其包括的生成模块生成预分配指令，通过其包括的发送模块向SSD发送预分配指令，使得SSD根据该预分配指令在为SSD中预分配存储空间，提前分配预留的存储区域。这样，当SSD中有数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
应理解的是，本实施例的数据处理的装置可以通过专用集成电路 (application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。也可以通过软件实现图3～图8所示的数据处理方法时，本申请的数据处理的装置及其各个模块也可以为软件模块。
图10为本申请提供的数据处理的装置的结构示意图二，参见图10，本实施例的数据处理的装置300包括：接收模块31和确定模块32；
所述接收模块31，用于从主机接收预分配指令，所述预分配指令包括起始逻辑地址和长度；所述主机通过第一存储传输协议与所述数据处理的装置进行通信；所述第一存储传输协议包括非易失性高速传输总线NVMe协议、基于网络的非易失性高速传输总线NoF协议、因特网小型计算机系统接口iSCSI协议、小型计算机系统接口SCSI协议；
所述确定模块32，用于根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，并为所述至少一个第一逻辑地址中每个第一逻辑地址在所述数据处理的装置中映射一个第一物理地址，得到所述第一存储空间。所述第一存储空间为空闲的存储空间。
可选地，所述数据处理的装置中包括第一映射表、第一属性表和第二属性表，所述第一映射表用于标识所述数据处理的装置的逻辑地址和物理地址的映射关系，所述第一属性表用于标识各个逻辑地址的预分配属性，所述预分配的属性包括预分配、空闲和已写入；所述第二属性表，用于标识各个物理地址的分配属性，所述分配属性包括空闲、预分配、有效和失效。所述确定模块32，还用于在所述数据处理装置初始化时，将所述第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零；以及，将所述第一属性表中每个逻辑地址的属性初始化为空闲，将所述第二属性表中每个物理地址的属性初始化为空闲；在所述接收模块31从主机接收预分配指令之后，将所述第一映射表中所述第一逻辑地址映射的物理地址更新为所述确定模块32根据所述预分配指令为所述第一逻辑地址在所述数据处理的装置中映射的第一物理地址；以及，将所述第一属性表中的所述第一逻辑地址的属性更新为预分配，将所述第二属性表中的所述第一物理地址的属性更新为预分配。
可选地，所述接收模块31，还用于从所述主机接收读指令；所述确定模块32，还用于根据所述第一属性表判断所述读指令对应的逻辑地址中是否包括属性为预分配的第二逻辑地址，所述第二逻辑地址为所述至少一个第一逻辑地址中的地址；若是，则向所述主机发送读响应，所述读响应包括预置结果，所述预置结果用于指示与所述第二逻辑地址存在映射关系的第一物理地址未写过数据。
可选地，所述接收模块31，还用于从所述主机接收写指令；所述确定模块32，还用于根据所述第一属性表判断所述写指令对应的逻辑地址中是否包括属性为预分配的第三逻辑地址，所述第三逻辑地址为所述至少一个第一逻辑地址中的地址；若是，则根据所述第一映射表和所述第三逻辑地址确定与所述第三逻辑地址存在映射关系的第 一物理地址；以及，将所述待写入数据中与所述第三逻辑地址对应的数据写入与所述第三逻辑地址存在映射关系的第一物理地址，并将所述第一属性表中所述第三逻辑地址的属性更新为已写入，将所述第二属性表中与所述第三逻辑地址存在映射关系的第一物理地址的属性更新为有效。
可选地，所述接收模块31，还用于：从所述主机接收TRIM指令；所述确定模块32，还用于根据所述第一属性表判断所述TRIM指令对应的逻辑地址中是否包括属性为预分配的第四逻辑地址，所述第四逻辑地址为所述至少一个第一逻辑地址中的地址，若是，则根据所述第一映射表和所述第四逻辑地址确定与所述第四逻辑地址存在映射关系的第一物理地址；以及，将所述第一属性表中的所述第四逻辑地址的属性更新为空闲，将所述第二属性表中与所述第四逻辑地址存在映射关系的第一物理地址的属性更新为空闲，将所述第一映射表中所述四逻辑地址映射的第一物理地址更新为无效地址或零。
可选地，所述数据处理装置中还记录有第二映射表，所述第二映射表用于记录预分配的物理地址和预分配的逻辑地址的映射关系；当所述数据处理的装置执行垃圾回收操作时，所述确定模块32还用于根据所述第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址；若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；以及，将所述第二映射表和所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。
可选地，当所述数据处理的装置执行垃圾回收操作时，所述确定模块32还用于根据所述第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址；若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；以及，将所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。
可选地，所述确定模块32，还用于在接收到所述预分配指令后，将所述第二属性表中的第四物理地址的属性更新为无效，所述第四物理地址为在接收到所述预分配指令之前，所述第六逻辑地址在所述第一映射表中映射的物理地址，所述第六逻辑地址为所述至少一个逻辑地址中的地址。
根据本申请的数据处理装置可对应于执行本申请中描述的方法，并且数据处理装置中的各个模块和其它操作和/或功能分别为了实现图3至图8中的各个方法的SSD对应的相应流程，为了简洁，在此不再赘述。
本实施例中的数据处理的装置，通过其包括的接收模块接收预分配指令，通过其包括的确定模块根据该预分配指令在该数据处理的装置中预分配存储空间，提前分配预留的存储区域。这样，当本实施例的数据处理的装置中有数据写入时，可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，提高数据写入速度。
应理解的是，本实施例的数据处理的装置可以通过专用集成电路 (application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。也可以通过软件实现图3～图8所示的数据处理方法时，本申请的数据处理的装置及其各个模块也可以为软件模块。
图11为本发明实施例提供的数据处理装置的结构示意图三。如图所示，所述数据处理装置包括处理器601、通信接口602、第一存储器603、总线604、固态硬盘605；其中，处理器601、通信接口602、第一存储器603、固态硬盘605通过总线604进行通信；第一存储器603用于存储指令，处理器601用于执行第一存储器603存储的指令；固态硬盘605包括控制器6051和第二存储器6052，第二存储器6052用于存储指令，控制器6051用于执行第二存储器6052存储的指令。
具体地，第一存储器603存储有第一程序代码6031，且处理器601可以调用第一存储器603中存储的第一程序代码6031执行以下操作：向固态硬盘605发送预分配指令，所述预分配指令用于指示所述固态硬盘605在所述固态硬盘605中分配第一存储空间，所述预分配指令包括起始逻辑地址和长度。
第二存储器6052存储有控制器6051的第二程序代码6053，且处理器控制器6051可以调用第二存储器6052中存储的第二程序代码6053执行以下操作：接收所述预分配指令，根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，以及为所述至少一个第一逻辑地址中每个第一逻辑地址在所述固态硬盘605中映射一个第一物理地址，得到所述第一存储空间。
可选地，本实施例的数据处理的装置还可包括RAID控制器606；RAID控制器606与处理器601可以是同一个结构，也可以是独立的两个结构。
本实施例的数据处理装置中的处理器601或者RAID控制器606可为图1或图2中所示的系统中的主机，本实施例中的固态硬盘605可为图1或图2中所示的系统中的SSD。
进一步地，本实施例的数据处理的装置的处理器601或者RAID控制器606，还可以与另一数据处理的装置的固态硬盘通过无线传输等手段实现通信；本实施例的数据处理的装置的固态硬盘605，还可以与另一数据处理的装置的处理器或者RAID控制器通过无线传输等手段实现通信。其中，本实施例的数据处理的装置和该另一数据处理的装置的结构相同。
应理解，在本申请实施例中，该处理器601可以是CPU，该处理器601还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。
该第一存储器603可以包括只读存储器和随机存取存储器，并向处理器601提供指令和数据。存储器第一存储器603还可以包括非易失性随机存取存储器。例如，第一存储器603还可以存储设备类型的信息。
该第二存储器6052可以包括只读存储器和随机存取存储器，并向控制器6051提供指令和数据。该第二存储器6052还可以包括非易失性随机存取存储器。例如，第二存储器6052还可以存储设备类型的信息。
该第一存储器603和第二存储器6052均可以是易失性存储器或非易失性存储器，或均可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
该总线604除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线604。
本实施的数据处理的装置，处理器或者RAID控制器可向固态硬盘发送预分配指令，固态硬盘根据该预分配指令在固态硬盘中预分配存储空间，提前分配预留的存储区域，因此，当固态硬盘中数据写入时，固态硬盘可以根据预分配存储空间的逻辑地址和物理地址的映射关系，将数据写入到预分配的存储区域，避免触发垃圾回收，实现数据快速写入，从而提高了数据写入速度。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (16)

  1. 一种数据处理的系统，其特征在于，所述系统包括主机和固态硬盘SSD，所述主机通过第一存储传输协议与所述SSD进行通信：
    所述主机，用于向所述SSD发送预分配指令，所述预分配指令用于指示所述SSD在所述SSD中分配第一存储空间，所述预分配指令包括起始逻辑地址和长度；
    所述SSD，用于接收所述预分配指令，根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，以及为所述至少一个第一逻辑地址中每个第一逻辑地址在所述SSD中映射一个第一物理地址，得到所述第一存储空间。
  2. 根据权利要求1所述系统，其特征在于，所述主机，还用于：
    当所述系统的输入/输出I/O负载小于或等于第一阈值时，向所述SSD发送所述预分配指令；或者，
    当所述系统初始化时，向所述SSD发送所述预分配指令；或者，
    在所述主机为所述主机创建的RAID组分配热备空间后，向所述SSD发送所述预分配指令。
  3. 根据权利要求1或2所述系统，其特征在于，所述SSD中包括第一映射表、第一属性表和第二属性表，所述第一映射表用于标识所述SSD的逻辑地址和物理地址的映射关系，所述第一属性表用于标识各个逻辑地址的预分配属性，所述预分配属性包括预分配、空闲和已写入；所述第二属性表，用于标识各个物理地址的分配属性，所述分配属性包括空闲、预分配、有效和失效；
    所述SSD，还用于在所述系统初始化时，将所述第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零；将所述第一属性表中每个逻辑地址的属性初始化为空闲；将所述第二属性表中每个物理地址的属性初始化为空闲；在接收所述预分配指令后，将所述第一映射表中所述第一逻辑地址映射的物理地址更新为所述SSD根据所述预分配指令为所述第一逻辑地址在所述SSD中映射的第一物理地址，将所述第一属性表中的所述第一逻辑地址的属性更新为预分配，将所述第二属性表中的所述第一物理地址的属性更新为预分配。
  4. 根据权利要求1至3任一所述系统，其特征在于，若所述主机创建了RAID组，所述RAID组的热备空间包括至少一个所述第一存储空间，在所述RAID组中任一数据盘故障时，所述热备空间用于故障数据盘的数据恢复。
  5. 根据权利要求3所述系统，其特征在于，
    所述主机，还用于向所述SSD发送读指令；
    所述SSD，还用于根据所述第一属性表判断所述读指令对应的逻辑地址中是否包括属性为预分配的第二逻辑地址，若是，则向所述主机发送读响应，所述读响应包括预置结果，所述预置结果用于指示与所述第二逻辑地址存在映射关系的第一物理地址未写过数据；所述第二逻辑地址为所述至少一个第一逻辑地址中的地址。
  6. 根据权利要求3或5所述系统，其特征在于，
    所述主机，还用于向所述SSD发送写指令，所述写指令包括待写入数据；
    所述SSD，还用于根据所述第一属性表判断所述写指令对应的逻辑地址中是否包括属性为预分配的第三逻辑地址，若是，则根据所述第一映射表和所述第三逻辑地址 确定与所述第三逻辑地址存在映射关系的第一物理地址，将所述待写入数据中与所述第三逻辑地址对应的数据写入与所述第三逻辑地址存在映射关系的第一物理地址，并将所述第一属性表中所述第三逻辑地址的属性更新为已写入，将所述第二属性表中与所述第三逻辑地址存在映射关系的第一物理地址的属性更新为有效；其中，所述第三逻辑地址为所述至少一个第一逻辑地址中的地址。
  7. 根据权利要求3、5或6所述系统，其特征在于，
    所述主机，还用于向所述SSD发送TRIM指令；
    所述SSD，还用于根据所述第一属性表判断所述TRIM指令对应的逻辑地址中是否包括属性为预分配的第四逻辑地址，若是，则将所述第一属性表中的所述第四逻辑地址的属性更新为空闲；根据所述第一映射表和所述第四逻辑地址确定与所述第四逻辑地址存在映射关系的第一物理地址，将所述第二属性表中与所述第四逻辑地址存在映射关系的第一物理地址的属性更新为空闲，并将所述第一映射表中所述四逻辑地址映射的第一物理地址更新为无效地址或零；其中，所述第四逻辑地址为所述至少一个第一逻辑地址中的地址。
  8. 根据权利要求3、5～7任一所述系统，其特征在于，所述SSD中还记录有第二映射表，
    所述第二映射表用于记录预分配的第一物理地址和预分配的第一逻辑地址之间的映射关系；
    所述SSD，还用于当执行垃圾回收操作时，根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址，若是，则重新为与所述第二物理地址映射的第五逻辑地址在所述SSD映射一个第三物理地址，并将所述第二映射表和所述第一映射表中的所述第二物理地址更新为所述第三物理地址；将所述第二属性表中的所述第三物理地址的属性更新为预分配，所述第二物理地址的属性更新为空闲。
  9. 根据权利要求3、5～7任一所述系统，其特征在于，所述SSD，还用于当执行垃圾回收操作时，根据第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址，若是，则重新为与所述第二物理地址映射的第五逻辑地址在所述SSD映射一个第三物理地址，并将所述第一映射表中的所述第二物理地址更新为所述第三物理地址；将所述第二属性表中的所述第三物理地址的属性更新为预分配，所述第二物理地址的属性更新为空闲。
  10. 一种数据处理的方法，其特征在于，包括：
    主机生成预分配指令，所述预分配指令包括起始逻辑地址和长度；所述预分配指令用于指示SSD在所述SSD中分配第一存储空间，所述起始逻辑地址和长度用于所述SSD确定至少一个第一逻辑地址，所述第一逻辑地址为需要所述SSD在所述SSD中映射一个第一物理地址的地址；
    所述主机向所述SSD发送所述预分配指令；
    其中，所述主机通过第一存储传输协议与所述SSD进行通信。
  11. 根据权里要求10所述的方法，其特征在于，所述主机向所述SSD发送所述预分配指令，包括，
    当所述主机所在的系统的输入/输出I/O负载小于或等于第一阈值时，所述主机向所述SSD发送所述预分配指令；或者，
    当所述主机所在的系统初始化时，所述主机向所述SSD发送所述预分配指令；或者，
    在所述主机为所述主机创建的RAID组分配热备空间后，所述主机向所述SSD发送所述预分配指令。
  12. 根据权利要求10所述的方法，其特征在于，若所述主机创建了RAID组，所述RAID组的热备空间包括至少一个所述第一存储空间，在所述RAID组中任一数据盘故障时，所述热备空间用于故障数据盘的数据恢复。
  13. 一种数据处理的方法，其特征在于，包括
    固态硬盘SSD从主机接收预分配指令，所述预分配指令包括起始逻辑地址和长度；所述主机通过第一存储传输协议与所述SSD进行通信；
    所述SSD，根据所述起始逻辑地址和所述长度确定至少一个第一逻辑地址，并为所述至少一个第一逻辑地址中每个第一逻辑地址在所述SSD中映射一个第一物理地址，得到所述第一存储空间。
  14. 根据权利要求13所述的方法，其特征在于，所述SSD中包括第一映射表、第一属性表和第二属性表，所述第一映射表用于标识所述SSD中逻辑地址和物理地址的映射关系，所述第一属性表用于标识各个逻辑地址的预分配属性，所述预分配的属性包括预分配、空闲和已写入；所述第二属性表，用于标识各个物理地址的分配属性，所述分配属性包括空闲、预分配、有效和失效；
    在所述SSD初始化时，所述SSD将所述第一映射表中每个逻辑地址映射的物理地址初始化为一个无效地址或零；以及，将所述第一属性表中每个逻辑地址的属性初始化为空闲；将所述第二属性表中每个物理地址的属性初始化为空闲；
    在所述SSD从主机接收预分配指令之后，还包括：
    所述SSD将所述第一映射表中所述第一逻辑地址映射的物理地址更新为所述SSD根据所述预分配指令为所述第一逻辑地址在所述SSD中映射的第一物理地址；
    所述SSD将所述第一属性表中的所述第一逻辑地址的属性更新为预分配，将所述第二属性表中的所述第一物理地址的属性更新为预分配。
  15. 根据权利要求13或14所述的方法，其特征在于，所述SSD中还记录有第二映射表，所述第二映射表用于记录预分配的物理地址和预分配的逻辑地址的映射关系；
    当所述SSD执行垃圾回收操作时，所述SSD根据所述第二属性表判断待擦除目标块对应的物理地址中是否包括属性为预分配的第二物理地址；
    若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；
    所述SSD将所述第二映射表和所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。
  16. 根据权利要求13或14所述的方法，其特征在于，
    当所述SSD执行垃圾回收操作时，所述SSD根据所述第二属性表判断待擦除目 标块对应的物理地址中是否包括属性为预分配的第二物理地址；
    若是，则所述SSD重新为与所述第二物理地址映射的第二逻辑地址在所述SSD映射一个第三物理地址；
    所述SSD将所述第一映射表中的所述第二物理地址更新为所述第三物理地址，将所述第二属性表中所述第三物理地址的属性更新为预分配，将所述第二物理地址的属性更新为空闲。
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