WO2020048508A1 - 一种码块生成方法、接收方法和装置 - Google Patents

一种码块生成方法、接收方法和装置 Download PDF

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Publication number
WO2020048508A1
WO2020048508A1 PCT/CN2019/104531 CN2019104531W WO2020048508A1 WO 2020048508 A1 WO2020048508 A1 WO 2020048508A1 CN 2019104531 W CN2019104531 W CN 2019104531W WO 2020048508 A1 WO2020048508 A1 WO 2020048508A1
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Prior art keywords
code
code block
unit
block unit
bit
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PCT/CN2019/104531
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English (en)
French (fr)
Inventor
张红标
肖帅
孙德胜
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to JP2021512784A priority Critical patent/JP7256868B2/ja
Priority to EP19858463.3A priority patent/EP3840262B1/en
Priority to KR1020217009668A priority patent/KR102449296B1/ko
Publication of WO2020048508A1 publication Critical patent/WO2020048508A1/zh
Priority to US17/193,374 priority patent/US11451325B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0075—Transmission of coding parameters to receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches

Definitions

  • the present application relates to the field of communications, and in particular, to a method, a method, and a device for generating a code block.
  • the fifth generation of communication technology (5-Generation, 5G) has begun extensive research in the industry.
  • the standard organization 3GPP defines three major scenarios of 5G: Enhance Mobile Broadband (eMBB), Massive Machine Type Communication (mMTC) and Ultra-Reliability and Low-Latency Service (URLLC); focus on high-traffic mobile broadband services such as 3D / Ultra HD video, large-scale IoT services, low latency and high Reliably connected businesses (such as driverless, industrial automation).
  • eMBB Enhance Mobile Broadband
  • mMTC Massive Machine Type Communication
  • URLLC Ultra-Reliability and Low-Latency Service
  • FIG. 1a shows a network device connected to a user at a network edge, such as a provider edge router (Provider Edge, PE).
  • the device is equipped with NNI Side and UNI side network interfaces.
  • Figure 1b shows a network device (Provider, P) in a network, and the device is only equipped with a network interface on the NNI side.
  • FIG. 2 a schematic diagram of using X-E technology to set up a network and forward data streams is shown.
  • the solid-line path that runs through the entire PE and P devices is the X-E end-to-end forwarding path.
  • the code stream exchanged by the L1.5 layer is clearly defined as 64B / 66B encoding, and the code stream type is shown in FIG. 3.
  • 64B / 66B encoding encodes 64bit data or control information into 66bit blocks for transmission.
  • the first two bits of the 66bit block represent the synchronization header, mainly due to the data alignment at the receiving end and the synchronization of the received data bitstream.
  • the synchronization header includes two types: "01” and "10". "01” indicates that the following 64 bits are data, and “10” indicates that the following 64 bits are a mixture of data and control information. 8bit is the type field, and the next 56bit is control information or data or a mixture of both.
  • Figure 4 shows a typical bearer multi-service type and rate situation.
  • SDH synchronous digital hierarchy
  • OFTUk optical converter unit
  • the code stream types of the other services are 8B / 10B code streams except 64B / 66B. Therefore, before multi-service access, these 8B / 10B code streams need to be uniformly converted into Standard 64B / 66B coded code stream, and the boundary of control information and data is determined according to the converted 64B / 66B code.
  • This application provides a method for generating a code block, which can save the overhead of additional indication information. Specifically, the following technical solutions are disclosed:
  • the present application provides a method for generating a code block, the method including: an adapting unit generating a first code block and a second code block, wherein the first code block includes a first code block unit, and The second code block includes a second code block unit, and a first indication bit is set in the first code block unit, and the first indication bit is used to indicate whether the second code block unit is a control code; sending The first code block and the second code block.
  • the second code block is located after the first code block or before the first code block; if the second code block is located after the first code block, the first indicator bit is used to indicate the current The next code block of the first code block, and whether the second code block is a control code; if the second code block is located before the first code block, the first indicator bit is used to indicate the previous of the current first code block Whether a code block is a control code.
  • the first code block and the second code block are two adjacent code blocks, and each code block is a 64B / 66B code block.
  • the first indicator bit is represented by a, occupying 1 bit space.
  • an indicator bit is configured on a code block unit in a first code block to indicate whether an adjacent code block is a control code, so that the boundary between the control code and the data code can be determined, and an additional instruction is avoided.
  • Information to indicate thereby saving the overhead of the instruction information.
  • the first indication bit indicates that the second code block unit is a control code
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit.
  • the first code block unit further includes a second indicator bit, and the second indicator bit is used to indicate whether a third code block unit before the first code block unit is a control code.
  • the second indication bit indicates that the third code block unit is a control code
  • the third code block unit is not a control code, but a data code.
  • the boundary between the third code block unit and the first code block unit is a boundary between a data code and a control code.
  • the second indicator bit is represented by b and occupies 1 bit space.
  • the control code includes a K code, or consists of a K code and at least one D code; the first code block unit is the In the case of a control code, a third indication bit is further set in the first code block unit, and the third indication bit is used to indicate the number of D codes in the first code block unit.
  • the D code is a data code used to indicate the type of the K code, for example, the Di code indicates that the K code is an IDLE control code; the Dt code indicates that the K code is a T control code.
  • the type of the K code is determined by the original code stream, and the original code block may be a 6B / 10B code block or a 10GBASE-R 64B / 66B code stream, which is not limited in the embodiment of the present application.
  • the number of the D codes can be represented by the length of the code block unit.
  • the control codes are in units of 4 bytes, that is, 32 bits, and the structure is K + D + D + D.
  • the number of D codes is 3, and each D code is an 8-bit code block unit.
  • the number of D codes in the first code block unit is represented by cc, occupying 2 bits of space.
  • the second code block further includes a fourth code block unit, and the fourth code block unit is located after the second code block unit, At least one indicator bit is set in the second code block unit, the at least one indicator bit is used to indicate whether the fourth code block unit is a control code, and to indicate whether the first code block unit is a control code; and When the second code block unit is a control code, the at least one indication bit is further used to indicate the number of D codes in the second code block unit.
  • the at least one indication bit includes a first indication bit, which is used to indicate whether a next code block unit of the current code block unit is a control code; and a second indication bit, which is used to indicate a previous code of the current code block unit. Whether the block unit is a control code; and a third indicator bit is also used to indicate the number of D codes in the code block unit constituting the control code.
  • At least one indicator bit is configured in the code block unit to indicate whether the code block unit before and after the current code block unit is a control code, and the D code length of the control code.
  • the stepwise indication of the indicator bit determines the boundary between the control code and the data code, avoiding the overhead of additional information.
  • the generating the first code block and the second code block includes: obtaining a first code stream, where the first code stream includes a control code; Compress the control code in the first code stream, and set a first indicator bit in the remaining space of the compressed code block to generate the first code block and the second code block.
  • the first code stream may be an 8B code stream, and the 8B code stream is converted from a 10B code stream in the 8B / 10B code stream; or the first code stream may also be 10GE 64B / 66B code stream of the service.
  • the control code of the first code stream includes at least one 8-bit code block unit, and performs control on the control code in the first code stream.
  • the block unit is compressed to obtain N-bit remaining space, N ⁇ 8; the first indicator bit is set in the N-bit remaining space and filled with an 8-bit K code; according to the 8-bit K code Generating the first code block and the second code block.
  • control code in the original 8B code stream is compressed into multiple code block units, and each code block unit is compressed from the original 8 bits to 4 bits, and the remaining 4 bits are The space is used to configure the first indicator bit, the second indicator bit, and the third indicator bit.
  • the first indicator bit and the second indicator bit each occupy 1 bit, and the third indicator bit takes 2 bits to form a K code, where the K code is an 8-bit code block unit; in addition, the control code before compression It can also include several D codes.
  • the control code is composed of a K code and 3 D codes, each D code is 8 bits, and the control code composed of the one K code and 3 D codes. Is a code block unit.
  • the indication bit is used to indicate the control code and data code conditions between adjacent code blocks, thereby saving the overhead of the instruction information and improving the transcoding efficiency.
  • the utilization rate of code block loading is increased by 25% compared to the D code block transparent bearer, and the boundary between the control code and the data code of the 8B / 10B code stream does not need to be restored, and it remains after being compressed by the control code.
  • the code block overhead indication is a way of associating adjacent code blocks step by step, thereby identifying the characteristics and meaning of the entire code stream.
  • the first code block is a T7 code block, and the second code block is a D code block;
  • the first code block is a S0 code block
  • the second code block is a D code block
  • the first code block is an O code block
  • the second code block is a D code block
  • the first code block is an IDLE code block
  • the second code block is a D code block
  • the T7 code block, the S0 code block, the O code block, and the IDLE code block are control codes, and the D code block is a data code.
  • the first code block may also be a D code block
  • the second code block may be a control code, such as a T7 code block, a S0 code block, and the like, which is not limited in this application.
  • code blocks such as the third code block and the fourth code block may be included, and the code stream composed of these code blocks includes but is not limited to: S0 code block + D code block, D code block + T code Blocks, O code blocks + D code blocks, S0 code blocks + D code blocks + T code blocks, etc.
  • the first code block is a T7 code block and the second code block is an S0 code block.
  • the above method further includes: generating a third code block, where the third code block is a D code block.
  • the method further includes: transcoding the D code into an S0 code block, the The SO code block includes: a type field, a K code block unit and at least one code block unit including a D code.
  • the code block unit including the K code is a code block unit generated by compressing all the code block units composed of one K code and at least one D code of the original D code block, and the K code
  • the code block unit includes at least one indicator bit.
  • the type field of the S0 code block is a "0x78" field or a code block unit.
  • the IDLE code blocks in the original code stream are compressed to generate a code block unit.
  • the code block unit is compressed from the code block units of the four control codes in the original code stream.
  • the block unit is located after the "0x78" field of the type field, and includes a first indicator bit, a second indicator bit, and a third indicator bit.
  • the first indicator bit is used to indicate the next code of the current code block unit
  • the block unit is a data code
  • the second indicator bit is used to indicate that the previous code block unit of the current code block unit is a control code
  • the third indicator bit is used to indicate that the current code block unit is compressed by the IDLE code of the 4 original code streams. to make.
  • the IDLE code block in the original code stream is further compressed, so that the transcoded code stream is compressed to be smaller than the original code stream bandwidth, so that it is suitable for some specific scenarios to the asynchronous networking system 100ppm Support for overhead characteristics such as frequency offset and bandwidth OAM.
  • the present application also provides a code block receiving method, which is used to receive a first code block and a second code block, and identify a boundary between a data code and a control code in a code stream.
  • the method includes: an adapting unit receives a first code block and a second code block, the first code block includes a first code block unit, the second code block includes a second code block unit, and the first code block unit A first indication bit is set therein; it is determined whether the second code block unit is a control code according to an indication of the first indication bit.
  • determining whether the second code block unit is a control code according to the indication of the first indication bit includes: if the first indication bit indicates that the second code block unit is the control code, the second code block unit may be determined according to the second code block unit; An indication bit set in the code to determine whether the next code block is a control code; if the first indication bit indicates that the second code block unit is not a control code, that is, a data code, it is determined that the second code block unit is a data code Before the second code block unit is a control code, a boundary between the control code and the data code is determined.
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit.
  • the first code block unit further includes a second indication bit, and the method further includes determining whether a third code block unit before the first code block unit is a control code according to an instruction of the second indication bit.
  • determining whether a third code block unit before the first code block unit is a control code according to an instruction of the second indication bit includes: if the second indication bit indicates that the third code block unit is a control Code, it is further determined whether the previous code block is a control code according to the indication bit in the third code block unit; if the second indication bit indicates that the third code block unit is not a control code and is a data code, the first A boundary between the three code block unit and the first code block unit is a boundary between a data code and a control code.
  • the control code includes a K code, or consists of a K code and at least one D code; the method further includes: in determining the first When a code block unit is the control code, the number of D codes in the first code block unit is determined according to a third indicator bit in the first code block unit.
  • the third indicator bit is not required to indicate, and the number of D codes can be determined. Number or length.
  • the second code block further includes a fourth code block unit, where the fourth code block unit is located after the second code block unit, The second code block unit is provided with at least one indication bit, and the method further includes: determining whether the fourth code block unit is a control code according to at least one indication bit in the second code block unit, and Describe whether the first unit code block is a control code.
  • the determining whether the second code block unit is a control code according to an indication of the first indication bit includes: if the first indication The information indicates that the second code block unit is not a control code, and then starts from the second code block unit as a data code.
  • the code block unit indicated by the first instruction information is a control code
  • the first indicator bit, the second indicator bit, and the third indicator bit may be carried by the compressed remaining space.
  • an 8-bit code block unit of a control code in the original 8B code stream is compressed into 4 bits.
  • the remaining 4-bit space is used to set three indicator bits, occupying a total of 4 bits, and finally generating an 8-bit K code;
  • the filled D codes can also be 8-bit code block units, and each D code is used for Indicates the type of the corresponding K code.
  • the number of the D codes may be 0 or 1, 3, and 7.
  • the present application further provides a code block generating device.
  • the device may be an adaptation unit, such as a uAdpt unit, where the device includes the first aspect and the first aspect. Units of method steps in various implementations.
  • the device includes an obtaining unit, a processing unit, and a sending unit, and may further include other units or modules such as a storage unit.
  • the present application further provides a code block receiving device.
  • the device may be an adaptation unit, such as a uAdpt unit.
  • the device includes a device for performing the second aspect and the second aspect. Units of method steps in various implementations.
  • the device includes an obtaining unit, a processing unit, and a sending unit, and may further include other units or modules such as a storage unit.
  • code block generating device described in the third aspect and the code block receiving device described in the fourth aspect may be the same device, such as a uAdpt unit; or may be different devices.
  • the present application further provides a network device.
  • the network element device may be a PE or a P, and may also be a packet bearer device.
  • the network device includes an interface board and a main control switch board.
  • the interface board includes a user-side processing chip, and the user-side processing chip is configured to implement the foregoing first aspect or the second aspect and various methods for generating the code block and receiving the code block.
  • the user-side processing chip may be provided or integrated in the user-side time-frequency unit uAdpt.
  • the user-side processing chip further includes a memory or a storage unit for storing one or more computer instructions.
  • the present application also provides a computer storage medium.
  • the computer storage medium may store a program.
  • the program When the program is executed, the foregoing aspects may be implemented, including implementation of the code block generation and code block reception methods provided in the present application. Some or all of the steps in the example.
  • the present application also provides a computer program product, which includes one or more computer instructions, such as a code block generation instruction, a code block transmission instruction, and a code block reception instruction.
  • a computer program product which includes one or more computer instructions, such as a code block generation instruction, a code block transmission instruction, and a code block reception instruction.
  • This application provides a method and device for generating a code block.
  • the code stream includes a first code block and a second code block, and at least one code block is configured in each code block.
  • the indicator bit is used to indicate whether the adjacent code block unit is a control code, so as to determine the boundary between the control code and the data code in the original code stream, which saves the overhead of additional instruction information.
  • FIG. 1a is a schematic structural diagram of a network device PE connected to a user at a network edge and provided by the present application;
  • FIG. 1a is a schematic structural diagram of a network device PE connected to a user at a network edge and provided by the present application;
  • FIG. 1b is a schematic structural diagram of a network device P in a network provided by this application.
  • FIG. 2 is a schematic diagram of using the X-E technology to form a network and forward data streams provided by this application;
  • FIG. 3 is a schematic diagram of a 64B / 66B Block type encoding of the IEEE802.3 standard provided by this application;
  • FIG. 4 is a schematic diagram of a typical multi-service type and code stream type provided by the present application.
  • FIG. 5 is a schematic structural diagram of an adaptation unit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another adaptation unit according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an 8B / 10B correspondence relationship according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a typical 8B / 10B code stream according to an embodiment of the present application.
  • 9a is a schematic structural diagram of a T7 code block according to an embodiment of the present application.
  • 9b is a schematic structural diagram of a S0 code block according to an embodiment of the present application.
  • 9c is a schematic structural diagram of a D code block according to an embodiment of the present application.
  • 9d is a schematic structural diagram of an O-code block according to an embodiment of the present application.
  • 9e is a schematic structural diagram of an IDLE code block according to an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for generating a code block according to an embodiment of the present application.
  • 11a is a schematic diagram of a code block structure according to an embodiment of the present application.
  • 11b is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11c is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11d is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11e is a schematic diagram of another code block structure according to an embodiment of the present application.
  • FIG. 11f is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11g is a schematic diagram of another code block structure according to an embodiment of the present application.
  • FIG. 11h is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11i is a schematic diagram of another code block structure according to an embodiment of the present application.
  • 11j is a schematic diagram of another code block structure according to an embodiment of the present application.
  • FIG. 12 is a schematic flowchart of a process of transcoding a 10B code stream into a 64B / 66B code stream according to an embodiment of the present application
  • FIG. 13 is a schematic flowchart of a process of transcoding a 10B code stream into an 8B code stream according to an embodiment of the present application
  • FIG. 14 is a schematic flowchart of a GE service 8B / 10B transcoding to a 64B / 66B code stream according to an embodiment of the present application;
  • FIG. 15 is a schematic flowchart of a process of converting a code block structure of a 64B / 66B code stream according to an embodiment of the present application.
  • FIG. 16 is a schematic flowchart of a process of transcoding an 8B code stream of a Fibre Channel service into a 64B / 66B code stream according to an embodiment of the present application;
  • 17 is a schematic diagram of a partial processing flow for transcoding an 8B code stream of a Fibre Channel service to a 64B / 66B code stream according to an embodiment of the present application;
  • 18a is a schematic diagram of a 10GBASE-R 64B / 66B encoding according to an embodiment of the present application
  • 18b is a schematic diagram of a 100GBASE-R 64B / 66B encoding according to an embodiment of the present application
  • 18c is a schematic structural diagram of a 64-bit code block unit of a 10GE service according to an embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a process for transcoding a 10GBASE-R 64B / 66B code stream to 100GBASE-R 64B / 66B according to an embodiment of the present application;
  • 20 is a schematic structural diagram of a device for generating a code block according to an embodiment of the present application.
  • 21 is a schematic structural diagram of a code block receiving apparatus according to an embodiment of the present application.
  • 22 is a schematic structural diagram of a packet bearer device according to an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a user-side processing chip according to an embodiment of the present application.
  • Ethernet is a baseband LAN specification and is the most common communication protocol standard used by existing LANs today.
  • Flexible Ethernet is an interface technology that implements service isolation and network segmentation. It has developed rapidly in the past two years and has been widely accepted by major standards organizations.
  • Ubiquitous Ethernet (X-Ethernet, XE) is a technology system based on the bit-block exchange of the physical layer of the Ethernet. It has the characteristics of deterministic ultra-low latency. 64B / 66B encoding types, etc.
  • M / N Bitblock coding refers to the encoding type of M payload bits and N total bits. Among them, the N total bits include M payload bits and several synchronization bits, that is, M ⁇ N in the bitblock. N.
  • M / N BitBlock flow is transmitted on the Ethernet physical layer link. For example, 1G Ethernet uses 8B / 10B encoding, and 1GE physical layer link transmits 8B / 10B code block flow; 10GE / 40GE / 100GE and Ethernet use 64B / 66B. Encoding, 10GE / 40GE / 100GE Ethernet physical layer link transmits 64B / 66B code block stream. With the development of Ethernet technology in the future, there will also be other encoding types, such as possible encoding schemes such as 128B / 130B, 256B / 257B encoding.
  • Non-M / N BitBlock coding means that the coding technology used is not M / N BitBlock coding, but other coding methods such as service frames, such as Synchronous Digital Hierarchy (SDH) or optical transmission network Optical (Transport Network, OTN) and so on.
  • service frames such as Synchronous Digital Hierarchy (SDH) or optical transmission network Optical (Transport Network, OTN) and so on.
  • SDH Synchronous Digital Hierarchy
  • OTN optical transmission network Optical
  • the service transmission method provided in this application includes at least two network devices, such as a first network device and the second network device.
  • the first network device and the second network device may be PEs or Ps in the X-E network.
  • PE is a network device connected to user equipment at the edge of the network.
  • the PE in the XE network may include a user-side adaptation unit (uAdpt), a switching unit (Switch), and a network-side adaptation unit (nAdpt ).
  • uAdpt includes uAdpt deployed at the network entrance, referred to as uAdpt (i), and uAdpt deployed at the network exit, referred to as uAdpt (e).
  • uAdpt (i) is used to implement the adaptation and interleaving of low-speed service signals or low-speed pipes to connect service signals to FlexE high-speed pipes
  • uAdpt (e) is used to complete the recovery of low-speed service signals or low-speed pipes from FlexE high-speed pipes. Functions such as deinterleaving and adaptation.
  • nAdpt is mainly used to complete the multiplexing of the FlexE pipeline to FlexE, and the SHIM is transmitted through the FlexE interface, or the FlexE pipeline is restored from the FlexE interface of the FlexE interface.
  • the received N service signals can be multiplexed and transmitted through uAdpt or nAdpt in the PE, or the original N service signals can be recovered from the one service signal formed by the multiplexing.
  • the method of the present application can be implemented by deploying a control unit in uAdpt or nAdpt.
  • the control unit can be software, a programmable device, or an integrated circuit.
  • the integrated circuit can be an application-specific integrated circuit (Application Specific Integrated Circuit). , ASIC) and so on.
  • FIG. 1b is a schematic structural diagram of P in an X-E network provided in the present application.
  • P in the X-E network may include nAdpts on both sides and an intermediate Switch.
  • the received N service signals can be multiplexed and transmitted through nAdpt in P, or the original N service signals can be recovered from the one service signal formed by multiplexing.
  • the method of the present application may be implemented by deploying a control unit in nAdpt.
  • the control unit may be software, a programmable device, or an integrated circuit.
  • the integrated circuit may be an ASIC.
  • a user-side interface (UNI) is used to connect the network device and the user device; and an interface (Network-to-Network Interface (NNI)) of the PE device is used to connect between networks or Devices within the network.
  • NNI Network-to-Network Interface
  • both interfaces NN1 are used to connect various devices in the network.
  • the original 8B / 10B stream passes the uAdpt of the PE1 device
  • the original 8B / 10B stream is transcoded into a 64B / 66B stream, and then the 64B / 66B stream passes through the L1.5 layer.
  • the switching unit and nAdpt are input to the P device. After passing the P device, they are input to the PE2 device.
  • the 64B / 66B code stream is converted to the 8B / 10B code stream by the nAdpt of the PE2 device, and is output to the user equipment.
  • the user-side adaptation unit may be uAdpt. Further, the uAdpt includes a physical layer (PHY) and encoding. (ENC) unit, where the ENC unit is used to convert the input 8B / 10B code stream into a 64B / 66B coded stream and transmit it to the XE exchange unit.
  • PHY physical layer
  • ENC encoding.
  • the network-side adaptation unit may be nAdpt. Further, the nAdpt includes a physical layer (Physical, PHY) and decoding (decoding, DEC). ) Unit, in which the DEC unit is used to convert a 64B / 66B code stream input by a device in the network into an 8B / 10B code stream and output it to the outside.
  • PHY Physical, PHY
  • DEC decoding
  • This application is to solve the technical problem of converting extra 8B / 10 coded stream to 100GE standard 64B / 66B codestream, and need to configure additional instruction information to indicate the control code and data code.
  • 8B / 10B also called 8 bytes / 10 bytes or 8B10B.
  • 8B / 10B encoding is a coding method often used in current high-speed serial communications. Its purpose is to calm the 0 and 1 in the bit stream by converting a byte-wide data into a 10-bit wide character through a mapping mechanism. The number is equal to the effect of DC balance. Because directly encoding 8-bit data into 10-bit for transmission will take up a large physical area of the chip and seriously affect the transmission efficiency of the data, most of the current use of a series of 8-bit binary numbers is divided into low 5 bits and high 3 bits.
  • the character HGFEDCBA is used to represent the 8-bit binary number before encoding, then the lower 5 bits are EDCBA, and the upper 3 bits are HGF.
  • the 6-bit binary representation after 5B / 6B encoding is abcdei
  • the 4-bit binary representation after 3B / 4B encoding is fghj
  • the final ten-digit binary number is abcdeifghj.
  • people are used to representing 8-bit data in the form of "Dx.y”
  • the control code is in the form of "Kx.y” where D is a data code, K is a special command code, and x is the original input.
  • 8B / 10B coding is the coding mechanism adopted by many high-speed serial buses at present, such as USB3.0, 1394b, Serial ATA, PCI Express, Infini-band, Fiber Channel, RapidIO and other buses or networks.
  • the 8B code stream characteristics obtained after decoding include:
  • the 8B service code stream can be regarded as a series of interleaved transmission of continuous control codes and continuous data codes.
  • the payload area (payload) carried in the service is the D code stream, that is, the data code stream, and the other including the IDLE (referred to as "I") is the C code stream, that is, the control code stream.
  • a frame structure may be composed of S codes, D codes, T codes, and R codes, where D codes are data codes and other code blocks are control codes.
  • the configuration code (Configuration, C) includes a configuration code C1 and a configuration code C2, where the encodings (Encoding) corresponding to the configuration code C1 are K28.5 and D21.5; The corresponding codes of configuration code C2 are K28.5 and D2.2.
  • the idle code may include an idle code I1 and an idle code I2, which may be encoded as K28.5 / D5.6 and K28.5 / D16.2.
  • I1 an idle code
  • I2 an idle code I2
  • K28.5 / D5.6 an idle code I2
  • K28.5 / D16.2 an idle code I2
  • K28.5 / D16.2 an idle code I2
  • K28.5 / D16.2 For the ordered set of other control codes, refer to the coding rules shown in Table 1. This embodiment does not provide examples one by one.
  • control code defined in the 8B / 10B coding specification, which are: K28.0, K28.1, K28.2, K28.3, K28.4, K28.5, K28 .6, K28.7, K23.7, K27.7, K29.7, and K30.7, as shown in Table 2, and then the remaining limited space can be obtained by re-encoding the limited number of K codes, such as compression processing Used to indicate the type of code stream or the boundary between the control code and the data code.
  • An embodiment of the present application provides a transcoding method, which can convert an original 8B / 10B code stream into a 64B / 66B code stream with a predetermined structure, which can not only save instruction information indicating the boundary between a control code and a data code in the original code stream, It can also include the transparency of the code block.
  • the transparency of the code block can be understood as that the content information carried in the code block before and after the transcoding is unchanged, and can be identified by the sending and receiving ends.
  • the technical solutions provided by the embodiments of the present application first convert the 10B encoding in the 8B / 10B code stream to the 8B encoding, so as to eliminate the 20% fixed overhead caused by the 10B encoding method, and then transcode the above
  • the 8B code stream is filled into the 64B code blocks in the 64B / 66B code stream, thereby achieving efficient transcoding and saving overhead.
  • FIG. 9a a code block with a specific structure is selected to configure an indicator bit, and a mapping relationship between 8 8-bit and 1 64-bit code blocks is established.
  • FIGS. 9a to 9e five fixed 66B bit code block structures are exemplified, including T7 code blocks (as shown in FIG. 9a), S0 code blocks (as shown in FIG. 9b), and O code blocks (as shown in FIG. 9a).
  • Figure 9d IDLE code block (as shown in Figure 9e) and D code block (as shown in Figure 9c).
  • the T7 code block, the S code block, the O code block, and the IDLE code block are control codes, and are indicated by a “10” 2-bit synchronization header, and “10” indicates that the following 64 bits are a mixture of data and control information.
  • the data can be carried by a data code (abbreviated as "D code”); the control information can be carried by a control code (abbreviated as "K code"), where 8bit next to the sync header indicates the type field, and the following 56bit It is a control code, a data code, or a mixture of both.
  • the control code I in the C code stream carries a mixture of both control information and data.
  • the control code I can be encoded by the codes K28.5 / D5.6, or K28.5 / D16.2 composition.
  • K28.5 carries control information and can be called a control code or "K” code;
  • D5.6 or D16.2 carries data and can be called a data code or "D” code. That is, the control code I can be expressed as a structure of "K code + D code”.
  • the synchronization header "01" indicates that the code block is a data code, and the 64 bits after the synchronization header "01" all carry data, which can be called a data code or a D code.
  • the control code of the "K code + D code” structure or a control code composed of one K code and multiple D codes, between these D codes and K codes
  • the boundary of is the "small boundary”; in the original code stream shown in Figure 8, the boundary between the D code stream and the C code stream is called the "big boundary”.
  • the D code stream includes multiple 8-bit data codes.
  • the C code stream includes different types of control codes.
  • the determination of the boundary between the control code and the data code refers to determining the difference between the D code stream and the C code stream. "The Big Boundary.”
  • This embodiment provides a method for generating a code block.
  • the code block can save the overhead of the indication information in the original code stream.
  • the method may be performed by an adaptation unit, such as uAdpt, or by another network element device including the adaptation unit.
  • the interface chip in the interface board is not limited.
  • the method includes the following steps:
  • Step 101 Generate a first code block and a second code block, wherein the first code block includes a first code block unit, the second code block includes a second code block unit, and the first code block unit A first indication bit is set in the first indication bit, and the first indication bit is used to indicate whether the second code block unit is a control code.
  • Step 102 Send the first code block and the second code block.
  • the positions of the first code block and the second code block include the following relationship: as shown in FIG. 11a, the first code block is located before the second code block; and, as shown in FIG. 11b, the first code block After the second code block.
  • the first indication bit is represented by "a" and occupies 1 bit.
  • the first code block unit is composed of N 8-bit units, N is greater than or equal to 1, and is a positive integer.
  • the second code block unit is also composed of N 8 bits, and N is greater than or equal to 1.
  • the first indicator bit a in the first code block unit is used to indicate whether the second code block unit of the subsequent code block is a control code; see FIG. 11b, If the first code block is located after the second code block, the first indicator bit a is used to indicate whether the second code block unit of the previous code block is a control code.
  • one possible indication mode is: if the content of the first indication bit a is "1", it indicates that the code block unit indicated by it is a control code; if the content of the first indication bit a is "0", then It indicates that the code block unit indicated by it is a data code, that is, a data code in a D code stream.
  • the first code block and the second code block may or may not be adjacent.
  • first code block and the second code block are both 64B / 66B code blocks, and the first code block and the second code block may further include other code block units.
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit, as shown in FIG. 11c, the A second indication bit is also set in the first code block unit, and the second indication bit is used to indicate whether a third code block unit before the first code block unit is a control code.
  • the third code block unit may be further disposed after the first code block unit, and the second indicator bit is used to indicate whether the third code block unit is a control code.
  • the second indicator bit is represented by “b” and occupies 1 bit.
  • both the first code block and the second code block may be a data code or a control code that is a mixture of data and control information.
  • the control code includes A K code, or a K code and at least one D code; the D code is a data code and is used to indicate the type of the K code, such as a Di code, indicating that the K code is an IDLE control code.
  • the first code block unit is a control code
  • a third indication bit is further provided in the first code block unit, and the third indication bit is used to indicate a D code in the first code block unit. Number.
  • the third indicator bit is used to indicate that the number of D codes in the first code block unit is one. It can also be 0,1,3,7.
  • the third indicator bit is represented by “cc" and occupies 2 bits.
  • this embodiment further provides a code block structure, as shown in FIG. 11f, including a first code block and a second code block.
  • the first code block includes a first code block unit
  • the second code block includes a second code block unit.
  • the first code block unit includes a control code K code and a data code D code, wherein a first indication bit a and a third indication bit cc are set in the control code K code, and the first indication bit a is used to indicate Whether the second code block unit is a control code, and the third indicator bit cc is used to indicate the number (or length) of D codes in the first code block unit.
  • the number of D codes in the first code block unit is one.
  • the second code block further includes a fourth code block unit, and the fourth code block unit is located in the second code block.
  • the at least one indicator bit is used to indicate whether the fourth code block unit is a control code and whether the first code block unit is a control
  • the at least one indicator bit is further used to indicate the number of D codes in the second code block unit.
  • the second code block includes a second code block unit and a fourth code block unit, and the second code block unit includes an indication bit a, b and cc; further, the indication bit a in the second code block unit is used to indicate whether the first code block unit is a control code, and the indication bit b is used to indicate the number of D codes in the second code block unit, indicating the bit cc is used to indicate whether the fourth code block unit is a control code.
  • the second code block includes a second code block unit and a fourth code block unit, and the second code block unit includes an indication bit a , B and cc;
  • the first code block includes a first code block unit, and the first code block unit is composed of a control code K code and a data code D code, and the control code K code is set There is a first indicator bit a.
  • the first code block includes a first code block unit and a third code block unit, where the first code block unit includes: a first indicator bit a and a second indicator bit b, and the first indicator bit a is used to indicate a second Whether the code block unit is a control code, and the second indicator bit b is used to indicate whether the third code block unit is a control code.
  • the structure of the second code block is the same as that of FIGS. 11g to 11j, and details are not described again.
  • the first code block includes a first code block unit, and the first code block unit is composed of a K code and at least one D code.
  • the K code is provided with a first indicator bit a and a third indicator.
  • Bit cc, and the first indication bit a is used to indicate whether the second code block unit is a control code
  • the third indication bit cc is used to indicate the number of D codes in the first code block unit.
  • the number of D codes is The number is one.
  • the second indicator bit b in the second code block unit is used to indicate whether the first code block unit of the previous code block is a control code
  • the first code block unit is The K code is composed of at least one D code
  • the last unit in the generated first code block unit is a K code and is used to carry at least one indicator bit.
  • the first code block is a T7 control code block
  • the last position "D6" of the T7 code block is set to the K code, and the position is exchanged with the data code D correspondingly, so that the second in the second code block unit
  • the indication bit b indicates that the first code block unit is a control code.
  • more code blocks can be generated, such as the third code block, the fourth code block, and the like, and each code block can include at least one code block unit, and An indicator bit can be configured in each code block unit to indicate whether adjacent code block units are control codes step by step, and finally the large boundary between the control code and the data code of the original code stream can be determined.
  • This embodiment only lists the first code block and the second code block, and the first code block unit and the third code block unit in the first code block, and the second code block unit and the fourth code block unit in the second code block.
  • the configuration and indication of the indicator bits if other code blocks are generated, such as the third and fourth code blocks, etc., for the specific structure and configuration of the indicator bits, refer to the first code block and the second code block.
  • the method and indication of the code block are not exemplified in this embodiment.
  • the generating the first code block and the second code block includes: obtaining a first code stream, where the first code stream includes a control code; for example, the first code stream Is an 8B code stream; the control code in the first code stream is compressed, and a first indicator bit is set in the remaining space of the compressed code block to generate the first code block and the second code block.
  • the first code stream includes a control code; for example, the first code stream Is an 8B code stream; the control code in the first code stream is compressed, and a first indicator bit is set in the remaining space of the compressed code block to generate the first code block and the second code block.
  • the control code of the first code stream includes at least one 8-bit code block unit.
  • control code in the first code stream is compressed, and a first indicator bit is set in the remaining space of the compressed code block to generate the first code block and the second code block, including: : Compressing an 8-bit code block unit in the first code stream to obtain N-bit remaining space, N ⁇ 8; setting the first indicator bit in the N-bit remaining space, and filling it with An 8-bit K code; generating the first code block and the second code block according to the 8-bit K code.
  • a second indicator bit and a third indicator bit may also be set.
  • At least one indicator bit may be set in the K code of the second code block unit, so as to indicate whether an adjacent code block unit is a control code.
  • the method for compressing a code block to generate a first code block and a second code block specifically includes:
  • Step 1 Obtain a first code stream.
  • the first code block may be an original 8B / 10B code stream, and the original 8B / 10B code stream includes a data code D code and a control code, such as a control code type T / R. / I / S code, etc.
  • the original 8B / 10B code stream is decoded into an 8B code stream, and instruction information is generated, and the instruction information is used to indicate a control code block and a data code block in the 8B code stream.
  • the original 10B code stream Tx_10b [9: 0] is decoded into an 8B code stream Tx_8b [7: 0] and a 1-bit instruction information Tx_en. In this way, Can eliminate the fixed 25% overhead of 10B encoding.
  • the service code stream is composed of a series of continuous control code blocks and a series of continuous data code blocks.
  • all control codes are composed of K code + D code * n (n ⁇ 4).
  • control codes T, R, and S are indicated by /K29.7/, /K23.7/, and /K27.7/ respectively, and are represented by Kt, Kr, and Ks in Figure 13;
  • control The code I is indicated by /K28.5/D5.6/ or /K28.5/D16.2/, which are respectively represented by Ki + Di in the figure.
  • the method further includes:
  • the second step compress the control code in the decoded 8B code stream to obtain the intermediate state code stream structure.
  • the K codes in the 8B code stream are compressed into 4-bit instructions, such as KtC / KrC / KiC / KsC and so on.
  • KtC / KrC / KiC / KsC each occupy 4 bits, and the remaining high 4 bits can be used to configure other information to indicate other meanings, so that the final size of each code block unit is 8 bits.
  • the remaining upper 4 bits are reserved as indication bits of other meanings.
  • the remaining upper 4 bits after compression can be configured according to the indication bits a, b, and cc, for example, the configuration “a” and “b “1” and “cc" are 2-bit indicator bits.
  • the 8B code stream indicator bit Tx_en can be carried on the bandwidth of the 8B code stream, thereby saving the overhead of the instruction information.
  • each indicator bit is as follows:
  • the first indicator bit a: 1 bit is used to indicate whether the next code block unit of the current code block unit is a control code.
  • the first indicator bit a is "1" it means that the next code block unit of the current code block unit is a control code; if it is "0", it means that the next code block unit is not a control code and is a data code D code.
  • the second indication bit b 1 bit, which is used to indicate whether the previous code block unit of the current code block unit is a control code.
  • the second indicator bit b is "1" it means that the previous code block unit of the current code block unit is a control code; if it is "0", it means that the previous code block unit is not a control code and is a data code D code.
  • the third indication bit cc 2 bits, which is used to indicate the length of the current code block unit, or the number of D codes in the code block unit where the third indication bit is located.
  • control code is composed of K code, or one K code and n D codes.
  • 1 indicates that the K code occupies an 8-bit code block unit. According to the relationship, Table 3 can be obtained.
  • Step 4 Map the indicator bits of the compressed state code stream to the corresponding specific code block structure according to the specific code block structure in the 64B / 66B code stream to form a 100GE standard 64B / 66B code stream.
  • the 100GE standard 64B / 66B code stream includes at least two code blocks, such as a first code block and a second code block, and each code block has a length of 64 bits. Further, the first code block And the second code block includes but is not limited to the following various situations:
  • the first code block is a T7 code block, and the second code block is a D code block;
  • the first code block is a S0 code block
  • the second code block is a D code block
  • the first code block is an O code block
  • the second code block is a D code block
  • the first code block is an IDLE code block
  • the second code block is a D code block
  • the T7 code block, the S0 code block, the O code block, and the IDLE code block are control codes, and the D code block is a data code.
  • the first code block may also be a D code block
  • the second code block may be any one of a T7 code block, a S0 code block, an O code block, and an IDLE code block, or It can also be other types of code blocks.
  • the embodiments of this application do not specifically limit the code block structure of the first code block and the second code block.
  • code block structure in the 64B / 66B code stream generated by the embodiment of this application includes, but is not limited to, various code block structures such as S0 + D, D + T, O + D, and S0 + D + T.
  • This embodiment only lists some of the more common situations, and may also include other combinations, which is not limited in this application.
  • the method provided in this embodiment generates a code stream with a specific code block structure, the code stream includes a first code block and a second code block, and each code block is configured with at least one indicator bit to indicate the phase. Whether the adjacent code block unit is a control code, thereby determining the boundary between the control code and the data code in the original code stream, and saving the overhead of additional instruction information.
  • the first code block is a T7 code block
  • the second code block is a D code block.
  • the first code block includes two 8-bit data codes and several code block units.
  • the type field 0xFF of the T7 code block replaces the first code block unit "a, b, cc, KtC" of the control code in the compressed state code stream, as shown by the arrow, corresponding to the control code in the original 10B code stream T;
  • the second code block unit "a, b, cc, KrC" in the compressed state code stream is arranged at the D2 position in the T7 code block, corresponding to the control code R in the original 10B code stream;
  • the block unit includes a K code and a D code, the K code is "a, b, cc, KiC", and the D code is "Di", corresponding to the control code IDLE in the original 10B code stream; similarly, The control code IDLE in the remaining original 10B code stream is compressed and configured as a
  • the first code block generated by the above method includes the following code block units: a data code D code, a first code block unit, a second code block unit, and a third code block unit, where the first code block unit is composed of a K code It occupies an 8-bit length.
  • the second code block unit is composed of a K code and a D code and occupies a 16-bit length.
  • the third code block unit is also composed of a K code and a D code and occupies a 16-bit length.
  • the K code in the first code block unit is provided with three indication bits, which are respectively "1,0,0" in the order of "a, b, cc", and "1" is used to indicate the second code block.
  • the unit is a control code
  • "0” is used to indicate that the previous code block unit of the first code block unit is a data code
  • "0" is used to indicate that the number of data codes in the first code block unit is zero, that is, only one is included.
  • K code is 8 bits in length.
  • each IDLE code consists of a KiC code and a Di code composition.
  • the "i" in the "Di" code is used to indicate that the K code in which it is located is an IDLE code (abbreviated as I), that is, the type of the control code is I.
  • the second code block unit is composed of "Di” and "a, b, cc, KiC", each occupying an 8-bit length;
  • the third code block unit is also composed of "Di” and "a, b, cc, KiC ", each occupying 8-bit length.
  • the second indicator bit b set on the first code block unit in the second code block is used to indicate the first Whether the last code block unit of a code block is a control code, so the last position D6 of the first code block is set to the control code "1,1,1, KiC”; at this time, the original compressed control code I generates "
  • the positions of "Di” and "a, b, cc, KiC” are interchanged.
  • the positions of the "Di” code and the "a, b, cc, KiC” code in the previous second code block unit are also interchanged compared to the compressed state code stream.
  • the second code block includes 4 code block units, and each code block unit is compressed by the control code I in the original code stream.
  • Each code block unit includes a KiC code and a Di code. Is composed of 16 bits.
  • the KiC code in each code block unit is set with three indicator bits, which are "1, 1, 1,” respectively. Specifically, "1" indicates that the next code block unit of the current code block unit is a control code; “1” indicates that the previous code block unit of the current code block unit is a control code; “1" indicates that the number of D codes in the current code block unit is one.
  • the first code block unit in the third code block is "0,1,0, KsC", occupying 8 bits, and is compressed and set by the control code S in the original 10B code stream. to make.
  • the first indication bit a is “0”, indicating that the next code block is a data code, it is determined that the control code follows from the first code block unit in the third code block.
  • the next code block of the first code block is the starting point, that is, the first code block unit of the D code block is the starting point, and each code block is determined one by one according to the first, second, and third indicator bits. Whether the unit is a control code, and then identify the boundary between the data code and the control code in the original 8B / 10B stream, and then identify the boundary between the control code and the data code through the indicator bit defined in the third step, and finally identify all codes Stream information, avoiding separate configuration instructions, resulting in extra overhead.
  • the transcoding process provided by this embodiment is a general process, which only needs to specifically identify the T code in the original code block. In theory, it can universally solve the transcoding problem of 8B / 10B encoding of all frame structures.
  • the transcoding is 64B / 66B T + D structure.
  • This embodiment provides a method of 8B / 10B transparent transcoding 64B / 66B.
  • the 10B code stream is first decoded into an 8B code stream, which can save 20% fixed overhead, and then the decoded 8B code stream control code Compression is performed, and at least one indicator bit is configured in the remaining space after compression to indicate the control code and data code conditions between adjacent code blocks, thereby saving the overhead of the instruction information, improving the transcoding efficiency, and the code block loading utilization
  • the transparent bearer is increased by 25%, and the boundary between the control code and the data code of the 8B / 10B code stream does not need to be restored.
  • the remaining code block overhead indication after the control code compression the adjacent code blocks are gradually associated. Method to identify the characteristics and meaning of the entire code stream.
  • this embodiment provides a method for receiving a code block.
  • the method includes: receiving a first code block and a second code block.
  • the code block includes a first code block unit, the second code block includes a second code block unit, and a first indication bit is set in the first code block unit; and the determining is performed according to an indication of the first indication bit. Whether the second code block unit is a control code.
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit, and the first A code block unit is further provided with a second indication bit, and the method further comprises: determining whether a third code block unit before the first code block unit is a control code according to the indication of the second indication bit.
  • control code includes a K code, or consists of a K code and at least one D code; the method further includes: in determining the first When a code block unit is the control code, the number of D codes in the first code block unit is determined according to a third indicator bit in the first code block unit.
  • the second code block further includes a fourth code block unit, and the fourth code block unit is located after the second code block unit, At least one indication bit is set in the second code block unit,
  • the method further includes determining whether the fourth code block unit is a control code and whether the first unit code block is a control code according to at least one indication bit in the second code block unit.
  • the determining whether the second code block unit is a control code according to an instruction of the first indicator bit includes: if the first instruction The information indicates that the second code block unit is not a control code, and then starts from the second code block unit as a data code.
  • the first indication information indicates that it is a control code
  • an indicator bit is configured on each code block unit, so that whether an adjacent code block unit of the current code block unit is a control code or not can be determined according to the indication of the indicator bit, and then the data code and the original code stream are determined. Control the boundaries of codes to avoid generating additional instruction information and save overhead.
  • the detailed description is based on the process of transcoding an 8B / 10B code stream into a 64B / 66B code stream without services.
  • This embodiment provides a specific method for transcoding 8B / 10B of a GE service into a 64B / 66B code stream.
  • the GE service is a typical Ethernet access service carried by multiple services.
  • the physical layer uses 8B / 10B coding, and the control code types are shown in Table 1 above.
  • the GE service can be transcoded into a T + D code block structure of a 100GE standard 64B / 66B code stream.
  • the main processing flow is as follows:
  • Step 1 Obtain a 10B code stream Tx_10b [9: 0] in the original 8B / 10B code stream.
  • the 10B code stream includes a control code and a data code.
  • Step 2 Decode the original 10B code stream Tx_10b [9: 0] into an 8B code stream Tx_8b [7: 0], and generate 1-bit instruction information Tx_en, which is used to indicate that the decoded 8B code stream is
  • the control code is also a data code. For example, a high level in the indication information indicates that a code block in the code stream is a data code, and a low level indicates that the code block in the code stream is a control code.
  • Kt / Kr / Ks in the decoded 8B code stream Tx_8b [7: 0] represents / T / R / S / three types of control codes; / Ki / Di / represents two components of / I / code. 8bit data.
  • Step 3 According to the characteristics of the service code stream, since the control codes are all composed of K codes + D codes * n (n ⁇ 4), the control codes or the K codes constituting the control codes are compressed to obtain a compressed state code stream Tx_n8b [ 7: 0], while retaining the indication information Tx_en.
  • Each 8-bit K code is compressed to a 4-bit size (up to 12 types), and it is represented by a 4-bit KtC / KrC / KiC / KsC. It is reserved for carrying at least one indicator bit, and each K code finally generated is still guaranteed to be 8 bits.
  • Step 4 Allocate at least one indicator bit in the space remaining after compression, and the indicator bit is used to indicate whether an adjacent code block unit is a control code.
  • an indicator bit configuration method includes: setting a first indicator bit a, a second indicator bit b, and a third indicator bit cc in the remaining 4 bit space, wherein the first indicator bit a is used to indicate a current code block. Whether the next code block unit of the unit is a control code; the second indicator bit b is used to indicate whether the previous code block unit of the current code block unit is a control code; the third indicator bit cc is used to indicate the length of the current code block unit, Or indicate the number of D codes in the code block unit where the third indicator bit is located.
  • control code is composed of K code, or one K code and n D codes.
  • Step 5 Convert the compressed state code stream Tx_n8b [7: 0] with the indicator bit compressed and configured into a 64B / 66B code stream with a predetermined structure.
  • the process of transcoding into a 64B / 66B code stream with a predetermined structure includes:
  • the 8 8-bit code blocks that have been compressed and configured with indicator bits are combined into a 64-bit code block, such as the first code block.
  • a second 64-bit code block, a third code block, and a fourth code block are generated.
  • the first code block generated after transcoding may be a T7 code block
  • the second code block may be a D code block, or may be another type of code block, such as an S0 code block, an O code block, and the like.
  • the first code block generated is a T7 code block and the second code block is a D code block as an example.
  • the structural characteristics of the first code block and the second code block, and the configuration principle of the indicator bits are introduced. ,details as follows:
  • the principle of configuring the indication bit is: when a code block (block) including the T code in the original code stream is transcoded to a T7 code block, it is used to identify the boundary between the D code and the control code in the original code stream.
  • the original code T code is determined as the start control code, and is replaced with the type field in T7, which does not participate in the association; the subsequent K codes are associated in the manner of "a, b, cc", and pass the control after T7
  • the indicator bit indicates whether the control code is included in T7. Except for other blocks containing T code, the code is D code.
  • the control codes are all compressed in the above manner, which can indicate whether the adjacent previous and next code blocks are controlled. code.
  • the 8B / 10B GE code stream is transparently transcoded into a 100GE standard 64B / 66B T + D code block structure.
  • the synchronization header "10" of the first code block indicates that the code block is a control code composed of data and control information
  • the type field of the T7 code block "0xFF” replaces the first in the compressed state code stream K codes “a, b, cc, KtC”, and then the data code and control code in the compressed state code stream are retained after the type field “0xFF”.
  • the synchronization header "01" of the second code block indicates that all subsequent data carried in this code block are data; the first K code "1,1,1, KtC" in the D code block is used to indicate Whether the last code block unit in the first code block is a control code. Since the positions of the K code and the D code in the control code need to be swapped in the forward and backward directions, the K code and the D code constituting the control code I in the first code block need to be interchanged in position.
  • the indication bit of the first code block unit after the synchronization header "01" is set includes "1,1,1", where the second "1" indicates the next code block of the current code block unit
  • the unit is a control code; the second "1" indicates that the previous code block unit of the current code block unit (that is, the last code block unit in the T7 code block) is the control code; the third "1" indicates the current control code or
  • the length of the code block unit occupies 2 bytes, that is, 16 bits, or it indicates that a data code D code is associated with the control code K code.
  • the The last three code block units are all control codes.
  • the penultimate code block unit "1,0,0, KrC” the second indicator bit b is "0", indicating that the previous code block unit is a data code, so It is determined that the boundary between the control code and the data in the original 10B code stream is a control code from the third code block unit of the first code block to the next, and the third code block unit of the first code block is data before code.
  • the type of each code block unit is judged step by step backward, that is, whether it is a control code.
  • the second code block includes 4 code block units, and the first indication bit a set in each code block unit is “1”, which indicates that they are all control codes.
  • the first code block unit of the third code block includes the first indication bit a as "0" and the third indication bit cc is also "0", which indicates that the next code block unit of the code block unit is a data code, and further It is obtained that a data code starts from a second code block unit of a third code block, and a control code before the second code block, that is, a position at which the control code ends is distinguished.
  • the boundary between the data code and the control code in the original 8B code stream can be identified through the indication bit information of each position in the T7 code block, and the control code to the data code are identified by the indication bits defined during the compression process. Boundary, finally identify all code stream information, saving the overhead of the indication information in the original code stream.
  • a more general 8B / 10B transcoding to 100GE standard 64B / 66B scheme is used, which can be applied to transcoding of service flows of various frame structures to ensure complete codeword transparency without loss of original code blocks.
  • the information in the stream is transcoded one-to-one, with 100% transcoding efficiency and no bandwidth expansion.
  • the above method further includes: transcoding the code blocks in the 66B code stream into an S + D + T code block structure, so as to support the frequency offset of the networking system and the operation and maintenance management (Operations, Administration) , and Maintenance (OAM).
  • OAM operation and maintenance management
  • the method further includes:
  • Step 6 Transcode the next code block (D code block) of the first code block (T7 code block) into an S0 code block, and add a "0x78" type field field; this type field field will pass The S code in the original 8B / 10B code stream is deleted for supplement.
  • step 6 also has two possibilities:
  • next code block unit of the first code block is the S code in the original 8B / 10B code stream.
  • the code block must contain at least one code block unit as a control code.
  • next code block unit is a preamble of the data code
  • the code block where the preamble is located is a data code
  • the compression coding of "0x5" is reserved, and the remaining 4 bits of space are used to determine whether to carry the byte "5" to form a type field "0x55" field, thereby being able to determine "0x78"
  • Whether the next code block of the code block unit is a control code can also avoid conflict with the preamble of the code block whose type field is "0x55".
  • next code block unit of the first code block is not an S code in the original 8B / 10B code stream, or a non-S code, and the "0x78" type field can be directly inserted.
  • the S code (0,1,0, KsC" code block unit) in the original 10B code stream is subsequently deleted, and the processing method is shown in FIG. 15.
  • Step 7 Compress and convert the IDLE code blocks in the transcoded 64B / 66B code stream to generate a new 64B / 66B code stream.
  • the above-mentioned transcoding process is fully transparent transcoding, that is, the information carried in the original code block is not changed during the compression and transcoding process.
  • this embodiment can compress the IDLE code in the original 8B / 10B code stream, that is, define a new compression code type, which is represented by "KicC",
  • KicC a new compression code type
  • a compression code used to indicate that the code block unit includes at least two IDLE codes.
  • the length of the code block unit is fixed to 1 Byte (8 bits), and the indication bit cc in the compressed code is used to indicate that the number of original IDLE codes to be replaced is 4 (square of 2).
  • each IDLE code (abbreviated I code) is converted into a 66B code stream to form a code block unit composed of a KiC code and a D code.
  • a total of 4 said code block units are compressed into one 8 Bit KicC code (code block unit), all code block units in subsequent S0 code blocks are filled with the data code D code, and finally a new 66B code stream structure with a code block structure of "T7 + S0 + D" is generated.
  • the new 66B code stream structure is mapped to the frame structure, it is used to start with S0 when synchronizing, so the structure of the new 66B code stream "T7 + S0 + D" is also It can be called “S0 + D + T” code block structure.
  • the transcoding method of the original 8B / 10B code stream can be transparently transcoded into the "T + D" structure of the 100GE standard 64B / 66B code stream.
  • Further extended steps 6 and 7 change the code block structure of the transcoded 64B / 66B code stream.
  • the 8B / 10B GE code stream can be transparently transcoded to 100GE.
  • the standard 64B / 66B "S + D + T" code block structure is suitable for some specific application scenarios.
  • step 6 further supplements the bitstream bandwidth of the transcoding mechanism of this patent, and compresses the IDLE code blocks in the original bitstream, thereby compressing the transcoded bitstream to be smaller than the original bitstream bandwidth, so that It is applicable to the support of 100ppm frequency offset of asynchronous networking system and OAM in bandwidth in some specific scenarios.
  • This embodiment provides a method for transcoding an 8B / 10B code stream into a 64B / 66B code stream under a Fibre Channel (FC) service.
  • the FC service is a typical access service carried by multiple services.
  • the physical layer of the low-rate interface uses 8B / 10B coding.
  • the control code coding in the 8B / 10B coded stream is shown in Table 4 below.
  • the control code and data code are based on 4Byte alignment, but for the control code, the ordered set uses only K28.5 and one K code, and the remaining three code blocks are D codes, that is, "K + D + D + D "structure.
  • control code of "SOFC1” it can be composed of "K28.5-D21.5-D23.0-D23.0” code blocks; “EOFt” can be composed of "K28.5-D21.4-D21. 3-D21.3 "code block, so the meaning of different code blocks can be distinguished by the 3 bytes of data after the K code.
  • Step 1 Obtain an 8B original code stream.
  • the 8B original code stream is in a unit of 4 Bytes, that is, 32 bits.
  • the 8B original code stream includes a data code D and a control code EOF, IDLE, SOF, and the like.
  • Step 2 Decode the 10B original code stream into an 8B code stream, and generate indication information Tx_en.
  • the decoded 8B code stream may be represented by "Tx_8b [7: 0]", and at the same time, 1bit instruction information Tx_en is used to indicate which code blocks in the decoded 8B code stream are control codes and which code blocks Is the data code.
  • Fibre Channel services only use K28.5, and EOF, IDLE, and SOF control codes are all composed of 4 bytes, as shown in Figure 16 and Figure 17, after decoding the EOF code, it is expressed as K + Dt + Dt + Dt, IDLE code is expressed as K + Di + Di + Di. Among them, K, Dt, and Di are 8-bit code blocks.
  • Step 3 Compress the control code in the 8B original code stream to generate a compressed code stream "Tx_n8b [7: 0]".
  • This embodiment is based on the fact that the K code is still compressed according to a maximum of 12 types of K codes into 4 bits and represented by KC, and the remaining 4 bit space 4'bx is reserved for configuring subsequent indication bits.
  • Step 4 Allocate at least one indication bit in the compressed remaining space, so as to replace the indication information to indicate the control code and data code in the original 8B code stream.
  • a principle of configuring indicator bits includes:
  • the 8B code stream indication bit Tx_en is carried in the bandwidth of the 8B code stream.
  • the first indicator bit a is used to indicate whether the next code block unit of the current code block unit is a K code
  • a second indicator bit b used to indicate whether the previous code block unit of the current code block unit is a K code
  • the third indication bit cc is used to indicate the length of the current code block unit, or to indicate the number of D codes in the code block unit where the third indication bit is located.
  • the number cc of the D code blocks may correspond to 0/1/3/7, respectively.
  • the sender and the receiver both know in advance that the structure of the ordered set of control codes is "K + D + D + D" That is, one K code is associated with three D codes, and the third indicator bit cc need not be configured, and the receiving end can also determine that the length of each code block unit is 32 bits.
  • Step 4 Use the remaining 4 bits of the K-code compression to retain the associated indication code block unit type to generate the intermediate state code stream Tx_8b [7: 0].
  • the indicator bit information of each K code is determined according to the pre and post code block units, and at least one indicator bit is set in each K code.
  • the specific process of setting the indicator bit is the same as that of the first embodiment. For details, refer to the description of step 4 in the first embodiment. , Will not repeat them here.
  • Step 5 Generate a 64B code stream with a predetermined structure according to the intermediate state code stream, that is, convert the intermediate state code stream Tx_8b [7: 0] into a 64B / 66B code stream Tx_66b [65: 0], which is a 64B / 66B code stream Tx_66b [65: 0] includes at least two code blocks, such as a first code block and a second code block.
  • eight 8-bit code blocks are transcoded into one 64B code block, and two code blocks of a predetermined structure are generated after transcoding, such as generating a first code block as a T7 code block and a second code block as a D code block.
  • the boundary between the data code and the control code in the 8B original code stream is identified by the second indicator bit in the T7 code block, and the control code to the data code is identified through the association between the first indicator bit and the third indicator bit defined in step 3. Boundary, and finally identify all code stream information.
  • Condition 1 Transcoding of the code block including the EOF code in the original code stream and generating a code block unit, which is a part of the T7 code block, is used to identify the boundary between the D code and the control code in the original code stream.
  • the original control code EOF code is transcoded into a first code block unit, where the The KC code is used to replace the type field in the T7 code block, so it does not participate in the association and set the indicator bit, and the first code block unit is configured in front of the T7 code block by the structure of K + D + D + D Position, 4 8 bits of the original data code D code are set after the first code block unit. Subsequent control codes are associated and set in the manner of step 4 above, and the boundary between the data code and the control code in the original code stream is determined by the indicator bits in the next code block unit of the T7 code block.
  • control code KC in the third code block unit is provided with a second indication bit b of 0, which indicates that the previous code block unit (second code block unit) of the current third code block unit is data.
  • code it is determined that the boundary between the data code and the control code of the 66B code stream after transcoding is the boundary between the second code block unit and the third code block unit.
  • Condition 2 Except for other code blocks that include EOF codes, transcode them into D code blocks.
  • the control codes are all compressed as described above, and the indicator bits are configured to indicate whether the adjacent previous and next code block units are control codes. .
  • control code “a, b, cc, KC” of the first code block unit in the compressed 8B code stream is transcoded to the T7 code block of the 66B code stream, which is determined by the type field in T7.
  • the "0xFF" field is replaced, and 3 D codes are associated with each other to form a 4 Byte code block unit; then the data codes in the original 8B code stream are sequentially extended backward to form a second code block unit.
  • the KC code of the third code block unit is provided with an indication bit of "1,0,2", wherein the first indication bit "1" indicates that the subsequent code block unit is a control code; the second The indication bit "0" indicates that the previous code block unit (ie, the second code block unit) is a data code; the third indication bit "2" indicates that the current control code occupies 4 (22) Bytes, that is, 32 bits.
  • control codes EOF, IDLE, and SOF in the FC service are transcoded and the indicator bit is configured.
  • the transcoding is a structure of T7 code blocks and D code blocks, and the original 8B code stream is converted to 100B standard 64B / 66B code stream T + D structure.
  • This embodiment provides a universal 8B / 10B transparent transcoding method of 64B / 66B.
  • the original 8B / 10B code stream is transcoded into a 10B code stream, thereby reducing the fixed overhead by 20%.
  • the control code in the 8B code stream of the service is compressed to save the remaining space for configuring at least one indicator bit. These indicator bits are used for the correlation between code blocks.
  • the compressed code stream shape is mapped to a predetermined structure.
  • the 64B code stream includes a special T7 code block, and using the T7 code block as a starting point, the remaining indicator bits after the control code compression are used for adjacent recognition, and finally the entire code stream information is accurately identified. And determine the boundary of the control code, thus avoiding 8B / 10B loss and re-recovery.
  • this compression and transcoding method is not only applicable to K codes, but also similar processing on other types of code blocks.
  • the method can also be applied to the transcoding of service streams of various frame structures; full codeword transparency, without loss of information in the original code block stream; transcoding is one-to-one, 1: 1 transcoding efficiency, no bandwidth expansion .
  • the method provided in this embodiment is another typical access service Fibre Channel in addition to the GE service.
  • the 8B / 10B transcoding of the Fbire Channel service is implemented as a standard 100GE. 64B / 66B code stream to meet various business needs.
  • the code block length information in the compressed instruction information can be used as part of the compression coding content at the same time, that is, code blocks of different lengths are separately encoded, thereby improving The number of code blocks that can be supported.
  • the indication bits of the compressed code block are not limited to the first indication bit, the second indication bit, and the third indication bit in the embodiment of the present application, occupying a total of 4 bits, and more can be defined as required. Or fewer bits.
  • the remaining indication bits after the control code compression is not limited to the specific data structure described in this patent. Includes other data structure definitions that can form relationships between adjacent code blocks.
  • each indicator bit after the configuration indicates the mechanism of successively associating adjacent code blocks to determine the boundary between the control code and the data code. among them.
  • the initial identification point after the control code is compressed may be, but is not limited to, the T7 code block and the S code block mentioned in the embodiments of the present application, and may also include other code blocks such as the S code block.
  • the associated indication may be, but is not limited to, the forward indication and the backward indication mentioned in the embodiments of the present application, and may be one of them, or two types of indications may be multiplexed onto 1 bit, and the code block type is S or T. Make a distinction.
  • the predetermined 64B code stream structure after transcoding includes but is not limited to S + D code blocks, D + T code blocks, O + D code blocks, S + D + T code blocks, and other structural forms.
  • the examples in this application are only examples. There are several common code block structures mentioned above. For other code block structures, the embodiments of the present application are not limited.
  • This embodiment provides a method for transcoding a 10GE 64B / 66B code stream into a 100GE standard 64B / 66B code stream.
  • FIG. 18a and FIG. 18b a schematic diagram of a 64G / 66B encoding of 10GBASE-R and a schematic diagram of a 64B / 66B encoding of 100GBASE-R are shown, respectively.
  • 10GBASE-R As a typical access service carried by multi-service, the 64B / 66B code used is not completely consistent with the 100GBASE-R 64B / 66B code, so transparent transcoding is also required before performing the L1.5 layer switching unit.
  • the input data includes: bit position, data block format, and control block format.
  • the data code block format is composed of D0D1D2D3 / D4D5D6D7
  • the control code block format may be composed of C code, O code, D code, S code, and data code D code.
  • the 64B / 66B code blocks of the following eight different code block payload regions can be transcoded.
  • the type fields of the eight different types of control code blocks are:
  • the format of a control code block is "D0D1T2C3 / C4C5C6C7" as an example.
  • the control code type field corresponding to the code block format is "0xaa”.
  • the code block unit includes: a data code D0 and D1, control codes C3 to C7, where each D code is 8 bits and each C code is 7 bits, that is, each C code is 1 bit less than the D code, and there are 5 control codes from C3 to C7, so 5 bits less than the D code, the remaining 5 bit space is reserved, and the code block is finally guaranteed to contain a code block unit with a length of 64 bits.
  • the transcoding process provided by this embodiment is as follows:
  • Step 1 Obtain the original 66B code stream.
  • the original 66B code stream includes a 66B code block whose type field is "0xaa", and the 66B code block includes data codes D0 and D1, and control codes C3 to C7.
  • Step 2 The original 66B code stream is decoded into a 64B code stream, and the control code and data code conditions in the decoded 64B code stream are indicated by a 1-bit signal Tx_en.
  • Step 3 According to the control block format of the decoded 64B code stream, all control code blocks in the 64B code stream except for the code block unit at the T2 position are compressed to generate multiple code block units.
  • Each code block unit includes a 4-bit "KcC” and a 4-bit remaining space.
  • the 4-bit remaining space is used to carry indication bits "a, b, cc", and the indication bits are used for association indication.
  • the indication bit a is used to indicate whether the next code block unit is a control code
  • the indication bit b is used to indicate whether the previous code block unit is a control code
  • the indication bit cc is used to indicate the current code block unit length.
  • the length of each code block unit is 1 Byte (that is, 8 bits).
  • step 3 because the indication bits "a, b, cc" are arranged in the remaining space after compression to indicate the control code of the adjacent code block, and then the boundary between the control code and the data code is determined, the original indication information is eliminated. Tx_en indication, thus saving overhead.
  • the type field in the original 64B / 66B stream is: 0x1e, 0x2d, 0x33, 0x66, 0x55, 0x78, 0x4b.
  • the control codes can be Kt0, Kt1, Kt2, Kt3, Kt4, Kt5, Kt6 said.
  • the type field "0x1e" in the original 66B code stream becomes "Kt0C" after compression.
  • Step 4 Convert the compressed intermediate stream Tx_n64b [63: 0] with the indicator bit into a 100GE standard 64B / 66B stream.
  • the converted 100GE standard 64B / 66B code stream includes a first code block and a second code block.
  • the first code block is a T7 code block
  • the second code block is a D code block.
  • the type field "0xaa” field in the intermediate state code block is replaced by the type field "0xFF" field of the T7 code block to form a standard "T7 code block + D code block” pattern structure.
  • the other code blocks are transcoded into D code blocks.
  • the D code block includes a "1,1,3Kt0C" control code, which is the start code block of the D code block.
  • the first indication bit “1" indicates that the next code block unit (third code block) is a control code;
  • the second indication bit “1” indicates the previous code block unit (the last code block unit of the first code block) Is the control code;
  • the third indicator bit “3” indicates that the size and length of the current code block unit is 8 (the third power of 2) C codes, that is, 56 bits, and each C code is 7 bits.
  • This method transparently transcodes the original 10GBASE-R 64B / 66B code stream into a 100GE standard 64B / 66B code stream through the above mechanism, and the code blocks before and after the transcoding are all code blocks of 8 byte units.
  • the method realizes completely transparent transcoding of code blocks, and the code stream after transcoding does not lose information in the original code block stream.
  • Transcoding is one-to-one, 100% transcoding efficiency, no bandwidth expansion.
  • this application can also use the above method to transcode other original code streams with similar structure to form a 100GE standard 64B / 66B code stream.
  • configuration indicator bits, transcoding, etc. realizes transcoding of other types of code streams, which is not limited in the embodiment of the present application.
  • the type field is 0x99, 0x4b, 0xcc and other types of codes. It is also possible to use the transcoding method of this embodiment to generate a 100GE standard 64B / 66B encoded code stream. This embodiment will not repeat the process of transcoding these code blocks.
  • the device 20 is a schematic structural diagram of a code block generating apparatus according to an embodiment of the present application.
  • the device may be an adaptation unit in any of the foregoing embodiments, such as uAdpt, for implementing the method steps in the foregoing embodiments.
  • the device 200 may include: an obtaining unit 2001, a processing unit 2002, and a sending unit 2003.
  • the device 200 may further include more or fewer components, such as a storage unit, and the like. This is not limited.
  • the processing unit 2002 is configured to generate a first code block and a second code block, wherein the first code block includes a first code block unit, the second code block includes a second code block unit, and the A first indication bit is set in the first code block unit, and the first indication bit is used to indicate whether the second code block unit is a control code; and the sending unit 2003 is used to send the first code block and the first code block.
  • Two code blocks are configured to generate a first code block and a second code block, wherein the first code block includes a first code block unit, the second code block includes a second code block unit, and the A first indication bit is set in the first code block unit, and the first indication bit is used to indicate whether the second code block unit is a control code; and the sending unit 2003 is used to send the first code block and the first code block.
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit;
  • the first code block unit further includes a second indicator bit, and the second indicator bit is used to indicate whether a third code block unit before the first code block unit is a control code.
  • control code includes a K code, or consists of a K code and at least one D code; the first code block unit is the In the case of a control code, a third indication bit is further set in the first code block unit, and the third indication bit is used to indicate the number of D codes in the first code block unit.
  • the second code block further includes a fourth code block unit, and the fourth code block unit is located after the second code block unit.
  • At least one indicator bit is set in the second code block unit, the at least one indicator bit is used to indicate whether the fourth code block unit is a control code, and to indicate whether the first code block unit is a control code; and When the second code block unit is a control code, the at least one indication bit is further used to indicate the number of D codes in the second code block unit.
  • the obtaining unit 2001 is configured to obtain a first code stream, where the first code stream includes a control code; and the processing unit 2002 is specifically configured to perform The control code in the first code stream is compressed, and a first indicator bit is set in the remaining space of the compressed code block to generate the first code block and the second code block.
  • the first code stream may be an 8B code stream (after being converted into a 10B code stream into an 8B code stream), and may also be a 10GE64B / 66B code stream.
  • control code of the first code stream includes at least one 8-bit code block unit
  • processing unit 2002 is specifically configured to perform An 8-bit code block unit in the first code stream is compressed to obtain N-bit remaining space, N ⁇ 8; the first indicator bit is set in the N-bit remaining space, and is filled into an 8-bit K code; generating the first code block and the second code block according to the 8-bit K code.
  • the first indicator bit, the second indicator bit, and the third indicator bit can be configured on the remaining 4 bits.
  • the first indicator bit a occupies 1 bit
  • the second indicator bit b occupies 1 bit
  • the third indicator bit cc occupies 2 bits.
  • the first indication bit a and the second indication bit b are "1", it indicates that the indicated code block unit is a control code; the first indication bit a and the second indication bit b When it is "0", it indicates that the indicated code block unit is a data code.
  • the third indication bit cc may be set in the code block unit or may not be set, but the receiving end and the sending end need to agree in advance, and both ends know the length of the code block unit.
  • the control code and data code for the Fibre Channel service are encoded in units of 4 bytes. Therefore, in this case, each control code K code is associated with 3 D codes, that is, "K + D + D + D "Structure, so only the first indicator bit and the second indicator bit need to be set to indicate whether the next code block and the previous code block are control codes, thereby improving the recognition efficiency and saving 2bit overhead, which can be used to carry other information.
  • the first code block is a T7 code block
  • the second code block is a D code block
  • the first code block is a S0 code block
  • the second code block is a D code block
  • the first code block is an O code block
  • the second code block is a D code block
  • the first code block is an IDLE code block
  • the second code block is a D code block
  • the T7 code block, the S0 code block, the O code block, and the IDLE code block are control codes, and the D code block is a data code.
  • the first code block may also be a D code block
  • the second code block is any one of a T7 code block, an SO code block, an O code block, and an IDLE code block.
  • the first code block is a D code
  • the second code block is any one of a T7 code block, an S0 code block, an O code block, and an IDLE code block.
  • a third code block is also included, the third code block is a D code block, the second code block is an S0 code block, and the first code block is a T7 code block, and then the transcoded 64B
  • the code block structure of the / 66B code stream is "S0 + D + T".
  • the processing unit 2002 is further configured to: when the first code block is a T7 code block and the second code block is a D code block, The D code is transcoded into a S0 code block, and the SO code block includes: a type field, a code block unit including a K code, and at least one code block unit including a D code;
  • a code block unit is a code block unit generated by compressing all code block units composed of one K code and at least one D code of the original D code block, and the K code code block unit includes at least one
  • the indicator bits for example, include 3 indicator bits, which are a, b, and cc.
  • the type field of the S0 code block is "0x78".
  • the D code block can also be transcoded into other types of code blocks, such as O code blocks, IDLE code blocks, and the like.
  • the first code block is a T7 code block
  • the second code block is an S0 code block
  • the processing unit 2002 is further configured to generate A third code block, where the third code block is a D code block.
  • the processing unit 2002 can also generate more code blocks, such as the fourth code block and the fifth code block, according to the characteristics of the original code stream.
  • the specific generation process is the same as the previous embodiment of the method. This embodiment I will not repeat them here.
  • a code block receiving device is also provided.
  • the device 210 includes: an obtaining unit 2101, a processing unit 2102, and a sending unit 2103.
  • the device 210 also It may include more or fewer components, such as a storage unit, etc., which is not limited in this application.
  • An obtaining unit 2101 is configured to receive a first code block and a second code block, where the first code block includes a first code block unit, the second code block includes a second code block unit, and the first code block A first indication bit is set in the unit.
  • the processing unit 2102 is configured to determine whether the second code block unit is a control code according to an instruction of the first indicator bit.
  • the first code block further includes a third code block unit, and the third code block unit is located before the first code block unit.
  • the first code block unit is further provided with a second indication bit, and the processing unit 2102 is further configured to determine whether a third code block unit before the first code block unit is a control according to an instruction of the second indication bit. code.
  • control code includes a K code, or consists of a K code and at least one D code; the processing unit 2102 is further configured to determine When the first code block unit is the control code, the number of D codes in the first code block unit is determined according to a third indicator bit in the first code block unit.
  • the second code block further includes a fourth code block unit, and the fourth code block unit is located after the second code block unit, The second code block unit is provided with at least one indicator bit, and the processing unit 2102 is further configured to determine whether the fourth code block unit is a control code according to at least one indicator bit in the second code block unit, And whether the first unit code block is a control code.
  • the processing unit 2102 is specifically configured to: if the first instruction information indicates that the second code block unit is not a control code, The two-code block unit starts as a data code.
  • the code block receiving device may be the code block generating device in the foregoing embodiment, or an adaptation unit in the foregoing embodiment, such as uAdpt or nAdpt, for implementing the foregoing embodiment.
  • the corresponding code block receiving method, and the boundary between the control code and the data code in the original code stream is identified by this method.
  • At least one indicator bit is configured in the code block unit to indicate whether the code block unit before and after the current code block unit is a control code, and the D code length of the control code, and then the upper limit of each code block unit is passed.
  • the stepwise indication of the indicator bit determines the boundary between the control code and the data code, avoiding the overhead of additional information.
  • a packet bearer device 220 is also provided.
  • the device may be an IP mobile bearer network (Radio Access Network, RAN) or a packet transport network (Packet) that is planned to load XE characteristics.
  • RAN Radio Access Network
  • Packet packet transport network
  • a transport network (PTN) device is used to implement various functions of the PE or P in the foregoing embodiments.
  • the packet bearer device 220 includes: an interface board 2201, an interface board 2203, and a main control switching board 2202.
  • the interface board 2201 is connected to the input terminal of the main control switch board 2202, and the interface board 2203 is connected to the output terminal of the main control switch board 2202.
  • the interface board 2201 includes a user-side interface chip for implementing various functions of the uAdpt of the PE;
  • the main control switching board 2202 includes a network processor (Network Processor) or a switching network chip for implementing the PE The function of the switching unit;
  • the interface board 2203 includes a network-side interface chip for implementing various functions of the nAdpt of the PE.
  • the user-side processing chip of the interface board 2201 may further include a transceiver 2301, a processor 2302, and a memory 2303, as shown in FIG.
  • the user-side processing chip may also include more or fewer components, or some components may be combined, or different component arrangements, which are not limited in this application.
  • the processor 2302 is a control center of the user-side processing chip, and executes various functions of the user-side processing chip by running or executing software programs and / or unit modules stored in the memory 2303 and calling data stored in the memory.
  • the processor 2302 may be composed of an integrated circuit (IC), for example, may be composed of a single packaged IC, or may be composed of multiple packaged ICs connected to the same function or different functions.
  • the processor may include only a CPU, or a combination of a GPU, a digital signal processor (DSP), and a control chip in a transceiver module.
  • DSP digital signal processor
  • the transceiver 2301 may include components such as a receiver, a transmitter, and an antenna, for receiving the original code stream and sending the transcoded code stream, where the transcoded code stream includes a first code block, a second code block, and the like .
  • the transceiver 2301 is also used to implement communication transmission between a user side and a network device.
  • the transceiver 2301 may include a communication module such as a wireless local area network module, a Bluetooth module, and a baseband module, and a radio frequency (RF) circuit corresponding to the communication module, for performing wireless local area network communication, Bluetooth communication, infrared communication and / or cellular communication system communication.
  • a communication module such as a wireless local area network module, a Bluetooth module, and a baseband module
  • RF radio frequency
  • the transceiver 2301 can also support direct memory access.
  • various transceiver modules in the transceiver 2301 generally appear in the form of integrated circuit chips, and can be selectively combined without necessarily including all transceiver modules and corresponding Antenna group.
  • the transceiver may include only a baseband chip, a radio frequency chip, and a corresponding antenna to provide communication functions in a cellular communication system.
  • a wireless communication connection established via the transceiver module such as wireless local area network access or WCDMA access.
  • the memory 2303 is configured to store application program code that executes the technical solution of the present application, and is controlled and executed by the processor 2302.
  • the processor 2302 is configured to execute application program code stored in the memory to implement the code block generating method and the code block receiving method in the foregoing embodiments.
  • the memory 2303 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or can store information and instructions
  • ROM read-only memory
  • RAM random access memory
  • Other types of dynamic storage devices can also be electrically erasable programmable read-only memory (Electrically Programmable Read-Only Memory (EEPROM)), Compact Disc (Read-Only Memory, CD-ROM) or other optical disk storage , Optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store the desired program code in the form of instructions or data structures and Any other medium that can be accessed by a computer, but is not limited to this.
  • the memory can exist independently or integrated with the processor.
  • the functions to be implemented by the obtaining unit 2001 and the sending unit 2003 may be implemented by the transceiver 2301 of the user-side processing chip, or by the processor 2302.
  • the control transceiver 2301 is implemented; the functions to be implemented by the processing unit 2002 may be implemented by the processor 2302.
  • the functions to be implemented by the receiving unit 2101 and the sending unit 2103 may be implemented by the transceiver 2301 of the user-side processing chip, or by the processor 2302.
  • the control transceiver 2301 is implemented; the functions to be implemented by the processing unit 2102 may be implemented by the processor 2302.
  • the user-side processing chip 230 shown in FIG. 23 in the present application may be provided or integrated in a user-side adaptation unit (uAdpt) shown in FIG. 1a to implement all functions of uAdpt.
  • uAdpt user-side adaptation unit
  • the memory 2303 is configured to store a computer program product, where the computer program product includes one or more computer instructions, such as a synchronous carrier frequency signal sending instruction.
  • the computer program When the computer program is loaded and executed by a computer, the processes or functions according to the embodiments of the foregoing embodiments of the present application are generated in whole or in part.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be from a network site, computer, server, or data center. Transmission to another site, computer, or server by wire or wireless.
  • the computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory ROM or a random access memory RAM.
  • the system may be an Ethernet network, a FlexE network, or an X-E network.
  • the network system includes a user equipment UE and a network device PE or P, and the PE is configured to execute the code block generating method and the receiving method in the foregoing embodiments.
  • PE1 transcodes the original code stream into a 100GE standard 64B / 66B coded stream, and sends the transcoded standard code stream to P.
  • P transmits the received standard code stream to PE2.
  • PE2 After receiving the standard 64B / 66B coded stream, PE2 transcodes it into the original 8B / 10B coded stream, and outputs the value to the user equipment.
  • This embodiment provides a device and a system. Since a first code block and a second code block are included in a transmitted code stream, and at least one indicator bit is configured on a code block unit in the first code block, it can indicate The control code and data code conditions of adjacent code blocks, so that the boundary between the control code and the data code can be determined by the content of the code block after transcoding, which saves the overhead of the instruction information.
  • the technology in the embodiment of the present invention can be implemented by means of software plus a necessary universal hardware platform. Based on such an understanding, the technical solutions in the embodiments of the present invention can be embodied in the form of software products that are essentially or contribute to the existing technology.
  • the computer software product can be stored in a storage medium, such as ROM / RAM. , Magnetic disks, optical disks, etc., including a number of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention or certain parts of the embodiments.

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Abstract

公开了一种码块生成方法、接收方法和装置，所述码块生成方法包括：生成第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码；发送所述第一码块和所述第二码块。本方法通过在第一码块中的码块单元上配置指示位来指示相邻码块是否为控制码，进而确定出控制码和数据码的边界，避免额外的指示信息指示，从而节约了指示信息的开销。

Description

一种码块生成方法、接收方法和装置
本申请要求于2018年9月7日提交中国专利局、申请号为201811042289.8、发明名称为“一种码块生成方法、接收方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种码块生成方法、接收方法和装置。
背景技术
第五代通讯技术(5-Generation，5G)在业界已经开始广泛研究，标准组织3GPP定义了5G的三大场景：增强移动宽带(Enhance Mobile Broadband，eMBB)、大规模物联网(massive Machine Type of Communication，mMTC)和超高可靠低时延业务(Ultra-Reliability and Low-Latency Service，URLLC)；分别聚焦3D/超高清视频等大流量移动宽带业务、大规模物联网业务、低时延和高可靠连接的业务(如无人驾驶、工业自动化)等。其中，一项重要的课题就是降低时延，并保证业务传输的可靠性和安全性。
目前，公开一种基于灵活以太网(Ethernet)物理层的比特码块(bit block)交换技术，简称X-E(X-Ethernet)技术，比如64B/66B类型码块，具备确定性超低时延的特性。该技术体系抽象为图1a和图1b所示的设备装置，其中，图1a表示一种网络边缘与用户连接的网络设备，例如运营商边缘路由器(Provider Edge，PE)，该设备上配备有NNI侧和UNI侧的网络接口。图1b表示一种网络内的网络设备(Provider，P)，该设备上仅配备NNI侧的网络接口。
参见图2，示出了一种采用X-E技术组建网络并转发数据流的示意图。其中，贯穿整个PE和P设备的实线路径为X-E端到端转发的路径。在该转发的路径中，利用L1.5层交换的码流被明确定义为64B/66B编码，码流类型如图3所示。其中，64B/66B编码将64bit数据或控制信息编码成66bit块传输，66bit块的前两位表示同步头，主要由于接收端的数据对齐和接收数据位流的同步。具体地，同步头包括“01”和“10”两种，“01”表示后面的64bit都是数据，“10”表示后面的64bit是数据和控制信息的混合，其中，紧挨着同步头的8bit是类型域，后面的56bit是控制信息或者数据或者两者的混合。
中国移动要求基于Flex E的新型接口和交换技术，简单来说就是L1.5层交换技术，其中，在L1.5层交换技术体系中的一个重要的课题是承载多业务。比如图4示出了一种典型的承载多业务类型及速率情况，由图4中可以看出，除了同步数字体系(Synchronous Digital Hierarchy，SDH)业务和光转换器单元(Optical Transponder Unit，OTUk)业务采用帧结构的数据流之外，其余业务的码流类型除64B/66B以外都是8B/10B的码流类型，因此，在多业务接入前，需要将这些8B/10B码流统一转换为标准的64B/66B编码码流，并根据转换后的64B/66B编码来确定控制信息和数据的边界。
目前，在识别转换后的64B/66B编码码流的控制信息和数据的边界时，需要通过额外的指示信息来指示，这额外的指示信息会占用一定比特资源、增加开销。
发明内容
本申请提供了一种码块生成方法，该方法可以省去额外指示信息的开销。具体地，公开了如下技术方案：
第一方面，本申请提供了一种码块生成方法，所述方法包括：适配单元生成第一码块和第二码块，其中，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码；发送所述第一码块和所述第二码块。
可选的，所述第二码块位于第一码块之后，或者位于第一码块之前；如果所述第二码块位于第一码块之后，则所述第一指示位用于指示当前第一码块的后一个码块，第二码块是否是控制码；如果所述第二码块位于第一码块之前，则所述第一指示位用于指示当前第一码块的前一个码块是否是控制码。
可选的，所述第一码块和和第二码块是相邻的两个码块，每个码块为64B/66B码块。
可选的，所述第一指示位用a表示，占用1比特空间。
本方面提供的方法，通过在第一码块中的码块单元上配置指示位来指示相邻码块是否为控制码，从而能够确定出控制码和数据码的边界，避免了通过额外的指示信息来指示，从而节约了指示信息的开销。
进一步地，如果所述第一指示位指示第二码块单元为控制码，则可以根据第二码块单元中设置的指示位来确定下一个码块是否为控制码；如果所述第一指示位指示第二码块单元不是控制码，即为数据码，则确定从第二码块单元开始为数据码，所述第二码块单元之前均为控制码，进而确定出控制码与数据码的边界。
结合第一方面，在第一方面的一种可能的实现中，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，所述第二指示位用于指示所述第一码块单元之前的第三码块单元是否为控制码。
进一步地，如果第二指示位指示所述第三码块单元为控制码，则进一步根据第三码块单元中的指示位来确定前一个码块是否是控制码；如果第二指示位指示所述第三码块单元不是控制码，为数据码，则所述第三码块单元与所述第一码块单元之间的界限为数据码和控制码的边界。
可选的，所述第二指示位用b表示，占用1比特空间。
结合第一方面，在第一方面的另一种可能的实现中，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；在所述第一码块单元为所述控制码的情况下，所述第一码块单元中还设置有第三指示位，所述第三指示位用于指示所述第一码块单元中的D码的个数。
可选的，所述D码为数据码，用于表示K码的类型，例如Di码，表示K码是IDLE控制码；Dt码，表示K码是T控制码。进一步地，所述K码的类型由原始码流决定，所述原始码块可以是6B/10B码块，或者10GBASE-R的64B/66B码流，本申请实施例对此不予限制。
可选的，所述D码的个数可通过码块单元的长度表示，例如在Fibre Channel业务下，控制码均以4byte为单元，即32比特，结构为K+D+D+D，则D码的个数为3，每个D码为8比特的码块单元。
可选的，所述第一码块单元中的D码的个数用cc表示，占用2比特空间。
结合第一方面，在第一方面的又一种可能的实现中，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，所述至少一个指示位用于指示所述第四码块单元是否为控制码、指示所述第一码块单元是否为控制码；以及，在所述第二码块单元为控制码的情况下，所述至少一个指示位还用于指示所述第二码块单元中的D码的个数。
进一步地，所述至少一个指示位包括第一指示位，用于指示当前码块单元的下一个码块单元是否为控制码；包括第二指示位，用于指示当前码块单元的前一个码块单元是否为控制码；还包括第三指示位，用于指示组成控制码的码块单元中D码的个数。
本实现方式中，通过在码块单元中配置至少一个指示位，来指示当前码块单元的前后码块单元是否为控制码，以及控制码的D码长度，进而通过每个码块单元的上指示位的逐级指示确定出控制码和数据码的边界，避免了额外信息的开销。
结合第一方面，在第一方面的又一种可能的实现中，所述生成第一码块和第二码块，包括：获取第一码流，所述第一码流中包括控制码；对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块。
可选的，所述第一码流可以是8B码流，所述8B码流是从8B/10B码流中的10B码流转换而来的；或者，所述第一码流还可以是10GE业务的64B/66B码流。
结合第一方面，在第一方面的又一种可能的实现中，所述第一码流的控制码中包括至少一个8比特的码块单元，对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块，包括：对所述第一码流中的一个8比特的码块单元进行压缩，得到N比特剩余空间，N≤8；在所述N比特的剩余空间内设置所述第一指示位，并填充成一个8比特的K码；根据所述8比特的K码生成所述第一码块，以及所述第二码块。
可选的，在一种可能的实现方式中，将原始的8B码流中的控制码压缩为多个码块单元，每个码块单元由原来的8比特压缩为4比特，并剩余4比特空间用于配置第一指示位、第二指示位和第三指示位。
其中，所述第一指示位和第二指示位各占用1比特，第三指示位占用2比特，形成一个K码，所述K码为8比特的码块单元；此外，压缩前的控制码还可以包括若干个D码，例如在一种业务下，控制码由一个K码和3个D码组成，每个D码为8比特，且该一个K码与3个D码组成的控制码为一个码块单元。
本实现中，先将10B码流译码为8B码流得到第一码流，可以节约20％固定开销，然后对第一码流的控制码进行压缩，压缩后在剩余空间配置指示位，该指示位以用于指示相邻码块之间的控制码和数据码情况，进而节约了指示信息的开销，提高了转码效率。
此外，在本实现中，码块装载的利用率相对于D码块透明承载提高了25％，且8B/10B码流的控制码和数据码的边界不需要重新恢复，通过控制码压缩后剩余码块开销指示，逐级关联相邻码块的方式，进而识别出整个码流特征及含义。
结合第一方面，在第一方面的又一种可能的实现中，
所述第一码块为T7码块，所述第二码块为D码块；
或者，所述第一码块为S0码块，所述第二码块为D码块；
或者，所述第一码块为O码块，所述第二码块为D码块；
或者，所述第一码块为IDLE码块，所述第二码块为D码块；
其中，所述T7码块、S0码块、O码块和IDLE码块为控制码，所述D码块为数据码。
可选的，所述第一码块也可以为D码块，所述第二码块为控制码，例如T7码块、S0码块等，本申请对此不予限制。
可选的，还可以包括第三码块、第四码块等更多的码块，且这些码块组成的码流包括但不限于：S0码块+D码块、D码块+T码块、O码块+D码块、S0码块+D码块+T码块等各种形态。
可选的，所述第一码块为T7码块，所述第二码块为S0码块，上述方法还包括：生成第三码块，所述第三码块为D码块。
可选的，在所述第一码块为T7码块，所述第二码块为D码块的情况下，所述方法还包括：将所述D码转码为S0码块，所述SO码块中包括：一个类型域，一个K码的码块单元和至少一个包括D码的码块单元。
其中，所述包括K码的码块单元是，原所述D码块的由一个K码和至少一个D码组成的所有码块单元进行压缩后生成的一个码块单元，且所述K码的码块单元中包括至少一个指示位。S0码块的类型域为“0x78”字段或者码块单元。
例如，对原始码流中的IDLE码块进行了压缩生成一个码块单元，该码块单元是由原始码流中的4个控制码的码块单元压缩而成，所述压缩后生成的码块单元位于所述类型域“0x78”字段之后，且包括第一指示位、第二指示位和第三指示位，进一步地，所述第一指示位用于指示当前码块单元的后一个码块单元为数据码；第二指示位用于指示当前码块单元的前一个码块单元是控制码；第三指示位用于指示当前码块单元是通过4个原始码流的IDLE码压缩而成。
本实现方式中，通过进一步地对原码流中的IDLE码块进行了压缩，从而将转码后的码流压缩到小于原始码流带宽，以便适用于某些具体场景对异步组网系统100ppm频偏以及带宽内OAM等开销特性的支持。
第二方面，本申请还提供了一种码块接收方法，该方法用于接收第一码块和第二码块，并识别码流中数据码和控制码的边界，具体地，所述方法包括：适配单元接收第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位；根据所述第一指示位的指示确定所述第二码块单元是否为控制码。
可选的，根据所述第一指示位的指示确定所述第二码块单元是否为控制码，包括：如果第一指示位指示第二码块单元为控制码，可以根据第二码块单元中设置的指示位来确定下一个码块是否为控制码；如果所述第一指示位指示第二码块单元不是控制码，即为数据码，则确定从第二码块单元开始为数据码，所述第二码块单元之前均为控制码，进而确定出控制码与数据码的边界。
结合第二方面，在第二方面的一种可能的实现中，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，所述方法还包括：根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码。
可选的，根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码，包括：如果第二指示位指示所述第三码块单元为控制码，则进一步根据第三码块单元中的指示位来确定前一个码块是否是控制码；如果第二指示位指示所述第三码块单元不是控制码，为数据码，则所述第三码块单元与所述第一码块单元之间的界限为数据码和控制码的边界。
结合第二方面，在第二方面的另一种可能的实现中，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；所述方法还包括：在确定所述第一码块单元为所述控制码的情况下，根据所述第一码块单元中的第三指示位确定所述第一码块单元中的D码的个数。
可选的，如果发送端和接收端已经预先约定码块单元的长度，或者在特定业务条件下，例如Fibre Channel业务下，则不需要第三指示位来指示，就可以确定出D码的个数或长度。
结合第二方面，在第二方面的又一种可能的实现中，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，所述方法还包括：根据所述第二码块单元中的至少一个指示位确定所述第四码块单元是否为控制码、以及所述第一单元码块是否为控制码。
结合第二方面，在第二方面的又一种可能的实现中，所述根据所述第一指示位的指示确定所述第二码块单元是否为控制码，包括：如果所述第一指示信息指示所述第二码块单元不是控制码，则从所述第二码块单元开始为数据码。
另外，可选的，如果第一指示信息指示的码块单元是控制码，则进一步判断所述第二码块单元中的指示位是否指示下一个码块单元为控制码，以此类推，直到指示不是控制码为止，进而能够确定出控制码和数据码的边界。
可选的，上述第一指示位、第二指示位和第三指示位可以通过压缩后的剩余空间承载，例如，原始8B码流中控制码的一个8比特码块单元压缩成4比特，剩余4比特空间用于设置三个指示位，共占用4比特，最后生成一个8比特的K码；此外，填充的D码也都可以是8比特的码块单元，且每个D码用于指示对应K码的类型，所述D码的个数可以是0或者是1，3，7。
第三方面，本申请还提供了一种码块生成装置，所述装置可以是一种适配单元，例如uAdpt单元，其中，所述装置中包括用于执行上述第一方面以及第一方面的各种实现方式中方法步骤的单元。
具体地，所述装置包括获取单元、处理单元和发送单元，此外，还可以还包括存储单元等其他单元或模块。
第四方面，本申请还提供了一种码块接收装置，所述装置可以是一种适配单元，例如uAdpt单元，其中，所述装置中包括用于执行上述第二方面以及第二方面的各种实现方式中方法步骤的单元。
具体地，所述装置包括获取单元、处理单元和发送单元，此外，还可以还包括存储单元等其他单元或模块。
需要说明的是，本申请第三方面所述的码块生成装置和第四方面所述的码块接收装置可以是同一个装置，例如uAdpt单元；也可以是不同的装置。
第五方面，本申请还提供了一种网络设备，所述网元设备可以是PE或者P，还可以是分组承载设备，进一步地，所述网络设备包括接口板主控交换板，其中，所述接口板中包括用户侧处理芯片，该用户侧处理芯片用于实现上述第一方面或第二方面以及各种实现所述的码块生成、码块接收方法。
可选的，所述用户侧处理芯片可以设置或集成在用户侧时频单元uAdpt中。
可选的，所述用户侧处理芯片中还包括存储器或存储单元，用于存储一个或多个计算机指令。
第六方面，本申请还提供了一种计算机存储介质，该计算机存储介质可存储有程序，该程序执行时可实现上述各个方面中，包括本申请提供的码块生成、码块接收方法各实施例中的部分或全部步骤。
第七方面，本申请还提供了一种计算机程序产品，所述计算机程序产品包括一个或多个计算机指令，例如码块生成指令、码块发送指令、码块接收指令。在计算机加载和执行所述计算机程序时，可实现包括本申请提供的码块生成、码块接收方法各实施例中的部分或全部步骤。
本申请提供了一种码块生成方法和装置，通过生成具有特定码块结构的码流，该码流中包括第一码块和第二码块，且每个码块中都配置有至少一个指示位，来指示相邻码块单元是否为控制码，从而确定出原始码流中控制码与数据码的边界，节约了额外指示信息的开销。
附图说明
图1a为本申请提供的一种网络边缘与用户连接的网络设备PE的结构示意图；
图1b为本申请提供的一种网络内的网络设备P的结构示意图；
图2为本申请提供的一种采用X-E技术组建网络并转发数据流的示意图；
图3为本申请提供的IEEE802.3规范的64B/66B Block类型编码的示意图；
图4为本申请提供的一种典型的多业务类型及码流类型的示意图；
图5为本申请实施例提供的一种适配单元的结构示意图；
图6为本申请实施例提供的另一种适配单元的结构示意图；
图7为本申请实施例提供的一种8B/10B对应关系的示意图；
图8为本申请实施例提供的一种8B/10B典型码流的结构示意图；
图9a为本申请实施例提供的一种T7码块的结构示意图；
图9b为本申请实施例提供的一种S0码块的结构示意图；
图9c为本申请实施例提供的一种D码块的结构示意图；
图9d为本申请实施例提供的一种O码块的结构示意图；
图9e为本申请实施例提供的一种IDLE码块的结构示意图；
图10为本申请实施例提供的一种码块生成方法的流程图；
图11a为本申请实施例提供的一种码块结构的示意图；
图11b为本申请实施例提供的另一种码块结构的示意图；
图11c为本申请实施例提供的又一种码块结构的示意图；
图11d为本申请实施例提供的又一种码块结构的示意图；
图11e为本申请实施例提供的又一种码块结构的示意图；
图11f为本申请实施例提供的又一种码块结构的示意图；
图11g为本申请实施例提供的又一种码块结构的示意图；
图11h为本申请实施例提供的又一种码块结构的示意图；
图11i为本申请实施例提供的又一种码块结构的示意图；
图11j为本申请实施例提供的又一种码块结构的示意图；
图12为本申请实施例提供的一种10B码流转码为64B/66B码流的处理流程示意图；
图13为本申请实施例提供的一种10B码流转码为8B码流的处理流程示意图；
图14为本申请实施例提供的一种GE业务8B/10B转码为64B/66B码流的处理流程示意图；
图15为本申请实施例提供的一种64B/66B码流的码块结构转换的处理流程示意图；
图16为本申请实施例提供的一种Fibre Channel业务8B码流转码为64B/66B码流的处理流程示意图；
图17为本申请实施例提供的一种Fibre Channel业务8B码流转码为64B/66B码流的局部处理流程示意图；
图18a为本申请实施例提供的一种10GBASE-R 64B/66B编码的示意图；
图18b为本申请实施例提供的一种100GBASE-R 64B/66B编码的示意图；
图18c为本申请实施例提供的一种10GE业务的64bit码块单元的结构示意图；
图19为本申请实施例提供的一种10GBASE-R 64B/66B码流转码为100GBASE-R 64B/66B的处理流程示意图；
图20为本申请实施例提供的一种码块生成装置的结构示意图；
图21为本申请实施例提供的一种码块接收装置的结构示意图；
图22为本申请实施例提供的一种分组承载设备的结构示意图；
图23为本申请实施例提供的用户侧处理芯片的结构示意图。
具体实施方式
在对本申请实施例的技术方案说明之前，首先对本申请涉及的名词进行介绍。
以太网(Ethernet)是一种基带局域网规范，是当今现有局域网采用的最通用的通信协议标准。
灵活以太网(Flexible Ethernet，FlexE)是实现业务隔离承载和网络分片的一种接口技术，近两年发展迅速，被各大标准组织广泛接纳。
泛在以太网(X-Ethernet，X-E)是一种基于Ethernet物理层的比特码块(Bit Block)交换的技术体系，具备确定性超低时延的特征，X-E所采用的编码类型可以为64B/66B编码类型等。
M/N Bit Block编码
M/N Bit Block编码是指M个净荷Bit、N个总Bit的编码类型，其中，N个总Bit包括M个净荷Bit和若干个同步Bit，即M/N Bit Block中的M≤N。在Ethernet物理层链路传递的就是M/N Bit Block流，比如1G Ethernet采用8B/10B编码，1GE物理层链路传递的就是8B/10B码块流；10GE/40GE/100GE Ethernet采用64B/66B编码，10GE/40GE/100GE Ethernet物理层链路传递的就是64B/66B码块流。未来随着Ethernet技术的发展，也会出现其他编码类型，比如可能出现128B/130B、256B/257B编码等可能的编码方案。
非M/N Bit Block编码
非M/N Bit Block编码是指采用的编码技术不是M/N Bit Block编码，而是采用业务帧(Frame)等其他编码方法，比如同步数字体系(Synchronous Digital Hierarchy，SDH)或光传送网(Optical Transport Network，OTN)等。
下面，对本申请的技术方案的应用场景和系统架构进行详细介绍。
本申请各实施例提供的技术方案基于FlexE的端到端组网技术，下文简称为X-E。
例如，以本申请提供的业务传输方法应用于基于X-E技术传输业务信号的场景为例，包括至少两个网络设备，比如第一网络设备和该第二网络设备。其中，所述第一网络设备和第二网络设备可以为X-E组网中的PE或P。
其中，PE为网络边缘与用户设备连接的网络设备，如图1a所示，X-E组网中的PE可以包括用户侧适配单元(uAdpt)、交换单元(Switch)和网络侧适配单元(nAdpt)。
其中，uAdpt包括部署在网络入口的uAdpt，简称uAdpt(i)，以及部署于网络出口的uAdpt，简称uAdpt(e)。uAdpt(i)用于实施低速业务信号或低速管道的适配和交织工作，以将业务信号接入到FlexE高速管道，uAdpt(e)用于完成从FlexE高速管道恢复出低速业务信号或低速管道的解交织和适配等功能。
nAdpt主要用于完成FlexE管道复用到FlexE SHIM经过FlexE接口传送，或者从FlexE接口的FlexE SHIM恢复出FlexE管道。本申请各个实施例中，可以通过PE中的uAdpt或nAdpt实现将接收到的N路业务信号复用传输，或者实现从复用形成的一路业务信号中恢复出原来的N路业务信号。实际应用中，可以通过在uAdpt或nAdpt中部署控制单元实现本申请的方法，该控制单元可以为软件、可编程器件或集成电路等，例如，该集成电路可以为专用集成电路(Application Specific Integrated Circuit，ASIC)等。
图1b是本申请提供的一种X-E组网中的P的结构示意图，如图1b所示，X-E组网中的P可以包括两侧的nAdpt和中间的Switch。本申请中，可以通过P中的nAdpt实现将接收到的N路业务信号复用传输，或者实现从复用形成的一路业务信号中恢复出原来的N路业务信号。实际应用中，可以通过在nAdpt中部署控制单元实现本申请的方法，该控制单元可以为软件、可编程器件或集成电路等，例如，该集成电路可以为ASIC等。
其中，图1a所示的PE设备中，一个用户侧接口(User network interface，UNI)用于连接网络设备和用户设备；PE设备的一个接口(Network to Network interface，NNI)用于连接网络之间或网络内的设备。图1b所示的P设备中，两个接口NN1均用于连接网络内的各个设备。
如图2或图5所示，原始8B/10B码流经过PE1设备的uAdpt后，将原始8B/10B码流转码为64B/66B码流，然后该64B/66B码流再经过L1.5层交换单元和nAdpt输入至P设备，经过P设备后再输入至PE2设备，最后通过PE2设备的nAdpt将64B/66B码流转换为8B/10B码流，对外输出至用户设备。
其中，参见图5，为本实施例提供的一种用户侧适配单元的结构示意图，该用户侧适配单元可以是uAdpt，进一步地，该uAdpt包括物理层(Physical，PHY)和编码(encoding，ENC)单元，其中，ENC单元用于将输入的8B/10B码流转换为64B/66B编码码流，并传输给X-E交换单元。
参见图6，为本实施例提供的一种网络侧适配单元的结构示意图，该网络侧适配单元 可以是nAdpt，进一步地，该nAdpt包括物理层(Physical，PHY)和解码(decoding，DEC)单元，其中，DEC单元用于将网络内设备输入的64B/66B码流转换为8B/10B编码码流，并对外输出。
本申请为解决将8B/10编码的码流转换为100GE标准的64B/66B码流时，需要配置额外的指示信息来指示控制码和数据码，导致额外开销的技术问题。
在介绍本申请的技术方案之前，首先，对8B/10编码的码流特点做简单的介绍。
8B/10B，也叫做8字节/10字节或8B10B。8B/10B编码是目前高速串行通信中经常用到的一种编码方式，其目的是通过将一个字节宽度的数据经过映射机制转化为10位宽度的字符，来平和位流中0与1的个数，也就是达到平衡直流的作用。由于直接将8bit数据编码成10bit来传输在实现上将占用芯片的大片物理面积，并且严重影响数据的传输效率，所以目前大都采用将一串8位二进制数分为低5位和高3位，然后对低5位进行5B/6B编码，对高3位进行3B/4B编码，最后再将6为和4位合在一起编码，这样不仅减少芯片占用面积，而且还简化了编码，提高了数据的传输效率。
如图7所示，一般地，用字符HGFEDCBA来表示编码前的8位二进制数，则低5位就是EDCBA，高3位就是HGF。5B/6B编码后6位二进制的表示方式为abcdei，而3B/4B编码后4位二进制数的表示方式为fghj，最后合成的十位二进制数为abcdeifghj。通常，人们习惯将8bit数据表示成“Dx.y”的形式，而控制码用“Kx.y”的形式，其中，D表示为数据代码，K表示为特殊的命令代码，x表示输入的原始数据的低5位EDCBA，y表示输入的原始数据的高3位HGF。进一步地，x＝5LSB(least significant bit为最低有效位)，y＝3MSB(most significant bit为最高有效位)。
其中，8B/10B编码是目前许多高速串行总线采用的编码机制，如USB3.0、1394b、Serial ATA、PCI Express、Infini-band、Fiber Channel、RapidIO等总线或网络等。
在本申请的各个实施例中，根据以太网(Ethernet，ETH)和光纤通道(Fibre Channel,FC)业务等典型的8B/10B编码业务在译码后得到的8B码流特性包括：
如图8所示，8B业务码流可以看成是一串连续控制码和连续数据码的交织发送。其中，业务中承载的净荷区(payload)为D码流，即数据码流，其他包括IDLE(简称为“I”)在内的为C码流，即控制码流。
另外，如图8所示，一种帧(frame)的结构可以由S码、D码、T码和R码组成，其中D码为数据码，其它码块(block)为控制码。
目前的一种控制码编码类型和编码方式如表1所示。
Figure PCTCN2019104531-appb-000001
Figure PCTCN2019104531-appb-000002
表1
表1所示的控制码流中，吉比特以太网(Gigabit Ethernet，GE)协议中定义的控制码类型只有/C/、/I/、/R/、/S/、/T/、/V/、/LI/这7种类型。进一步地，根据有序集(Ordered Set)的内容，配置码(Configuration，C)包括配置码C1和配置码C2，其中，配置码C1对应的编码(Encoding)为K28.5和D21.5；配置码C2对应的编码为K28.5和D2.2。空闲码(IDLE，I)可包括空闲码I1和空闲码I2，分别可以编码为K28.5/D5.6，和，K28.5/D16.2。其余控制码的有序集可参见表1所示的编码规则，本实施例不逐一举例。
由于Ethernet和Fibre Channel业务8B/10B码流的控制码类型有限，典型结构为K码+D码*n(n<4)，n表示D码的数量。目前，8B/10B编码规范中定义的控制码“K码”类型总共有12种，分别为：K28.0、K28.1、K28.2、K28.3、K28.4、K28.5、K28.6、K28.7、K23.7、K27.7、K29.7和K30.7，如表2所示，进而可以通过对上述有限个K码进行重新编码，比如压缩处理，得到剩余部分空间用于指示码流类型或者指示控制码与数据码的边界。
Figure PCTCN2019104531-appb-000003
Figure PCTCN2019104531-appb-000004
表2
下面对本申请提供的技术方案进行详细地说明。本申请实施例提供了一种转码方法，可以将原始的8B/10B码流转换为预定结构的64B/66B码流，不仅能够节约指示原始码流中控制码与数据码边界的指示信息，还能包括码块的透明性，所述码块的透明性可以理解为，转码前后的码块中所承载的内容信息不变，且能够被收发两端识别。
具体地，本申请各个实施例提供的技术方案，首先将8B/10B码流中的10B编码转换为8B编码，以便消除了10B编码方式带来的20％固定开销，然后再将上述转码后的8B码流填充到64B/66B码流中的64B码块中，从而达到高效转码，节约开销。
另外，为了达到换码后的信息能够被识别，即达到码块透明的效果，还建立了一种将8个连续8比特码块单元映射到1个64比特码块单元的对应关系，并通过在每个码块单元上配置指示位，来指示相邻码块的控制码或数据码情况，从而实现了不增加额外开销的情况下，确定原始码流中数据码和控制码的边界。
其中，根据图3所示的64B/66B编码选取特定结构的码块，来配置指示位，建立8个8比特与1个64比特码块之间的映射关系。具体地，如图9a至9e所示，例举了5中固定66B比特的码块结构，其中，包括T7码块(如图9a)、S0码块(如图9b)、O码块(如图9d)、IDLE码块(如图9e)和D码块(如图9c)。
进一步地，T7码块、S码块、O码块和IDLE码块为控制码，并通过同步头(sync)“10”2比特指示，“10”表示后面的64bit是数据和控制信息的混合，所述数据可以通过数据码(简称“D码”)承载；所述控制信息可以通过控制码(简称“K码”)承载，其中，紧挨着同步头的8bit表示类型域，后面的56bit是控制码、数据码或者两者的混合。
例如上面表1所示，C码流中的控制码I中承载有控制信息和数据两者的混合，进一步地，控制码I可以由编码K28.5/D5.6，或，K28.5/D16.2组成。K28.5承载控制信息，可称为控制码或者称为“K”码；D5.6或D16.2承载数据，可称为数据码或者称为“D”码。即控制码I可以表示为“K码+D码”的结构。同理地，同步头“01”表示该码块是数据码，同步头“01”之后的64比特均承载的是数据，可称为数据码或D码。
需要说明的是，在本申请各个实施例中，所述“K码+D码”结构的控制码，或者由一个K码与多个D码组成的控制码，这些D码与K码之间的界限为“小边界”；在图8所示的原始码流中，D码流与C码流之间的界限称为“大边界”，D码流中包括多个8比特的数据码，C码流中包括不同类型的控制码，本申请各个实施例中，如不特殊说明，“所述确定控制码与数据码之间的边界”是指确定D码流与C码流之间的“大边界”。
本实施例提供了一种码块生成方法，该码块可以节省原码流中指示信息的开销，该方法可以由适配单元，例如uAdpt来执行，或者由包括适配单元的其它网元设备来执行，例如接口板中的接口芯片等，本申请实施例对此不予限制。
具体地，如图10所示，该方法包括以下步骤：
步骤101：生成第一码块和第二码块，其中，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码。
步骤102：发送所述第一码块和所述第二码块。
可选的，所述第一码块与第二码块的位置包括以下关系：如图11a所示，第一码块位于第二码块之前；和，如图11b所示，第一码块位于第二码块之后。
可选的，所述第一指示位用“a”表示，占用1比特。所述第一码块单元由N个8比特组成，N大于等于1，且为正整数。同理地，所述第二码块单元也由N个8比特组成，N大于等于1。
参见图11a，第一码块位于第二码块之前，则第一码块单元中的第一指示位a用于指示后一个码块的第二码块单元是否为控制码；参见图11b，第一码块位于第二码块之后，则所述第一指示位a用于指示前一个码块的第二码块单元是否为控制码。
具体地，一种可能的指示方式是，如果第一指示位a的内容为“1”，则表示其指示的码块单元为控制码；如果第一指示位a的内容为“0”，则表示其指示的码块单元为数据码，即D码流中的数据码。
其中，所述第一码块和第二码块可以相邻，也可以不相邻。
可选的，所述第一码块和第二码块均为64B/66B码块，并且，所述第一码块和第二码块中还可以包括其它码块单元。
在本实施例的一种可能的实现方式中，所述第一码块中还包括第三码块单元，所述第三码块单元位于第一码块单元之前，如图11c所示，该第一码块单元中还设置有第二指示位，所述第二指示位用于指示所述第一码块单元之前的第三码块单元是否为控制码。
可选的，如图11d所示，第三码块单元还可以设置在第一码块单元之后，第二指示位用于指示第三码块单元是否为控制码。
可选的，第二指示位用“b”表示，占用1比特。
在本实施例的另一种可能的实现方式中，对于第一码块和第二码块而言，均可以是数据码，或者由数据和控制信息的混合的控制码，例如该控制码包括一个K码，或者由一个K码和至少一个D码组成；所述D码为数据码，用于表示K码的类型，例如Di码，表示K码是IDLE控制码。在所述第一码块单元为控制码的情况下，所述第一码块单元中还设置有第三指示位，所述第三指示位用于指示第一码块单元中的D码的个数。
可选的，如图11e所示，第三指示位用于指示第一码块单元中的D码的个数为一个。此外，还可以是0，1，3，7。
可选的，第三指示位用“cc”表示，占用2比特。
可选的，结合图11a所示的结构，本实施例还提供了一种码块结构，如图11f所示，包括第一码块和第二码块。其中，第一码块中包括第一码块单元，第二码块中包括第二码 块单元。第一码块单元中包括：控制码K码和数据码D码，其中，在控制码K码中设置有第一指示位a和第三指示位cc，所述第一指示位a用于指示第二码块单元是否为控制码，所述第三指示位cc用于指示第一码块单元中D码的个数(或长度)。本例中，第一码块单元中的D码个数为1。
在本实施例的又一种可能的实现方式中，在上述的码块结构基础上，第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，并且，第二码块单元中设置有至少一个指示位，所述至少一个指示位用于指示所述第四码块单元是否为控制码、指示所述第一码块单元是否为控制码；以及，在所述第二码块单元为控制码的情况下，所述至少一个指示位还用于指示所述第二码块单元中的D码的个数。
进一步地，包括以下各种情况：
情况一：
如图11g所示，在本实施例的一种码块结构中，所述第二码块包括：第二码块单元和第四码块单元，且第二码块单元中包括指示位a，b和cc；进一步地，第二码块单元中的指示位a用于指示第一码块单元是否为控制码，指示位b用于指示第二码块单元中D码的个数，指示位cc用于指示第四码块单元是否为控制码。
情况二：
如图11h所示，在本实施例的另一种码块结构中，所述第二码块包括：第二码块单元和第四码块单元，且第二码块单元中包括指示位a，b和cc；所述第一码块中包括第一码块单元，且所述第一码块单元由一个控制码K码和一个数据码D码组成，且所述控制码K码中设置有第一指示位a。
情况三：
如图11i所示，在本实施例的又一种码块结构中，第二码块的结构与图11g和11h的结构相同，不再赘述。第一码块中包括第一码块单元和第三码块单元，其中第一码块单元中包括：第一指示位a和第二指示位b，且第一指示位a用于指示第二码块单元是否为控制码，第二指示位b用于指示第三码块单元是否为控制码。
情况四：
如图11j所示，在本实施例的又一种码块结构中，第二码块的结构与图11g至11j的结构相同，不再赘述。区别在于，第一码块中包括第一码块单元，且第一码块单元由一个K码和至少一个D码组成，进一步地，在K码中设置有第一指示位a和第三指示位cc，且第一指示位a用于指示第二码块单元是否为控制码，第三指示位cc用于指示第一码块单元中D码的个数，本实施例中，D码个数为一个。
需要说明的是，上述各种情况中，由于第二码块单元中的第二指示位b用于指示前一个码块的第一码块单元是否为控制码，且第一码块单元由一个K码和至少一个D码组成，因为生成的第一码块单元中的最后一个单元为K码，用于承载至少一个指示位。例如，如果第一码块是T7控制码块，则将T7码块的最后一个位置“D6”设置成K码，对应地与数据码D进行位置调换，使得第二码块单元中的第二指示位b指示第一码块单元为控制码。
另外，在本实施例的各种码块结构中，还可以生成更多的码块，例如第三码块，第四码块等，且每个码块都可以包括至少一个码块单元，并且每个码块单元中均可以配置指示位，来逐级指示相邻码块单元是否为控制码，最终能够确定出原始码流的控制码与数据码 的大边界。
本实施例仅列举了第一码块和第二码块，以及第一码块中第一码块单元和第三码块单元，第二码块中第二码块单元和第四码块单元的指示位的配置和指示情况，如果生成其它码块，例如第三码块和第四码块等，具体生成码块的结构和配置指示位的情况，可以参考上述第一码块和第二码块的生成方法和指示情况，本实施例不一一举例。
可选的，在上述步骤101中，所述生成第一码块和第二码块，包括：获取第一码流，所述第一码流中包括控制码；例如，所述第一码流为8B码流；对第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块。
其中，所述第一码流的控制码中包括至少一个8比特的码块单元。
进一步地，对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块，包括：对所述第一码流中的一个8比特的码块单元进行压缩，得到N比特剩余空间，N≤8；在所述N比特的剩余空间内设置所述第一指示位，并填充成一个8比特的K码；根据所述8比特的K码生成所述第一码块，以及所述第二码块。
可选的，在生成8比特的K码过程中，还可以设置第二指示位和第三指示位。
同理地，生成的第二码块中，第二码块单元的K码中也可以设置至少一个指示位，以便指示相邻码块单元是否为控制码。
如图12所示，上述对码块进行压缩生成第一码块和第二码块的方法，具体包括：
第一步：获取第一码流，所述第一码块可以是原始8B/10B码流，且该原始8B/10B码流中包括数据码D码和控制码，比如控制码类型T/R/I/S码等。
将原始8B/10B码流译码为8B码流，并生指示信息，所述指示信息用于指示所述8B码流中控制码块和数据码块。
如图13所示，根据8B/10B码流编码规则，将原始10B码流Tx_10b[9:0]译码为8B码流Tx_8b[7:0]和1bit的指示信息Tx_en，通过这种方式，可以消除10B编码的固定25％额外开销。
此外，根据低速Ethernet和Fibre Channel等典型的8B/10B编码业务特点，业务码流都是由一串连续控制码块和一串连续数据码块交织发发送组合而成。其中，所有的控制码都是由K码+D码*n(n<4)构成。
在一种典型的GE业务流下，控制码T、R、S分别通过/K29.7/、/K23.7/、/K27.7/指示，图13中分别通过Kt、Kr和Ks表示；控制码I通过/K28.5/D5.6/或/K28.5/D16.2/指示，图中分别通过Ki+Di表示。
如图12所示，方法还包括：
第二步：对译码后的8B码流中的控制码进行压缩，得到中间态码流结构。
具体地，根据8B/10B码流中定义的12种K码类型，将8B码流中的K码压缩为4bit指示，如KtC/KrC/KiC/KsC等。其中，KtC/KrC/KiC/KsC各占4比特，剩余的高4比特可用于配置其它信息，来指示其它含义，使得最终每个码块单元的大小均为8比特。
进一步地，所述剩余高4bit保留用作其他含义的指示位，如图12所示，压缩后剩余的高4bit可以按照指示位a、b和cc来配置，例如，配置“a”和“b”各为1比特，“cc” 为2比特的指示位，通过这三个指示位可以将8B码流指示位Tx_en在8B码流的带宽上承载，进而节省了指示信息的开销。
可选的，配置各个指示位的含义如下：
第一指示位a：1bit，用于指示当前码块单元的后一个码块单元是否为控制码。
如果第一指示位a是“1”，则表示当前码块单元的后一个码块单元是控制码；如果是“0”，则表示所述后一个码块单元不是控制码，是数据码D码。
第二指示位b：1bit，用于指示当前码块单元的前一个码块单元是否为控制码。
如果第二指示位b是“1”，则表示当前码块单元的前一个码块单元是控制码；如果是“0”，则表示所述前一个码块单元不是控制码，是数据码D码。
第三指示位cc：2bit，用于指示当前码块单元的长度，或者指示第三指示位所在的码块单元中D码的个数。
一般地，控制码由K码，或者一个K码和n个D码组成，D码的个数与第三指示位cc满足以下关系式：n＝2 cc-1
其中，1表示K码占用一个8比特码块单元，根据该关系式可得表3
第三指示位cc n(D码个数) 码块单元的结构(码)
0 0 K
1 1 K+D
2 3 K+D+D+D
3 7 K+D+D+D+D+D+D+D
表3
参见表3，当第三指示位cc取值分别为0、1、2、3时，对应的D码个数分别为0、1、3、7。
在压缩后的剩余4比特空间配置每个码块的指示位a，b和cc，用于关联和指示相邻码块单元的控制码或数据码情况。
第四步：根据64B/66B码流中的特定码块结构，将所述压缩态码流的各指示位映射在对应的特定码块结构中，形成100GE标准的64B/66B码流。
其中，所述100GE标准的64B/66B码流中包括至少两个码块，例如第一码块和第二码块，每个码块都为64比特长度，进一步地，所述第一码块和第二码块包括但不限于以下各种情况：
第一码块为T7码块，第二码块为D码块；
或者，第一码块为S0码块，第二码块为D码块；
或者，第一码块为O码块，第二码块为D码块；
或者，第一码块为IDLE码块，第二码块为D码块；
其中，所述T7码块、S0码块、O码块和IDLE码块为控制码，所述D码块为数据码。
另外，需要说明的是，所述第一码块还可以为D码块，第二码块可以为T7码块、S0码块、O码块和IDLE码块中的任意一种控制码，或者还可以是其它类型码块，本申请实施例对第一码块和第二码块的码块结构不做具体限制。
需要说明的是，本申请实施例生成的64B/66B码流中的码块结构，包括但不限于S0+D、 D+T、O+D以及S0+D+T等各种码块结构，本实施例中只是列举了其中某些较常见的情况，还可以包括其它组合情况，本申请对此不予限制。
本实施例提供的方法，通过生成具有特定码块结构的码流，该码流中包括第一码块和第二码块，且每个码块中都配置有至少一个指示位，来指示相邻码块单元是否为控制码，从而确定出原始码流中控制码与数据码的边界，节约了额外指示信息的开销。
例如图12所示，第一码块为T7码块，第二码块为D码块，且第一码块中包括：两个8比特的数据码和若干个码块单元。进一步地，T7码块的类型域0xFF替换压缩态码流中控制码的第一个码块单元“a,b,cc，KtC”，如箭头所示，对应于原始10B码流中的控制码T；压缩态码流中的第二个码块单元“a,b,cc，KrC”被配置在T7码块中的D2位置，对应于原始10B码流中的控制码R；第三个码块单元包括一个K码和一个D码，所述K码为“a,b,cc，KiC”，所述D码为“Di”，对应于原始10B码流中的控制码IDLE；同理地，其余原始10B码流中的控制码IDLE都被压缩和配置为一个K码和一个D码组成的码块单元。
通过上述方法生成的第一码块包括以下码块单元：数据码D码、第一码块单元、第二码块单元和第三码块单元，其中，第一码块单元由一个K码组成，占8个比特长度，第二码块单元由一个K码和一个D码组成，占16比特长度，第三码块单元也由一个K码和一个D码组成，占16比特长度。
进一步地，第一码块单元中的K码中设置有3个指示位，按照“a,b,cc”的顺序分别为“1,0,0”，“1”用于指示第二码块单元为控制码，“0”用于指示第一码块单元的前一个码块单元为数据码，“0”用于指示第一码块单元中的数据码个数是零，即只包括一个K码，长度为8比特，通过第一码块单元中的第二指示位b，可以确定原始8B/10B码流中数据码和控制码的大边界为T7码块的D1位置和D2位置之间的界限。
同理地，生成第一码块中的第二码块单元和第三码块单元，均由原始8B/10B码流中的控制码IDLE压缩生成的，每个IDLE码由一个KiC码和一个Di码组成。其中，“Di”码中的“i”用于指示其所在的K码为IDLE码(简称为I)，即指示控制码的类型是I。
在生成的第一码块中，第二码块单元由“Di”和“a,b,cc，KiC”组成，各占8比特长度；第三码块单元也由“Di”和“a,b,cc，KiC”组成，各占8比特长度。需要说明的是，在设置“Di”和“a,b,cc，KiC”的位置时，由于第二码块中的第一个码块单元上设置的第二指示位b，用于指示第一码块的最后一个码块单元是否为控制码，所以第一码块的最后一个位置D6被设置为控制码“1,1,1，KiC”；此时原压缩的控制码I生成的“Di”和“a,b,cc，KiC”码位置互换。对应地，前一个第二码块单元中的“Di”码和“a,b,cc，KiC”码的位置也相比于压缩态码流发生互换。
如图12所示，第二码块包括4个码块单元，每个码块单元均由原始码流中的控制码I压缩而成，每个码块单元中包括一个KiC码和一个Di码组成，共占16个比特。进一步地，每个码块单元中的KiC码被设置3个指示位，分别是“1,1,1”，具体地，“1”指示当前码块单元的下一个码块单元为控制码；“1”指示当前码块单元的前一个码块单元为控制码；“1”指示当前码块单元中的D码个数是1。
此外，还包括第三码块，第三码块中的第一个码块单元为“0,1,0，KsC”，占用8比特，由原始10B码流中的控制码S压缩和设置而成。其中，第一指示位a是“0”，指示下一个码块是数据码，则确定从第三码块中的第一个码块单元之后为控制码。
本实施例提供的方法，第一码块的后一个码块为起点，即D码块的第一个码块单元为起点，根据第一、第二和第三指示位逐个确定每个码块单元是否为控制码，进而识别出原始8B/10B码流中数据码与控制码的边界，然后通过第三步中定义的指示位关联识别出控制码到数据码的边界，最终识别出所有码流信息，避免单独配置指示信息，产生额外开销。
本实施例提供的转码过程为一个通用过程，只需要特殊识别原始码块中T码，理论上可以通用解决所有帧结构的8B/10B编码的转码问题，转码为100GE标准的64B/66B T+D结构。
本实施例提供了一种8B/10B透明转码64B/66B的方法，先将10B码流译码为8B码流，可以节约20％固定开销，然后对译码后的8B码流的控制码进行压缩，压缩后在剩余空间配置至少一个指示位，用于指示相邻码块之间的控制码和数据码情况，进而节约了指示信息的开销，提高了转码效率，码块装载利用率相对于D码块透明承载提高了25％，且8B/10B码流的控制码和数据码的边界不需要重新恢复，通过控制码压缩后剩余码块开销指示，逐级关联相邻码块的方式，进而识别出整个码流特征及含义。
本申请的另一个实施例中，对应于上述码块的生成方法，本实施例提供了一种码块接收方法，所述方法包括：接收第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位；根据所述第一指示位的指示确定所述第二码块单元是否为控制码。
可选的，在本实施例的一种可能的实现方式中，所述第一码块中还包括第三码块单元，第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，所述方法还包括：根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码。
可选的，在本实施例的另一种可能的实现方式中，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；所述方法还包括：在确定所述第一码块单元为所述控制码的情况下，根据所述第一码块单元中的第三指示位确定所述第一码块单元中的D码的个数。
可选的，在本实施例的又一种可能的实现方式中，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，
所述方法还包括：根据所述第二码块单元中的至少一个指示位确定所述第四码块单元是否为控制码、以及所述第一单元码块是否为控制码。
可选的，在本实施例的又一种可能的实现方式中，所述根据所述第一指示位的指示确定所述第二码块单元是否为控制码，包括：如果所述第一指示信息指示所述第二码块单元不是控制码，则从所述第二码块单元开始为数据码。
另一个方面，如果第一指示信息指示是控制码，则进一步判断所述第二码块单元中的指示位是否指示下一个码块单元为控制码，直到指示不是控制码为止。
本实施例中，通过在每个码块单元上配置指示位，从而能够根据指示位的指示确定当前码块单元的相邻码块单元是否为控制码，进而确定出原始码流中数据码与控制码的边界，避免生成额外的指示信息，节约了开销。
下面根据不用业务的8B/10B码流转码成64B/66B码流的过程进行详细说明。
实施例一
本施例提供了一种GE业务的8B/10B转码成64B/66B码流的具体方法。其中，GE业务作为多业务承载的一种典型以太接入业务，物理层采用了8B/10B编码，控制码类型如上面表1所示。
按照上述实施例的核心方法流程，GE业务可以被转码为100GE标准64B/66B码流的T+D码块结构。如图14所示，主要处理流程如下：
步骤1：获取原始8B/10B码流中10B码流Tx_10b[9:0]，该10B码流中包括控制码和数据码。
步骤2：将原始10B码流Tx_10b[9:0]译码为8B码流Tx_8b[7:0]，同时生成1比特的指示信息Tx_en，该指示信息用于指示译码后的8B码流是控制码还是数据码，例如，指示信息中的高电平指示该码流中的码块是数据码，低电平指示码流中的码块是控制码。
其中，译码后的8B码流Tx_8b[7:0]中的Kt/Kr/Ks分别表示/T/R/S/三种控制码；/Ki/Di/表示组成/I/码的两个8bit数据。
步骤3：根据业务码流特征，由于控制码都是由K码+D码*n(n<4)构成，所以对控制码或组成控制码的K码进行压缩，得到压缩态码流Tx_n8b[7:0]，同时保留指示信息Tx_en。
参见上述表2中包括12种K码类型，将每个8bit的K码压缩为4bit大小(最多12种)，并且分别用4bit的KtC/KrC/KiC/KsC来表示，剩余4bit空间4’bx保留用于承载至少一个指示位，最终生成的每个K码任然保证是8bit。
步骤4：在压缩后剩余的空间内配置至少一个指示位，所述指示位用于指示相邻码块单元是否是控制码。
具体地，一种指示位的配置方法包括：在剩余的4bit空间内设置第一指示位a、第二指示位b和第三指示位cc，其中，第一指示位a用于指示当前码块单元的后一个码块单元是否为控制码；第二指示位b用于指示当前码块单元的前一个码块单元是否为控制码；第三指示位cc用于指示当前码块单元的长度，或者指示第三指示位所在的码块单元中D码的个数。
一般地，控制码由K码，或者一个K码和n个D码组成，D码的个数与第三指示位cc满足以下关系式：n＝2 cc-1
步骤5：将压缩并配置完指示位的压缩态码流Tx_n8b[7:0]转换为具有预定结构的64B/66B码流。
具体地，转码成具有预定结构的64B/66B码流的过程包括：
将8个压缩并配置完指示位的8bit码块组成一个64bit的码块，比如第一码块，同理地，生成一个64bit的第二码块、第三码块、第四码块等。转码后生成的第一码块可以是T7码块，第二码块可以是D码块，或者还可以是其它类型的码块，比如S0码块、O码块等。
本实施例以转码后，生成的第一码块是T7码块，第二码块是D码块为例，介绍第一码块和第二码块的结构特征，以及指示位的配置原则，具体如下：
本实施例中，配置指示位的原则为：包含原码流中T码的码块(block)转码为T7码块时，用于识别原码流中D码和控制码的边界。原码流T码确定为起始控制码，替换为T7中的类型域(type field)，不参与关联；后续的K码按照“a,b,cc”的方式进行关联， 通过T7后一个控制码压缩后指示位指示T7中是否包含控制码；除包含T码的其他block转码为D码，控制码全部按照上述方式进行压缩，可以指示相邻的前一个和后一个码块是否为控制码。
通过上述机制，实现了将8B/10B的GE码流透明转码为100GE标准的64B/66B的T+D码块结构。
例如：第一码块(T7码块)的同步头“10”表示该码块是由数据和控制信息组成的控制码；T7码块的类型域“0xFF”替换压缩态码流中的第一个K码“a,b,cc,KtC”，然后，类型域“0xFF”之后保留压缩态码流中的数据码和控制码。
第二码块(D码块)的同步头“01”表示该码块中后续承载的都是数据；D码块中的第一个K码“1,1,1,KtC”，用于指示第一码块中的最后一个码块单元是否是控制码。由于前后指示需要将控制码中的K码和D码的位置调换，所以第一码块中，组成控制码I的K码和D码要进行位置互换。
在D码块中，设置同步头“01”之后的第一个码块单元的指示位包括“1,1,1”，其中，第2个“1”表示当前码块单元的后一个码块单元为控制码；第2个“1”表示当前码块单元的前一个码块单元(即T7码块中的最后一个码块单元)为控制码；第3个“1”表示当前控制码或码块单元的长度占2byte，即16bit，或者表示控制码K码后关联1个数据码D码。
按照从第二码块(D码块)的第一个码块单元的第二指示位b开始，向第一码块(T7码块)从后向前指示的顺序判断，第一码块的后三个码块单元均为控制码，直到倒数第三个码块单元“1,0,0，KrC”的第二指示位b为“0”，表示前一个码块单元是数据码，所以判断出原始10B码流中控制码和数据吗的边界为从第一码块的第三个码块单元开始往后都是控制码，所述第一码块的第三码块单元之前为数据码。
从第二码块的第一个码块单元开始，根据每个码块单元中设置的第一指示位和第三指示位，向后逐级判断每个码块单元的类型，即是否为控制码。参见图14，第二码块中包括4个码块单元，且每个码块单元中设置的第一指示位a均为“1”表示均为控制码。
第三码块的第一个码块单元中包括第一指示位a为“0”，第三指示位cc也是“0”，则表示该码块单元的下一个码块单元是数据码，进而得到从第三码块的第二个码块单元开始为数据码，第二个码块之前为控制码，即区分出控制码结束的位置。
本实施例中，通过T7码块中各个位置的指示位信息能够识别出原始8B码流中数据码到控制码的边界，并通过压缩过程中定义的指示位，关联识别出控制码到数据码的边界，最终识别出所有码流信息，节约了原始码流中指示信息的开销。
此外，本实施例中采用了一种较通用的8B/10B转码成100GE标准64B/66B的方案，可以应用于各种帧结构的业务流转码，保证完全码字透明，不损失原始码块流中的信息，转码为一对一转码，100％的转码效率，无带宽膨胀。
可选的，在本实施例中，上述方法还包括：将66B码流中的码块转码为S+D+T码块结构，以便支持组网系统频偏以及操作维护管理(Operations,Administration,and Maintenance，OAM)等开销。
具体地，方法还包括：
步骤6：将第一码块(T7码块)的后一个码块(D码块)转码为S0码块，同时增加“0x78” 的类型域(type field)字段；该类型域字段将通过删除原8B/10B码流中的S码进行补充。
进一步地，该步骤6也存在两种可能：
一种可能的情况是，第一码块(T7码块)的后一个码块单元是原8B/10B码流中的S码，根据低速率以太，比如GE业务帧间隙的定义，此时T7码块的内部一定包含至少一个码块单元是控制码；通过判断“0x78”的类型域字段(或码块单元)的后一个码块单元是否为“0x55”可以区分该码块是数据码中的前导码，或者是经过压缩后的控制码；
具体地，如果是“0x55”类型域，则表示后一个码块单元是数据码的前导码，该前导码所在的码块为数据码；如果否，则表示后一个码块单元是经过压缩后的控制码。本实施例的这种判断方法，通过将“0x5”的压缩编码保留，剩余4比特空间用于判断是否承载字节“5”，来形成类型域“0x55”字段，从而能够判断出“0x78”码块单元的后一个码块是否是控制码，还能够避免与类型域为“0x55”的码块的前导码发生冲突。
另一种可能的情况是，第一码块(T7码块)的后一个码块单元不是原8B/10B码流中的S码，或者是非S码，则可以直接插入“0x78”的类型域字段，后续将原始10B码流中的S码(“0,1,0，KsC”码块单元)删除，处理方式如图15所示。
步骤7：对转码后的64B/66B码流中的IDLE码块进行压缩和转换，生成新的64B/66B码流。
上述转码过程为全透明转码，即在压缩和转码过程中不更改原码块中携带的信息。
为了支持如以太异步组网条件下100ppm的频偏处理，本实施例可以对原始8B/10B码流中的IDLE码进行压缩，也就是定义一种新的压缩码类型，以“KicC”表示，用于指示该码块单元包括至少两个IDLE码的压缩码。该码块单元长度固定为1Byte(8bit)，压缩码中的指示位cc用于指示替代的原IDLE码的个数为4个(2的平方)。
如图15所示，每个IDLE码(简写I码)在转换成66B码流后形成一个由KiC码和一个D码组成的码块单元，将总共4个所述码块单元压缩成一个8比特的KicC码(码块单元)，后续S0码块中的所有码块单元均由数据码D码填充，最终生成新的66B码流结构为“T7+S0+D”的码块结构。
可选的，由于在将所述新的66B码流结构映射到帧结构的过程中，同步时习惯以S0为起始数据，所以该新的66B码流的结构“T7+S0+D”也可以称为“S0+D+T”码块结构。
本实施例，通过上述步骤1至步骤5转码方法，可以将原始8B/10B码流的GE码流透明转码为100GE标准的64B/66B码流的“T+D”结构。进一步地拓展的步骤6和步骤7对转码的64B/66B码流的码块结构进行了改变，通过对控制码IDLE码块的压缩，可以将8B/10B的GE码流透明转码为100GE标准的64B/66B的“S+D+T”码块结构，以便适用于某些具体应用场景。
具体地，上述步骤6对本专利转码机制的码流带宽做了进一步补充，对原码流中的IDLE码块进行了压缩，从而将转码后的码流压缩到小于原始码流带宽，以便适用于某些具体场景对异步组网系统100ppm频偏以及带宽内OAM等开销特性的支持。
实施例二
本实施例提供了一种光纤通道(Fibre Channel，FC)业务下的8B/10B码流转码为64B/66B码流的方法。其中，所述FC业务作为多业务承载的一种典型接入业务，低速率接 口物理层采用了8B/10B编码，该8B/10B编码的码流中控制码编码如下表4所示。
Figure PCTCN2019104531-appb-000005
表4
参见图16，该FC业务的8B/10B码流以4Byte为单位，其中，1Byte＝8bit，即4Byte＝32bit。控制码和数据码均基于4Byte对齐，但是对于控制码而言，有序集(ordered set)仅仅使用了K28.5一个K码，其余的3个码块都是的D码，即“K+D+D+D”结构。
例如对于“SOFC1”的控制码而言，可以由“K28.5-D21.5-D23.0-D23.0”码块组成；“EOFt”可以由“K28.5-D21.4-D21.3-D21.3”码块组成，因此可以通过K码后面3Byte的数据区分不同的码块含义。
基于Fibre Channel业务的8B/10B码流特点。如图16所示，本实施例提供技术方案，Fibre Channel业务的8B/10B码流透明转码64B/66B的主要步骤如下：
步骤1：获取8B原始码流，该8B原始码流以4Byte为单位，即32bit，所述8B原始码流包括：数据码D和控制码EOF，IDLE，SOF等。
步骤2：将10B原始码流译码为8B码流，并生成指示信息Tx_en。
可选的，所述译码后的8B码流可以用“Tx_8b[7:0]”表示，同时通过1bit指示信息Tx_en指示译码后的8B码流中哪些码块是控制码，哪些码块是数据码。
由于Fibre Channel业务中只使用K28.5一种，且EOF、IDLE、SOF这些控制码都是4Byte构成，如图16和图17中所示，EOF码译码后表示为K+Dt+Dt+Dt，IDLE码译码后表示为K+Di+Di+Di。其中，K、Dt、Di均为8比特的码块。
步骤3：对8B原始码流中的控制码进行压缩，生成压缩后的码流“Tx_n8b[7:0]”。
根据Fibre Channel业务码流特征，控制码都是由K码+D码*n(n＝3)构成，由于Fibre Channel业务中只使用了K28.5一种K码，所以理论上可以将该K码域段完全压缩掉，剩余全部的8bit保留空间用于配置至少一个指示位。
本实施例基于依旧按照最大12种类型的K码，将K码压缩为4bit用KC表示，剩余4bit空间4’bx保留用于配置后续指示位。
步骤4：在压缩后的剩余空间配置至少一个指示位，以便替代指示信息对原始8B码流中的控制码和数据码进行指示。
具体地，一种配置指示位的原则包括：
在剩余的4bit空间配置三个指示位，分别是第一指示位a，占用1bit空间；第二指 示位b，占用1bit空间；第三指示位cc，占用2bit空间；通过这三个指示位可以将8B码流指示位Tx_en在8B码流的带宽承载。
三种指示位含义如下：
第一指示位a：用于指示当前码块单元的后一个码块单元是否为K码；
第二指示位b：用于指示当前码块单元的前一个码块单元是否为K码；
第三指示位cc：用于指示当前码块单元的长度，或者指示第三指示位所在的码块单元中D码的个数。
可选的，所述D码块的个数cc可以分别对应0/1/3/7。
进一步地，对于第一指示位a和第二指示位b而言，“1”表示指示的是控制码，“0”表示指示的是数据码。
可选的，对于Fibre Channel业务的8B/10B码流，由于都是以4Byte为单位，则发送端和接收端预先都知道，控制码有序集的结构是“K+D+D+D”，即一个K码关联3个D码，则可以不需要配置第三指示位cc，接收端也能够确定出每个码块单元的长度为32bit。
步骤4：利用K码压缩后剩余的4bit保留关联指示码块单元类型，生成中间态码流Tx_8b[7:0]。
根据前后码块单元确定每个K码的指示位信息，并在各个K码中设置至少一个指示位，具体的设置指示位的过程与实施例一相同，可参见上述实施例一的步骤4描述，此处不再赘述。
步骤5：根据中间态码流生成具有预定结构的64B码流，即将中间态的码流Tx_8b[7:0]转换为64B/66B码流Tx_66b[65:0]，该64B/66B码流Tx_66b[65:0]中包括至少两个码块，比如第一码块和第二码块等。
具体地，将8个8bit码块转码为1个64B码块，转码后生成预定结构的两种码块，比如生成第一码块为T7码块，第二码块为D码块。并且，通过T7码块中的第二指示位识别8B原始码流中数据码到控制码的边界，通过步骤3中定义的第一指示位和第三指示位关联识别出控制码到数据码的边界，最终识别出所有码流信息。
其中，上述码流在转码的过程中要求满足以下条件：
条件一：包含原码流中EOF码的码块转码并生成一个码块单元，该码块单元为T7码块的一部分，用于识别原码流中D码和控制码的边界。
在压缩后8B码流Tx_n8b[7:0]转换为66B码流Tx_66b[65:0]的过程中，原控制码EOF码转码成第一码块单元，其中，第一码块单元中的KC码用于替换T7码块中的类型域(type field)段，所以不参与关联和设置指示位，且第一码块单元由K+D+D+D的结构配置在T7码块的前面位置，原数据码D码的4个8bit设置在第一码块单元之后。后续控制码按照上述步骤4方式进行关联和设置，并且，通过T7码块的后一个码块单元中指示位来确定原始码流中数据码到控制码的边界。
如图17所示，第三码块单元中的控制码KC上，设置有第二指示位b为0，表示当前第三码块单元的前一个码块单元(第二码块单元)是数据码，则确定转码后的66B码流的数据码与控制码的边界为第二码块单元和第三码块单元之间的界限。
条件二：除包含EOF码的其他码块转码为D码块，控制码全部按照上述方式进行压缩，并配置指示位，以便可以指示相邻的前一个和后一个码块单元是否为控制码。
如图17所示，压缩后的8B码流中的第一码块单元的控制码“a,b,cc,KC”在转码到66B码流的T7码块时，被T7中的类型域“0xFF”字段替换，同时关联3个D码组成4Byte的码块单元；然后原始8B码流中的数据码依次向后顺延，形成第二码块单元。
在第二码块中，第三码块单元的KC码中配置指示位为“1,0,2”，其中，第一指示位“1”指示其后一个码块单元为控制码；第二指示位“0”指示其前一个码块单元(即第二码块单元)为数据码；第三指示位“2”指示当前控制码占4(22)Byte，即32bit。
本实施例中对FC业务中的控制码EOF、IDLE、SOF进行转码和指示位配置，转码为T7码块和D码块的结构，实现了将原始8B码流转码为100GE标准的64B/66B码流T+D结构。
本实施例提供了一种通用的8B/10B透明转码64B/66B的方法，先将原始的8B/10B码流转码为10B码流进而减小了20％的固定开销，然后通过对Fibre Channel业务的8B码流中的控制码进行压缩，节省出剩余空间用于配置至少一个指示位，这些指示位用于码块间的相互关联，最后再将压缩后的码流形态映射至预定结构的64B码流中，所述预定结构的64B码流包括特殊的T7码块，且以该T7码块为起点，通过控制码压缩后剩余指示位进行相邻识别，最终准确识别整个码流信息，以及判断出控制码的边界，从而避免了8B/10B丢失和再重新恢复。
需要说明的是，本实施例提供的对8B/10B码流进行压缩的方法，此压缩转码方式不仅适用于K码，也可对其他类型码块进行相似处理。
此外，本方法还可以应用于各种帧结构的业务流转码；完全码字透明，不损失原始码块流中的信息；转码为一对一，1:1的转码效率，无带宽膨胀。
本实施例提供的方法是除GE业务之外的另一种较典型的接入业务Fibre Channel，基于上述译码、转码的通用规则，实现了Fbire Channel业务的8B/10B转码为标准100GE的64B/66B码流，以适应各种业务需求。
此外，对于上述各个实施例，在将8B原始码流压缩的过程中，压缩后指示信息中的码块长度信息可以同时作为压缩编码内容的一部分，也就是不同长度的码块单独编码，从而提高能够支持的码块数量。另外，根据需要的特定信息编码数量，压缩后码块的指示位不限于本申请实施例中的第一指示位、第二指示位和第三指示位，共占用4bit，可以根据需要定义更多或是更少比特数。控制码压缩后剩余指示位不限于本专利中描述的特定数据结构。包括能够构成相邻码块关系的其他数据结构定义。
在根据压缩后码流形态配置并转码为64B码流的过程中，配置后的各个指示位指示，逐级关联相邻码块的机制，进而确定控制码和数据码的边界。其中。控制码压缩后起始识别点可以但不限定是本申请实施例中提到的T7码块，S码块，还可以包括等其他码块，比如S码块。
所述关联指示可以但不限于本申请实施例中提到的前向指示和后向指示，可以是其中的一种，或是两种指示复用到1bit上，通过S或T的码块类型进行区分。
转码后的预定64B码流结构包括但不限于S+D码块、D+T码块、O+D码块、S+D+T码块等各种结构形态，本申请实例仅例举上述常见的几种码块结构，对于其它码块结构，本申请实施例不予限制。
实施例三
本实施例提供了一种将10GE的64B/66B码流转码为100GE标准的64B/66B码流的方 法。
如图18a和图18b所示，分别示出了一种10GBASE-R的64B/66B编码的示意图，和，一种100GBASE-R的64B/66B编码的示意图，其中，图18a中，10GBASE-R的编码作为多业务承载的一种典型接入业务，其采用的64B/66B编码和100GBASE-R 64B/66B编码不完全一致，所以在进行L1.5层交换单元前也需要进行透明转码。
其中，输入数据(Input Data)中包括：比特位置(bit position)、数据码块格式(data block format)和控制码块格式(control block format)。进一步地，数据码块格式由：D0D1D2D3/D4D5D6D7组成，控制码块格式可以由C码、O码、D码、S码以及数据码D码混合组成。
参见图18a，对于10BASE-R 64B/66B编码的所有控制码块格式中，在转换成图18b所示的100GBASE-R 64B/66B编码码流的过程中，对除了原10GE的7种控制码块格式中的码块单元T0至T7之外的所有码块单元进行编码，生成一个码块单元。该码块单元的长度为64bit，即8byte。
可选的，根据T0至T7的8种不同的控制码块格式可以对以下8种不同码块净荷区(block payboad)的64B/66B码块进行转码。比如图18a所示，这8种不同类型的控制码码块的类型域分别为：
Ox87，0x99,0xaa，0xb4，0xcc，0xd2，0xe1，0xff。
本实施例中以一种控制码块的格式为“D0D1T2C3/C4C5C6C7”为例，该码块格式对应的控制码类型域为“0xaa”，如图18c所示，该码块单元包括：数据码D0和D1，控制码C3至C7，其中，每个D码为8bit，每个C码为7bit，即每个C码相比于D码少1bit，共有C3至C7 5个控制码，所以相比于D码少5bit，则保留剩余5bit空间，最终保证该码块包含一个码块单元，长度是64bit。
下面，以该类型域为“0xaa”的码块为例，对10GE业务下的64B/66B编码进行转换做详细的说明。
如图19所示，具体地，本实施例提供的转码处理过程如下：
步骤1：获取原始66B码流。
可选的，所述原始66B码流中包括类型域为“0xaa”的66B码块，该66B码块中包括数据码D0和D1，控制码C3至C7。
步骤2：将原始66B码流译码为64B码流，同时通过1bit信号Tx_en指示译码后的64B码流中的控制码和数据码情况。
步骤3：根据译码后的64B码流的控制码块格式，对该64B码流中除了T2位置的码块单元之外的所有控制码块进行压缩，生成多个码块单元。其中，每个码块单元中包括4比特的“KcC”和4比特的剩余空间，所述4比特的剩余空间用于承载指示位“a,b,cc”，所述指示位用于关联指示相邻码块或码块单元的类型。进一步地，指示位a用于指示后一个码块单元是否为控制码；指示位b用于指示当前码块单元的前一个码块单元是否为控制码；指示位cc用于指示当前码块单元的长度。
可选的，本实施例中，每个码块单元长度均为1Byte(即8bit)。
在步骤3中，由于对压缩后剩余的空间内配置指示位“a,b,cc”来指示相邻码块的控制码情况，进而确定控制码与数据码的边界，所以消除了原指示信息Tx_en的指示，从而 节约了开销。
可选的，在压缩过程中，原始64B/66B码流中类型域为：0x1e，0x2d，0x33，0x66，0x55，0x78，0x4b的控制码可以用Kt0、Kt1、Kt2、Kt3、Kt4、Kt5、Kt6表示。例如，图19所示，原始66B码流中的类型域“0x1e”压缩后变成“Kt0C”。
具体地，通过指示位“a,b,cc”来确定原始码流中控制码和数据码的边界情况可以参考上述实施例，本实施例对此不再详细赘述。
步骤4：将压缩后并设置有指示位的中间态码流Tx_n64b[63:0]转换成100GE标准的64B/66B码流。
其中，所述转换后的100GE标准64B/66B码流中包括第一码块和第二码块。
可选的，所述第一码块为T7码块，所述第二码块为D码块。所述中间态码块中的类型域“0xaa”字段被T7码块的类型域“0xFF”字段替代，形成标准的“T7码块+D码块”的码型结构。其他码块转码为D码块。
在D码块中，包括一个“1,1,3Kt0C”的控制码，为D码块的起始码块。其中，第一指示位“1”指示后一个码块单元(第三码块)为控制码；第二指示位“1”指示前一个码块单元(第一码块的最后一个码块单元)是控制码；第三指示位“3”指示当前码块单元的大小长度为8(2的三次方)个C码的长度，即56bit，每个C码为7bit。
本方法通过上述机制，将原始的10GBASE-R的64B/66B码流透明转码为100GE标准的64B/66B编码的码流，且转码前后的码块均为8byte为单位的码块。
本方法实现了码块完全透明转码，转码后的码流不损失原始码块流中的信息。转码为一对一，100％的转码效率，无带宽膨胀。
可以理解地，本申请还可以采用上述方法对其他具有与类似结构的原始码流进行转码，形成100GE标准的64B/66B码流，另外，还可以根据上述压缩、配置指示位、转码等一系列步骤实现对其他类型码流的转码，本申请实施例对此不予限制。
需要说明的是，本实施例中仅以类型域为“0xaa”的64bit码块为例进行转码，附图18a所示的其他码块，比如类型域是0x99、0x4b、0xcc等类型的码块，也可采用本实施例的转码方法，生成100GE标准的64B/66B编码码流，本实施例对这些码块的转码过程不再赘述。
参见图20，为本申请实施例提供的一种码块生成装置的结构示意图。该装置可以是前述任意实施例中的适配单元，例如uAdpt，用于实现前述各个实施例中的方法步骤。
如图20所示，该装置200可以包括：获取单元2001，处理单元2002和发送单元2003，此外，所述装置200还可以包括更多或更少的部件，例如存储单元等，本实施例对此不进行限定。
进一步地，处理单元2002用于生成第一码块和第二码块，其中，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码；发送单元2003用于发送所述第一码块和所述第二码块。
可选的，在本实施例的一种具体的实现方式中，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前；所述第一码块单元中还设置有第二指示位，所述第二指示位用于指示所述第一码块单元之前的第三码块单元是否为控制码。
可选的，在本实施例的另一种具体的实现方式中，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；在所述第一码块单元为所述控制码的情况下，所述第一码块单元中还设置有第三指示位，所述第三指示位用于指示所述第一码块单元中的D码的个数。
可选的，在本实施例的又一种具体的实现方式中，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后。
所述第二码块单元中设置有至少一个指示位，所述至少一个指示位用于指示所述第四码块单元是否为控制码、指示所述第一码块单元是否为控制码；以及，在所述第二码块单元为控制码的情况下，所述至少一个指示位还用于指示所述第二码块单元中的D码的个数。
可选的，在本实施例的又一种具体的实现方式中，获取单元2001用于获取第一码流，所述第一码流中包括控制码；所述处理单元2002具体用于对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块。
其中，所述第一码流可以为8B编码码流(经过10B转码为8B码流)，还可以10GE64B/66B编码码流。
可选的，在本实施例的又一种具体的实现方式中，所述第一码流的控制码中包括至少一个8比特的码块单元，所述处理单元2002，具体用于对所述第一码流中的一个8比特的码块单元进行压缩，得到N比特剩余空间，N≤8；在所述N比特的剩余空间内设置所述第一指示位，并填充成一个8比特的K码；根据所述8比特的K码生成所述第一码块，以及所述第二码块。
例如，N＝4，则可以在剩余的4bit上配置第一指示位、第二指示位和第三指示位。
进一步地，所述第一指示位a占用1bit，第二指示位b占用1bit，第三指示位cc占用2bit。
其中，在所述第一指示位a和第二指示位b是“1”的情况下，表示指示的码块单元为控制码；在所述第一指示位a和所述第二指示位b是“0”的情况下，表示指示的码块单元为数据码。
此外，对于第三指示位cc可以在码块单元中设置，也可以不设置，但接收端和发送端需要预先约定，并且两端都知道码块单元的长度。例如，对于Fibre Channel业务的控制码和数据码均以4byte为单位来编码，所以，在这种情况下，每个控制码K码均关联3个D码，即“K+D+D+D”结构，所以仅需要设置第一指示位和第二指示位来指示后一个码块和前一个码块是否为控制码即可，从而更提高了识别效率，并节约2bit开销，可用于承载其它信息。
可选的，在本实施例的又一种具体的实现方式中，所述第一码块为T7码块，所述第二码块为D码块；
或者，所述第一码块为S0码块，所述第二码块为D码块；
或者，所述第一码块为O码块，所述第二码块为D码块；
或者，所述第一码块为IDLE码块，所述第二码块为D码块；
其中，所述T7码块、S0码块、O码块和IDLE码块为控制码，所述D码块为数据码。
此外，所述第一码块还可以是D码块，所述第二码块为T7码块、S0码块、O码块和 IDLE码块中的任意一种。
可选的，所述第一码块为D码，所述第二码块为T7码块、S0码块、O码块和IDLE码块中的任意一种。
可选的，还包括第三码块，所述第三码块为D码块，所述第二码块为S0码块，所述第一码块为T7码块，则转码后的64B/66B码流的码块结构为“S0+D+T”。
此外，还可以转码成其他结构的64B/66B码流，本实施例对此不予限制。
可选的，在本实施例的又一种具体的实现方式中，所述处理单元2002，还用于在第一码块为T7码块，第二码块为D码块的情况下，将所述D码转码为S0码块，所述SO码块中包括：一个类型域，一个包括K码的码块单元和至少一个包括D码的码块单元；其中，所述包括K码的码块单元是，原所述D码块的由一个K码和至少一个D码组成的所有码块单元进行压缩后生成的一个码块单元，且所述K码的码块单元中包括至少一个指示位，比如包括3个指示位，分别是a,b和cc。
其中，所述S0码块的类型域为“0x78”。
此外，本实施例中，还可以将D码块转码为其它类型的码块，比如O码块、IDLE码块等。
可选的，在本实施例的又一种具体的实现方式中，所述第一码块为T7码块，所述第二码块为S0码块，所述处理单元2002，还用于生成第三码块，所述第三码块为D码块。
可以理解地，所述处理单元2002还可以根据原始码流的特点生成更多的码块，比如第四码块和第五码块等，具体的生成过程与方法前述实施例相同，本实施例对此不再赘述。
在本申请的又一个实施例中，还提供了一种码块接收装置，如图21所示，该装置210包括：获取单元2101，处理单元2102和发送单元2103，此外，所述装置210还可以包括更多或更少的部件，例如存储单元等，本申请对此不进行限定。
获取单元2101，用于接收第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位。
处理单元2102，用于根据所述第一指示位的指示确定所述第二码块单元是否为控制码。
可选的，在本实施例的一种具体的实现方式中，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，所述处理单元2102还用于根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码。
可选的，在本实施例的另一种具体的实现方式中，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；所述处理单元2102还用于在确定所述第一码块单元为所述控制码的情况下，根据所述第一码块单元中的第三指示位确定所述第一码块单元中的D码的个数。
可选的，在本实施例的又一种具体的实现方式中，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，所述处理单元2102还用于根据所述第二码块单元中的至少一个指示位确定所述第四码块单元是否为控制码、以及所述第一单元码块是否为控制码。
可选的，在本实施例的又一种具体的实现方式中，所述处理单元2102具体用于如果 所述第一指示信息指示所述第二码块单元不是控制码，则从所述第二码块单元开始为数据码。
需要说明的是，本实施例提供的码块接收装置可以是前述实施例中的码块生成装置，或者是前述实施例中的一种适配单元，例如uAdpt或nAdpt，用于实现上述实施例对应的码块接收方法，并通过该方法识别出原始码流中的控制码和数据码的边界。
本实施例中，通过在码块单元中配置至少一个指示位，来指示当前码块单元的前后码块单元是否为控制码，以及控制码的D码长度，进而通过每个码块单元的上指示位的逐级指示确定出控制码和数据码的边界，避免了额外信息的开销。
在一个具体硬件实施例中，如图22所示，还提供了一种分组承载设备220，该设备可以是规划加载X-E特性的IP移动承载网(Radio Access Network，RAN)或分组传送网(Packet transport network，PTN)设备，用于实现前述实施例中的PE或P的各种功能。
具体地，参见图22，分组承载设备220包括：接口板2201、接口板2203和主控交换板2202。其中，接口板2201连接至主控交换板2202的输入端，接口板2203连接至主控交换板2202的输出端。
进一步地，接口板2201中包括用户侧接口芯片，用于实现PE的uAdpt的各项功能；主控交换板2202中包括网络处理器(Network Processor，NP)或交换网芯片，用于实现PE的交换单元的功能；接口板2203中包括网络侧接口芯片，用于实现PE的nAdpt的各项功能。
此外，还可以在接口板2201和接口板2203上承载其他功能单元，比如多业务功能单元。
进一步地，在所述接口板2201的用户侧处理芯片中还可以包括：收发器2301、处理器2302和存储器2303，如图23所示。此外，该用户侧处理芯片中还可以包括更多或更少的部件，或者组合某些部件，或者不同的部件布置，本申请对此不进行限定。
处理器2302为用户侧处理芯片的控制中心，通过运行或执行存储在存储器2303内的软件程序和/或单元模块，以及调用存储在存储器内的数据，以执行用户侧处理芯片的各种功能。
所述处理器2302可以由集成电路(integrated circuit，IC)组成，例如可以由单颗封装的IC所组成，也可以由连接多颗相同功能或不同功能的封装IC而组成。举例来说，处理器可以仅包括CPU，也可以是GPU、数字信号处理器(digital signal processor，DSP)、及收发模块中的控制芯片的组合。
收发器2301可以包括接收机、发射机与天线等部件，用于接收原始码流，发送转码后的码流，所述转码后的码流中包括第一码块、第二码块等。此外，收发器2301还用于实现用户侧与网络设备的通信传输。
具体地，所述收发器2301可以包括无线局域网模块、蓝牙模块、基带(base band)模块等通信模块，以及该通信模块对应的射频(radio frequency，RF)电路，用于进行无线局域网络通信、蓝牙通信、红外线通信及/或蜂窝式通信系统通信。此外，收发器2301还可以支持直接内存存取(direct memory access)。
在本申请的不同实施方式中，所述收发器2301中的各种收发模块一般以集成电路芯片(integrated circuit chip)的形式出现，并可进行选择性组合，而不必包括所有收 发模块及对应的天线组。例如，收发器可以仅包括基带芯片、射频芯片以及相应的天线以在一个蜂窝通信系统中提供通信功能。经由所述收发模块建立的无线通信连接，例如无线局域网接入或WCDMA接入。
存储器2303用于存储执行本申请技术方案的应用程序代码，并由处理器2302来控制执行。具体地，处理器2302用于执行所述存储器中存储的应用程序代码，实现上述各实施例中的码块生成方法、码块接收方法。
进一步地，存储器2303可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，也可以和处理器集成在一起。
示例性地，在本申请图20所示的码块生成装置实施例中，获取单元2001和发送单元2003所要实现的功能可以由所述用户侧处理芯片的收发器2301实现，或者由处理器2302控制收发器2301实现；所述处理单元2002所要实现的功能则可以由处理器2302实现。
示例性地，在本申请图21所示的码块接收装置实施例中，接收单元2101和发送单元2103所要实现的功能可以由所述用户侧处理芯片的收发器2301实现，或者由处理器2302控制收发器2301实现；所述处理单元2102所要实现的功能则可以由处理器2302实现。
另外，在本申请图23所示的用户侧处理芯片230可以设置或集成在图1a所示的用户侧适配单元(uAdpt)中，用于实现uAdpt的所有功能。
进一步地，所述存储器2303用于存储计算机程序产品，所述计算机程序产品包括一个或多个计算机指令，例如同步载频信号发送指令。在计算机加载和执行所述计算机程序时，全部或部分地产生按照本申请上述实施例各实施例所述的流程或功能。
所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网络站点、计算机、服务器或数据中心通过有线或无线方式向另一个站点、计算机或服务器进行传输。所述计算机可读存储介质可为磁碟、光盘、只读存储记忆体ROM或随机存储记忆体RAM等。
在本申请的实施例中，还提供了一种系统，如图2所示，该系统可以是Ethernet网，FlexE网络或者X-E组网。具体地，所述网络系统中包括：用户设备UE和网络设备PE或P，所述PE用于执行上述各实施例中的码块生成方法和接收方法。例如，PE1将原始码流转码为100GE标准的64B/66B编码码流，以及将转码后的标准码流发送给P。P将接收的标准码流传输给PE2，PE2接收到该标准的64B/66B编码码流之后再将其转码为原始的8B/10B码流，以及对外输出值用户设备。
本实施例提供了一种装置和系统，由于在传输的码流中包括第一码块和第二码块，且在第一码块中的码块单元上配置了至少一个指示位，可以指示相邻码块的控制码和数据码情况，从而能够通过转码后的码块内容确定出控制码和数据码的边界，节约了指示信息的开销。
本领域的技术人员可以清楚地了解到本发明实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本发明实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例或者实施例的某些部分所述的方法。
本说明书中各个实施例之间相同相似的部分互相参见即可。尤其，对于一种码块生成装置、接收装置、分组承载设备和系统的实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例中的说明即可。
此外，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
以上所述的本申请实施方式并不构成对本申请保护范围的限定。

Claims (29)

  1. 一种码块生成方法，其特征在于，所述方法包括：
    生成第一码块和第二码块，其中，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码；
    发送所述第一码块和所述第二码块。
  2. 根据权利要求1所述的方法，其特征在于，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，
    所述第一码块单元中还设置有第二指示位，所述第二指示位用于指示所述第一码块单元之前的第三码块单元是否为控制码。
  3. 根据权利要求1或2所述的方法，其特征在于，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；
    在所述第一码块单元为所述控制码的情况下，所述第一码块单元中还设置有第三指示位，所述第三指示位用于指示所述第一码块单元中的D码的个数。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，
    所述第二码块单元中设置有至少一个指示位，所述至少一个指示位用于指示所述第四码块单元是否为控制码、指示所述第一码块单元是否为控制码；
    以及，在所述第二码块单元为控制码的情况下，所述至少一个指示位还用于指示所述第二码块单元中的D码的个数。
  5. 根据权利要求1所述的方法，其特征在于，所述生成第一码块和第二码块，包括：
    获取第一码流，所述第一码流中包括控制码；
    对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块。
  6. 根据权利要求5所述的方法，其特征在于，所述第一码流的控制码中包括至少一个8比特的码块单元，
    对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块，包括：
    对所述第一码流中的一个8比特的码块单元进行压缩，得到N比特剩余空间，N≤8；
    在所述N比特的剩余空间内设置所述第一指示位，并填充成一个8比特的K码；
    根据所述8比特的K码生成所述第一码块，以及所述第二码块。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，
    所述第一码块为T7码块，所述第二码块为D码块；
    或者，所述第一码块为S0码块，所述第二码块为D码块；
    或者，所述第一码块为O码块，所述第二码块为D码块；
    或者，所述第一码块为IDLE码块，所述第二码块为D码块；
    其中，所述T7码块、S0码块、O码块和IDLE码块为控制码，所述D码块为数据 码。
  8. 根据权利要求1-6任一项所述的方法，其特征在于，在所述第一码块为T7码块，所述第二码块为D码块的情况下，所述方法还包括：
    将所述D码转码为S0码块，所述SO码块中包括：一个类型域，一个K码的码块单元和至少一个包括D码的码块单元；
    其中，所述包括K码的码块单元是，原所述D码块的由一个K码和至少一个D码组成的所有码块单元进行压缩后生成的一个码块单元，且所述K码的码块单元中包括至少一个指示位。
  9. 根据权利要求1-6任一项所述的方法，其特征在于，所述第一码块为T7码块，所述第二码块为S0码块，
    所述方法还包括：
    生成第三码块，所述第三码块为D码块。
  10. 一种码块接收方法，其特征在于，所述方法包括：
    接收第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位；
    根据所述第一指示位的指示确定所述第二码块单元是否为控制码。
  11. 根据权利要求10所述的方法，其特征在于，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，
    所述方法还包括：
    根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码。
  12. 根据权利要求10或11所述的方法，其特征在于，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；
    所述方法还包括：
    在确定所述第一码块单元为所述控制码的情况下，根据所述第一码块单元中的第三指示位确定所述第一码块单元中的D码的个数。
  13. 根据权利要求10-12任一项所述的方法，其特征在于，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，
    所述方法还包括：
    根据所述第二码块单元中的至少一个指示位确定所述第四码块单元是否为控制码、以及所述第一码块单元是否为控制码。
  14. 根据权利要求10所述的方法，其特征在于，所述根据所述第一指示位的指示确定所述第二码块单元是否为控制码，包括：
    如果所述第一指示信息指示所述第二码块单元不是控制码，则从所述第二码块单元开始为数据码。
  15. 一种码块生成装置，其特征在于，所述装置包括：
    处理单元，用于生成第一码块和第二码块，其中，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位，所述第一指示位用于指示所述第二码块单元是否为控制码；
    发送单元，用于发送所述第一码块和所述第二码块。
  16. 根据权利要求15所述的装置，其特征在于，
    所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前；
    所述第一码块单元中还设置有第二指示位，所述第二指示位用于指示所述第一码块单元之前的第三码块单元是否为控制码。
  17. 根据权利要求15或16所述的装置，其特征在于，
    所述控制码包括一个K码，或者由一个K码和至少一个D码组成；
    在所述第一码块单元为所述控制码的情况下，所述第一码块单元中还设置有第三指示位，所述第三指示位用于指示所述第一码块单元中的D码的个数。
  18. 根据权利要求15-17任一项所述的装置，其特征在于，
    所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，
    所述第二码块单元中设置有至少一个指示位，所述至少一个指示位用于指示所述第四码块单元是否为控制码、指示所述第一码块单元是否为控制码；以及，在所述第二码块单元为控制码的情况下，所述至少一个指示位还用于指示所述第二码块单元中的D码的个数。
  19. 根据权利要求15所述的装置，其特征在于，还包括获取单元，
    所述获取单元，用于获取第一码流，所述第一码流中包括控制码；
    所述处理单元，具体用于对所述第一码流中的控制码进行压缩，并在压缩后的码块的剩余空间内设置第一指示位，生成所述第一码块和所述第二码块。
  20. 根据权利要求19所述的装置，其特征在于，所述第一码流的控制码中包括至少一个8比特的码块单元，
    所述处理单元，具体用于对所述第一码流中的一个8比特的码块单元进行压缩，得到N比特剩余空间，N≤8；在所述N比特的剩余空间内设置所述第一指示位，并填充成一个8比特的K码；根据所述8比特的K码生成所述第一码块，以及所述第二码块。
  21. 根据权利要求15-20任一项所述的装置，其特征在于，
    所述第一码块为T7码块，所述第二码块为D码块；
    或者，所述第一码块为S0码块，所述第二码块为D码块；
    或者，所述第一码块为O码块，所述第二码块为D码块；
    或者，所述第一码块为IDLE码块，所述第二码块为D码块；
    其中，所述T7码块、S0码块、O码块和IDLE码块为控制码，所述D码块为数据码。
  22. 根据权利要求15-20任一项所述的装置，其特征在于，
    所述处理单元，还用于在所述第一码块为T7码块，所述第二码块为D码块的情况 下，将所述D码转码为S0码块，所述SO码块中包括：一个类型域，一个包括K码的码块单元和至少一个包括D码的码块单元；
    其中，所述包括K码的码块单元是，原所述D码块的由一个K码和至少一个D码组成的所有码块单元进行压缩后生成的一个码块单元，且所述K码的码块单元中包括至少一个指示位。
  23. 根据权利要求15-20任一项所述的装置，其特征在于，所述第一码块为T7码块，所述第二码块为S0码块，
    所述处理单元，还用于生成第三码块，所述第三码块为D码块。
  24. 一种码块接收装置，其特征在于，所述装置包括：
    获取单元，用于接收第一码块和第二码块，所述第一码块包括第一码块单元，所述第二码块包括第二码块单元，且所述第一码块单元中设置有第一指示位；
    处理单元，用于根据所述第一指示位的指示确定所述第二码块单元是否为控制码。
  25. 根据权利要求24所述的装置，其特征在于，所述第一码块中还包括第三码块单元，所述第三码块单元位于所述第一码块单元之前，所述第一码块单元中还设置有第二指示位，
    所述处理单元，还用于根据所述第二指示位的指示确定所述第一码块单元之前的第三码块单元是否为控制码。
  26. 根据权利要求24或25所述的装置，其特征在于，所述控制码包括一个K码，或者由一个K码和至少一个D码组成；
    所述处理单元，还用于在确定所述第一码块单元为所述控制码的情况下，根据所述第一码块单元中的第三指示位确定所述第一码块单元中的D码的个数。
  27. 根据权利要求24-26任一项所述的装置，其特征在于，所述第二码块中还包括第四码块单元，所述第四码块单元位于所述第二码块单元之后，所述第二码块单元中设置有至少一个指示位，
    所述处理单元，还用于根据所述第二码块单元中的至少一个指示位确定所述第四码块单元是否为控制码、以及所述第一单元码块是否为控制码。
  28. 根据权利要求24所述的装置，其特征在于，
    所述处理单元，具体用于如果所述第一指示信息指示所述第二码块单元不是控制码，则从所述第二码块单元开始为数据码。
  29. 一种计算机可读存储介质，所述存储介质中存储有指令，其特征在于，
    当所述指令被运行时，实现如权利要求1至9、或10至14中任一项所述的方法。
PCT/CN2019/104531 2018-09-07 2019-09-05 一种码块生成方法、接收方法和装置 WO2020048508A1 (zh)

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