WO2020042312A1 - 一种驱动电路及其内部过流设定值的校正方法 - Google Patents

一种驱动电路及其内部过流设定值的校正方法 Download PDF

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Publication number
WO2020042312A1
WO2020042312A1 PCT/CN2018/111644 CN2018111644W WO2020042312A1 WO 2020042312 A1 WO2020042312 A1 WO 2020042312A1 CN 2018111644 W CN2018111644 W CN 2018111644W WO 2020042312 A1 WO2020042312 A1 WO 2020042312A1
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Prior art keywords
current
signal
chip
current signal
value
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Ceased
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PCT/CN2018/111644
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English (en)
French (fr)
Inventor
王明良
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/312,068 priority Critical patent/US11038343B2/en
Publication of WO2020042312A1 publication Critical patent/WO2020042312A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the embodiments of the present application belong to the field of electronic technology, and in particular, to a driving circuit and a method for correcting an internal overcurrent setting value thereof.
  • the traditional LCD display panel usually integrates the gate driver chip on the display panel.
  • This design method greatly limits the reduction of the display frame.
  • the existing display usually uses a doorless driver ( Gate driver less (GDL) architecture.
  • GDL Gate driver less
  • the GDL circuit divides the gate driver chip into a boost chip and a shift register chip, integrates the boost chip on the driver board, the shift register chip is integrated on the display panel, and the high voltage is output through the boost chip.
  • the logic signal is sent to the shift register chip to complete the display driving, thereby further reducing the frame length. Due to uncontrollable factors in the production process, the display panel may work abnormally.
  • a protection mechanism is usually set on the boost chip and power management chip.
  • the current output of the boost chip is turned off, or when the current signal output by the power management chip is too large, the current output of the power management chip is turned off.
  • the over-current protection circuit used by the existing boost chip and power management chip often causes the panel to burn out due to the failure to turn off the corresponding current output in time, which has great safety risks.
  • over-current protection circuits used by the existing boost chip and power management chip often cause the panel to burn out due to failure to turn off the corresponding current output in time, which has great safety risks.
  • the embodiments of the present application provide a driving circuit and a method for correcting an internal overcurrent set value thereof, which aim to solve an overcurrent protection circuit used by a boost chip and a power management chip, which is often caused by failure to turn off a corresponding current output in time. If the panel is burnt out, it has a great potential safety hazard.
  • An embodiment of the present application provides a driving circuit including a first chip and a second chip.
  • the driving circuit further includes:
  • a current detection module configured to obtain a first current signal output by the first chip
  • the timing control module is configured to receive the first current signal and convert the first current signal into a second current signal, and the second current signal is set to a set value of an internal overcurrent of the second chip. Make adjustments.
  • the second chip includes:
  • a boosting module configured to perform boosting processing on an input first logic signal and output a second logic signal
  • the overcurrent setting module is configured to perform current limiting control on the second logic signal according to the internal overcurrent setting value.
  • the second chip is a boost chip.
  • the first chip is a power management chip.
  • the current detection module includes:
  • a first conversion unit configured to convert a first current signal output by the first chip into a corresponding first data signal
  • the first storage unit is configured to store the first data signal.
  • the timing control module includes:
  • a second storage unit configured to set and store a second data signal corresponding to the first data signal
  • the control unit is configured to acquire the first data signal, and acquire the second data signal from the second storage unit according to the first data signal.
  • the overcurrent setting module is further configured to:
  • the overcurrent setting module is further configured to:
  • the current value of the second current signal is set as the internal overcurrent set value.
  • the overcurrent setting module is further configured to:
  • the timing control module is connected to the current detection module through an I2C interface.
  • An embodiment of the present application further provides a driving circuit, where the driving circuit includes:
  • a power management chip configured to output a first current signal
  • a boosting chip configured to perform boosting processing on an input first logic signal to output a second logic signal, and perform current limit control on the second logic signal according to an internal overcurrent set value
  • a current detection module configured to obtain the first current signal
  • the timing control module is configured to receive the first current signal and convert the first current signal into a second current signal, and the second current signal is set to a set value of an internal overcurrent of the boost chip. Make adjustments.
  • the current detection module includes:
  • a first conversion unit configured to convert the first current signal into a corresponding first data signal
  • the first storage unit is configured to store the first data signal.
  • the timing control module includes:
  • a second storage unit configured to set and store a second data signal corresponding to the first data signal
  • the control unit is configured to acquire the first data signal, and acquire the second data signal from the second storage unit according to the first data signal.
  • the second data signal is configured to correct the internal overcurrent set value.
  • An embodiment of the present application further provides a method for correcting an internal overcurrent set value of a driving circuit, wherein the driving circuit includes:
  • a first chip configured to output a first current signal
  • a second chip configured to receive a first logic signal, and perform boost processing on the first logic signal to output a second logic signal
  • the correction method includes:
  • the second current signal is set to adjust an internal overcurrent set value of the second chip, and the internal The over-current set value is set to perform current limiting control on the second logic signal.
  • the acquiring the first current signal output by the first chip includes:
  • a current detection module is used to obtain a first current signal output by the first chip.
  • the receiving the first current signal and converting the first current signal into a second current signal includes:
  • the converting the first current signal to the second current signal according to the first current signal and a preset current conversion relation table includes:
  • the setting of the second current signal to adjust an internal overcurrent setting value of the second chip includes:
  • the current value of the second current signal is set as the internal overcurrent set value.
  • the setting of the internal overcurrent setting value to perform current limiting control on the second logic signal includes:
  • the second logic signal is stopped from being output.
  • An embodiment of the present application provides a driving circuit and a method for correcting an internal overcurrent set value thereof.
  • a first current signal output by a first chip is obtained through a current detection module, and then the timing control module converts the first current signal into A second current signal configured to adjust an internal overcurrent setting value of the second chip, so that the internal overcurrent setting value of the second chip can be adjusted according to the first current signal output by the first chip It realizes that the output current of the second chip can be turned off in time when it is too high, and the over-current protection circuit used by the existing boost chip and power management chip is often caused by the failure to turn off the corresponding current output in time. The situation of burnout has great potential safety hazards.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 5 is a lookup table for a conversion relationship between a current value of a first current signal and a current value of a second current signal according to an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application
  • step S20 is a schematic flowchart of step S20 in a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application;
  • FIG. 9 is a schematic flowchart of step S22 in a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application.
  • the GDL circuit divides the gate IC into a level shifter IC and a shift register. register) chip, where the boost chip is integrated on the driver board and the shift register chip is integrated on the display panel.
  • the boost chip outputs a clock signal to the shift register chip to complete the display driver, thereby further reducing the length of the frame.
  • the effective display area can be continuously increased.
  • the chip is usually equipped with an overcurrent protection mechanism. For example,
  • the power management chip is configured to convert the input voltage of the power supply into various types of voltage signals for output.
  • the voltage signal output by the power management chip includes: set to turn on a thin film transistor (Thin Film Transistor (TFT) turn-on voltage signal VGH, turn-off voltage signal VGL set to turn off the TFT, etc.
  • TFT Thi Film Transistor
  • an overcurrent protection mechanism is usually set inside the power management signal.
  • the boost chip is configured to perform boost processing on the input low-voltage logic signal and output a high-voltage logic signal. In order to avoid the voltage value of the high-voltage logic signal generated by the boost processing being too high, an overvoltage is usually provided at the output of the boost chip Protection mechanism, shut off the output signal in time when the output high-voltage logic signal is over-voltage.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present application.
  • the driving circuit in this embodiment includes a first chip 10 and a second chip 40.
  • the driving circuit further includes:
  • the current detection module 20 is configured to obtain a first current signal output by the first chip 10;
  • the timing control module 30 is configured to receive the first current signal and convert the first current signal into a second current signal, and the second current signal is configured to set an internal overcurrent setting of the second chip 40. Adjust the value.
  • the current detection module 20 detects the first current signal output by the first chip 10, and the detection process includes a detection process and a conversion process. Specifically, the first chip 10 generates different Voltage signal, such as on-voltage signal, off-voltage signal, etc., the current detection module 20 selects the detection output port to detect the first voltage signal.
  • the first voltage signal can be any one of the output ports of the first chip 10. After outputting the voltage signal, the current detection module 20 detects the first voltage signal, converts the first voltage signal into a first current signal, and outputs the converted first current signal.
  • the timing control module 30 receives the first current signal output by the current detection module 20 and converts the first current signal into a second current signal.
  • the second current signal is set to the inside of the second chip 40. Over current setpoint is adjusted.
  • the timing control module 30 may convert the first current signal into a second current signal set to adjust the internal overcurrent setting value of the second chip 40 according to a preset current conversion relationship, and the current conversion The relationship may be set according to user needs.
  • the current conversion relationship may be: subtracting a preset value from the current value received by the timing control module 30 as the current value of the second current signal, for example, the first current signal received by the timing control module 30
  • the current value of the current signal is 30 mA
  • the preset value set by the user is 20 mA.
  • the current value of the second current signal is 10 mA
  • the timing control module 30 sets the current value of the first 30 mA
  • the current signal is converted into a second current signal with a current value of 10 mA to adjust an internal overcurrent setting value of the second chip 40.
  • the preset current conversion relationship may also be a preset linear relationship.
  • the current value of the second current signal is set to 0.9 times or 0.8 times the current value of the first current signal.
  • the module 30 After receiving the first current signal with a current value of 100 mA, the module 30 performs a down-flow processing on the first current signal to obtain a second current signal with a current value of 80 mA, and outputs the second current signal to the second chip 40.
  • the preset current conversion relationship may also be set as a preset algorithm for calculation according to user needs, or a pre-stored current lookup table may be used to compare the current value of the first current signal received with the timing control module 30 The current value of the corresponding second current signal is set.
  • the overvoltage protection value of the first chip 10 in this embodiment is not lower than that set in the second chip 40
  • the over-voltage protection value, specifically, the current value of the first current signal is not lower than the current value of the second current signal.
  • the current detection module 20 may further store the current value of the converted first current signal.
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • the second chip 40 in this embodiment includes:
  • the boosting module 410 is configured to perform a boosting process on the input first logic signal and output a second logic signal;
  • the overcurrent setting module 420 is configured to perform current limiting control on the second logic signal according to an internal overcurrent setting value.
  • the over-current setting module 420 in the second chip 40 performs current-limiting control on the second logic signal output by the boost module 410 according to the internal over-current setting value.
  • the first logic signal in this embodiment Both the second logic signal and the second logic signal may be voltage signals.
  • the over-current setting module 420 performs current limit control on the second logic signal may include turning off the output of the second logic signal or performing a step-down process on the second logic signal. It is avoided that the second logic signal voltage output by the second chip 40 is too high and the panel glass is burned.
  • the first chip 10 in this embodiment is a power management chip.
  • the second chip 40 in this embodiment is a boost chip.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • the current detection module 20 includes:
  • the first conversion unit 201 is configured to convert a first current signal output by the first chip 10 into a corresponding first data signal
  • the first storage unit 202 is configured to store a first data signal.
  • the first conversion unit 201 converts the received first current signal into a corresponding first data signal, and stores the first data signal in the first storage unit 202, for example, the current detection module 20 When a current value of 100 mA is detected, the first conversion unit 201 converts the first current signal into a first data signal.
  • the first data signal includes information that the current value of the first current signal is 100 mA.
  • the first data is stored.
  • the first storage unit 202 waits for the timing control module 30 to read.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • the timing control module 30 includes:
  • a second storage unit 301 configured to set and store a second data signal corresponding to the first data signal
  • the control unit 302 is configured to acquire a first data signal and acquire a second data signal according to the first data signal.
  • control unit 302 may include a general integrated circuit, such as a CPU (Central Processing Unit, central processing unit), or an ASIC. (Application Specific Integrated Circuit).
  • a CPU Central Processing Unit, central processing unit
  • ASIC Application Specific Integrated Circuit
  • control unit 302 may also be a screen driving board (TCON, Timing Controller) of the display device.
  • TCON Timing Controller
  • the second storage unit 301 stores a second data signal corresponding to the first data signal.
  • the second data signal can also be set according to user needs.
  • the control unit 302 reads from the current detection module 20 Fetch the first data signal, and then read the corresponding second data signal from the second storage unit 301 according to the first data signal, the second data signal containing the second data of the current value information corresponding to the first data signal.
  • the signal, specifically, the second data signal corresponding to the first data signal stored in the second storage unit 301 may be a lookup table for a current conversion relationship, and the lookup table may be set according to user needs.
  • FIG. 5 is a lookup table for a conversion relationship between a current value of a first current signal and a current value of a second current signal according to an embodiment of the present application.
  • the control unit 302 obtains a second data signal containing the second current signal information from the second storage unit 301 according to the information about the first current signal contained in the first data signal.
  • the second data signal corresponding to the first data signal stored in the second storage unit 301 may be a lookup table for a current conversion relationship, and may further include: a current value threshold interval of the first current signal and a second current The look-up table for the conversion relationship of the current value of the signal, specifically, first confirm the threshold interval in which the current value of the first current signal is located, and determine the current value of the second current signal corresponding to the threshold interval according to the threshold interval, for example, the first The overvoltage protection value of a chip 10 is 100mA. Each interval of 10mA is used as a threshold interval interval. From 0 to 100mA, there are 10 threshold intervals. These 10 threshold intervals may correspond to the currents of 10 identical or different second current signals.
  • the current value of the second current signal corresponding to 70mA to 80mA, 80mA to 90mA, 90mA to 100mA can be 50mA
  • the current value of the second current signal corresponding to 50mA to 60mA can be 80mA
  • the threshold interval in which the current value is located is determined. For example, if the current of the current signal is detected as 55 mA, The 50mA 60mA corresponding to a second predetermined threshold is 80mA
  • the control unit 302 reads the second data signal comprises a second current signal of a current value of 80mA information from the second storage unit 301.
  • the timing control module 30 may further include a third conversion unit configured to convert the second data signal into a corresponding second current signal and output the second data signal to the overcurrent setting module 420 in the second chip 40. .
  • the overcurrent setting module 420 is further configured to:
  • the current value of the second current signal is set to an internal overcurrent setting value of the second chip.
  • the timing control module 30 may also directly send the second data signal read by the control unit 302 from the second storage unit 301 to the overcurrent setting module 420 in the second chip, and the overcurrent setting module 420 Corrects the internal overcurrent setting value by the received second data signal.
  • the overcurrent setting module 420 is further configured to set the current value of the second current signal to an internal overcurrent setting value.
  • the overcurrent setting module 420 sets the current value of the second current signal to the internal overcurrent setting value of the second chip 40, and the current value of the second current signal can be determined according to The current of the first current signal is adjusted according to a preset current value conversion relationship. Therefore, setting the current value of the second current signal to the internal overcurrent setting value of the second chip 40 can reach the internal overcurrent setting of the adjustment driving circuit. The purpose of the value.
  • the overcurrent setting module 420 is further configured to turn off the output of the second logic signal when the second logic signal is greater than or equal to the internal overcurrent setting value.
  • the timing control module 30 is connected to the current detection module through an I2C interface.
  • FIG. 6 is a schematic structural diagram of a driving circuit according to another embodiment of the present application.
  • the driving circuit in this embodiment includes:
  • the power management chip 10 is configured to output a first current signal
  • the boosting chip 40 is configured to perform boosting processing on the input first logic signal to output a second logic signal, and perform current limit control on the second logic signal according to an internal overcurrent set value;
  • the current detection module 20 is configured to obtain the first current signal
  • the timing control module 30 is configured to receive the first current signal and convert the first current signal into a second current signal, and the second current signal is set to set an internal overcurrent of the boost chip. Value to adjust.
  • the current detection module 20 includes:
  • a first conversion unit configured to convert the first current signal into a corresponding first data signal
  • the first storage unit is configured to store the first data signal.
  • the timing control module 30 includes:
  • a second storage unit configured to set and store a second data signal corresponding to the first data signal
  • the control unit is configured to acquire the first data signal, and acquire the second data signal from the second storage unit according to the first data signal.
  • the control unit 302 when the current value of the first current signal in the first data signal read by the control unit 302 is 100 mA, the second current signal in the second data signal read from the second storage unit 301 The current value is 50 mA. When the current value of the first current signal in the first data signal read by the control unit 302 is 90 mA, the second current signal in the second data signal read from the second storage unit 301 The current value is 60 mA, and so on.
  • the control unit 302 obtains a second data signal containing the second current signal information from the second storage unit 301 according to the information about the first current signal contained in the first data signal.
  • the second data signal corresponding to the first data signal stored in the second storage unit 301 may be a lookup table for a current conversion relationship, and may further include: a current value threshold interval of the first current signal and a second current The look-up table for the conversion relationship of the current value of the signal, specifically, first confirm the threshold interval in which the current value of the first current signal is located, and determine the current value of the second current signal corresponding to the threshold interval according to the threshold interval, for example, the first The overvoltage protection value of a chip 10 is 100mA. Each interval of 10mA is used as a threshold interval interval. From 0 to 100mA, there are 10 threshold intervals. These 10 threshold intervals may correspond to the currents of 10 identical or different second current signals.
  • the current value of the second current signal corresponding to 70mA to 80mA, 80mA to 90mA, 90mA to 100mA can be 50mA
  • the current value of the second current signal corresponding to 50mA to 60mA can be 80mA
  • the threshold interval in which the current value is located is determined. For example, if the current of the current signal is detected as 55 mA, The 50mA 60mA corresponding to a second predetermined threshold is 80mA
  • the control unit 302 reads the second data signal comprises a second current signal of a current value of 80mA information from the second storage unit 301.
  • the second data signal is configured to correct the internal overcurrent set value.
  • the timing control module may also directly send the second data signal read by the control unit from the second storage unit to the boosting chip 60, and the boosting chip 60 overcurrents the internal through the received second data signal The set value is corrected, that is, the current value in the second data signal is set as an internal overcurrent set value of the boost chip.
  • FIG. 7 is a schematic flowchart of a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application.
  • the driving circuit includes:
  • a first chip configured to output a first current signal
  • the second chip is configured to receive a first logic signal, and perform boost processing on the first logic signal to output a second logic signal.
  • the correction method in this embodiment includes:
  • Step S10 acquiring a first current signal output by the first chip
  • Step S20 receiving the first current signal and converting the first current signal into a second current signal; the second current signal is set to adjust an internal overcurrent setting value of the second chip, The internal overcurrent set value is set to perform current limiting control on the second logic signal.
  • step S10 includes:
  • a current detection module is used to obtain a first current signal output by the first chip.
  • the driving circuit further includes a current detection module 20 and a timing control module 30.
  • Obtaining the first current signal output by the first chip includes: using a current detection module 20 to detect the first current signal output by the first chip 10, and the detection process includes a detection process and a conversion process.
  • the first The chip 10 generates different voltage signals according to the requirements of the back-end circuit, such as the on voltage signal and the off voltage signal.
  • the current detection module 20 selects the detection output port to detect the first voltage signal.
  • the first voltage signal can be For the voltage signal output from any one of the output ports of the first chip 10, the current detection module 20 detects the first voltage signal, converts the first voltage signal into a first current signal, and converts the converted first current signal. For output.
  • receiving the first current signal and converting the first current signal into a second current signal includes: adopting a timing control module 30 to convert the first current signal into a first current signal according to a preset current conversion relationship.
  • the second current signal is set to adjust the internal overcurrent set value of the second chip 40.
  • the current conversion relationship can be set according to user needs.
  • the current conversion relationship can be: the current value received by the timing control module 30.
  • the preset value is subtracted as the current value of the second current signal.
  • the current value of the first current signal received by the timing control module 30 is 30 mA
  • the preset value set by the user is 20 mA.
  • the timing control module 30 converts the first current signal with a current value of 30 mA into a second current signal with a current value of 10 mA to set an internal overcurrent of the second chip 40. Adjust the value.
  • the current detection module 20 may further store the current value of the converted first current signal.
  • FIG. 8 is a schematic flowchart of step S20 in a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application.
  • step S20 includes:
  • Step S21 receiving the first current signal
  • Step S22 converting the first current signal into the second current signal according to the first current signal and a preset current conversion relation table.
  • FIG. 5 is a lookup table for a conversion relationship between a current value of a first current signal and a current value of a second current signal according to an embodiment of the present application.
  • the control unit 302 obtains a second data signal containing the second current signal information from the second storage unit 301 according to the information about the first current signal contained in the first data signal.
  • the second data signal corresponding to the first data signal stored in the second storage unit 301 may be a lookup table for a current conversion relationship, and may further include: a current value threshold interval of the first current signal and a second current The look-up table for the conversion relationship of the current value of the signal, specifically, first confirm the threshold interval in which the current value of the first current signal is located, and determine the current value of the second current signal corresponding to the threshold interval according to the threshold interval, for example, the first The overvoltage protection value of a chip 10 is 100mA. Each interval of 10mA is used as a threshold interval interval. From 0 to 100mA, there are 10 threshold intervals. These 10 threshold intervals may correspond to the currents of 10 identical or different second current signals.
  • the current value of the second current signal corresponding to 70mA to 80mA, 80mA to 90mA, 90mA to 100mA can be 50mA
  • the current value of the second current signal corresponding to 50mA to 60mA can be 80mA
  • the threshold interval in which the current value is located is determined. For example, if the current of the current signal is detected as 55 mA, The 50mA 60mA corresponding to a second predetermined threshold is 80mA
  • the control unit 302 reads the second data signal comprises a second current signal of a current value of 80mA information from the second storage unit 301.
  • FIG. 9 is a schematic flowchart of step S22 in a method for correcting an internal overcurrent set value of a driving circuit according to an embodiment of the present application.
  • step S22 includes:
  • Step S221 acquiring a first current value of the first current signal
  • Step S222 Obtain a second current value from a preset current conversion relationship table according to the first current value
  • Step S223 Convert the first current signal into the second current signal according to the second current value.
  • the preset current conversion relationship may also be a preset linear relationship.
  • the current value of the second current signal is set to 0.9 times or 0.8 times the current value of the first current signal.
  • the module 30 After receiving the first current signal with a current value of 100 mA, the module 30 performs a down-flow processing on the first current signal to obtain a second current signal with a current value of 80 mA, and outputs the second current signal to the second chip 40.
  • the preset current conversion relationship may also be set as a preset algorithm for calculation according to user needs, or a pre-stored current lookup table may be used to compare the current value of the first current signal received with the timing control module 30 The current value of the corresponding second current signal is set.
  • the setting of the second current signal to adjust an internal overcurrent setting value of the second chip includes:
  • the current value of the second current signal is set as the internal overcurrent set value.
  • the overvoltage protection value of the first chip 10 in this embodiment is not lower than that set in the second chip 40
  • the over-voltage protection value, specifically, the current value of the first current signal is not lower than the current value of the second current signal.
  • the setting of the internal overcurrent setting value to perform current limiting control on the second logic signal includes:
  • the second logic signal is stopped from being output.
  • the overvoltage protection value of the first chip 10 in this embodiment is not lower than that set in the second chip 40
  • the over-voltage protection value, specifically, the current value of the first current signal is not lower than the current value of the second current signal.
  • the units in the apparatus of the embodiment of the present application may be combined, divided, and deleted according to actual needs.
  • the program can be stored in a computer-readable storage medium.
  • the program When executed, the processes of the embodiments of the methods described above may be included.
  • the storage medium may be a magnetic disk, an optical disc, or a read-only storage memory (Read-Only Memory (ROM) or Random Access Memory (Random Access Memory, RAM).

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Abstract

一种驱动电路及其内部过流设定值的校正方法，通过时序控制模块(30)将第一芯片(10)输出的第一电流信号转换为对第二芯片(40)的内部过流设定值进行调节的第二电流信号。

Description

一种驱动电路及其内部过流设定值的校正方法 技术领域
本申请实施例属于电子技术领域，尤其涉及一种驱动电路及其内部过流设定值的校正方法。
 背景技术
传统的液晶显示面板通常将门驱动芯片集成在显示面板上，这种设计方式极大的限制了显示器边框的减小，为了能够减小显示器的边框，现有的显示器通常采用一种无门驱动器（Gate driver less，GDL）架构，GDL电路是将门驱动芯片拆分为升压芯片和移位寄存器芯片，将升压芯片集成在驱动板上，移位寄存器芯片集成在显示面板上，通过升压芯片输出高压逻辑信号给移位寄存器芯片以完成显示器驱动，从而进一步压缩边框长度。由于生产工艺中的不可控因素可能会造成显示器面板的工作异常，为了避免升压芯片和电源管理芯片的输出电流过大而烧毁显示面板，通常对升压芯片和电源管理芯片设置保护机制，以使得升压芯片输出的电流信号过大时关闭升压芯片的电流输出，或者在电源管理芯片输出的电流信号过大时关闭电源管理芯片的电流输出。
然而，现有的升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患。
 技术问题
现有的升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患。
 技术解决方案
本申请实施例提供一种驱动电路及其内部过流设定值的校正方法，旨在解决升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患的问题。
本申请实施例提供了一种驱动电路，包括第一芯片和第二芯片
所述驱动电路还包括：
电流侦测模块，设置为获取所述第一芯片输出的第一电流信号；以及
时序控制模块，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节。
可选地，所述第二芯片包括：
升压模块，设置为对输入的第一逻辑信号进行升压处理，并输出第二逻辑信号；以及
过流设定模块，设置为根据所述内部过流设定值对所述第二逻辑信号进行限流控制。
所述第二芯片为升压芯片。
所述第一芯片为电源管理芯片。
可选地，所述电流侦测模块包括：
第一转换单元，设置为将所述第一芯片输出的第一电流信号转换为对应的第一数据信号；以及
第一存储单元，设置为存储所述第一数据信号。
可选地，所述时序控制模块包括：
第二存储单元，设置为设置和存储与所述第一数据信号对应的第二数据信号；
控制单元，设置为获取所述第一数据信号，并根据所述第一数据信号从所述第二存储单元中获取所述第二数据信号。
可选地，所述过流设定模块还设置为：
接收所述第二数据信号，并将所述第二数据信号设置为所述内部过流设定值。
可选地，所述过流设定模块还设置为：
将所述第二电流信号的电流值设置为所述内部过流设定值。
可选地，所述过流设定模块还设置为：
在所述第二逻辑信号大于或者等于所述内部过流设定值时，关断所述第二逻辑信号的输出。
可选地，所述时序控制模块通过I2C接口与所述电流侦测模块连接。
本申请实施例还提出了一种驱动电路，所述驱动电路包括：
电源管理芯片，设置为输出第一电流信号；
升压芯片，设置为对输入的第一逻辑信号进行升压处理以输出第二逻辑信号，并根据内部过流设定值对所述第二逻辑信号进行限流控制；
电流侦测模块，设置为获取所述第一电流信号；以及
时序控制模块，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述升压芯片的内部过流设定值进行调节。
可选地，所述电流侦测模块包括：
第一转换单元，设置为将所述第一电流信号转换为对应的第一数据信号；以及
第一存储单元，设置为存储所述第一数据信号。
可选地，所述时序控制模块包括：
第二存储单元，设置为设置和存储与所述第一数据信号对应的第二数据信号；
控制单元，设置为获取所述第一数据信号，并根据所述第一数据信号从所述第二存储单元中获取所述第二数据信号。
可选地，所述第二数据信号设置为对所述内部过流设定值进行校正。
本申请实施例还提出了一种驱动电路的内部过流设定值的校正方法，其中，所述驱动电路包括：
第一芯片，设置为输出第一电流信号；
第二芯片，设置为接收第一逻辑信号，并对所述第一逻辑信号进行升压处理以输出第二逻辑信号；
所述校正方法包括：
获取所述第一芯片输出的第一电流信号；
接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号；所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制。
可选地，所述获取所述第一芯片输出的第一电流信号，包括：
采用电流侦测模块获取所述第一芯片输出的第一电流信号。
可选地，所述接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，包括：
接收所述第一电流信号；
根据所述第一电流信号以及预设的电流转换关系表将所述第一电流信号转换为所述第二电流信号。
可选地，所述根据所述第一电流信号以及预设的电流转换关系表将所述第一电流信号转换为所述第二电流信号，包括：
获取所述第一电流信号的第一电流值；
根据所述第一电流值从预设的电流转换关系表中获取第二电流值；
根据所述第二电流值将所述第一电流信号转换为所述第二电流信号。
可选地，所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，包括：
将所述第二电流信号的电流值设置为所述内部过流设定值。
可选地，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制，包括：
若所述第二逻辑信号的电流值等于或大于所述内部过流设定值，则停止输出所述第二逻辑信号。
 有益效果
本申请实施例提供一种驱动电路及其内部过流设定值的校正方法，通过电流侦测模块获取第一芯片输出的第一电流信号，然后时序控制模块将所述第一电流信号转换为第二电流信号，该第二电流信号设置为对第二芯片的内部过流设定值进行调节，使得第二芯片的内部过流设定值可以根据第一芯片输出的第一电流信号进行调节，实现了第二芯片的输出电流在过高时可以及时关断，解决了现有的升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请的一个实施例提供的驱动电路的结构示意图；
图2为本申请的另一个实施例提供的驱动电路的结构示意图；
图3为本申请的另一个实施例提供的驱动电路的结构示意图；
图4为本申请的另一个实施例提供的驱动电路的结构示意图；
图5为本申请的一个实施例提供的第一电流信号的电流值和第二电流信号的电流值之间的转换关系查找表；
图6为本申请另一个实施例提供的驱动电路的结构示意图；
图7为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法的流程示意图；
图8为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法中的步骤S20的流程示意图；
图9为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法中的步骤S22的流程示意图。
 本发明的实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“包括”以及它们任何变形，意图在于覆盖不排他的包含。例如包含一系列步骤或单元的过程、方法或系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同对象，而非用于描述特定顺序。
在无门驱动器（Gate driver less，GDL）架构中，GDL电路是将门驱动芯片（gate IC）拆分为升压芯片（level shifter IC）和移位寄存器（shift register）芯片两部分，其中，升压芯片集成在驱动板上，移位寄存器芯片集成在显示面板上，通过升压芯片输出时钟信号给移位寄存器芯片以完成显示器驱动，从而进一步压缩边框长度，使得有效显示区能够不断增加。为了保护避免芯片因为输出信号过流而烧毁，芯片内部通常均设置有过流保护机制，例如，
电源管理芯片设置为将电源输入的电压转换为各种类型的电压信号进行输出，在显示装置中，电源管理芯片输出的电压信号包括：设置为导通薄膜晶体管（Thin Film Transistor，TFT）的开启电压信号VGH、设置为关断TFT的关断电压信号VGL等，为了避免烧毁显示面板，通常电源管理信号内部设置有过流保护机制。升压芯片设置为对输入的低压逻辑信号进行升压处理，并输出高压逻辑信号，为了避免升压处理产生的高压逻辑信号的电压值过高，通常在升压芯片的输出端设置有过压保护机制，在输出的高压逻辑信号过压时及时关断输出信号。
图1为本申请的一个实施例提供的驱动电路的结构示意图。
如图1所示，本实施例中的驱动电路包括第一芯片10和第二芯片40，在本实施例中，驱动电路还包括：
电流侦测模块20，设置为获取所述第一芯片10输出的第一电流信号；以及
时序控制模块30，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述第二芯片40的内部过流设定值进行调节。
在一个实施例中，电流侦测模块20对第一芯片10输出的第一电流信号进行检测，该检测过程包括侦测过程和转换过程，具体的，第一芯片10根据后端电路需要产生不同的电压信号，例如开启电压信号、关断电压信号等，电流侦测模块20选择需要侦测输出端口对第一电压信号进行侦测，该第一电压信号可以为第一芯片10任意一个输出端口输出的电压信号，电流侦测模块20侦测到该第一电压信号后将该第一电压信号转换为第一电流信号，并将转换后的第一电流信号进行输出。
在一个实施例中，时序控制模块30接收电流侦测模块20输出的第一电流信号，并将第一电流信号转换为第二电流信号，该第二电流信号设置为对第二芯片40的内部过流设定值进行调节。
在一个实施例中，时序控制模块30可以根据预先设置的电流转换关系将第一电流信号转换为设置为对第二芯片40的内部过流设定值进行调节的第二电流信号，该电流转换关系可以根据用户需要设置，例如，该电流转换关系可以为：将时序控制模块30接收的电流值减去预设值作为第二电流信号的电流值，例如，时序控制模块30接收到的第一电流信号的电流值为30mA，用户设置的预设值为20mA，则根据该预设的电流转换关系，第二电流信号的电流值为10mA，则时序控制模块30将电流值为30mA的第一电流信号转换为电流值为10mA的第二电流信号，以对第二芯片40的内部过流设定值进行调节。
在一个实施例中，该预设的电流转换关系还可以为预设的线性关系，例如，将第二电流信号的电流值设置为第一电流信号的电流值的0.9倍或者0.8倍，时序控制模块30接收到电流值为100mA的第一电流信号后对第一电流信号进行降流处理得到电流值为80mA的第二电流信号，并输出至第二芯片40中。
在一个实施例中，该预设的电流转换关系还可以根据用户需要设置成预设的算法进行计算，或者采用预先存储的电流查找表对与时序控制模块30接收的第一电流信号的电流值对应的第二电流信号的电流值进行设置。
在一个实施例中，为了使得第二芯片40和第一芯片10可以在过流时及时关闭电流输出，本实施例中的第一芯片10的过压保护值不低于第二芯片40中设置的过压保护值，具体的，第一电流信号的电流值不低于第二电流信号的电流值。
在一个实施例中，电流侦测模块20还可以将转换得到的第一电流信号的电流值进行存储。
图2为本申请的另一个实施例提供的驱动电路的结构示意图。
如图2所示，本实施例中的第二芯片40包括：
升压模块410，设置为将输入的第一逻辑信号进行升压处理后，输出第二逻辑信号；以及
过流设定模块420，设置为根据内部过流设定值对第二逻辑信号进行限流控制。
在一个实施例中，第二芯片40中的过流设定模块420根据内部过流设定值对升压模块410输出的第二逻辑信号进行限流控制，本实施例中的第一逻辑信号和第二逻辑信号均可以为电压信号，具体的，过流设定模块420对第二逻辑信号进行限流控制可以包括关断第二逻辑信号的输出或者对第二逻辑信号进行降压处理，避免第二芯片40输出的第二逻辑信号电压过高而烧毁面板玻璃。
在一个实施例中，本实施例中的第一芯片10为电源管理芯片。
在一个实施例中，本实施例中的第二芯片40为升压芯片。
图3为本申请的另一个实施例提供的驱动电路的结构示意图。
如图3所示，电流侦测模块20包括：
第一转换单元201，设置为将第一芯片10输出的第一电流信号转换为对应的第一数据信号；以及
第一存储单元202，设置为存储第一数据信号。
在一个实施例中，第一转换单元201将接收的第一电流信号转换为对应的第一数据信号，并将该第一数据信号存储于第一存储单元202中，例如，电流侦测模块20侦测到电流值为100mA的，第一转换单元201将该第一电流信号转换为第一数据信号，该第一数据信号包含第一电流信号的电流值为100mA的信息，该第一数据存储在第一存储单元202中等待时序控制模块30读取。
图4为本申请的另一个实施例提供的驱动电路的结构示意图。
如图4所示，时序控制模块30包括：
第二存储单元301，设置为设置和存储与第一数据信号对应的第二数据信号；以及
控制单元302，设置为获取第一数据信号，并根据第一数据信号获取第二数据信号。
在一个实施例中，控制单元302可以包括可以通过通用集成电路，例如CPU（Central Processing Unit，中央处理器），或通过ASIC (Application Specific Integrated Circuit，专用集成电路）来实现。
在一个实施例中，控制单元302也可以是显示装置的屏驱动板（TCON，Timing Controller）。
在一个实施例中，第二存储单元301中存储有与第一数据信号对应的第二数据信号，该第二数据信号还可以根据用户需要进行设置，控制单元302从电流侦测模块20中读取到第一数据信号，然后根据该第一数据信号从第二存储单元301中读取对应的第二数据信号，该第二数据信号包含与第一数据信号对应的电流值信息的第二数据信号，具体的，第二存储单元301中存储的与第一数据信号对应的第二数据信号可以为电流转换关系的查找表，该查找表可以根据用户需要设置。
图5为本申请的一个实施例提供的第一电流信号的电流值和第二电流信号的电流值之间的转换关系查找表。
如图5所示，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为100mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为50mA，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为90mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为60mA，以此类推，控制单元302根据第一数据信号中包含的关于第一电流信号的信息从第二存储单元301中获取包含第二电流信号信息的第二数据信号。
在一个实施例中，第二存储单元301中存储的与第一数据信号对应的第二数据信号可以为电流转换关系的查找表还可以包括：第一电流信号的电流值阈值区间与第二电流信号的电流值的转换关系查找表，具体的，首先确认第一电流信号的电流值所处的阈值区间，根据该阈值区间确定与该阈值区间对应的第二电流信号的电流值，例如，第一芯片10的过压保护值为100mA，每间隔10mA作为一个阈值间隔区间，从0到100mA包含10个阈值区间，这10个阈值区间可以对应10个相同的或者不同的第二电流信号的电流值，例如，70mA至80mA，80mA至90mA，90mA至100mA所对应的第二电流信号的电流值均可以为50mA，50mA至60mA所对应的第二电流信号的电流值可以为80mA，依次类推，当检测到第一电流信号的电流值时，判断该电流值所处的阈值区间，例如，若检测到电流信号的电流为55mA时，则根据50mA至60mA所对应的第二预设阈值为80mA，则控制单元302从第二存储单元301中读取包含第二电流信号的电流值为80mA的信息的第二数据信号。
在一个实施例中，时序控制模块30还可以包括第三转换单元，设置为将该第二数据信号转换为对应的第二电流信号后输出至第二芯片40中的过流设定模块420中。
在一个实施例中，过流设定模块420还设置为：
接收到第二电流信号后将第二电流信号的电流值设置为第二芯片的内部过流设定值。
在一个实施例中，时序控制模块30还可以直接将控制单元302从第二存储单元301中读取的第二数据信号发送至第二芯片中的过流设定模块420，过流设定模块420通过接收的第二数据信号对内部过流设定值进行校正。
在一个实施例中，过流设定模块420还设置为：将第二电流信号的电流值设置为内部过流设定值。
具体的，过流设定模块420在接收到第二电流信号后，将第二电流信号的电流值设置为第二芯片40的内部过流设定值，而第二电流信号的电流值可以根据第一电流信号的电流按照预设的电流值转换关系进行调整，因此，第二电流信号的电流值设置为第二芯片40的内部过流设定值可以达到调节驱动电路的内部过流设定值的目的。
在一个实施例中，过流设定模块420还设置为：在第二逻辑信号大于或者等于内部过流设定值时，关断第二逻辑信号的输出。
在一个实施例中，时序控制模块30通过I2C接口与电流侦测模块连接。
图6为本申请另一个实施例提供的驱动电路的结构示意图。
如图6所示，本实施例中的驱动电路包括：
电源管理芯片10，设置为输出第一电流信号；
升压芯片40，设置为对输入的第一逻辑信号进行升压处理以输出第二逻辑信号，并根据内部过流设定值对所述第二逻辑信号进行限流控制；
电流侦测模块20，设置为获取所述第一电流信号；以及
时序控制模块30，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述升压芯片的内部过流设定值进行调节。
在一个实施例中，电流侦测模块20包括：
第一转换单元，设置为将所述第一电流信号转换为对应的第一数据信号；以及
第一存储单元，设置为存储所述第一数据信号。
在一个实施例中，时序控制模块30包括：
第二存储单元，设置为设置和存储与所述第一数据信号对应的第二数据信号；
控制单元，设置为获取所述第一数据信号，并根据所述第一数据信号从所述第二存储单元中获取所述第二数据信号。
在一个实施例中，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为100mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为50mA，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为90mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为60mA，以此类推，控制单元302根据第一数据信号中包含的关于第一电流信号的信息从第二存储单元301中获取包含第二电流信号信息的第二数据信号。
在一个实施例中，第二存储单元301中存储的与第一数据信号对应的第二数据信号可以为电流转换关系的查找表还可以包括：第一电流信号的电流值阈值区间与第二电流信号的电流值的转换关系查找表，具体的，首先确认第一电流信号的电流值所处的阈值区间，根据该阈值区间确定与该阈值区间对应的第二电流信号的电流值，例如，第一芯片10的过压保护值为100mA，每间隔10mA作为一个阈值间隔区间，从0到100mA包含10个阈值区间，这10个阈值区间可以对应10个相同的或者不同的第二电流信号的电流值，例如，70mA至80mA，80mA至90mA，90mA至100mA所对应的第二电流信号的电流值均可以为50mA，50mA至60mA所对应的第二电流信号的电流值可以为80mA，依次类推，当检测到第一电流信号的电流值时，判断该电流值所处的阈值区间，例如，若检测到电流信号的电流为55mA时，则根据50mA至60mA所对应的第二预设阈值为80mA，则控制单元302从第二存储单元301中读取包含第二电流信号的电流值为80mA的信息的第二数据信号。
可选的，所述第二数据信号设置为对所述内部过流设定值进行校正。
在一个实施例中，时序控制模块还可以直接将控制单元从第二存储单元中读取的第二数据信号发送至升压芯片60，升压芯片60通过接收的第二数据信号对内部过流设定值进行校正，即将第二数据信号中的电流值设置为升压芯片的内部过流设定值。
图7为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法的流程示意图。
在本实施例中，驱动电路包括：
第一芯片，设置为输出第一电流信号；
第二芯片，设置为接收第一逻辑信号，并对所述第一逻辑信号进行升压处理以输出第二逻辑信号。
如图7所示，本实施例中的校正方法包括：
步骤S10：获取所述第一芯片输出的第一电流信号；
步骤S20：接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号；所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制。
在一个实施例中，步骤S10包括：
采用电流侦测模块获取所述第一芯片输出的第一电流信号。
在一个实施例中，驱动电路还包括：电流侦测模块20，时序控制模块30。获取所述第一芯片输出的第一电流信号包括：采用电流侦测模块20对第一芯片10输出的第一电流信号进行检测，该检测过程包括侦测过程和转换过程，具体的，第一芯片10根据后端电路需要产生不同的电压信号，例如开启电压信号、关断电压信号等，电流侦测模块20选择需要侦测输出端口对第一电压信号进行侦测，该第一电压信号可以为第一芯片10任意一个输出端口输出的电压信号，电流侦测模块20侦测到该第一电压信号后将该第一电压信号转换为第一电流信号，并将转换后的第一电流信号进行输出。
在一个实施例中，接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号包括：采用时序控制模块30可以根据预先设置的电流转换关系将第一电流信号转换为设置为对第二芯片40的内部过流设定值进行调节的第二电流信号，该电流转换关系可以根据用户需要设置，例如，该电流转换关系可以为：将时序控制模块30接收的电流值减去预设值作为第二电流信号的电流值，例如，时序控制模块30接收到的第一电流信号的电流值为30mA，用户设置的预设值为20mA，则根据该预设的电流转换关系，第二电流信号的电流值为10mA，则时序控制模块30将电流值为30mA的第一电流信号转换为电流值为10mA的第二电流信号，以对第二芯片40的内部过流设定值进行调节。
在一个实施例中，电流侦测模块20还可以将转换得到的第一电流信号的电流值进行存储。
图8为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法中的步骤S20的流程示意图。
如图8所示，步骤S20包括：
步骤S21：接收所述第一电流信号；
步骤S22：根据所述第一电流信号以及预设的电流转换关系表将所述第一电流信号转换为所述第二电流信号。
图5为本申请的一个实施例提供的第一电流信号的电流值和第二电流信号的电流值之间的转换关系查找表。
如图5所示，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为100mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为50mA，当控制单元302读取到的第一数据信号中的第一电流信号的电流值为90mA，则从第二存储单元301读取的第二数据信号中的第二电流信号的电流值为60mA，以此类推，控制单元302根据第一数据信号中包含的关于第一电流信号的信息从第二存储单元301中获取包含第二电流信号信息的第二数据信号。
在一个实施例中，第二存储单元301中存储的与第一数据信号对应的第二数据信号可以为电流转换关系的查找表还可以包括：第一电流信号的电流值阈值区间与第二电流信号的电流值的转换关系查找表，具体的，首先确认第一电流信号的电流值所处的阈值区间，根据该阈值区间确定与该阈值区间对应的第二电流信号的电流值，例如，第一芯片10的过压保护值为100mA，每间隔10mA作为一个阈值间隔区间，从0到100mA包含10个阈值区间，这10个阈值区间可以对应10个相同的或者不同的第二电流信号的电流值，例如，70mA至80mA，80mA至90mA，90mA至100mA所对应的第二电流信号的电流值均可以为50mA，50mA至60mA所对应的第二电流信号的电流值可以为80mA，依次类推，当检测到第一电流信号的电流值时，判断该电流值所处的阈值区间，例如，若检测到电流信号的电流为55mA时，则根据50mA至60mA所对应的第二预设阈值为80mA，则控制单元302从第二存储单元301中读取包含第二电流信号的电流值为80mA的信息的第二数据信号。
图9为本申请的一个实施例提供的驱动电路的内部过流设定值的校正方法中的步骤S22的流程示意图。
如图9所示，步骤S22包括：
步骤S221：获取所述第一电流信号的第一电流值；
步骤S222：根据所述第一电流值从预设的电流转换关系表中获取第二电流值；
步骤S223：根据所述第二电流值将所述第一电流信号转换为所述第二电流信号。
在一个实施例中，该预设的电流转换关系还可以为预设的线性关系，例如，将第二电流信号的电流值设置为第一电流信号的电流值的0.9倍或者0.8倍，时序控制模块30接收到电流值为100mA的第一电流信号后对第一电流信号进行降流处理得到电流值为80mA的第二电流信号，并输出至第二芯片40中。
在一个实施例中，该预设的电流转换关系还可以根据用户需要设置成预设的算法进行计算，或者采用预先存储的电流查找表对与时序控制模块30接收的第一电流信号的电流值对应的第二电流信号的电流值进行设置。
在一个实施例中，所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，包括：
将所述第二电流信号的电流值设置为所述内部过流设定值。
在一个实施例中，为了使得第二芯片40和第一芯片10可以在过流时及时关闭电流输出，本实施例中的第一芯片10的过压保护值不低于第二芯片40中设置的过压保护值，具体的，第一电流信号的电流值不低于第二电流信号的电流值。
在一个实施例中，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制，包括：
若所述第二逻辑信号的电流值等于或大于所述内部过流设定值，则停止输出所述第二逻辑信号。
在一个实施例中，为了使得第二芯片40和第一芯片10可以在过流时及时关闭电流输出，本实施例中的第一芯片10的过压保护值不低于第二芯片40中设置的过压保护值，具体的，第一电流信号的电流值不低于第二电流信号的电流值。
本申请实施例装置中的单元可以根据实际需要进行合并、划分和删减。
本申请实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体（Read-Only Memory，ROM）或随机存储记忆体（Random Access Memory，RAM）等。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种驱动电路，包括第一芯片和第二芯片，其中，所述驱动电路还包括：
    电流侦测模块，设置为获取所述第一芯片输出的第一电流信号；以及
    时序控制模块，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节。
  2. 如权利要求1所述的驱动电路，其中，所述第二芯片包括：
    升压模块，设置为对输入的第一逻辑信号进行升压处理，并输出第二逻辑信号；以及
    过流设定模块，设置为根据所述内部过流设定值对所述第二逻辑信号进行限流控制。
  3. 如权利要求2所述的驱动电路，其中，所述第二芯片为升压芯片。
  4. 如权利要求1所述的驱动电路，其中，所述第一芯片为电源管理芯片。
  5. 如权利要求1所述的驱动电路，其中，所述电流侦测模块包括：
    第一转换单元，设置为将所述第一芯片输出的第一电流信号转换为对应的第一数据信号；以及
    第一存储单元，设置为存储所述第一数据信号。
  6. 如权利要求5所述的驱动电路，其中，所述时序控制模块包括：
    第二存储单元，设置为设置和存储与所述第一数据信号对应的第二数据信号；
    控制单元，设置为获取所述第一数据信号，并根据所述第一数据信号从所述第二存储单元中获取所述第二数据信号。
  7. 如权利要求6所述的驱动电路，其中，所述过流设定模块还设置为：
    接收所述第二数据信号，并将所述第二数据信号设置为所述内部过流设定值。
  8. 如权利要求2所述的驱动电路，其中，所述过流设定模块还设置为：
    将所述第二电流信号的电流值设置为所述内部过流设定值。
  9. 如权利要求2所述的驱动电路，其中，所述过流设定模块还设置为：
    在所述第二逻辑信号大于或者等于所述内部过流设定值时，关断所述第二逻辑信号的输出。
  10. 如权利要求1所述的驱动电路，其中，所述时序控制模块通过I2C接口与所述电流侦测模块连接。
  11. 一种驱动电路，其中，所述驱动电路包括：
    电源管理芯片，设置为输出第一电流信号；
    升压芯片，设置为对输入的第一逻辑信号进行升压处理以输出第二逻辑信号，并根据内部过流设定值对所述第二逻辑信号进行限流控制；
    电流侦测模块，设置为获取所述第一电流信号；以及
    时序控制模块，设置为接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，所述第二电流信号设置为对所述升压芯片的内部过流设定值进行调节。
  12. 如权利要求11所述的驱动电路，其中，所述电流侦测模块包括：
    第一转换单元，设置为将所述第一电流信号转换为对应的第一数据信号；以及
    第一存储单元，设置为存储所述第一数据信号。
  13. 如权利要求12所述的驱动电路，其中，所述时序控制模块包括：
    第二存储单元，设置为设置和存储与所述第一数据信号对应的第二数据信号；
    控制单元，设置为获取所述第一数据信号，并根据所述第一数据信号从所述第二存储单元中获取所述第二数据信号。
  14. 如权利要求13所述的驱动电路，其中，所述第二数据信号设置为对所述内部过流设定值进行校正。
  15. 一种驱动电路的内部过流设定值的校正方法，其中，所述驱动电路包括：
    第一芯片，设置为输出第一电流信号；
    第二芯片，设置为接收第一逻辑信号，并对所述第一逻辑信号进行升压处理以输出第二逻辑信号；
    所述校正方法包括：
    获取所述第一芯片输出的第一电流信号；
    接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号；所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制。
  16. 如权利要求15所述的校正方法，其中，所述获取所述第一芯片输出的第一电流信号，包括：
    采用电流侦测模块获取所述第一芯片输出的第一电流信号。
  17. 如权利要求15所述的校正方法，其中，所述接收所述第一电流信号，并将所述第一电流信号转换为第二电流信号，包括：
    接收所述第一电流信号；
    根据所述第一电流信号以及预设的电流转换关系表将所述第一电流信号转换为所述第二电流信号。
  18. 如权利要求17所述的校正方法，其中，所述根据所述第一电流信号以及预设的电流转换关系表将所述第一电流信号转换为所述第二电流信号，包括：
    获取所述第一电流信号的第一电流值；
    根据所述第一电流值从预设的电流转换关系表中获取第二电流值；
    根据所述第二电流值将所述第一电流信号转换为所述第二电流信号。
  19. 如权利要求15所述的校正方法，其中，所述第二电流信号设置为对所述第二芯片的内部过流设定值进行调节，包括：
    将所述第二电流信号的电流值设置为所述内部过流设定值。
  20. 如权利要求15所述的校正方法，其中，所述内部过流设定值设置为对所述第二逻辑信号进行限流控制，包括：
    若所述第二逻辑信号的电流值等于或大于所述内部过流设定值，则停止输出所述第二逻辑信号。
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