WO2020042309A1 - 一种限流电路、限流装置及显示装置 - Google Patents

一种限流电路、限流装置及显示装置 Download PDF

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Publication number
WO2020042309A1
WO2020042309A1 PCT/CN2018/111484 CN2018111484W WO2020042309A1 WO 2020042309 A1 WO2020042309 A1 WO 2020042309A1 CN 2018111484 W CN2018111484 W CN 2018111484W WO 2020042309 A1 WO2020042309 A1 WO 2020042309A1
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WIPO (PCT)
Prior art keywords
current
resistor
terminal
voltage signal
signal
Prior art date
Application number
PCT/CN2018/111484
Other languages
English (en)
French (fr)
Inventor
王明良
Original Assignee
重庆惠科金渝光电科技有限公司
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201811012965.7A external-priority patent/CN108767810B/zh
Priority claimed from CN201821431391.2U external-priority patent/CN208835727U/zh
Application filed by 重庆惠科金渝光电科技有限公司, 惠科股份有限公司 filed Critical 重庆惠科金渝光电科技有限公司
Priority to US16/311,736 priority Critical patent/US11018500B2/en
Publication of WO2020042309A1 publication Critical patent/WO2020042309A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current

Definitions

  • the embodiments of the present application belong to the field of electronic technology, and in particular, to a current limiting circuit, a current limiting device, and a display device.
  • the liquid crystal display panel usually integrates a gate driving chip on the display panel.
  • This design method greatly limits the reduction of the display frame.
  • the existing display usually uses a gateless driver (Gate driver less (GDL) architecture.
  • GDL Gate driver less
  • the GDL circuit divides the gate driver chip into a boost chip and a shift register chip, integrates the boost chip on the driver board, and integrates the shift register chip on the display panel.
  • the high-voltage logic signal is sent to the shift register chip to complete the display driving, thereby further reducing the frame length. Due to uncontrollable factors in the production process, the display panel may work abnormally.
  • a protection mechanism is usually set on the boost chip and power management chip.
  • the current output of the boost chip is turned off, or when the current signal output by the power management chip is too large, the current output of the power management chip is turned off.
  • the overcurrent protection circuit used by the boost chip and power management chip often causes the panel to burn out due to the failure to turn off the corresponding current output in time, which has great safety risks.
  • over-current protection circuits used by the booster chip and the power management chip often cause the panel to burn out due to the inability to turn off the corresponding current output in time, which has great safety risks.
  • the embodiments of the present application provide a current-limiting circuit, a current-limiting device, and a display device.
  • the purpose is to solve the over-current protection circuits used in the existing boost chip and power management chip because the corresponding current output cannot be turned off in time. Causes the panel to burn out, which has a great potential safety hazard.
  • the current limiting circuit includes:
  • the current detection module is configured to receive a first current signal output by the power management chip, and convert the first current signal into a corresponding first voltage signal.
  • the current detection module is connected to the power management chip. ;as well as
  • the current limit setting module is configured to receive the first voltage signal and output a second current signal that performs current limit control on the current output signal of the boost chip.
  • the current limit setting module and the current detection The test module and the boost chip are connected.
  • the boost chip includes:
  • An internal current limit setting module configured to control the boost chip to stop outputting the current output signal when the current output signal is greater than or equal to the internal current limit setting value.
  • the current detection module includes:
  • a current detection unit configured to detect the first current signal and output a first detection voltage signal and a second detection voltage signal according to the first current signal, and the current detection unit is connected to the power management chip; as well as
  • An operational amplification unit configured to receive the first detection voltage signal and the second detection voltage signal, and output a first voltage signal according to the first detection voltage signal and the second detection voltage signal, and the operation amplification A unit is connected to the current detection unit.
  • the current detection unit includes:
  • a first terminal of the first resistor is connected to the power management chip as a first terminal of the current detection unit, and a second terminal of the first resistor is used as a second terminal of the current detection unit.
  • the operational amplification unit includes:
  • a first terminal of the second resistor is connected to the current detection unit as a first detection voltage signal input terminal of the operational amplifier unit, and a second terminal of the second resistor and a first terminal of the third resistor And the non-inverting input terminal of the operational amplifier is connected in common, the second terminal of the third resistor is grounded, and the first terminal of the fourth resistor is used as the second detection voltage signal input terminal of the operational amplifier unit and the The current detection unit is connected, the second terminal of the fourth resistor, the first terminal of the eighth resistor and the negative input terminal of the operational amplifier are connected in common, and the output terminal of the operational amplifier is connected to the eighth resistor
  • the second terminal is connected in common as a first voltage signal output terminal of the operational amplifier unit.
  • the resistance value of the second resistor is the same as the resistance value of the third resistor.
  • the current limit setting module includes:
  • a voltage dividing unit configured to receive the first voltage signal and output a second voltage signal according to the first voltage signal, and the voltage dividing unit is connected to the current detection module;
  • the resistance unit is configured to receive the second voltage signal and output a second current signal according to the second voltage signal.
  • the resistance unit is connected to the voltage division unit.
  • the voltage dividing unit includes: a reference voltage source, a fifth resistor, a sixth resistor, and a seventh resistor;
  • the first terminal of the sixth resistor and the first terminal of the seventh resistor are connected in common as a first voltage signal input terminal of the voltage dividing unit and connected to the current detection module.
  • the two terminals are grounded, and the second terminal of the sixth resistor and the first terminal of the fifth resistor are connected in common as a second voltage signal output terminal of the voltage dividing unit to be connected to the resistor unit, and the fifth resistor
  • the second terminal of is connected to the reference voltage source.
  • the resistance unit is a resistor, and a resistance value of the resistor is proportional to a voltage value of the second voltage signal.
  • the resistor is a digital resistor.
  • An embodiment of the present application further provides a current limiting device, where the current limiting device includes:
  • a boosting chip configured to output a current output signal, and performing current limit control on the current output signal through an internal current limit setting module inside the boosting chip;
  • a power management chip configured to output a first current signal
  • the current detection module is configured to receive a first current signal output by the power management chip, and convert the first current signal into a corresponding first voltage signal.
  • the current detection module is connected to the power management chip. ;as well as
  • the current limit setting module is configured to receive the first voltage signal and output a second current signal, and the second current signal is set to adjust an internal current limit setting value in the internal current limit setting module.
  • the current limit setting module is connected to the current detection module and the boost chip.
  • the internal current limit setting module is configured to control the boost chip to stop outputting the current output signal when the current output signal is greater than or equal to the internal current limit setting value.
  • the current detection module includes:
  • a current detection unit configured to detect the first current signal and output a first detection voltage signal and a second detection voltage signal according to the first current signal, and the current detection unit is connected to the power management chip; as well as
  • An operational amplification unit configured to receive the first detection voltage signal and the second detection voltage signal, and output a first voltage signal according to the first detection voltage signal and the second detection voltage signal, and the operation amplification A unit is connected to the current detection unit.
  • the current detection unit includes: a first resistor
  • a first terminal of the first resistor is connected to the power management chip as a first terminal of the current detection unit, and a second terminal of the first resistor is used as a second terminal of the current detection unit.
  • the operational amplification unit includes:
  • a first terminal of the second resistor is connected to the current detection unit as a first detection voltage signal input terminal of the operational amplifier unit, and a second terminal of the second resistor and a first terminal of the third resistor And the non-inverting input terminal of the operational amplifier is connected in common, the second terminal of the third resistor is grounded, and the first terminal of the fourth resistor is used as the second detection voltage signal input terminal of the operational amplifier unit and the The current detection unit is connected, the second terminal of the fourth resistor, the first terminal of the eighth resistor and the negative input terminal of the operational amplifier are connected in common, and the output terminal of the operational amplifier is connected to the eighth resistor
  • the second terminal is connected in common as a first voltage signal output terminal of the operational amplifier unit.
  • the resistance value of the second resistor is the same as the resistance value of the third resistor.
  • the current limit setting module includes:
  • a voltage dividing unit configured to receive the first voltage signal and output a second voltage signal according to the first voltage signal, and the voltage dividing unit is connected to the current detection module;
  • the resistance unit is configured to receive the second voltage signal and output a second current signal according to the second voltage signal.
  • the resistance unit is connected to the voltage division unit.
  • the voltage dividing unit includes: a reference voltage source, a fifth resistor, a sixth resistor, and a seventh resistor;
  • the first terminal of the sixth resistor and the first terminal of the seventh resistor are connected in common as a first voltage signal input terminal of the voltage dividing unit and connected to the current detection module.
  • the two terminals are grounded, and the second terminal of the sixth resistor and the first terminal of the fifth resistor are connected in common as a second voltage signal output terminal of the voltage dividing unit to be connected to the resistor unit, and the fifth resistor
  • the second terminal of is connected to the reference voltage source.
  • the resistance unit is a resistor, and a resistance value of the resistor is proportional to a voltage value of the second voltage signal.
  • An embodiment of the present application further provides a display device, where the display device includes:
  • a boost chip is provided on the driving board, and a shift register is provided on the display panel, and the shift register is configured to receive a current output signal output by the boost chip to drive the display panel;
  • the current limiting circuit is connected to the boost chip and the power management chip;
  • the current limiting circuit includes:
  • the current detection module is configured to receive a first current signal output by the power management chip, and convert the first current signal into a corresponding first voltage signal.
  • the current detection module is connected to the power management chip. ;as well as
  • the current limit setting module is configured to receive the first voltage signal and output a second current signal that performs current limit control on the current output signal of the boost chip.
  • the current limit setting module and the current detection The test module and the boost chip are connected.
  • the embodiments of the present application provide a current limiting circuit, a current limiting device, and a display device.
  • the current limiting circuit is connected to a boost chip and a power management chip, and processes and processes the first current signal output by the power management chip of the current detection module.
  • the first voltage signal is output, and the current limit setting module processes the first voltage signal and outputs a second current signal to the boost chip, so that the boost chip can set the internal current limit according to the first current signal output by the power management chip.
  • the fixed value is adjusted to achieve timely shutdown of the chip when the output current of the boost chip and power management chip is too large, avoiding the display panel from being burned due to overcurrent, and solving the overcurrent protection used by the boost chip and power management chip
  • the circuit often burns the panel because the corresponding current output cannot be turned off in time, which has a great potential safety hazard.
  • FIG. 1 is a schematic structural diagram of a gateless driver GDL architecture display according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a current limiting circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a current limiting circuit according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a current limiting circuit according to another embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a current limiting device according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a gateless driver GDL architecture display according to an embodiment of the present application.
  • the GDL circuit divides a gate driver chip (gate IC) into a boost chip (level). shifter IC) and shift register, as shown in Figure 1, the boost chip is integrated on the driver board, and the driver board is connected to the display panel through multiple drive pins, such as pin 1 in Figure 1.
  • the shift register chip is integrated on the display panel.
  • the boost chip outputs high-voltage logic signals to the shift register chip to complete the display driver, thereby further reducing the length of the frame, so that the effective display area on the display panel can be continuously increased. .
  • the boost chip and the power management chip in the embodiments of the present application are both provided with an overcurrent protection mechanism.
  • the power management chip is used to convert the voltage output by the power supply into various types of voltage signals, for example, for turning on a thin film transistor ( Thin Film Transistor (TFT) turn-on voltage signal VGH, turn-off voltage signal VGL used to turn off the TFT, etc.
  • the boost chip is usually used to convert low-voltage logic signals into high-voltage logic signals.
  • the over-current protection mechanism inside the boost chip is an internal current limit setting module for limiting the current output signal of the boost chip.
  • the internal current limit setting module outputs the output current according to the internal current limit setting value.
  • the internal current setting value can be adjusted according to user needs. For example, an external pin is connected to an external resistor to set a specific current value. The larger the external setting resistance, the greater the internal current limit setting. The smaller the setting.
  • FIG. 2 is a schematic structural diagram of a current limiting circuit according to an embodiment of the present application.
  • the current-limiting circuit in this embodiment is connected to the boost chip 20 and the power management chip 10 respectively, where the current-limiting circuit includes:
  • the current detection module 30 is configured to receive a first current signal output by the power management chip and convert the first current signal into a corresponding first voltage signal.
  • the current detection module and the power management chip Connect;
  • the current-limit setting module 40 is configured to receive the first voltage signal and output a second current signal that performs current-limit control on the current output signal of the boost chip.
  • the current-limit setting module and the current The detection module and the boost chip are connected.
  • the current detection module 30 detects a first current signal output by the power management chip 10 and outputs a corresponding first voltage signal according to the first current signal.
  • the current limit setting module 40 detects the first current signal according to the first current signal.
  • the voltage signal generates a second current signal for adjusting an internal current limiting set value in the boost chip 20. For example, when the first current signal output by the power management chip 10 is too large, the current detection module 30 is based on the first current signal. The first voltage signal output by the current signal is also increased.
  • the current limit setting module 40 controls the internal current limit set value of the boost chip 20 to decrease according to the second current signal generated by the first voltage signal, so that the power supply When the first current signal output by the management chip 10 is too large, the over-current shutdown value of the boost chip 20 is reduced.
  • the over-current shutdown value is the internal current limit setting value of the boost chip 20 and reaches the power management chip 10
  • the boost chip 20 has the effect of turning off the output current at the same time when the output current is too high.
  • the boost chip 20 includes:
  • An internal current limit setting module configured to control the boost chip to stop outputting the current output signal when the current output signal is greater than or equal to the internal current limit setting value.
  • the boost chip 20 is provided with an internal current limit setting module.
  • the internal current limit setting module is provided with an internal current limit setting value. When the high-voltage logic signal output by the boost chip 20 exceeds the internal current limit, When the value is set, the boost chip 20 stops outputting a high-voltage logic signal.
  • the internal current limit setting value of the boost chip 20 can be set and adjusted as needed.
  • FIG. 3 is a schematic structural diagram of a current limiting circuit according to another embodiment of the present application.
  • the current detection module 30 includes:
  • the current detection unit 301 is configured to detect the first current signal and output a first detection voltage signal and a second detection voltage signal according to the first current signal.
  • the operation amplifying unit 302 is configured to receive the first detection voltage signal and the second detection voltage signal, and output a first voltage signal according to the first detection voltage signal and the second detection voltage signal.
  • the amplifying unit 302 is connected to the current detecting unit 301.
  • the resistance value of the current detection unit 301 can be set according to the user's needs.
  • the operational amplifier unit 302 can be based on the first detection voltage signal, the second detection voltage signal output by the current detection unit 301, and the user.
  • the preset resistance value of the current detection unit 301 obtains a current value of a first current signal output by the power management chip 10 and outputs a corresponding first voltage signal.
  • FIG. 4 is a schematic structural diagram of a current limiting circuit according to another embodiment of the present application.
  • the current detection unit 301 includes: a first resistor R1;
  • the first terminal of the first resistor R1 is connected to the power management chip 10 as the first terminal of the current detection unit 301, and the second terminal of the first resistor R1 is used as the second terminal of the current detection unit 301.
  • a first terminal of the first resistor R1 outputs a first detection voltage signal
  • a second terminal of the first resistor R1 outputs a second detection voltage signal.
  • the first resistor R1 may be an induction resistor, and the resistance of the induction resistor may be changed according to the magnitude of the current value.
  • the first end and the second end of the induction resistor are respectively used as the first ends of the current detection unit 301. And the second end.
  • the operational amplifier unit 302 includes: a second resistor R2, a third resistor R3, a fourth resistor R4, an eighth resistor R8, and an operational amplifier U1;
  • the first terminal of the second resistor R2 is connected to the current detection unit 301 as the first detection voltage signal input terminal of the operational amplifier unit U1, the second terminal of the second resistor R2, the first terminal of the third resistor R3, and the operation
  • the non-inverting input terminal (+) of the amplifier U1 is connected in common
  • the second terminal of the third resistor R3 is grounded
  • the first terminal of the fourth resistor R4 is connected to the current detection unit 301 as the second detection voltage signal input terminal of the operational amplifier unit U1.
  • the second terminal of the fourth resistor R4, the first terminal of the eighth resistor R8, and the negative input terminal of the operational amplifier U1 are connected in common.
  • the output terminal of the operational amplifier U1 and the second terminal of the eighth resistor R8 are connected in common as an operational amplifier.
  • the resistance of the second resistor R2 is the same as the resistance of the third resistor R3.
  • V + is the non-inverting input terminal of the operational amplifier U1.
  • V- is the signal voltage input at the reverse input terminal
  • A0 is the low-frequency gain of the operational amplifier U1.
  • the voltage value of the first detection voltage signal at the first end of the first resistor R1 is V1
  • the voltage value of the second detection voltage signal is V2
  • the voltage signal input from the non-inverting input terminal of the operational amplifier U1 is obtained by dividing the first detection voltage signal through the second resistor R2 and the third resistor R3, where the voltage values of the second resistor R2 and the third resistor R3 are obtained.
  • the current limit setting module 40 includes:
  • the voltage dividing unit 401 is configured to receive the first voltage signal and output a second voltage signal according to the first voltage signal, and the voltage dividing unit 401 is connected to the current detection module 30;
  • the resistance unit 402 is configured to receive the second voltage signal and output a second current signal according to the second voltage signal.
  • the resistance unit 402 is connected to the voltage division unit 401.
  • the voltage dividing unit 401 includes:
  • the first terminal of the sixth resistor R6 and the first terminal of the seventh resistor R7 are connected in common as the first voltage signal input terminal of the voltage dividing unit 401 and connected to the current detection module 30, and the second terminal of the seventh resistor R7 Ground, the second terminal of the sixth resistor R6 and the first terminal of the fifth resistor R5 are connected in common as the second voltage signal output terminal of the voltage dividing unit 401 and the resistor unit 402, and the second terminal of the fifth resistor R5 and the reference voltage Source Vref is connected.
  • the reference voltage source Vref is divided by a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.
  • the output terminal of the operational amplifier U1 is connected between the sixth resistor R6 and the seventh resistor R7. That is, the voltage value of the first voltage signal received by the voltage dividing unit 401 is Vout. It is assumed that the voltage value of the second voltage signal output by the voltage dividing unit 401 according to the first voltage signal is Vs, and the resistance value of the fifth resistor R5 is R5.
  • Vs (R6 * Vref + Vout * R5) / (R5 + R6), that is, at this time, the voltage value Vs of the second voltage signal and the voltage value of the first voltage signal It is proportional to Vout.
  • the resistance unit 402 is a resistor U2, and the resistance value of the resistor U2 is proportional to the voltage value of the second voltage signal.
  • the second voltage signal is used as a working power source for the resistor U2.
  • the resistance of the resistor U2 is proportional to the voltage value Vs of the second voltage signal. The larger the voltage value Vs of the second voltage signal, the resistor U2 The larger the resistance value of, the resistance value of the resistor U2 can be changed by changing the voltage value Vs of the second voltage signal, thereby changing the current value of the second current signal, so as to change the internal current limit of the boost chip 20 Set value.
  • the resistor U2 may be a digital resistor.
  • the digital resistor is a digitally adjustable resistor whose resistance value is proportional to the voltage value of the received voltage signal, that is, the voltage value of the received voltage signal. The larger the resistance is, the larger it is.
  • the voltage value Vout of the first voltage signal output by the current detection module 30 increases.
  • the second voltage output by the voltage dividing unit 401 The voltage value Vs of the signal will also increase, and the resistance value of the resistor U2 will also increase. Therefore, the internal current limit set value of the boost chip 20 is reduced, and the internal current limit set value is the value of the boost chip 20
  • the over-current shutdown value that is, the current of the high-voltage logic signal output by the boost chip 20 reaches the over-current shutdown value, and the output is turned off.
  • the power management chip 10 and the boost chip 20 are turned off when the output current is too high. Effect.
  • FIG. 5 is a schematic structural diagram of a current limiting device according to an embodiment of the present application.
  • the current limiting device in this embodiment includes:
  • the boosting chip 20 is configured to output a current output signal, and the current output signal is limited by the internal current limiting setting module 210 inside the boosting chip 20;
  • the power management chip 10 is configured to output a first current signal
  • the current detection module 30 is configured to receive a first current signal output by the power management chip and convert the first current signal into a corresponding first voltage signal.
  • the current limit setting module 40 is configured to receive the first voltage signal and output a second current signal.
  • the second current signal is set to an internal current limit setting value in the internal current limit setting module 210.
  • the current limit setting module 40 is connected to the current detection module 30 and the boost chip 20.
  • the current limiting device includes a current limiting circuit as in any one of the above.
  • the boosting chip 20 is provided with an internal current limiting device for limiting the current output signal of the boosting chip 20. ⁇ modules.
  • the internal current limit setting module 210 is configured to control the boost chip to stop outputting the current output signal when the current output signal is greater than or equal to the internal current limit setting value.
  • the internal current limit setting module 210 uses the internal current limit setting value to perform current limit control on the current output signal of the booster chip 20, and the internal current limit setting value is set according to the second current signal.
  • the current value of the second current signal is inversely proportional to the resistance value of the resistor U2. When the resistance value of the resistor U2 is larger, the current value of the second current signal is smaller, and the internal current is limited at this time. The smaller the internal current limit setting value in the setting module is, the smaller the shutdown current reached by the boost chip 20 is.
  • the current detection module 30 detects a first current signal output by the power management chip 10 and outputs a corresponding first voltage signal according to the first current signal.
  • the current limit setting module 40 detects the first current signal according to the first current signal.
  • the voltage signal generates a second current signal for adjusting an internal current limiting set value in the boost chip 20. For example, when the first current signal output by the power management chip 10 is too large, the current detection module 30 is based on the first current signal. The first voltage signal output by the current signal is also increased.
  • the current limit setting module 40 controls the internal current limit set value of the boost chip 20 to decrease according to the second current signal generated by the first voltage signal, so that the power supply When the first current signal output by the management chip 10 is too large, the over-current shutdown value of the boost chip 20 is reduced.
  • the over-current shutdown value is the internal current limit setting value of the boost chip 20 and reaches the power management chip 10
  • the boost chip 20 has the effect of turning off the output current at the same time when the output current is too high.
  • the current detection module 30 includes:
  • the current detection unit 301 is configured to detect the first current signal and output a first detection voltage signal and a second detection voltage signal according to the first current signal.
  • the operation amplifying unit 302 is configured to receive the first detection voltage signal and the second detection voltage signal, and output a first voltage signal according to the first detection voltage signal and the second detection voltage signal.
  • the amplifying unit 302 is connected to the current detecting unit 301.
  • the resistance value of the current detection unit 301 can be set according to the user's needs.
  • the operational amplifier unit 302 can be based on the first detection voltage signal, the second detection voltage signal output by the current detection unit 301, and the user.
  • the preset resistance value of the current detection unit 301 obtains a current value of a first current signal output by the power management chip 10 and outputs a corresponding first voltage signal.
  • the current detection unit 301 includes: a first resistor R1;
  • the first terminal of the first resistor R1 is connected to the power management chip 10 as the first terminal of the current detection unit 301, and the second terminal of the first resistor R1 is used as the second terminal of the current detection unit 301.
  • a first terminal of the first resistor R1 outputs a first detection voltage signal
  • a second terminal of the first resistor R1 outputs a second detection voltage signal.
  • the first resistor R1 may be an induction resistor, and the resistance of the induction resistor may be changed according to the magnitude of the current value.
  • the first end and the second end of the induction resistor are respectively used as the first ends of the current detection unit 301. And the second end.
  • the operational amplifier unit 302 includes: a second resistor R2, a third resistor R3, a fourth resistor R4, an eighth resistor R8, and an operational amplifier U1;
  • the first terminal of the second resistor R2 is connected to the current detection unit 301 as the first detection voltage signal input terminal of the operational amplifier unit U1, the second terminal of the second resistor R2, the first terminal of the third resistor R3, and the operation
  • the non-inverting input terminal (+) of the amplifier U1 is connected in common
  • the second terminal of the third resistor R3 is grounded
  • the first terminal of the fourth resistor R4 is connected to the current detection unit 301 as the second detection voltage signal input terminal of the operational amplifier unit U1.
  • the second terminal of the fourth resistor R4, the first terminal of the eighth resistor R8, and the negative input terminal of the operational amplifier U1 are connected in common.
  • the output terminal of the operational amplifier U1 and the second terminal of the eighth resistor R8 are connected in common as an operational amplifier.
  • the resistance of the second resistor R2 is the same as the resistance of the third resistor R3.
  • V + is the non-inverting input terminal of the operational amplifier U1.
  • V- is the signal voltage input at the reverse input terminal
  • A0 is the low-frequency gain of the operational amplifier U1.
  • the voltage value of the first detection voltage signal at the first end of the first resistor R1 is V1
  • the voltage value of the second detection voltage signal is V2
  • the voltage signal input from the non-inverting input terminal of the operational amplifier U1 is obtained by dividing the first detection voltage signal through the second resistor R2 and the third resistor R3, where the voltage values of the second resistor R2 and the third resistor R3 are obtained.
  • the current limit setting module 40 includes:
  • the voltage dividing unit 401 is configured to receive the first voltage signal and output a second voltage signal according to the first voltage signal, and the voltage dividing unit 401 is connected to the current detection module 30;
  • the resistance unit 402 is configured to receive the second voltage signal and output a second current signal according to the second voltage signal.
  • the resistance unit 402 is connected to the voltage division unit 401.
  • the voltage dividing unit 401 includes:
  • the first terminal of the sixth resistor R6 and the first terminal of the seventh resistor R7 are connected in common as the first voltage signal input terminal of the voltage dividing unit 401 and connected to the current detection module 30, and the second terminal of the seventh resistor R7 Ground, the second terminal of the sixth resistor R6 and the first terminal of the fifth resistor R5 are connected in common as the second voltage signal output terminal of the voltage dividing unit 401 and the resistor unit 402, and the second terminal of the fifth resistor R5 and the reference voltage Source Vref is connected.
  • the reference voltage source Vref is divided by a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.
  • the output terminal of the operational amplifier U1 is connected between the sixth resistor R6 and the seventh resistor R7. That is, the voltage value of the first voltage signal received by the voltage dividing unit 401 is Vout. It is assumed that the voltage value of the second voltage signal output by the voltage dividing unit 401 according to the first voltage signal is Vs, and the resistance value of the fifth resistor R5 is R5.
  • Vs (R6 * Vref + Vout * R5) / (R5 + R6), that is, at this time, the voltage value Vs of the second voltage signal and the voltage value of the first voltage signal It is proportional to Vout.
  • the resistance unit 402 is a resistor U2, and the resistance value of the resistor U2 is proportional to the voltage value of the second voltage signal.
  • the second voltage signal is used as a working power source for the resistor U2.
  • the resistance of the resistor U2 is proportional to the voltage value Vs of the second voltage signal. The larger the voltage value Vs of the second voltage signal, the resistor U2 The larger the resistance value of, the resistance value of the resistor U2 can be changed by changing the voltage value Vs of the second voltage signal, thereby changing the current value of the second current signal, so as to change the internal current limit of the boost chip 20 Set value.
  • the resistor U2 may be a digital resistor.
  • the digital resistor is a digitally adjustable resistor whose resistance value is proportional to the voltage value of the received voltage signal, that is, the voltage value of the received voltage signal. The larger the resistance is, the larger it is.
  • the voltage value Vout of the first voltage signal output by the current detection module 30 increases.
  • the second voltage output by the voltage dividing unit 401 The voltage value Vs of the signal will also increase, and the resistance value of the resistor U2 will also increase. Therefore, the internal current limit set value of the boost chip 20 is reduced, and the internal current limit set value is the value of the boost chip 20
  • the over-current shutdown value that is, the current of the high-voltage logic signal output by the boost chip 20 reaches the over-current shutdown value, and the output is turned off.
  • the power management chip 10 and the boost chip 20 are turned off when the output current is too high. Effect.
  • An embodiment of the present application further provides a display device, where the display device includes:
  • a boost chip 20 is provided on the driving board, and a shift register is provided on the display panel, and the shift register is configured to receive a current output signal output from the boost chip to drive the display panel;
  • the current limiting circuit is connected to the boost chip and the power management chip 10;
  • FIG. 2 a schematic diagram of the structure of the current limiting circuit is shown in FIG. 2.
  • the current limiting circuit in this embodiment includes:
  • the current detection module 30 is configured to receive a first current signal output by the power management chip and convert the first current signal into a corresponding first voltage signal.
  • the current detection module and the power management chip Connect;
  • the current-limit setting module 40 is configured to receive the first voltage signal and output a second current signal that performs current-limit control on the current output signal of the boost chip.
  • the current-limit setting module and the current The detection module and the boost chip are connected.
  • the current detection module 30 detects a first current signal output by the power management chip 10 and outputs a corresponding first voltage signal according to the first current signal.
  • the current limit setting module 40 detects the first current signal according to the first current signal.
  • the voltage signal generates a second current signal for adjusting an internal current limiting set value in the boost chip 20. For example, when the first current signal output by the power management chip 10 is too large, the current detection module 30 is based on the first current signal. The first voltage signal output by the current signal is also increased.
  • the current limit setting module 40 controls the internal current limit set value of the boost chip 20 to decrease according to the second current signal generated by the first voltage signal, so that the power supply When the first current signal output by the management chip 10 is too large, the over-current shutdown value of the boost chip 20 is reduced.
  • the over-current shutdown value is the internal current limit setting value of the boost chip 20 and reaches the power management chip 10
  • the boost chip 20 has the effect of turning off the output current at the same time when the output current is too high.
  • the boost chip 20 includes:
  • An internal current limit setting module configured to control the boost chip to stop outputting the current output signal when the current output signal is greater than or equal to the internal current limit setting value.
  • the boost chip 20 is provided with an internal current limit setting module.
  • the internal current limit setting module is provided with an internal current limit setting value. When the high-voltage logic signal output by the boost chip 20 exceeds the internal current limit, When the value is set, the boost chip 20 stops outputting a high-voltage logic signal.
  • the internal current limit setting value of the boost chip 20 can be set and adjusted as needed.

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Abstract

本申请实施例提供一种限流电路、限流装置及显示装置，通过电流侦测模块根据电源管理芯片输出的第一电流信号输出第一电压信号，然后通过限流设定模块根据第一电压信号输出对升压芯片的电流输出信号进行限流控制的第二电流信号。

Description

一种限流电路、限流装置及显示装置 技术领域
本申请实施例属于电子技术领域，尤其涉及一种限流电路、限流装置及显示装置。
 背景技术
液晶显示面板通常将门驱动芯片集成在显示面板上，这种设计方式极大的限制了显示器边框的减小，为了能够减小显示器的边框，现有的显示器通常采用一种无门驱动器（Gate driver less，GDL）架构，GDL电路是将门驱动芯片拆分为升压芯片和移位寄存器芯片，将升压芯片集成在驱动板上，移位寄存器芯片集成在显示面板上，通过升压芯片输出高压逻辑信号给移位寄存器芯片以完成显示器驱动，从而进一步压缩边框长度。由于生产工艺中的不可控因素可能会造成显示器面板的工作异常，为了避免升压芯片和电源管理芯片的输出电流过大而烧毁显示面板，通常对升压芯片和电源管理芯片设置保护机制，以使得升压芯片输出的电流信号过大时关闭升压芯片的电流输出，或者在电源管理芯片输出的电流信号过大时关闭电源管理芯片的电流输出。
然而，升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患。
 技术问题
升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患。
 技术解决方案
本申请实施例提供了一种限流电路、限流装置及显示装置，旨在解决现有的升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患的问题。
本申请提出了一种限流电路，与升压芯片以及电源管理芯片连接，所述限流电路包括：
电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
限流设定模块，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
可选的，所述升压芯片包括：
内部限流设定模块，所述内部限流设定模块设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
可选的，所述电流侦测模块包括：
电流检测单元，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元与所述电源管理芯片连接；以及
运算放大单元，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元与所述电流检测单元连接。
可选的，所述电流检测单元包括：
第一电阻；
所述第一电阻的第一端作为所述电流检测单元的第一端与所述电源管理芯片连接，所述第一电阻的第二端作为所述电流检测单元的第二端。
可选的，所述运算放大单元包括：
第二电阻、第三电阻、第四电阻、第八电阻以及运算放大器；
所述第二电阻的第一端作为所述运算放大单元的第一检测电压信号输入端与所述电流检测单元连接，所述第二电阻的第二端、所述第三电阻的第一端以及所述运算放大器的正相输入端共接，所述第三电阻的第二端接地，所述第四电阻的第一端作为所述运算放大单元的第二检测电压信号输入端与所述电流检测单元连接，所述第四电阻的第二端、所述第八电阻的第一端以及所述运算放大器的负相输入端共接，所述运算放大器的输出端与所述第八电阻的第二端共接作为所述运算放大单元的第一电压信号输出端。
可选的，所述第二电阻的阻值与所述第三电阻的阻值相同。
可选的，所述限流设定模块包括：
分压单元，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元与所述电流侦测模块连接；
电阻单元，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元与所述分压单元连接。
可选的，所述分压单元包括：参考电压源、第五电阻、第六电阻以及第七电阻；
所述第六电阻的第一端和所述第七电阻的第一端共接作为所述分压单元的第一电压信号输入端与所述电流侦测模块连接，所述第七电阻的第二端接地，所述第六电阻的第二端和所述第五电阻的第一端共接作为所述分压单元的第二电压信号输出端与所述电阻单元连接，所述第五电阻的第二端与所述参考电压源连接。
可选的，所述电阻单元为电阻器，所述电阻器的阻值与所述第二电压信号的电压值成正比。
可选的，所述电阻器为数字电阻器。
本申请实施例还提供了一种限流装置，所述限流装置包括：
升压芯片，设置为输出电流输出信号，并通过所述升压芯片内部的内部限流设定模块对所述电流输出信号进行限流控制；
电源管理芯片，设置为输出第一电流信号；
电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
限流设定模块，设置为接收所述第一电压信号，并输出第二电流信号，所述第二电流信号设置为对所述内部限流设定模块中的内部限流设定值进行调节，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
可选的，所述内部限流设定模块，设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
可选的，所述电流侦测模块包括：
电流检测单元，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元与所述电源管理芯片连接；以及
运算放大单元，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元与所述电流检测单元连接。
可选的，所述电流检测单元包括：第一电阻；
所述第一电阻的第一端作为所述电流检测单元的第一端与所述电源管理芯片连接，所述第一电阻的第二端作为所述电流检测单元的第二端。
可选的，所述运算放大单元包括：
第二电阻、第三电阻、第四电阻、第八电阻以及运算放大器；
所述第二电阻的第一端作为所述运算放大单元的第一检测电压信号输入端与所述电流检测单元连接，所述第二电阻的第二端、所述第三电阻的第一端以及所述运算放大器的正相输入端共接，所述第三电阻的第二端接地，所述第四电阻的第一端作为所述运算放大单元的第二检测电压信号输入端与所述电流检测单元连接，所述第四电阻的第二端、所述第八电阻的第一端以及所述运算放大器的负相输入端共接，所述运算放大器的输出端与所述第八电阻的第二端共接作为所述运算放大单元的第一电压信号输出端。
可选的，所述第二电阻的阻值与所述第三电阻的阻值相同。
可选的，所述限流设定模块包括：
分压单元，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元与所述电流侦测模块连接；
电阻单元，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元与所述分压单元连接。
可选的，所述分压单元包括：参考电压源、第五电阻、第六电阻以及第七电阻；
所述第六电阻的第一端和所述第七电阻的第一端共接作为所述分压单元的第一电压信号输入端与所述电流侦测模块连接，所述第七电阻的第二端接地，所述第六电阻的第二端和所述第五电阻的第一端共接作为所述分压单元的第二电压信号输出端与所述电阻单元连接，所述第五电阻的第二端与所述参考电压源连接。
可选的，所述电阻单元为电阻器，所述电阻器的阻值与所述第二电压信号的电压值成正比。
本申请实施例还提供一种显示装置，所述显示装置包括：
显示面板；
驱动板；以及
限流电路；
所述驱动板上设有升压芯片，所述显示面板上设有移位寄存器，所述移位寄存器设置为接收所述升压芯片输出的电流输出信号对所述显示面板进行驱动；
所述限流电路与所述升压芯片以及电源管理芯片连接；
所述限流电路包括：
电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
限流设定模块，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
 有益效果
本申请实施例提供一种限流电路、限流装置及显示装置，所述限流电路与升压芯片和电源管理芯片连接，通过电流侦测模块电源管理芯片输出的第一电流信号进行处理并输出第一电压信号，限流设定模块对该第一电压信号进行处理后向升压芯片输出第二电流信号，使得升压芯片可以根据电源管理芯片输出的第一电流信号对内部限流设定值进行调节，实现了在升压芯片和电源管理芯片的输出电流过大时及时关闭芯片，避免了显示面板由于过流而烧毁，解决了升压芯片和电源管理芯片所采用的过流保护电路经常由于无法及时关断对应的电流输出而造成面板烧毁的情况，具有极大的安全隐患的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一个实施例提供的无门驱动器GDL架构显示器的结构示意图；
图2为本申请的一个实施例提供的一种限流电路的结构示意图；
图3为本申请的另一个实施例提供的一种限流电路的结构示意图；
图4为本申请的另一个实施例提供的一种限流电路的结构示意图；
图5为本申请一个实施例提出的一种限流装置的结构示意图。
 本发明的实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“包括”以及它们任何变形，意图在于覆盖不排他的包含。例如包含一系列步骤或单元的过程、方法或系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同对象，而非用于描述特定顺序。
图1为本申请一个实施例提供的无门驱动器GDL架构显示器的结构示意图，在无门驱动器GDL架构中，GDL电路是将门驱动芯片（gate IC）拆分为升压芯片（level shifter IC）和移位寄存器（shift register）两部分，如图1所示，升压芯片集成在驱动板上，驱动板通过多个驱动引脚与显示面板连接，例如图1中的引脚1至引脚12，移位寄存器芯片集成在显示面板上，通过升压芯片输出高压逻辑信号给移位寄存器芯片以完成显示器驱动，从而进一步压缩边框长度，使得显示器面板上的有效显示区能够不断增加。
本申请实施例中的升压芯片和电源管理芯片内部均设置有过流保护机制，电源管理芯片用于将电源输出的电压转换为各种类型的电压信号，例如：用于导通薄膜晶体管（Thin Film Transistor，TFT）的开启电压信号VGH、用于关断TFT的关断电压信号VGL等，升压芯片通常用于将低压逻辑信号转换为高压的逻辑信号。升压芯片内部的过流保护机制为用于对升压芯片的电流输出信号进行限流控制的内部限流设定模块，内部限流设定模块根据内部限流设定值对输出的电流输出信号进行控制，该内部电流设定值可以根据用户需要进行调节，例如，通过一个外置引脚接入一个外挂电阻来设定具体的电流值，外部设定电阻越大，则内部限流设定值就越小。
图2为本申请的一个实施例提供的一种限流电路的结构示意图。
如图2所示，本实施例中的限流电路分别与升压芯片20和电源管理芯片10连接，其中，限流电路包括：
电流侦测模块30，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
限流设定模块40，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
在一个实施例中，电流侦测模块30对电源管理芯片10输出的第一电流信号进行检测，并根据该第一电流信号输出对应的第一电压信号，限流设定模块40根据该第一电压信号生成用于调节升压芯片20中的内部限流设定值的第二电流信号，例如，当电源管理芯片10输出的第一电流信号过大时，电流侦测模块30根据该第一电流信号输出的第一电压信号也同样增大，此时，限流设定模块40根据该第一电压信号生成的第二电流信号控制升压芯片20的内部限流设定值降低，使得电源管理芯片10输出的第一电流信号过大的同时降低升压芯片20的过流关断值，该过流关断值即为升压芯片20的内部限流设定值，达到电源管理芯片10和升压芯片20在输出电流过高时同时关闭输出电流的效果。
在一个实施例中，所述升压芯片20包括：
内部限流设定模块，所述内部限流设定模块设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
在本实施例中，升压芯片20内部设置有内部限流设定模块，该内部限流设定模块设置有内部限流设定值，当升压芯片20输出的高压逻辑信号超过内部限流设定值时，升压芯片20停止输出高压逻辑信号。
在一个实施例中，升压芯片20的内部限流设定值可根据需要进行设置及调节。
图3为本申请的另一个实施例提供的一种限流电路的结构示意图。
如图3所示，电流侦测模块30包括：
电流检测单元301，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元301与所述电源管理芯片10连接；以及
运算放大单元302，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元302与所述电流检测单元301连接。
在一个实施例中，电流检测单元301的电阻值可以根据用户需要设定预设的电阻值，运算放大单元302可以根据电流检测单元301输出的第一检测电压信号、第二检测电压信号以及用户预设的电流检测单元301的电阻值获取电源管理芯片10输出的第一电流信号的电流值，并输出对应的第一电压信号。
图4为本申请的另一个实施例提供的一种限流电路的结构示意图。
参见图4，电流检测单元301包括：第一电阻R1；
具体的，第一电阻R1的第一端作为电流检测单元301的第一端与电源管理芯片10连接，第一电阻R1的第二端作为电流检测单元301的第二端。在本实施例中，第一电阻R1的第一端输出第一检测电压信号，第一电阻R1的第二端输出第二检测电压信号。
在一个实施例中，第一电阻R1可以为感应电阻，感应电阻的阻值可以根据电流值的大小变化，同时，感应电阻的第一端和第二端分别作为电流检测单元301的第一端和第二端。
在一个实施例中，参见图4，运算放大单元302包括：第二电阻R2、第三电阻R3、第四电阻R4、第八电阻R8以及运算放大器U1；
具体的，第二电阻R2的第一端作为运算放大单元U1的第一检测电压信号输入端与电流检测单元301连接，第二电阻R2的第二端、第三电阻R3的第一端以及运算放大器U1的正相输入端（+）共接，第三电阻R3的第二端接地，第四电阻R4的第一端作为运算放大单元U1的第二检测电压信号输入端与电流检测单元301连接，第四电阻R4的第二端、第八电阻R8的第一端以及运算放大器U1的负相输入端共接，运算放大器U1的输出端与第八电阻R8的第二端共接作为运算放大单元302的第一电压信号输出端。
在一个实施例中，第二电阻R2的阻值与第三电阻R3的阻值相同。
在一个实施例中，运算放大器U1的输出信号与其两个输入端的信号电压差成正比，即输出电压Vout=A0*（V+ - V-），具体的，V+为运算放大器U1的正相输入端输入的信号电压，V-为反向输入端输入的信号电压，A0为运算放大器U1的低频增益。
在一个实施例中，假设第一电阻R1的第一端的第一检测电压信号的电压值为V1，第二检测电压信号的电压值为V2，运算放大器U1的低频增益为1，即A0=1，运算放大器U1的正相输入端输入的电压信号是第一检测电压信号经过第二电阻R2和第三电阻R3分压后得到的，其中，第二电阻R2和第三电阻R3的电压值相同，第四电阻R4与第八电阻R8的阻值相同，则运算放大器U1的正相输入端输入的电压信号V+=（V1）/2，运算放大器U1的负相输入端输入的电压信号V- = V2-（V2-Vout）/2 =（V2+Vout）/2，根据运算放大器的特性V+ = V-，所以有（V1）/2 = （V2+Vout）/2，即V1=V2+Vout，最终得到Vout=V1-V2，Vout就是V1与V2的压差。
在一个实施例中，参见图3，限流设定模块40包括：
分压单元401，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元401与所述电流侦测模块30连接；
电阻单元402，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元402与所述分压单元401连接。
在一个实施例中，参见图4，分压单元401包括：
参考电压源Vref、第五电阻R5、第六电阻R6以及第七电阻R7；
具体的，第六电阻R6的第一端和第七电阻R7的第一端共接作为分压单元401的第一电压信号输入端与电流侦测模块30连接，第七电阻R7的第二端接地，第六电阻R6的第二端和第五电阻R5的第一端共接作为分压单元401的第二电压信号输出端与电阻单元402连接，第五电阻R5的第二端与参考电压源Vref连接。
在一个实施例中，参考电压源Vref通过第五电阻R5、第六电阻R6以及第七电阻R7进行电阻分压，运算放大器U1的输出端连接在第六电阻R6与第七电阻R7之间，即分压单元401接收的第一电压信号的电压值为Vout，假设分压单元401根据该第一电压信号输出的第二电压信号的电压值为Vs，第五电阻R5的阻值为R5，第六电阻R6的阻值为R6，则有Vs=（R6*Vref+Vout*R5）/（R5+R6），即此时，第二电压信号的电压值Vs与第一电压信号的电压值为Vout成正比。
在一个实施例中，参见图4，电阻单元402为电阻器U2，电阻器U2的阻值与第二电压信号的电压值成正比。
在一个实施例中，第二电压信号作为电阻器U2的工作电源，电阻器U2的阻值与第二电压信号的电压值Vs成正比，第二电压信号的电压值Vs越大，电阻器U2的电阻值就越大，因此，通过改变第二电压信号的电压值Vs即可改变电阻器U2的电阻值，从而改变第二电流信号的电流值，以达到改变升压芯片20的内部限流设定值。
在一个实施例中，电阻器U2可以为数字电阻器，该数字电阻器是数字可调型的电阻器，其电阻值与接收的电压信号的电压值成正比，即接收的电压信号的电压值越大，其电阻值就越大。
在一个实施例中，当电源管理芯片输出的第一电流信号增大时，电流侦测模块30输出的第一电压信号的电压值Vout增大，此时，分压单元401输出的第二电压信号的电压值Vs也会增大，电阻器U2的电阻值也会增大，因此，升压芯片20的内部限流设定值降低，该内部限流设定值即为升压芯片20的过流关断值，即升压芯片20输出的高压逻辑信号的电流达到该过流关断值即关闭输出，达到了电源管理芯片10和升压芯片20在输出电流过高时同时关闭输出电流的效果。
图5为本申请一个实施例提出的一种限流装置的结构示意图。
如图5所示，本实施例中的限流装置，包括：
升压芯片20，设置为输出电流输出信号，并通过所述升压芯片20内部的内部限流设定模块210对所述电流输出信号进行限流控制；
电源管理芯片10，设置为输出第一电流信号；
电流侦测模块30，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块30与所述电源管理芯片10连接；以及
限流设定模块40，设置为接收所述第一电压信号，并输出第二电流信号，所述第二电流信号设置为对所述内部限流设定模块210中的内部限流设定值进行调节，所述限流设定模块40与所述电流侦测模块30以及所述升压芯片20连接。
升压芯片20和电源管理芯片10，限流装置包括如上述任一项的限流电路，升压芯片20内设置有用于对升压芯片20的电流输出信号进行限流控制的内部限流设定模块。
在一个实施例中，所述内部限流设定模块210，设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
在一个实施例中，内部限流设定模块210采用内部限流设定值对升压芯片20的电流输出信号进行限流控制，内部限流设定值根据第二电流信号进行设置。在本实施例中的第二电流信号的电流值与电阻器U2的电阻值的成反比，当电阻器U2的阻值越大时，第二电流信号的电流值越小，此时内部限流设定模块中的内部限流设定值就越小，即升压芯片20所达到的关断电流就越小。
在一个实施例中，电流侦测模块30对电源管理芯片10输出的第一电流信号进行检测，并根据该第一电流信号输出对应的第一电压信号，限流设定模块40根据该第一电压信号生成用于调节升压芯片20中的内部限流设定值的第二电流信号，例如，当电源管理芯片10输出的第一电流信号过大时，电流侦测模块30根据该第一电流信号输出的第一电压信号也同样增大，此时，限流设定模块40根据该第一电压信号生成的第二电流信号控制升压芯片20的内部限流设定值降低，使得电源管理芯片10输出的第一电流信号过大的同时降低升压芯片20的过流关断值，该过流关断值即为升压芯片20的内部限流设定值，达到电源管理芯片10和升压芯片20在输出电流过高时同时关闭输出电流的效果。
在一个实施例中，参见图3，电流侦测模块30包括：
电流检测单元301，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元301与所述电源管理芯片10连接；以及
运算放大单元302，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元302与所述电流检测单元301连接。
在一个实施例中，电流检测单元301的电阻值可以根据用户需要设定预设的电阻值，运算放大单元302可以根据电流检测单元301输出的第一检测电压信号、第二检测电压信号以及用户预设的电流检测单元301的电阻值获取电源管理芯片10输出的第一电流信号的电流值，并输出对应的第一电压信号。
在一个实施例中，参见图4，电流检测单元301包括：第一电阻R1；
具体的，第一电阻R1的第一端作为电流检测单元301的第一端与电源管理芯片10连接，第一电阻R1的第二端作为电流检测单元301的第二端。在本实施例中，第一电阻R1的第一端输出第一检测电压信号，第一电阻R1的第二端输出第二检测电压信号。
在一个实施例中，第一电阻R1可以为感应电阻，感应电阻的阻值可以根据电流值的大小变化，同时，感应电阻的第一端和第二端分别作为电流检测单元301的第一端和第二端。
在一个实施例中，参见图4，运算放大单元302包括：第二电阻R2、第三电阻R3、第四电阻R4、第八电阻R8以及运算放大器U1；
具体的，第二电阻R2的第一端作为运算放大单元U1的第一检测电压信号输入端与电流检测单元301连接，第二电阻R2的第二端、第三电阻R3的第一端以及运算放大器U1的正相输入端（+）共接，第三电阻R3的第二端接地，第四电阻R4的第一端作为运算放大单元U1的第二检测电压信号输入端与电流检测单元301连接，第四电阻R4的第二端、第八电阻R8的第一端以及运算放大器U1的负相输入端共接，运算放大器U1的输出端与第八电阻R8的第二端共接作为运算放大单元302的第一电压信号输出端。
在一个实施例中，第二电阻R2的阻值与第三电阻R3的阻值相同。
在一个实施例中，运算放大器U1的输出信号与其两个输入端的信号电压差成正比，即输出电压Vout=A0*（V+ - V-），具体的，V+为运算放大器U1的正相输入端输入的信号电压，V-为反向输入端输入的信号电压，A0为运算放大器U1的低频增益。
在一个实施例中，假设第一电阻R1的第一端的第一检测电压信号的电压值为V1，第二检测电压信号的电压值为V2，运算放大器U1的低频增益为1，即A0=1，运算放大器U1的正相输入端输入的电压信号是第一检测电压信号经过第二电阻R2和第三电阻R3分压后得到的，其中，第二电阻R2和第三电阻R3的电压值相同，第四电阻R4与第八电阻R8的阻值相同，则运算放大器U1的正相输入端输入的电压信号V+=（V1）/2，运算放大器U1的负相输入端输入的电压信号V- = V2-（V2-Vout）/2 =（V2+Vout）/2，根据运算放大器的特性V+ = V-，所以有（V1）/2 = （V2+Vout）/2，即V1=V2+Vout，最终得到Vout=V1-V2，Vout就是V1与V2的压差。
在一个实施例中，参见图3，限流设定模块40包括：
分压单元401，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元401与所述电流侦测模块30连接；
电阻单元402，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元402与所述分压单元401连接。
在一个实施例中，参见图4，分压单元401包括：
参考电压源Vref、第五电阻R5、第六电阻R6以及第七电阻R7；
具体的，第六电阻R6的第一端和第七电阻R7的第一端共接作为分压单元401的第一电压信号输入端与电流侦测模块30连接，第七电阻R7的第二端接地，第六电阻R6的第二端和第五电阻R5的第一端共接作为分压单元401的第二电压信号输出端与电阻单元402连接，第五电阻R5的第二端与参考电压源Vref连接。
在一个实施例中，参考电压源Vref通过第五电阻R5、第六电阻R6以及第七电阻R7进行电阻分压，运算放大器U1的输出端连接在第六电阻R6与第七电阻R7之间，即分压单元401接收的第一电压信号的电压值为Vout，假设分压单元401根据该第一电压信号输出的第二电压信号的电压值为Vs，第五电阻R5的阻值为R5，第六电阻R6的阻值为R6，则有Vs=（R6*Vref+Vout*R5）/（R5+R6），即此时，第二电压信号的电压值Vs与第一电压信号的电压值为Vout成正比。
在一个实施例中，参见图4，电阻单元402为电阻器U2，电阻器U2的阻值与第二电压信号的电压值成正比。
在一个实施例中，第二电压信号作为电阻器U2的工作电源，电阻器U2的阻值与第二电压信号的电压值Vs成正比，第二电压信号的电压值Vs越大，电阻器U2的电阻值就越大，因此，通过改变第二电压信号的电压值Vs即可改变电阻器U2的电阻值，从而改变第二电流信号的电流值，以达到改变升压芯片20的内部限流设定值。
在一个实施例中，电阻器U2可以为数字电阻器，该数字电阻器是数字可调型的电阻器，其电阻值与接收的电压信号的电压值成正比，即接收的电压信号的电压值越大，其电阻值就越大。
在一个实施例中，当电源管理芯片输出的第一电流信号增大时，电流侦测模块30输出的第一电压信号的电压值Vout增大，此时，分压单元401输出的第二电压信号的电压值Vs也会增大，电阻器U2的电阻值也会增大，因此，升压芯片20的内部限流设定值降低，该内部限流设定值即为升压芯片20的过流关断值，即升压芯片20输出的高压逻辑信号的电流达到该过流关断值即关闭输出，达到了电源管理芯片10和升压芯片20在输出电流过高时同时关闭输出电流的效果。
本申请一个实施例还提供一种显示装置，所述显示装置包括：
显示面板；
驱动板；以及
限流电路；
所述驱动板上设有升压芯片20，所述显示面板上设有移位寄存器，所述移位寄存器设置为接收所述升压芯片输出的电流输出信号对所述显示面板进行驱动；
所述限流电路与所述升压芯片以及电源管理芯片10连接；
在本实施例中，限流电路的结构示意图参见图2，如图2所示，本实施例中的限流电路包括：
电流侦测模块30，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
限流设定模块40，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
在一个实施例中，电流侦测模块30对电源管理芯片10输出的第一电流信号进行检测，并根据该第一电流信号输出对应的第一电压信号，限流设定模块40根据该第一电压信号生成用于调节升压芯片20中的内部限流设定值的第二电流信号，例如，当电源管理芯片10输出的第一电流信号过大时，电流侦测模块30根据该第一电流信号输出的第一电压信号也同样增大，此时，限流设定模块40根据该第一电压信号生成的第二电流信号控制升压芯片20的内部限流设定值降低，使得电源管理芯片10输出的第一电流信号过大的同时降低升压芯片20的过流关断值，该过流关断值即为升压芯片20的内部限流设定值，达到电源管理芯片10和升压芯片20在输出电流过高时同时关闭输出电流的效果。
在一个实施例中，所述升压芯片20包括：
内部限流设定模块，所述内部限流设定模块设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
在本实施例中，升压芯片20内部设置有内部限流设定模块，该内部限流设定模块设置有内部限流设定值，当升压芯片20输出的高压逻辑信号超过内部限流设定值时，升压芯片20停止输出高压逻辑信号。
在一个实施例中，升压芯片20的内部限流设定值可根据需要进行设置及调节。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种限流电路，与升压芯片以及电源管理芯片连接，其中，所述限流电路包括：
    电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
    限流设定模块，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
  2. 如权利要求1所述的限流电路，其中，所述升压芯片包括：
    内部限流设定模块，所述内部限流设定模块设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
  3. 如权利要求1所述的限流电路，其中，所述电流侦测模块包括：
    电流检测单元，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元与所述电源管理芯片连接；以及
    运算放大单元，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元与所述电流检测单元连接。
  4. 如权利要求3所述的限流电路，其中，所述电流检测单元包括：
    第一电阻；
    所述第一电阻的第一端作为所述电流检测单元的第一端与所述电源管理芯片连接，所述第一电阻的第二端作为所述电流检测单元的第二端。
  5. 如权利要求3所述的限流电路，其中，所述运算放大单元包括：
    第二电阻、第三电阻、第四电阻、第八电阻以及运算放大器；
    所述第二电阻的第一端作为所述运算放大单元的第一检测电压信号输入端与所述电流检测单元连接，所述第二电阻的第二端、所述第三电阻的第一端以及所述运算放大器的正相输入端共接，所述第三电阻的第二端接地，所述第四电阻的第一端作为所述运算放大单元的第二检测电压信号输入端与所述电流检测单元连接，所述第四电阻的第二端、所述第八电阻的第一端以及所述运算放大器的负相输入端共接，所述运算放大器的输出端与所述第八电阻的第二端共接作为所述运算放大单元的第一电压信号输出端。
  6. 如权利要求5所述的限流电路，其中，所述第二电阻的阻值与所述第三电阻的阻值相同。
  7. 如权利要求1所述的限流电路，其中，所述限流设定模块包括：
    分压单元，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元与所述电流侦测模块连接；
    电阻单元，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元与所述分压单元连接。
  8. 如权利要求7所述的限流电路，其中，所述分压单元包括：参考电压源、第五电阻、第六电阻以及第七电阻；
    所述第六电阻的第一端和所述第七电阻的第一端共接作为所述分压单元的第一电压信号输入端与所述电流侦测模块连接，所述第七电阻的第二端接地，所述第六电阻的第二端和所述第五电阻的第一端共接作为所述分压单元的第二电压信号输出端与所述电阻单元连接，所述第五电阻的第二端与所述参考电压源连接。
  9. 如权利要求7所述的限流电路，其中，所述电阻单元为电阻器，所述电阻器的阻值与所述第二电压信号的电压值成正比。
  10. 如权利要求9所述的限流电路，其中，所述电阻器为数字电阻器。
  11. 一种限流装置，其中，所述限流装置包括：
    升压芯片，设置为输出电流输出信号，并通过所述升压芯片内部的内部限流设定模块对所述电流输出信号进行限流控制；
    电源管理芯片，设置为输出第一电流信号；
    电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
    限流设定模块，设置为接收所述第一电压信号，并输出第二电流信号，所述第二电流信号设置为对所述内部限流设定模块中的内部限流设定值进行调节，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
  12. 如权利要求11所述的限流装置，其中，所述内部限流设定模块，设置为在所述电流输出信号大于或等于所述内部限流设定值时，控制所述升压芯片停止输出所述电流输出信号。
  13. 如权利要求11所述的限流装置，其中，所述电流侦测模块包括：
    电流检测单元，设置为对所述第一电流信号进行检测，并根据所述第一电流信号输出第一检测电压信号和第二检测电压信号，所述电流检测单元与所述电源管理芯片连接；以及
    运算放大单元，设置为接收所述第一检测电压信号和所述第二检测电压信号，并根据所述第一检测电压信号和所述第二检测电压信号输出第一电压信号，所述运算放大单元与所述电流检测单元连接。
  14. 如权利要求13所述的限流装置，其中，所述电流检测单元包括：第一电阻；
    所述第一电阻的第一端作为所述电流检测单元的第一端与所述电源管理芯片连接，所述第一电阻的第二端作为所述电流检测单元的第二端。
  15. 如权利要求13所述的限流装置，其中，所述运算放大单元包括：
    第二电阻、第三电阻、第四电阻、第八电阻以及运算放大器；
    所述第二电阻的第一端作为所述运算放大单元的第一检测电压信号输入端与所述电流检测单元连接，所述第二电阻的第二端、所述第三电阻的第一端以及所述运算放大器的正相输入端共接，所述第三电阻的第二端接地，所述第四电阻的第一端作为所述运算放大单元的第二检测电压信号输入端与所述电流检测单元连接，所述第四电阻的第二端、所述第八电阻的第一端以及所述运算放大器的负相输入端共接，所述运算放大器的输出端与所述第八电阻的第二端共接作为所述运算放大单元的第一电压信号输出端。
  16. 如权利要求15所述的限流装置，其中，所述第二电阻的阻值与所述第三电阻的阻值相同。
  17. 如权利要求11所述的限流装置，其中，所述限流设定模块包括：
    分压单元，设置为接收所述第一电压信号，并根据所述第一电压信号输出第二电压信号，所述分压单元与所述电流侦测模块连接；
    电阻单元，设置为接收所述第二电压信号，并根据所述第二电压信号输出第二电流信号，所述电阻单元与所述分压单元连接。
  18. 如权利要求17所述的限流装置，其中，所述分压单元包括：参考电压源、第五电阻、第六电阻以及第七电阻；
    所述第六电阻的第一端和所述第七电阻的第一端共接作为所述分压单元的第一电压信号输入端与所述电流侦测模块连接，所述第七电阻的第二端接地，所述第六电阻的第二端和所述第五电阻的第一端共接作为所述分压单元的第二电压信号输出端与所述电阻单元连接，所述第五电阻的第二端与所述参考电压源连接。
  19. 如权利要求17所述的限流装置，其中，所述电阻单元为电阻器，所述电阻器的阻值与所述第二电压信号的电压值成正比。
  20. 一种显示装置，其中，所述显示装置包括：
    显示面板；
    驱动板；以及
    限流电路；
    所述驱动板上设有升压芯片，所述显示面板上设有移位寄存器，所述移位寄存器设置为接收所述升压芯片输出的电流输出信号对所述显示面板进行驱动；
    所述限流电路与所述升压芯片以及电源管理芯片连接；
    所述限流电路包括：
    电流侦测模块，设置为接收所述电源管理芯片输出的第一电流信号，并将所述第一电流信号转换为对应的第一电压信号，所述电流侦测模块与所述电源管理芯片连接；以及
    限流设定模块，设置为接收所述第一电压信号，并输出对所述升压芯片的电流输出信号进行限流控制的第二电流信号，所述限流设定模块与所述电流侦测模块以及所述升压芯片连接。
PCT/CN2018/111484 2018-08-31 2018-10-23 一种限流电路、限流装置及显示装置 WO2020042309A1 (zh)

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